diff options
Diffstat (limited to 'dts/src/arm/imx6sx-sdb.dtsi')
| -rw-r--r-- | dts/src/arm/imx6sx-sdb.dtsi | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/dts/src/arm/imx6sx-sdb.dtsi b/dts/src/arm/imx6sx-sdb.dtsi index c99aa273c2..b8c23eba9d 100644 --- a/dts/src/arm/imx6sx-sdb.dtsi +++ b/dts/src/arm/imx6sx-sdb.dtsi @@ -179,6 +179,15 @@ }; }; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sx-sdb-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + }; &audmux { @@ -281,6 +290,7 @@ }; &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; @@ -296,6 +306,14 @@ status = "disabled"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &ssi2 { status = "okay"; }; @@ -505,6 +523,13 @@ >; }; + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 @@ -562,6 +587,12 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 |