diff options
Diffstat (limited to 'dts/src/arm/imx6ull-tqma6ull2.dtsi')
-rw-r--r-- | dts/src/arm/imx6ull-tqma6ull2.dtsi | 76 |
1 files changed, 0 insertions, 76 deletions
diff --git a/dts/src/arm/imx6ull-tqma6ull2.dtsi b/dts/src/arm/imx6ull-tqma6ull2.dtsi deleted file mode 100644 index 326e6da91e..0000000000 --- a/dts/src/arm/imx6ull-tqma6ull2.dtsi +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2018-2022 TQ-Systems GmbH - * Author: Markus Niebel <Markus.Niebel@tq-group.com> - */ - -#include "imx6ull.dtsi" -#include "imx6ul-tqma6ul-common.dtsi" -#include "imx6ul-tqma6ulx-common.dtsi" - -/ { - model = "TQ-Systems TQMa6ULL2 SoM"; - compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; -}; - -&usdhc2 { - fsl,tuning-step= <6>; - /* Errata ERR010450 Workaround */ - max-frequency = <99000000>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <198000000>; -}; - -&iomuxc { - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 - /* rst */ - MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 - >; - }; -}; |