summaryrefslogtreecommitdiffstats
path: root/dts/src/arm/lan966x-pcb8291.dts
diff options
context:
space:
mode:
Diffstat (limited to 'dts/src/arm/lan966x-pcb8291.dts')
-rw-r--r--dts/src/arm/lan966x-pcb8291.dts64
1 files changed, 64 insertions, 0 deletions
diff --git a/dts/src/arm/lan966x-pcb8291.dts b/dts/src/arm/lan966x-pcb8291.dts
new file mode 100644
index 0000000000..3281af90ac
--- /dev/null
+++ b/dts/src/arm/lan966x-pcb8291.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * lan966x_pcb8291.dts - Device Tree file for PCB8291
+ */
+/dts-v1/;
+#include "lan966x.dtsi"
+
+/ {
+ model = "Microchip EVB - LAN9662";
+ compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &usart3;
+ };
+};
+
+&gpio {
+ fc_shrd7_pins: fc_shrd7-pins {
+ pins = "GPIO_49";
+ function = "fc_shrd7";
+ };
+
+ fc_shrd8_pins: fc_shrd8-pins {
+ pins = "GPIO_54";
+ function = "fc_shrd8";
+ };
+
+ fc3_b_pins: fcb3-spi-pins {
+ /* SCK, RXD, TXD */
+ pins = "GPIO_51", "GPIO_52", "GPIO_53";
+ function = "fc3_b";
+ };
+
+ can0_b_pins: can0_b_pins {
+ /* RX, TX */
+ pins = "GPIO_35", "GPIO_36";
+ function = "can0_b";
+ };
+};
+
+&can0 {
+ pinctrl-0 = <&can0_b_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ usart3: serial@200 {
+ pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+};
+
+&watchdog {
+ status = "okay";
+};