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-rw-r--r--dts/src/arm/mmp2.dtsi426
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diff --git a/dts/src/arm/mmp2.dtsi b/dts/src/arm/mmp2.dtsi
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index 6a2f072c1d..0000000000
--- a/dts/src/arm/mmp2.dtsi
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@@ -1,426 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Marvell Technology Group Ltd.
- * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
- */
-
-#include <dt-bindings/clock/marvell,mmp2.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- i2c0 = &twsi1;
- i2c1 = &twsi2;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&intc>;
- ranges;
-
- L2: l2-cache {
- compatible = "marvell,tauros2-cache";
- marvell,tauros2-cache-features = <0x3>;
- };
-
- axi@d4200000 { /* AXI */
- compatible = "mrvl,axi-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xd4200000 0x00200000>;
- ranges;
-
- intc: interrupt-controller@d4282000 {
- compatible = "mrvl,mmp2-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0xd4282000 0x1000>;
- mrvl,intc-nr-irqs = <64>;
- };
-
- intcmux4: interrupt-controller@d4282150 {
- compatible = "mrvl,mmp2-mux-intc";
- interrupts = <4>;
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x150 0x4>, <0x168 0x4>;
- reg-names = "mux status", "mux mask";
- mrvl,intc-nr-irqs = <2>;
- };
-
- intcmux5: interrupt-controller@d4282154 {
- compatible = "mrvl,mmp2-mux-intc";
- interrupts = <5>;
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x154 0x4>, <0x16c 0x4>;
- reg-names = "mux status", "mux mask";
- mrvl,intc-nr-irqs = <2>;
- mrvl,clr-mfp-irq = <1>;
- };
-
- intcmux9: interrupt-controller@d4282180 {
- compatible = "mrvl,mmp2-mux-intc";
- interrupts = <9>;
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x180 0x4>, <0x17c 0x4>;
- reg-names = "mux status", "mux mask";
- mrvl,intc-nr-irqs = <3>;
- };
-
- intcmux17: interrupt-controller@d4282158 {
- compatible = "mrvl,mmp2-mux-intc";
- interrupts = <17>;
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x158 0x4>, <0x170 0x4>;
- reg-names = "mux status", "mux mask";
- mrvl,intc-nr-irqs = <5>;
- };
-
- intcmux35: interrupt-controller@d428215c {
- compatible = "mrvl,mmp2-mux-intc";
- interrupts = <35>;
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x15c 0x4>, <0x174 0x4>;
- reg-names = "mux status", "mux mask";
- mrvl,intc-nr-irqs = <15>;
- };
-
- intcmux51: interrupt-controller@d4282160 {
- compatible = "mrvl,mmp2-mux-intc";
- interrupts = <51>;
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x160 0x4>, <0x178 0x4>;
- reg-names = "mux status", "mux mask";
- mrvl,intc-nr-irqs = <2>;
- };
-
- intcmux55: interrupt-controller@d4282188 {
- compatible = "mrvl,mmp2-mux-intc";
- interrupts = <55>;
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x188 0x4>, <0x184 0x4>;
- reg-names = "mux status", "mux mask";
- mrvl,intc-nr-irqs = <2>;
- };
-
- usb_phy0: usb-phy@d4207000 {
- compatible = "marvell,mmp2-usb-phy";
- reg = <0xd4207000 0x40>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usb_otg0: usb-otg@d4208000 {
- compatible = "marvell,pxau2o-ehci";
- reg = <0xd4208000 0x200>;
- interrupts = <44>;
- clocks = <&soc_clocks MMP2_CLK_USB>;
- clock-names = "USBCLK";
- phys = <&usb_phy0>;
- phy-names = "usb";
- status = "disabled";
- };
-
- mmc1: mmc@d4280000 {
- compatible = "mrvl,pxav3-mmc";
- reg = <0xd4280000 0x120>;
- clocks = <&soc_clocks MMP2_CLK_SDH0>;
- clock-names = "io";
- interrupts = <39>;
- status = "disabled";
- };
-
- mmc2: mmc@d4280800 {
- compatible = "mrvl,pxav3-mmc";
- reg = <0xd4280800 0x120>;
- clocks = <&soc_clocks MMP2_CLK_SDH1>;
- clock-names = "io";
- interrupts = <52>;
- status = "disabled";
- };
-
- mmc3: mmc@d4281000 {
- compatible = "mrvl,pxav3-mmc";
- reg = <0xd4281000 0x120>;
- clocks = <&soc_clocks MMP2_CLK_SDH2>;
- clock-names = "io";
- interrupts = <53>;
- status = "disabled";
- };
-
- mmc4: mmc@d4281800 {
- compatible = "mrvl,pxav3-mmc";
- reg = <0xd4281800 0x120>;
- clocks = <&soc_clocks MMP2_CLK_SDH3>;
- clock-names = "io";
- interrupts = <54>;
- status = "disabled";
- };
-
- camera0: camera@d420a000 {
- compatible = "marvell,mmp2-ccic";
- reg = <0xd420a000 0x800>;
- interrupts = <42>;
- clocks = <&soc_clocks MMP2_CLK_CCIC0>;
- clock-names = "axi";
- #clock-cells = <0>;
- clock-output-names = "mclk";
- status = "disabled";
- };
-
- camera1: camera@d420a800 {
- compatible = "marvell,mmp2-ccic";
- reg = <0xd420a800 0x800>;
- interrupts = <30>;
- clocks = <&soc_clocks MMP2_CLK_CCIC1>;
- clock-names = "axi";
- #clock-cells = <0>;
- clock-output-names = "mclk";
- status = "disabled";
- };
- };
-
- apb@d4000000 { /* APB */
- compatible = "mrvl,apb-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xd4000000 0x00200000>;
- ranges;
-
- timer0: timer@d4014000 {
- compatible = "mrvl,mmp-timer";
- reg = <0xd4014000 0x100>;
- interrupts = <13>;
- clocks = <&soc_clocks MMP2_CLK_TIMER>;
- };
-
- uart1: uart@d4030000 {
- compatible = "mrvl,mmp-uart";
- reg = <0xd4030000 0x1000>;
- interrupts = <27>;
- clocks = <&soc_clocks MMP2_CLK_UART0>;
- resets = <&soc_clocks MMP2_CLK_UART0>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart2: uart@d4017000 {
- compatible = "mrvl,mmp-uart";
- reg = <0xd4017000 0x1000>;
- interrupts = <28>;
- clocks = <&soc_clocks MMP2_CLK_UART1>;
- resets = <&soc_clocks MMP2_CLK_UART1>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart3: uart@d4018000 {
- compatible = "mrvl,mmp-uart";
- reg = <0xd4018000 0x1000>;
- interrupts = <24>;
- clocks = <&soc_clocks MMP2_CLK_UART2>;
- resets = <&soc_clocks MMP2_CLK_UART2>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- uart4: uart@d4016000 {
- compatible = "mrvl,mmp-uart";
- reg = <0xd4016000 0x1000>;
- interrupts = <46>;
- clocks = <&soc_clocks MMP2_CLK_UART3>;
- resets = <&soc_clocks MMP2_CLK_UART3>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- gpio: gpio@d4019000 {
- compatible = "marvell,mmp2-gpio";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xd4019000 0x1000>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <49>;
- interrupt-names = "gpio_mux";
- clocks = <&soc_clocks MMP2_CLK_GPIO>;
- resets = <&soc_clocks MMP2_CLK_GPIO>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ranges;
-
- gcb0: gpio@d4019000 {
- reg = <0xd4019000 0x4>;
- };
-
- gcb1: gpio@d4019004 {
- reg = <0xd4019004 0x4>;
- };
-
- gcb2: gpio@d4019008 {
- reg = <0xd4019008 0x4>;
- };
-
- gcb3: gpio@d4019100 {
- reg = <0xd4019100 0x4>;
- };
-
- gcb4: gpio@d4019104 {
- reg = <0xd4019104 0x4>;
- };
-
- gcb5: gpio@d4019108 {
- reg = <0xd4019108 0x4>;
- };
- };
-
- twsi1: i2c@d4011000 {
- compatible = "mrvl,mmp-twsi";
- reg = <0xd4011000 0x1000>;
- interrupts = <7>;
- clocks = <&soc_clocks MMP2_CLK_TWSI0>;
- resets = <&soc_clocks MMP2_CLK_TWSI0>;
- #address-cells = <1>;
- #size-cells = <0>;
- mrvl,i2c-fast-mode;
- status = "disabled";
- };
-
- twsi2: i2c@d4031000 {
- compatible = "mrvl,mmp-twsi";
- reg = <0xd4031000 0x1000>;
- interrupt-parent = <&intcmux17>;
- interrupts = <0>;
- clocks = <&soc_clocks MMP2_CLK_TWSI1>;
- resets = <&soc_clocks MMP2_CLK_TWSI1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- twsi3: i2c@d4032000 {
- compatible = "mrvl,mmp-twsi";
- reg = <0xd4032000 0x1000>;
- interrupt-parent = <&intcmux17>;
- interrupts = <1>;
- clocks = <&soc_clocks MMP2_CLK_TWSI2>;
- resets = <&soc_clocks MMP2_CLK_TWSI2>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- twsi4: i2c@d4033000 {
- compatible = "mrvl,mmp-twsi";
- reg = <0xd4033000 0x1000>;
- interrupt-parent = <&intcmux17>;
- interrupts = <2>;
- clocks = <&soc_clocks MMP2_CLK_TWSI3>;
- resets = <&soc_clocks MMP2_CLK_TWSI3>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
-
- twsi5: i2c@d4033800 {
- compatible = "mrvl,mmp-twsi";
- reg = <0xd4033800 0x1000>;
- interrupt-parent = <&intcmux17>;
- interrupts = <3>;
- clocks = <&soc_clocks MMP2_CLK_TWSI4>;
- resets = <&soc_clocks MMP2_CLK_TWSI4>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- twsi6: i2c@d4034000 {
- compatible = "mrvl,mmp-twsi";
- reg = <0xd4034000 0x1000>;
- interrupt-parent = <&intcmux17>;
- interrupts = <4>;
- clocks = <&soc_clocks MMP2_CLK_TWSI5>;
- resets = <&soc_clocks MMP2_CLK_TWSI5>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- rtc: rtc@d4010000 {
- compatible = "mrvl,mmp-rtc";
- reg = <0xd4010000 0x1000>;
- interrupts = <1 0>;
- interrupt-names = "rtc 1Hz", "rtc alarm";
- interrupt-parent = <&intcmux5>;
- clocks = <&soc_clocks MMP2_CLK_RTC>;
- resets = <&soc_clocks MMP2_CLK_RTC>;
- status = "disabled";
- };
-
- ssp1: spi@d4035000 {
- compatible = "marvell,mmp2-ssp";
- reg = <0xd4035000 0x1000>;
- clocks = <&soc_clocks MMP2_CLK_SSP0>;
- interrupts = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ssp2: spi@d4036000 {
- compatible = "marvell,mmp2-ssp";
- reg = <0xd4036000 0x1000>;
- clocks = <&soc_clocks MMP2_CLK_SSP1>;
- interrupts = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ssp3: spi@d4037000 {
- compatible = "marvell,mmp2-ssp";
- reg = <0xd4037000 0x1000>;
- clocks = <&soc_clocks MMP2_CLK_SSP2>;
- interrupts = <20>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- ssp4: spi@d4039000 {
- compatible = "marvell,mmp2-ssp";
- reg = <0xd4039000 0x1000>;
- clocks = <&soc_clocks MMP2_CLK_SSP3>;
- interrupts = <21>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- soc_clocks: clocks {
- compatible = "marvell,mmp2-clock";
- reg = <0xd4050000 0x1000>,
- <0xd4282800 0x400>,
- <0xd4015000 0x1000>;
- reg-names = "mpmu", "apmu", "apbc";
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
- };
-};
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-24 00:39:41 +0000