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-rw-r--r--dts/src/arm/nspire.dtsi10
1 files changed, 8 insertions, 2 deletions
diff --git a/dts/src/arm/nspire.dtsi b/dts/src/arm/nspire.dtsi
index c35fd66677..d9a0fd7524 100644
--- a/dts/src/arm/nspire.dtsi
+++ b/dts/src/arm/nspire.dtsi
@@ -95,8 +95,14 @@
reg = <0xC0000000 0x1000>;
interrupts = <21>;
- clocks = <&apb_pclk>;
- clock-names = "apb_pclk";
+ /*
+ * We assume the same clock is fed to APB and CLCDCLK.
+ * There is some code to scale the clock down by a factor
+ * 48 for the display so likely the frequency to the
+ * display is 1MHz and the CLCDCLK is 48 MHz.
+ */
+ clocks = <&apb_pclk>, <&apb_pclk>;
+ clock-names = "clcdclk", "apb_pclk";
};
adc: adc@C4000000 {