diff options
Diffstat (limited to 'dts/src/arm/qcom-ipq4019.dtsi')
| -rw-r--r-- | dts/src/arm/qcom-ipq4019.dtsi | 90 |
1 files changed, 87 insertions, 3 deletions
diff --git a/dts/src/arm/qcom-ipq4019.dtsi b/dts/src/arm/qcom-ipq4019.dtsi index 74d8e2c8e4..7bf1da916f 100644 --- a/dts/src/arm/qcom-ipq4019.dtsi +++ b/dts/src/arm/qcom-ipq4019.dtsi @@ -190,7 +190,7 @@ reg = <0x1800000 0x60000>; }; - rng@22000 { + prng: rng@22000 { compatible = "qcom,prng"; reg = <0x22000 0x140>; clocks = <&gcc GCC_PRNG_AHB_CLK>; @@ -209,6 +209,16 @@ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; }; + vqmmc: regulator@1948000 { + compatible = "qcom,vqmmc-ipq4019-regulator"; + reg = <0x01948000 0x4>; + regulator-name = "vqmmc"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + status = "disabled"; + }; + sdhci: sdhci@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x11c>, <0x7824000 0x800>; @@ -300,7 +310,7 @@ status = "disabled"; }; - crypto@8e3a000 { + crypto: crypto@8e3a000 { compatible = "qcom,crypto-v5.1"; reg = <0x08e3a000 0x6000>; clocks = <&gcc GCC_CRYPTO_AHB_CLK>, @@ -386,7 +396,7 @@ dma-names = "rx", "tx"; }; - watchdog@b017000 { + watchdog: watchdog@b017000 { compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; reg = <0xb017000 0x40>; clocks = <&sleep_clk>; @@ -605,5 +615,79 @@ reg = <4>; }; }; + + usb3_ss_phy: ssphy@9a000 { + compatible = "qcom,usb-ss-ipq4019-phy"; + #phy-cells = <0>; + reg = <0x9a000 0x800>; + reg-names = "phy_base"; + resets = <&gcc USB3_UNIPHY_PHY_ARES>; + reset-names = "por_rst"; + status = "disabled"; + }; + + usb3_hs_phy: hsphy@a6000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa6000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb3: usb3@8af8800 { + compatible = "qcom,dwc3"; + reg = <0x8af8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB3_MASTER_CLK>, + <&gcc GCC_USB3_SLEEP_CLK>, + <&gcc GCC_USB3_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xf8000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + }; + }; + + usb2_hs_phy: hsphy@a8000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa8000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb2: usb2@60f8800 { + compatible = "qcom,dwc3"; + reg = <0x60f8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB2_MASTER_CLK>, + <&gcc GCC_USB2_SLEEP_CLK>, + <&gcc GCC_USB2_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@6000000 { + compatible = "snps,dwc3"; + reg = <0x6000000 0xf8000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + }; + }; }; }; |