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-rw-r--r--dts/src/arm/qcom-msm8226.dtsi528
1 files changed, 0 insertions, 528 deletions
diff --git a/dts/src/arm/qcom-msm8226.dtsi b/dts/src/arm/qcom-msm8226.dtsi
deleted file mode 100644
index 28eca15b57..0000000000
--- a/dts/src/arm/qcom-msm8226.dtsi
+++ /dev/null
@@ -1,528 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/qcom,gcc-msm8974.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/reset/qcom,gcc-msm8974.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
-
- chosen { };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0>;
- };
-
- clocks {
- xo_board: xo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- };
-
- sleep_clk: sleep_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- firmware {
- scm {
- compatible = "qcom,scm-msm8226", "qcom,scm";
- clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
- clock-names = "core", "bus", "iface";
- };
- };
-
- tcsr_mutex: hwlock {
- compatible = "qcom,tcsr-mutex";
- syscon = <&tcsr_mutex_block 0 0x80>;
-
- #hwlock-cells = <1>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- smem_region: smem@3000000 {
- reg = <0x3000000 0x100000>;
- no-map;
- };
- };
-
- smd {
- compatible = "qcom,smd";
-
- rpm {
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
- qcom,smd-edge = <15>;
-
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-msm8226";
- qcom,smd-channels = "rpm_requests";
-
- rpmpd: power-controller {
- compatible = "qcom,msm8226-rpmpd";
- #power-domain-cells = <1>;
- operating-points-v2 = <&rpmpd_opp_table>;
-
- rpmpd_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- rpmpd_opp_ret: opp1 {
- opp-level = <1>;
- };
- rpmpd_opp_svs_krait: opp2 {
- opp-level = <2>;
- };
- rpmpd_opp_svs_soc: opp3 {
- opp-level = <3>;
- };
- rpmpd_opp_nom: opp4 {
- opp-level = <4>;
- };
- rpmpd_opp_turbo: opp5 {
- opp-level = <5>;
- };
- rpmpd_opp_super_turbo: opp6 {
- opp-level = <6>;
- };
- };
- };
- };
- };
- };
-
- smem {
- compatible = "qcom,smem";
-
- memory-region = <&smem_region>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
-
- hwlocks = <&tcsr_mutex 3>;
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- intc: interrupt-controller@f9000000 {
- compatible = "qcom,msm-qgic2";
- reg = <0xf9000000 0x1000>,
- <0xf9002000 0x1000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
-
- apcs: syscon@f9011000 {
- compatible = "syscon";
- reg = <0xf9011000 0x1000>;
- };
-
- sdhc_1: sdhci@f9824900 {
- compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
- reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
- reg-names = "hc_mem", "core_mem";
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>,
- <&xo_board>;
- clock-names = "core", "iface", "xo";
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc1_default_state>;
- status = "disabled";
- };
-
- sdhc_2: sdhci@f98a4900 {
- compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
- reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>,
- <&xo_board>;
- clock-names = "core", "iface", "xo";
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_default_state>;
- status = "disabled";
- };
-
- sdhc_3: sdhci@f9864900 {
- compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
- reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
- reg-names = "hc_mem", "core_mem";
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC3_APPS_CLK>,
- <&gcc GCC_SDCC3_AHB_CLK>,
- <&xo_board>;
- clock-names = "core", "iface", "xo";
- pinctrl-names = "default";
- pinctrl-0 = <&sdhc3_default_state>;
- status = "disabled";
- };
-
- blsp1_uart1: serial@f991d000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0xf991d000 0x1000>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
- };
-
- blsp1_uart3: serial@f991f000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0xf991f000 0x1000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
- };
-
- blsp1_uart4: serial@f9920000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0xf9920000 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
- };
-
- blsp1_i2c1: i2c@f9923000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9923000 0x1000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- pinctrl-names = "default";
- pinctrl-0 = <&blsp1_i2c1_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- blsp1_i2c2: i2c@f9924000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9924000 0x1000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- pinctrl-names = "default";
- pinctrl-0 = <&blsp1_i2c2_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- blsp1_i2c3: i2c@f9925000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9925000 0x1000>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- pinctrl-names = "default";
- pinctrl-0 = <&blsp1_i2c3_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- blsp1_i2c4: i2c@f9926000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9926000 0x1000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- pinctrl-names = "default";
- pinctrl-0 = <&blsp1_i2c4_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- blsp1_i2c5: i2c@f9927000 {
- status = "disabled";
- compatible = "qcom,i2c-qup-v2.1.1";
- reg = <0xf9927000 0x1000>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- pinctrl-names = "default";
- pinctrl-0 = <&blsp1_i2c5_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usb: usb@f9a55000 {
- compatible = "qcom,ci-hdrc";
- reg = <0xf9a55000 0x200>,
- <0xf9a55200 0x200>;
- interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_USB_HS_AHB_CLK>,
- <&gcc GCC_USB_HS_SYSTEM_CLK>;
- clock-names = "iface", "core";
- assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
- assigned-clock-rates = <75000000>;
- resets = <&gcc GCC_USB_HS_BCR>;
- reset-names = "core";
- phy_type = "ulpi";
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- adp-disable;
- ahb-burst-config = <0>;
- phy-names = "usb-phy";
- phys = <&usb_hs_phy>;
- status = "disabled";
- #reset-cells = <1>;
-
- ulpi {
- usb_hs_phy: phy {
- compatible = "qcom,usb-hs-phy-msm8226",
- "qcom,usb-hs-phy";
- #phy-cells = <0>;
- clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
- clock-names = "ref", "sleep";
- resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
- reset-names = "phy", "por";
- qcom,init-seq = /bits/ 8 <0x0 0x44
- 0x1 0x68 0x2 0x24 0x3 0x13>;
- };
- };
- };
-
- gcc: clock-controller@fc400000 {
- compatible = "qcom,gcc-msm8226";
- reg = <0xfc400000 0x4000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-
- tlmm: pinctrl@fd510000 {
- compatible = "qcom,msm8226-pinctrl";
- reg = <0xfd510000 0x4000>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 117>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
-
- blsp1_i2c1_pins: blsp1-i2c1 {
- pins = "gpio2", "gpio3";
- function = "blsp_i2c1";
- drive-strength = <2>;
- bias-disable;
- };
-
- blsp1_i2c2_pins: blsp1-i2c2 {
- pins = "gpio6", "gpio7";
- function = "blsp_i2c2";
- drive-strength = <2>;
- bias-disable;
- };
-
- blsp1_i2c3_pins: blsp1-i2c3 {
- pins = "gpio10", "gpio11";
- function = "blsp_i2c3";
- drive-strength = <2>;
- bias-disable;
- };
-
- blsp1_i2c4_pins: blsp1-i2c4 {
- pins = "gpio14", "gpio15";
- function = "blsp_i2c4";
- drive-strength = <2>;
- bias-disable;
- };
-
- blsp1_i2c5_pins: blsp1-i2c5 {
- pins = "gpio18", "gpio19";
- function = "blsp_i2c5";
- drive-strength = <2>;
- bias-disable;
- };
-
- sdhc1_default_state: sdhc1-default-state {
- clk {
- pins = "sdc1_clk";
- drive-strength = <10>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc1_cmd", "sdc1_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdhc2_default_state: sdhc2-default-state {
- clk {
- pins = "sdc2_clk";
- drive-strength = <10>;
- bias-disable;
- };
-
- cmd-data {
- pins = "sdc2_cmd", "sdc2_data";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- sdhc3_default_state: sdhc3-default-state {
- clk {
- pins = "gpio44";
- function = "sdc3";
- drive-strength = <8>;
- bias-disable;
- };
-
- cmd {
- pins = "gpio43";
- function = "sdc3";
- drive-strength = <8>;
- bias-pull-up;
- };
-
- data {
- pins = "gpio39", "gpio40", "gpio41", "gpio42";
- function = "sdc3";
- drive-strength = <8>;
- bias-pull-up;
- };
- };
- };
-
- restart@fc4ab000 {
- compatible = "qcom,pshold";
- reg = <0xfc4ab000 0x4>;
- };
-
- spmi_bus: spmi@fc4cf000 {
- compatible = "qcom,spmi-pmic-arb";
- reg-names = "core", "intr", "cnfg";
- reg = <0xfc4cf000 0x1000>,
- <0xfc4cb000 0x1000>,
- <0xfc4ca000 0x1000>;
- interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- qcom,ee = <0>;
- qcom,channel = <0>;
- #address-cells = <2>;
- #size-cells = <0>;
- interrupt-controller;
- #interrupt-cells = <4>;
- };
-
- rng@f9bff000 {
- compatible = "qcom,prng";
- reg = <0xf9bff000 0x200>;
- clocks = <&gcc GCC_PRNG_AHB_CLK>;
- clock-names = "core";
- };
-
- timer@f9020000 {
- compatible = "arm,armv7-timer-mem";
- reg = <0xf9020000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- frame@f9021000 {
- frame-number = <0>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9021000 0x1000>,
- <0xf9022000 0x1000>;
- };
-
- frame@f9023000 {
- frame-number = <1>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9023000 0x1000>;
- status = "disabled";
- };
-
- frame@f9024000 {
- frame-number = <2>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9024000 0x1000>;
- status = "disabled";
- };
-
- frame@f9025000 {
- frame-number = <3>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9025000 0x1000>;
- status = "disabled";
- };
-
- frame@f9026000 {
- frame-number = <4>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9026000 0x1000>;
- status = "disabled";
- };
-
- frame@f9027000 {
- frame-number = <5>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9027000 0x1000>;
- status = "disabled";
- };
-
- frame@f9028000 {
- frame-number = <6>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xf9028000 0x1000>;
- status = "disabled";
- };
- };
-
- rpm_msg_ram: memory@fc428000 {
- compatible = "qcom,rpm-msg-ram";
- reg = <0xfc428000 0x4000>;
- };
-
- tcsr_mutex_block: syscon@fd484000 {
- compatible = "syscon";
- reg = <0xfd484000 0x2000>;
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 2
- (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3
- (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 4
- (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1
- (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
- };
-};
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