diff options
Diffstat (limited to 'dts/src/arm/qcom-sdx65.dtsi')
-rw-r--r-- | dts/src/arm/qcom-sdx65.dtsi | 413 |
1 files changed, 0 insertions, 413 deletions
diff --git a/dts/src/arm/qcom-sdx65.dtsi b/dts/src/arm/qcom-sdx65.dtsi deleted file mode 100644 index df6f9d6288..0000000000 --- a/dts/src/arm/qcom-sdx65.dtsi +++ /dev/null @@ -1,413 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * SDX65 SoC device tree source - * - * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. - * - */ - -#include <dt-bindings/clock/qcom,gcc-sdx65.h> -#include <dt-bindings/clock/qcom,rpmh.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/qcom-rpmpd.h> -#include <dt-bindings/soc/qcom,rpmh-rsc.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; - interrupt-parent = <&intc>; - - memory { - device_type = "memory"; - reg = <0 0>; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - clock-frequency = <76800000>; - clock-output-names = "xo_board"; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - #clock-cells = <0>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved_memory: reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tz_heap_mem: memory@8fcad000 { - no-map; - reg = <0x8fcad000 0x40000>; - }; - - secdata_mem: memory@8fcfd000 { - no-map; - reg = <0x8fcfd000 0x1000>; - }; - - hyp_mem: memory@8fd00000 { - no-map; - reg = <0x8fd00000 0x80000>; - }; - - access_control_mem: memory@8fd80000 { - no-map; - reg = <0x8fd80000 0x80000>; - }; - - aop_mem: memory@8fe00000 { - no-map; - reg = <0x8fe00000 0x20000>; - }; - - smem_mem: memory@8fe20000 { - no-map; - reg = <0x8fe20000 0xc0000>; - }; - - cmd_db: reserved-memory@8fee0000 { - compatible = "qcom,cmd-db"; - reg = <0x8fee0000 0x20000>; - no-map; - }; - - tz_mem: memory@8ff00000 { - no-map; - reg = <0x8ff00000 0x100000>; - }; - - tz_apps_mem: memory@90000000 { - no-map; - reg = <0x90000000 0x500000>; - }; - - llcc_tcm_mem: memory@15800000 { - no-map; - reg = <0x15800000 0x800000>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdx65"; - reg = <0x00100000 0x001f7400>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - blsp1_uart3: serial@831000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x00831000 0x200>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01f40000 0x40000>; - #hwlock-cells = <1>; - }; - - sdhc_1: sdhci@8804000 { - compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x08804000 0x1000>; - reg-names = "hc_mem"; - interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - spmi_bus: qcom,spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0xc440000 0xd00>, - <0xc600000 0x2000000>, - <0xe600000 0x100000>, - <0xe700000 0xa0000>, - <0xc40a000 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "periph_irq"; - interrupt-controller; - #interrupt-cells = <4>; - #address-cells = <2>; - #size-cells = <0>; - cell-index = <0>; - qcom,channel = <0>; - qcom,ee = <0>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sdx65-tlmm"; - reg = <0xf100000 0x300000>; - interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 109>; - interrupt-controller; - interrupt-parent = <&intc>; - #interrupt-cells = <2>; - }; - - pdc: interrupt-controller@b210000 { - compatible = "qcom,sdx65-pdc", "qcom,pdc"; - reg = <0xb210000 0x10000>; - qcom,pdc-ranges = <0 147 52>, <52 266 32>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; - reg = <0x15000000 0x40000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; - }; - - intc: interrupt-controller@17800000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - interrupt-parent = <&intc>; - #interrupt-cells = <3>; - reg = <0x17800000 0x1000>, - <0x17802000 0x1000>; - }; - - a7pll: clock@17808000 { - compatible = "qcom,sdx55-a7pll"; - reg = <0x17808000 0x1000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "bi_tcxo"; - #clock-cells = <0>; - }; - - apcs: mailbox@17810000 { - compatible = "qcom,sdx55-apcs-gcc", "syscon"; - reg = <0x17810000 0x2000>; - #mbox-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; - clock-names = "ref", "pll", "aux"; - #clock-cells = <0>; - }; - - timer@17820000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17820000 0x1000>; - clock-frequency = <19200000>; - - frame@17821000 { - frame-number = <0>; - interrupts = <GIC_SPI 7 0x4>, - <GIC_SPI 6 0x4>; - reg = <0x17821000 0x1000>, - <0x17822000 0x1000>; - }; - - frame@17823000 { - frame-number = <1>; - interrupts = <GIC_SPI 8 0x4>; - reg = <0x17823000 0x1000>; - status = "disabled"; - }; - - frame@17824000 { - frame-number = <2>; - interrupts = <GIC_SPI 9 0x4>; - reg = <0x17824000 0x1000>; - status = "disabled"; - }; - - frame@17825000 { - frame-number = <3>; - interrupts = <GIC_SPI 10 0x4>; - reg = <0x17825000 0x1000>; - status = "disabled"; - }; - - frame@17826000 { - frame-number = <4>; - interrupts = <GIC_SPI 11 0x4>; - reg = <0x17826000 0x1000>; - status = "disabled"; - }; - - frame@17827000 { - frame-number = <5>; - interrupts = <GIC_SPI 12 0x4>; - reg = <0x17827000 0x1000>; - status = "disabled"; - }; - - frame@17828000 { - frame-number = <6>; - interrupts = <GIC_SPI 13 0x4>; - reg = <0x17828000 0x1000>; - status = "disabled"; - }; - - frame@17829000 { - frame-number = <7>; - interrupts = <GIC_SPI 14 0x4>; - reg = <0x17829000 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@17830000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x17830000 0x10000>, - <0x17840000 0x10000>; - reg-names = "drv-0", "drv-1"; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <1>; - qcom,tcs-config = <ACTIVE_TCS 2>, - <SLEEP_TCS 2>, - <WAKE_TCS 2>, - <CONTROL_TCS 1>; - - rpmhcc: clock-controller { - compatible = "qcom,sdx65-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sdx65-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS>; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM>; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; - }; - }; - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 12 0xf08>, - <1 10 0xf08>, - <1 11 0xf08>; - clock-frequency = <19200000>; - }; -}; |