diff options
Diffstat (limited to 'dts/src/arm/r9a06g032-rzn1d400-db.dts')
| -rw-r--r-- | dts/src/arm/r9a06g032-rzn1d400-db.dts | 152 |
1 files changed, 0 insertions, 152 deletions
diff --git a/dts/src/arm/r9a06g032-rzn1d400-db.dts b/dts/src/arm/r9a06g032-rzn1d400-db.dts deleted file mode 100644 index 4bf813335e..0000000000 --- a/dts/src/arm/r9a06g032-rzn1d400-db.dts +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZN1D-DB Board - * - * Copyright (C) 2018 Renesas Electronics Europe Limited - * - */ - -/dts-v1/; - -#include <dt-bindings/pinctrl/rzn1-pinctrl.h> -#include <dt-bindings/net/pcs-rzn1-miic.h> - -#include "r9a06g032.dtsi" - -/ { - model = "RZN1D-DB Board"; - compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &uart0; - }; -}; - -ð_miic { - status = "okay"; - renesas,miic-switch-portin = <MIIC_GMAC2_PORT>; -}; - -&gmac2 { - status = "okay"; - phy-mode = "gmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&mii_conv4 { - renesas,miic-input = <MIIC_SWITCH_PORTB>; - status = "okay"; -}; - -&mii_conv5 { - renesas,miic-input = <MIIC_SWITCH_PORTA>; - status = "okay"; -}; - -&pinctrl{ - pins_eth3: pins_eth3 { - pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>; - drive-strength = <6>; - bias-disable; - }; - - pins_eth4: pins_eth4 { - pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, - <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>; - drive-strength = <6>; - bias-disable; - }; - - pins_mdio1: pins_mdio1 { - pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>, - <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>; - }; -}; - -&rtc0 { - status = "okay"; -}; - -&switch { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; - - dsa,member = <0 0>; - - mdio { - clock-frequency = <2500000>; - - #address-cells = <1>; - #size-cells = <0>; - - switch0phy4: ethernet-phy@4 { - reg = <4>; - micrel,led-mode = <1>; - }; - - switch0phy5: ethernet-phy@5 { - reg = <5>; - micrel,led-mode = <1>; - }; - }; -}; - -&switch_port0 { - label = "lan0"; - phy-mode = "mii"; - phy-handle = <&switch0phy5>; - status = "okay"; -}; - -&switch_port1 { - label = "lan1"; - phy-mode = "mii"; - phy-handle = <&switch0phy4>; - status = "okay"; -}; - -&switch_port4 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&wdt0 { - timeout-sec = <60>; - status = "okay"; -}; |