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Diffstat (limited to 'dts/src/arm/socfpga_arria10.dtsi')
-rw-r--r--dts/src/arm/socfpga_arria10.dtsi40
1 files changed, 29 insertions, 11 deletions
diff --git a/dts/src/arm/socfpga_arria10.dtsi b/dts/src/arm/socfpga_arria10.dtsi
index 17e81dc921..94000cbe57 100644
--- a/dts/src/arm/socfpga_arria10.dtsi
+++ b/dts/src/arm/socfpga_arria10.dtsi
@@ -22,11 +22,6 @@
#address-cells = <1>;
#size-cells = <1>;
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -572,12 +567,6 @@
reg = <0xffcfb100 0x80>;
};
- sdramedac {
- compatible = "altr,sdram-edac-a10";
- altr,sdr-syscon = <&sdr>;
- interrupts = <0 2 4>, <0 0 4>;
- };
-
L2: l2-cache@fffff000 {
compatible = "arm,pl310-cache";
reg = <0xfffff000 0x1000>;
@@ -610,16 +599,45 @@
#size-cells = <1>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
ranges;
+ sdramedac {
+ compatible = "altr,sdram-edac-a10";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <49 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
+ <32 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8c3000 {
compatible = "altr,socfpga-a10-ocram-ecc";
reg = <0xff8c3000 0x400>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
+ <33 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emac0-rx-ecc@ff8c0800 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0800 0x400>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+ <36 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ emac0-tx-ecc@ff8c0c00 {
+ compatible = "altr,socfpga-eth-mac-ecc";
+ reg = <0xff8c0c00 0x400>;
+ altr,ecc-parent = <&gmac0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+ <37 IRQ_TYPE_LEVEL_HIGH>;
};
};