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Diffstat (limited to 'dts/src/arm/stih418-clock.dtsi')
-rw-r--r--dts/src/arm/stih418-clock.dtsi6
1 files changed, 3 insertions, 3 deletions
diff --git a/dts/src/arm/stih418-clock.dtsi b/dts/src/arm/stih418-clock.dtsi
index 0ab23daa28..ae6d9978ea 100644
--- a/dts/src/arm/stih418-clock.dtsi
+++ b/dts/src/arm/stih418-clock.dtsi
@@ -44,7 +44,7 @@
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+ compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -137,7 +137,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -146,7 +146,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;