diff options
Diffstat (limited to 'dts/src/arm/stm32mp15xx-dhcom-som.dtsi')
| -rw-r--r-- | dts/src/arm/stm32mp15xx-dhcom-som.dtsi | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/dts/src/arm/stm32mp15xx-dhcom-som.dtsi b/dts/src/arm/stm32mp15xx-dhcom-som.dtsi index 83e2c87713..238a611192 100644 --- a/dts/src/arm/stm32mp15xx-dhcom-som.dtsi +++ b/dts/src/arm/stm32mp15xx-dhcom-som.dtsi @@ -118,13 +118,12 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; mdio0 { #address-cells = <1>; @@ -136,7 +135,7 @@ /* LAN8710Ai */ compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc ETHCK_K>; + clocks = <&rcc CK_MCO2>; reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; reset-assert-us = <500>; reset-deassert-us = <500>; @@ -446,6 +445,21 @@ }; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + &rng1 { status = "okay"; }; |