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-rw-r--r--dts/src/arm/sun7i-a20.dtsi38
1 files changed, 34 insertions, 4 deletions
diff --git a/dts/src/arm/sun7i-a20.dtsi b/dts/src/arm/sun7i-a20.dtsi
index e529e4f..9c52712 100644
--- a/dts/src/arm/sun7i-a20.dtsi
+++ b/dts/src/arm/sun7i-a20.dtsi
@@ -122,6 +122,19 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
+ clocks = <&ccu CLK_CPU>;
+ clock-latency = <244144>; /* 8 32k periods */
+ operating-points = <
+ /* kHz uV */
+ 960000 1400000
+ 912000 1400000
+ 864000 1300000
+ 720000 1200000
+ 528000 1100000
+ 312000 1000000
+ 144000 1000000
+ >;
+ #cooling-cells = <2>;
};
};
@@ -239,8 +252,9 @@
#size-cells = <1>;
ranges;
- sram-controller@1c00000 {
- compatible = "allwinner,sun4i-a10-sram-controller";
+ system-control@1c00000 {
+ compatible = "allwinner,sun7i-a20-system-control",
+ "allwinner,sun4i-a10-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
@@ -254,7 +268,8 @@
ranges = <0 0x00000000 0xc000>;
emac_sram: sram-section@8000 {
- compatible = "allwinner,sun4i-a10-sram-a3-a4";
+ compatible = "allwinner,sun7i-a20-sram-a3-a4",
+ "allwinner,sun4i-a10-sram-a3-a4";
reg = <0x8000 0x4000>;
status = "disabled";
};
@@ -268,11 +283,26 @@
ranges = <0 0x00010000 0x1000>;
otg_sram: sram-section@0 {
- compatible = "allwinner,sun4i-a10-sram-d";
+ compatible = "allwinner,sun7i-a20-sram-d",
+ "allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
+
+ sram_c: sram@1d00000 {
+ compatible = "mmio-sram";
+ reg = <0x01d00000 0xd0000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01d00000 0xd0000>;
+
+ ve_sram: sram-section@0 {
+ compatible = "allwinner,sun7i-a20-sram-c1",
+ "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x80000>;
+ };
+ };
};
nmi_intc: interrupt-controller@1c00030 {