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Diffstat (limited to 'dts/src/arm64/altera/socfpga_stratix10_swvp.dts')
-rw-r--r--dts/src/arm64/altera/socfpga_stratix10_swvp.dts115
1 files changed, 115 insertions, 0 deletions
diff --git a/dts/src/arm64/altera/socfpga_stratix10_swvp.dts b/dts/src/arm64/altera/socfpga_stratix10_swvp.dts
new file mode 100644
index 0000000000..0d837d3e65
--- /dev/null
+++ b/dts/src/arm64/altera/socfpga_stratix10_swvp.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022, Intel Corporation
+ */
+
+#include "socfpga_stratix10.dtsi"
+
+/ {
+ model = "SOCFPGA Stratix 10 SWVP";
+ compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+
+ timer0 = &timer0;
+ timer1 = &timer1;
+ timer2 = &timer2;
+ timer3 = &timer3;
+
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ linux,initrd-start = <0x10000000>;
+ linux,initrd-end = <0x125c8324>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&cpu0 {
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
+};
+
+&cpu1 {
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
+};
+
+&cpu2 {
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
+};
+
+&cpu3 {
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x0000fff8>;
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>;
+ snps,max-mtu = <0x0>;
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>;
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>;
+};
+
+&mmc {
+ status = "okay";
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ broken-cd;
+ bus-width = <4>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
+ status = "okay";
+};
+
+&usb1 {
+ clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
+ status = "okay";
+};
+
+&rst {
+ altr,modrst-offset = <0x20>;
+};
+
+&sysmgr {
+ reg = <0xffd12000 0x1000>;
+ interrupts = <0x0 0x10 0x4>;
+ cpu1-start-addr = <0xffd06230>;
+};