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Diffstat (limited to 'dts/src/arm64/exynos/exynos7.dtsi')
-rw-r--r--dts/src/arm64/exynos/exynos7.dtsi37
1 files changed, 36 insertions, 1 deletions
diff --git a/dts/src/arm64/exynos/exynos7.dtsi b/dts/src/arm64/exynos/exynos7.dtsi
index 10244e59d5..c73a597ca6 100644
--- a/dts/src/arm64/exynos/exynos7.dtsi
+++ b/dts/src/arm64/exynos/exynos7.dtsi
@@ -54,6 +54,13 @@
compatible = "arm,cortex-a57";
reg = <0x0>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu_atlas1: cpu@1 {
@@ -61,6 +68,13 @@
compatible = "arm,cortex-a57";
reg = <0x1>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu_atlas2: cpu@2 {
@@ -68,6 +82,13 @@
compatible = "arm,cortex-a57";
reg = <0x2>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
};
cpu_atlas3: cpu@3 {
@@ -75,6 +96,20 @@
compatible = "arm,cortex-a57";
reg = <0x3>;
enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&atlas_l2>;
+ };
+
+ atlas_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
};
};
@@ -102,7 +137,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0x11001000 0x1000>,
- <0x11002000 0x1000>,
+ <0x11002000 0x2000>,
<0x11004000 0x2000>,
<0x11006000 0x2000>;
};