diff options
Diffstat (limited to 'dts/src/arm64/exynos/exynos7.dtsi')
| -rw-r--r-- | dts/src/arm64/exynos/exynos7.dtsi | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/dts/src/arm64/exynos/exynos7.dtsi b/dts/src/arm64/exynos/exynos7.dtsi index 93108f1a90..ca663dfe51 100644 --- a/dts/src/arm64/exynos/exynos7.dtsi +++ b/dts/src/arm64/exynos/exynos7.dtsi @@ -27,6 +27,7 @@ pinctrl6 = &pinctrl_fsys0; pinctrl7 = &pinctrl_fsys1; pinctrl8 = &pinctrl_bus1; + tmuctrl0 = &tmuctrl_0; }; cpus { @@ -95,6 +96,35 @@ <0x11006000 0x2000>; }; + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma0: pdma@10E10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10E10000 0x1000>; + interrupts = <0 225 0>; + clocks = <&clock_fsys0 ACLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@10EB0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10EB0000 0x1000>; + interrupts = <0 226 0>; + clocks = <&clock_fsys0 ACLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + clock_topc: clock-controller@10570000 { compatible = "samsung,exynos7-clock-topc"; reg = <0x10570000 0x10000>; @@ -538,6 +568,25 @@ clocks = <&clock_peric0 PCLK_PWM>; clock-names = "timers"; }; + + tmuctrl_0: tmu@10060000 { + compatible = "samsung,exynos7-tmu"; + reg = <0x10060000 0x200>; + interrupts = <0 108 0>; + clocks = <&clock_peris PCLK_TMU>, + <&clock_peris SCLK_TMU>; + clock-names = "tmu_apbif", "tmu_sclk"; + #include "exynos7-tmu-sensor-conf.dtsi" + }; + + thermal-zones { + atlas_thermal: cluster0-thermal { + polling-delay-passive = <0>; /* milliseconds */ + polling-delay = <0>; /* milliseconds */ + thermal-sensors = <&tmuctrl_0>; + #include "exynos7-trip-points.dtsi" + }; + }; }; }; |