diff options
Diffstat (limited to 'dts/src/arm64/freescale/imx8mm-venice-gw7901.dts')
| -rw-r--r-- | dts/src/arm64/freescale/imx8mm-venice-gw7901.dts | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts b/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts index 21c546c462..7e72310462 100644 --- a/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts +++ b/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts @@ -8,6 +8,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mm.dtsi" @@ -179,6 +180,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; @@ -286,6 +293,29 @@ }; }; +&gpio1 { + gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", + "", "uart1_rs232#", "dig1_in", "dig1_out", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "uart3_rs232#", "uart3_rs422#", + "uart3_rs485#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", + "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &gpu_2d { status = "disabled"; }; @@ -644,6 +674,28 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + &pgc_gpu { status = "disabled"; }; @@ -820,6 +872,13 @@ >; }; + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 |