diff options
Diffstat (limited to 'dts/src/arm64/freescale/imx8mn.dtsi')
-rw-r--r-- | dts/src/arm64/freescale/imx8mn.dtsi | 334 |
1 files changed, 304 insertions, 30 deletions
diff --git a/dts/src/arm64/freescale/imx8mn.dtsi b/dts/src/arm64/freescale/imx8mn.dtsi index da6c942fb7..136e75c512 100644 --- a/dts/src/arm64/freescale/imx8mn.dtsi +++ b/dts/src/arm64/freescale/imx8mn.dtsi @@ -4,6 +4,8 @@ */ #include <dt-bindings/clock/imx8mn-clock.h> +#include <dt-bindings/power/imx8mn-power.h> +#include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -63,6 +65,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; @@ -78,6 +86,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -91,6 +105,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -104,6 +124,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -112,6 +138,11 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; @@ -182,7 +213,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -239,7 +270,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mn-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -263,8 +294,9 @@ ranges; sai2: sai@30020000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI2_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -277,8 +309,9 @@ }; sai3: sai@30030000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -291,8 +324,9 @@ }; sai5: sai@30050000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -307,8 +341,9 @@ }; sai6: sai@30060000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI6_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -336,6 +371,7 @@ "pll8k", "pll11k", "clkext3"; dmas = <&sdma2 24 25 0x80000000>; dma-names = "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -364,8 +400,9 @@ }; sai7: sai@300b0000 { - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>; + #sound-dai-cells = <0>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SAI7_IPG>, <&clk IMX8MN_CLK_DUMMY>, @@ -392,7 +429,7 @@ "ctx2_rx", "ctx2_tx", "ctx3_rx", "ctx3_tx"; firmware-name = "imx/easrc/easrc-imx8mn.bin"; - fsl,asrc-rate = <8000>; + fsl,asrc-rate = <8000>; fsl,asrc-format = <2>; status = "disabled"; }; @@ -467,6 +504,8 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -521,7 +560,7 @@ reg = <0x30330000 0x10000>; }; - gpr: iomuxc-gpr@30340000 { + gpr: syscon@30340000 { compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -533,23 +572,40 @@ #address-cells = <1>; #size-cells = <1>; - imx8mn_uid: unique-id@410 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -581,6 +637,8 @@ clk: clock-controller@30380000 { compatible = "fsl,imx8mn-ccm"; reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; @@ -612,6 +670,51 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mn-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_hsiomix: power-domain@0 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; + clocks = <&clk IMX8MN_CLK_USB_BUS>; + }; + + pgc_otg1: power-domain@1 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_OTG1>; + }; + + pgc_gpumix: power-domain@2 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + }; + + pgc_dispmix: power-domain@3 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + }; + + pgc_mipi: power-domain@4 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_MIPI>; + power-domains = <&pgc_dispmix>; + }; + }; + }; }; aips2: bus@30400000 { @@ -628,7 +731,7 @@ clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, <&clk IMX8MN_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -639,7 +742,7 @@ clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, <&clk IMX8MN_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -650,7 +753,7 @@ clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, <&clk IMX8MN_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -661,7 +764,7 @@ clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, <&clk IMX8MN_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -780,6 +883,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -856,7 +960,7 @@ }; usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -864,13 +968,13 @@ <&clk IMX8MN_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -878,13 +982,13 @@ <&clk IMX8MN_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b60000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -892,7 +996,7 @@ <&clk IMX8MN_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -948,7 +1052,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; @@ -962,8 +1065,151 @@ #size-cells = <1>; ranges; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi@32e10000 { + compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + + isi: isi@32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x32e20000 0x8000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&disp_blk_ctrl>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + isi_in: endpoint { + remote-endpoint = <&mipi_csi_out>; + }; + }; + }; + }; + + disp_blk_ctrl: blk-ctrl@32e28000 { + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_dispmix>, <&pgc_mipi>, + <&pgc_mipi>; + power-domain-names = "bus", "isi", + "lcdif", "mipi-dsi", + "mipi-csi"; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; + clock-names = "disp_axi", "disp_apb", + "disp_axi_root", "disp_apb_root", + "lcdif-axi", "lcdif-apb", "lcdif-pix", + "dsi-pclk", "dsi-ref", + "csi-aclk", "csi-pclk"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_DISP_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, + <&clk IMX8MN_CLK_24M>, + <&clk IMX8MN_VIDEO_PLL1_OUT>, + <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <266000000>, + <24000000>, + <594000000>, + <500000000>, + <200000000>; + #power-domain-cells = <1>; + }; + + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_out: endpoint { + remote-endpoint = <&isi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; @@ -972,11 +1218,13 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x32e40200 0x200>; }; @@ -989,7 +1237,6 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; @@ -998,7 +1245,7 @@ gpmi: nand-controller@33002000 { compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -1011,6 +1258,32 @@ status = "disabled"; }; + gpu: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER>; + clock-names = "reg", "bus", "core", "shader"; + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, + <&clk IMX8MN_CLK_GPU_SHADER>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, + <400000000>, + <800000000>, + <400000000>, + <1200000000>; + power-domains = <&pgc_gpumix>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -1044,5 +1317,6 @@ assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg1>; }; }; |