diff options
Diffstat (limited to 'dts/src/arm64/freescale')
50 files changed, 5792 insertions, 154 deletions
diff --git a/dts/src/arm64/freescale/fsl-ls1028a-qds-13bb.dts b/dts/src/arm64/freescale/fsl-ls1028a-qds-13bb.dts new file mode 100644 index 0000000000..f748a2c12a --- /dev/null +++ b/dts/src/arm64/freescale/fsl-ls1028a-qds-13bb.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 13bb + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. + * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot2_qxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qxgmii0>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qxgmii1>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qxgmii2>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qxgmii3>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@4 { + target = <&mscc_felix>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-qds-65bb.dts b/dts/src/arm64/freescale/fsl-ls1028a-qds-65bb.dts new file mode 100644 index 0000000000..8ffb707a15 --- /dev/null +++ b/dts/src/arm64/freescale/fsl-ls1028a-qds-65bb.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 69xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "2500base-x"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@4 { + target = <&mscc_felix>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-qds-7777.dts b/dts/src/arm64/freescale/fsl-ls1028a-qds-7777.dts new file mode 100644 index 0000000000..eb6a1e674f --- /dev/null +++ b/dts/src/arm64/freescale/fsl-ls1028a-qds-7777.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 7777 + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing + * disabled, plugged in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot1_sxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + fragment@1 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sxgmii0>; + phy-mode = "2500base-x"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sxgmii1>; + phy-mode = "2500base-x"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sxgmii2>; + phy-mode = "2500base-x"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sxgmii3>; + phy-mode = "2500base-x"; + }; + }; + }; + + fragment@2 { + target = <&mscc_felix>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-qds-85bb.dts b/dts/src/arm64/freescale/fsl-ls1028a-qds-85bb.dts new file mode 100644 index 0000000000..8e90c3088b --- /dev/null +++ b/dts/src/arm64/freescale/fsl-ls1028a-qds-85bb.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85bb + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board with lane B rework. + * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + slot1_sgmii: ethernet-phy@1c { + /* 1st port on VSC8234 */ + reg = <0x1c>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + + __overlay__ { + phy-handle = <&slot1_sgmii>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mdio_slot2>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix_ports>; + + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@4 { + target = <&mscc_felix>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-qds-899b.dts b/dts/src/arm64/freescale/fsl-ls1028a-qds-899b.dts new file mode 100644 index 0000000000..5d0a094e6c --- /dev/null +++ b/dts/src/arm64/freescale/fsl-ls1028a-qds-899b.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + + fragment@1 { + target = <&enetc_port0>; + __overlay__ { + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; + }; + }; + + fragment@2 { + target = <&mscc_felix_ports>; + __overlay__ { + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@3 { + target = <&mscc_felix>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-qds-9999.dts b/dts/src/arm64/freescale/fsl-ls1028a-qds-9999.dts new file mode 100644 index 0000000000..1ef743c48e --- /dev/null +++ b/dts/src/arm64/freescale/fsl-ls1028a-qds-9999.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree fragment for LS1028A QDS board, serdes 85xx + * + * Copyright 2019-2021 NXP + * + * Requires a LS1028A QDS board without lane B rework. + * Requires a SCH-24801 card in slot 1. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target = <&mdio_slot1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; + }; + + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; + }; + + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + }; + + fragment@1 { + target = <&mscc_felix_ports>; + __overlay__ { + port@0 { + status = "okay"; + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sgmii3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + }; + }; + + fragment@2 { + target = <&mscc_felix>; + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-qds.dts b/dts/src/arm64/freescale/fsl-ls1028a-qds.dts index 6e2a1da662..177bc1405f 100644 --- a/dts/src/arm64/freescale/fsl-ls1028a-qds.dts +++ b/dts/src/arm64/freescale/fsl-ls1028a-qds.dts @@ -25,7 +25,7 @@ serial1 = &duart1; mmc0 = &esdhc; mmc1 = &esdhc1; - rtc1 = &ftm_alarm0; + rtc1 = &ftm_alarm1; }; chosen { @@ -211,6 +211,16 @@ status = "okay"; }; +&enetc_port1 { + phy-handle = <&qds_phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc_port2 { + status = "okay"; +}; + &esdhc { status = "okay"; }; @@ -234,6 +244,10 @@ }; }; +&ftm_alarm1 { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -272,11 +286,6 @@ vcc-supply = <&sb_3v3>; }; - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - eeprom@56 { compatible = "atmel,24c512"; reg = <0x56>; @@ -318,16 +327,28 @@ }; -&enetc_port1 { - phy-handle = <&qds_phy1>; - phy-mode = "rgmii-id"; +&i2c1 { status = "okay"; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; }; &lpuart0 { status = "okay"; }; +&lpuart1 { + status = "okay"; +}; + +&mscc_felix_port4 { + ethernet = <&enetc_port2>; + status = "okay"; +}; + &sai1 { status = "okay"; }; diff --git a/dts/src/arm64/freescale/fsl-ls1028a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1028a-rdb.dts index 7719f44bca..68c31cb8ee 100644 --- a/dts/src/arm64/freescale/fsl-ls1028a-rdb.dts +++ b/dts/src/arm64/freescale/fsl-ls1028a-rdb.dts @@ -2,7 +2,7 @@ /* * Device Tree file for NXP LS1028A RDB Board. * - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * * Harninder Rai <harninder.rai@nxp.com> * @@ -21,7 +21,14 @@ serial1 = &duart1; mmc0 = &esdhc; mmc1 = &esdhc1; - rtc1 = &ftm_alarm0; + rtc1 = &ftm_alarm1; + spi0 = &fspi; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port2; + ethernet2 = &mscc_felix_port0; + ethernet3 = &mscc_felix_port1; + ethernet4 = &mscc_felix_port2; + ethernet5 = &mscc_felix_port3; }; chosen { @@ -102,6 +109,48 @@ }; }; +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&enetc_mdio_pf3 { + sgmii_phy0: ethernet-phy@2 { + reg = <0x2>; + }; + + /* VSC8514 QSGMII quad PHY */ + qsgmii_phy0: ethernet-phy@10 { + reg = <0x10>; + }; + + qsgmii_phy1: ethernet-phy@11 { + reg = <0x11>; + }; + + qsgmii_phy2: ethernet-phy@12 { + reg = <0x12>; + }; + + qsgmii_phy3: ethernet-phy@13 { + reg = <0x13>; + }; +}; + +&enetc_port0 { + phy-handle = <&sgmii_phy0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&enetc_port2 { + status = "okay"; +}; + &esdhc { sd-uhs-sdr104; sd-uhs-sdr50; @@ -132,6 +181,10 @@ }; }; +&ftm_alarm1 { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -188,48 +241,6 @@ }; }; -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&enetc_mdio_pf3 { - sgmii_phy0: ethernet-phy@2 { - reg = <0x2>; - }; - - /* VSC8514 QSGMII quad PHY */ - qsgmii_phy0: ethernet-phy@10 { - reg = <0x10>; - }; - - qsgmii_phy1: ethernet-phy@11 { - reg = <0x11>; - }; - - qsgmii_phy2: ethernet-phy@12 { - reg = <0x12>; - }; - - qsgmii_phy3: ethernet-phy@13 { - reg = <0x13>; - }; -}; - -&enetc_port0 { - phy-handle = <&sgmii_phy0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; -}; - -&enetc_port2 { - status = "okay"; -}; - &mscc_felix { status = "okay"; }; @@ -275,6 +286,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &sai4 { status = "okay"; }; diff --git a/dts/src/arm64/freescale/fsl-ls1028a.dtsi b/dts/src/arm64/freescale/fsl-ls1028a.dtsi index fd3f3e8bb6..5bb8c26e08 100644 --- a/dts/src/arm64/freescale/fsl-ls1028a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1028a.dtsi @@ -66,6 +66,13 @@ }; }; + rtc_clk: rtc-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -637,6 +644,18 @@ status = "disabled"; }; + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ + interrupt-names = "pme"; + num-ib-windows = <6>; + num-ob-windows = <8>; + status = "disabled"; + }; + pcie2: pcie@3500000 { compatible = "fsl,ls1028a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ @@ -664,6 +683,18 @@ status = "disabled"; }; + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x88 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ + interrupt-names = "pme"; + num-ib-windows = <6>; + num-ob-windows = <8>; + status = "disabled"; + }; + smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; @@ -1084,7 +1115,7 @@ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - ports { + mscc_felix_ports: ports { #address-cells = <1>; #size-cells = <0>; @@ -1162,6 +1193,94 @@ reg = <0x01 0xf0800000 0x0 0x10000>; }; + pwm0: pwm@2800000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2800000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm1: pwm@2810000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2810000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm2: pwm@2820000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2820000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm3: pwm@2830000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2830000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm4: pwm@2840000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2840000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm5: pwm@2850000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2850000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm6: pwm@2860000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2860000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + + pwm7: pwm@2870000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2870000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&rtc_clk>, <&clockgen 4 1>; + status = "disabled"; + }; + rcpm: power-controller@1e34040 { compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; reg = <0x0 0x1e34040 0x0 0x1c>; @@ -1174,6 +1293,15 @@ reg = <0x0 0x2800000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ftm_alarm1: timer@2810000 { + compatible = "fsl,ls1028a-ftm-alarm"; + reg = <0x0 0x2810000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; }; diff --git a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts index 3516af4726..b290605e92 100644 --- a/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts +++ b/dts/src/arm64/freescale/fsl-ls1043a-rdb.dts @@ -94,6 +94,8 @@ compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-max-frequency = <1000000>; /* input clock */ + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <100>; }; slic@2 { diff --git a/dts/src/arm64/freescale/fsl-ls1088a.dtsi b/dts/src/arm64/freescale/fsl-ls1088a.dtsi index f891ef6a37..3ed1f2c51c 100644 --- a/dts/src/arm64/freescale/fsl-ls1088a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1088a.dtsi @@ -206,6 +206,13 @@ clock-output-names = "sysclk"; }; + reboot { + compatible = "syscon-reboot"; + regmap = <&reset>; + offset = <0x0>; + mask = <0x02>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -226,6 +233,11 @@ little-endian; }; + reset: syscon@1e60000 { + compatible = "fsl,ls1088a-reset", "syscon"; + reg = <0x0 0x1e60000 0x0 0x10000>; + }; + isc: syscon@1f70000 { compatible = "fsl,ls1088a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; @@ -485,6 +497,7 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; }; diff --git a/dts/src/arm64/freescale/fsl-lx2160a-qds.dts b/dts/src/arm64/freescale/fsl-lx2160a-qds.dts index d858d9c8b5..2ecfa90f5e 100644 --- a/dts/src/arm64/freescale/fsl-lx2160a-qds.dts +++ b/dts/src/arm64/freescale/fsl-lx2160a-qds.dts @@ -31,6 +31,130 @@ regulator-boot-on; regulator-always-on; }; + + mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* On-board PHY #1 RGMI1*/ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@8 { /* On-board PHY #2 RGMI2*/ + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@18 { /* Slot #1 */ + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@19 { /* Slot #2 */ + reg = <0x19>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1a { /* Slot #3 */ + reg = <0x1a>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1b { /* Slot #4 */ + reg = <0x1b>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1c { /* Slot #5 */ + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1d { /* Slot #6 */ + reg = <0x1d>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1e { /* Slot #7 */ + reg = <0x1e>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1f { /* Slot #8 */ + reg = <0x1f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* Slot #1 (secondary EMI) */ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { /* Slot #2 (secondary EMI) */ + reg = <0x01>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@2 { /* Slot #3 (secondary EMI) */ + reg = <0x02>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* Slot #4 (secondary EMI) */ + reg = <0x03>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@4 { /* Slot #5 (secondary EMI) */ + reg = <0x04>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@5 { /* Slot #6 (secondary EMI) */ + reg = <0x05>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@6 { /* Slot #7 (secondary EMI) */ + reg = <0x06>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@7 { /* Slot #8 (secondary EMI) */ + reg = <0x07>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; &can0 { @@ -81,6 +205,14 @@ }; }; +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { status = "okay"; }; @@ -107,6 +239,19 @@ &i2c0 { status = "okay"; + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", + "simple-mfd"; + reg = <0x66>; + + mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ + }; + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; @@ -156,6 +301,10 @@ }; }; +&optee { + status = "okay"; +}; + &sata0 { status = "okay"; }; diff --git a/dts/src/arm64/freescale/fsl-lx2160a-rdb.dts b/dts/src/arm64/freescale/fsl-lx2160a-rdb.dts index 028ff8074b..0c44b3cbef 100644 --- a/dts/src/arm64/freescale/fsl-lx2160a-rdb.dts +++ b/dts/src/arm64/freescale/fsl-lx2160a-rdb.dts @@ -49,6 +49,14 @@ managed = "in-band-status"; }; +&dpmac5 { + phy-handle = <&inphi_phy>; +}; + +&dpmac6 { + phy-handle = <&inphi_phy>; +}; + &dpmac17 { phy-handle = <&rgmii_phy1>; phy-connection-type = "rgmii-id"; @@ -109,6 +117,15 @@ }; }; +&emdio2 { + status = "okay"; + + inphi_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; +}; + &esdhc0 { sd-uhs-sdr104; sd-uhs-sdr50; @@ -202,6 +219,10 @@ }; }; +&optee { + status = "okay"; +}; + &pcs_mdio3 { status = "okay"; }; diff --git a/dts/src/arm64/freescale/fsl-lx2160a.dtsi b/dts/src/arm64/freescale/fsl-lx2160a.dtsi index 2433e6f2ed..7032505f5e 100644 --- a/dts/src/arm64/freescale/fsl-lx2160a.dtsi +++ b/dts/src/arm64/freescale/fsl-lx2160a.dtsi @@ -1023,6 +1023,7 @@ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; @@ -1034,6 +1035,7 @@ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + usb3-lpm-capable; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; @@ -1751,4 +1753,12 @@ }; }; }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; }; diff --git a/dts/src/arm64/freescale/fsl-lx2162a-qds.dts b/dts/src/arm64/freescale/fsl-lx2162a-qds.dts index e1defee1ad..a1644ceed1 100644 --- a/dts/src/arm64/freescale/fsl-lx2162a-qds.dts +++ b/dts/src/arm64/freescale/fsl-lx2162a-qds.dts @@ -167,6 +167,14 @@ }; }; +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + &crypto { status = "okay"; }; @@ -226,10 +234,17 @@ }; &esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; status = "okay"; }; &esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; status = "okay"; }; @@ -302,11 +317,17 @@ rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; + /* IRQ_RTC_B -> IRQ11_B(CPLD) -> IRQ11(CPU), active low */ + interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>; }; }; }; }; +&optee { + status = "okay"; +}; + &sata0 { status = "okay"; }; diff --git a/dts/src/arm64/freescale/imx8mm-beacon-baseboard.dtsi b/dts/src/arm64/freescale/imx8mm-beacon-baseboard.dtsi index 6f5e63696e..0da311898e 100644 --- a/dts/src/arm64/freescale/imx8mm-beacon-baseboard.dtsi +++ b/dts/src/arm64/freescale/imx8mm-beacon-baseboard.dtsi @@ -43,6 +43,27 @@ enable-active-high; }; + reg_usbotg1: regulator-usbotg1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_otg1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_camera: regulator-camera { + compatible = "regulator-fixed"; + regulator-name = "mipi_pwr"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -67,6 +88,10 @@ }; }; +&csi { + status = "okay"; +}; + &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_espi2>; @@ -90,6 +115,30 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clk IMX8MM_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <24000000>; + AVDD-supply = <®_camera>; /* 2.8v */ + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + + port { + /* MIPI CSI-2 bus endpoint */ + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; }; &i2c4 { @@ -141,6 +190,18 @@ }; }; +&mipi_csi { + status = "okay"; + ports { + port@0 { + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -169,6 +230,24 @@ status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usbotg1>; + disable-over-current; + dr_mode="otg"; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + disable-over-current; + dr_mode="host"; + status = "okay"; +}; + +&usbphynop2 { + reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -209,12 +288,26 @@ >; }; + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 >; }; + pinctrl_reg_usb_otg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/dts/src/arm64/freescale/imx8mm-beacon-som.dtsi b/dts/src/arm64/freescale/imx8mm-beacon-som.dtsi index 40f5e7a3b0..cf07987ccc 100644 --- a/dts/src/arm64/freescale/imx8mm-beacon-som.dtsi +++ b/dts/src/arm64/freescale/imx8mm-beacon-som.dtsi @@ -263,7 +263,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - pm-ignore-notify; keep-power-in-suspend; mmc-pwrseq = <&usdhc1_pwrseq>; status = "okay"; diff --git a/dts/src/arm64/freescale/imx8mm-evk.dtsi b/dts/src/arm64/freescale/imx8mm-evk.dtsi index e033d0257b..3bac87b7e1 100644 --- a/dts/src/arm64/freescale/imx8mm-evk.dtsi +++ b/dts/src/arm64/freescale/imx8mm-evk.dtsi @@ -116,6 +116,13 @@ reg = <0>; reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + qca,disable-smarteee; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; }; diff --git a/dts/src/arm64/freescale/imx8mm-icore-mx8mm-ctouch2.dts b/dts/src/arm64/freescale/imx8mm-icore-mx8mm-ctouch2.dts index 5389d6f2be..5027454028 100644 --- a/dts/src/arm64/freescale/imx8mm-icore-mx8mm-ctouch2.dts +++ b/dts/src/arm64/freescale/imx8mm-icore-mx8mm-ctouch2.dts @@ -91,7 +91,6 @@ max-frequency = <50000000>; bus-width = <4>; no-1-8-v; - pm-ignore-notify; keep-power-in-suspend; status = "okay"; }; diff --git a/dts/src/arm64/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/dts/src/arm64/freescale/imx8mm-icore-mx8mm-edimm2.2.dts index a4a2ada148..ddac8bc7ae 100644 --- a/dts/src/arm64/freescale/imx8mm-icore-mx8mm-edimm2.2.dts +++ b/dts/src/arm64/freescale/imx8mm-icore-mx8mm-edimm2.2.dts @@ -91,7 +91,6 @@ max-frequency = <50000000>; bus-width = <4>; no-1-8-v; - pm-ignore-notify; keep-power-in-suspend; status = "okay"; }; diff --git a/dts/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts b/dts/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts new file mode 100644 index 0000000000..7844878788 --- /dev/null +++ b/dts/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +/dts-v1/; + +#include "imx8mm-tqma8mqml.dtsi" +#include "mba8mx.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx"; + compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + aliases { + eeprom0 = &eeprom3; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + extcon_usbotg1: extcon-usbotg1 { + compatible = "linux,extcon-usb-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_extcon>; + id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + expander2: gpio@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&sai3 { + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; +}; + +&tlv320aic3x04 { + clock-names = "mclk"; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; +}; + +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "otg"; + extcon = <&extcon_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + over-current-active-low; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_hub_vbus>; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x00000006>, + <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x00000006>, + <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x00000006>, + <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00000006>; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x00000006>, + <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x00000006>, + <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x00000006>, + <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00000006>; + }; + + pinctrl_expander: expandergrp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x94>; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002>, + <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002>, + <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14>, + <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14>, + <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14>, + <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14>, + <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90>, + <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90>, + <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90>, + <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90>, + <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14>, + <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90>, + <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90>, + <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14>; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x84>, + <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x84>, + <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x84>; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x84>, + <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x84>; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000004>, + <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000004>; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000004>, + <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x40000004>; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000004>, + <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000004>; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000004>, + <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x40000004>; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x14>; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x14>; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x94>, + <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x94>, + <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x94>, + <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x94>, + <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x94>, + <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x94>, + <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x94>; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x16>, + <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x16>; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x16>, + <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x16>; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x16>, + <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x16>; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x16>, + <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x16>; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>, + <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>; + }; + + pinctrl_usb1_extcon: usb1-extcongrp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x84>; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>, + <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, + <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>, + <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, + <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>, + <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, + <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, + <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mm-tqma8mqml.dtsi b/dts/src/arm64/freescale/imx8mm-tqma8mqml.dtsi new file mode 100644 index 0000000000..284e62acc0 --- /dev/null +++ b/dts/src/arm64/freescale/imx8mm-tqma8mqml.dtsi @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include "imx8mm.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MM TQMa8MxML"; + compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* identical to buck4_reg, but should never change */ + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXML_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&gpu_2d { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* V_0V85_GPU / DRAM / VPU */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V9_MIPI */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +/* + * Attention: + * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR + * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. + */ +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi: flexspigrp { + fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>, + <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, + <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, + <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, + <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, + <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>, + <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>, + <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, + <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, + <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, + <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, + <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, + <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, + <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, + <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, + /* option USDHC3_RESET_B not defined, only in RM */ + <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, + <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, + <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, + <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, + <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, + <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, + <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, + <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, + /* option USDHC3_RESET_B not defined, only in RM */ + <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, + <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, + <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, + <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, + <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, + <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, + <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, + <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, + <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, + /* option USDHC3_RESET_B not defined, only in RM */ + <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mm.dtsi b/dts/src/arm64/freescale/imx8mm.dtsi index c2f3f118f8..f77f90ed41 100644 --- a/dts/src/arm64/freescale/imx8mm.dtsi +++ b/dts/src/arm64/freescale/imx8mm.dtsi @@ -65,6 +65,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; @@ -80,6 +86,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -93,6 +105,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -106,6 +124,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -114,6 +138,10 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; @@ -591,8 +619,7 @@ <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, - <&clk IMX8MM_AUDIO_PLL1>, - <&clk IMX8MM_AUDIO_PLL2>; + <&clk IMX8MM_AUDIO_PLL1>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_ARM_PLL_OUT>, <&clk IMX8MM_SYS_PLL3_OUT>, @@ -602,8 +629,7 @@ <400000000>, <750000000>, <594000000>, - <393216000>, - <361267200>; + <393216000>; }; src: reset-controller@30390000 { @@ -1054,7 +1080,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; @@ -1068,6 +1093,22 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + csi: csi@32e20000 { + compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; + reg = <0x32e20000 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; + clock-names = "mclk"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; + status = "disabled"; + + port { + csi_in: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_out>; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1095,6 +1136,41 @@ #power-domain-cells = <1>; }; + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL2_1000M>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; diff --git a/dts/src/arm64/freescale/imx8mn-beacon-baseboard.dtsi b/dts/src/arm64/freescale/imx8mn-beacon-baseboard.dtsi index 376ca8ff72..0f40b43ac0 100644 --- a/dts/src/arm64/freescale/imx8mn-beacon-baseboard.dtsi +++ b/dts/src/arm64/freescale/imx8mn-beacon-baseboard.dtsi @@ -126,7 +126,6 @@ compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - clock-names = "xclk"; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; diff --git a/dts/src/arm64/freescale/imx8mn-beacon-som.dtsi b/dts/src/arm64/freescale/imx8mn-beacon-som.dtsi index 3b2d627a03..1133cded9b 100644 --- a/dts/src/arm64/freescale/imx8mn-beacon-som.dtsi +++ b/dts/src/arm64/freescale/imx8mn-beacon-som.dtsi @@ -274,7 +274,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - pm-ignore-notify; keep-power-in-suspend; mmc-pwrseq = <&usdhc1_pwrseq>; status = "okay"; diff --git a/dts/src/arm64/freescale/imx8mn-bsh-smm-s2-common.dtsi b/dts/src/arm64/freescale/imx8mn-bsh-smm-s2-common.dtsi new file mode 100644 index 0000000000..c11895d9d5 --- /dev/null +++ b/dts/src/arm64/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + * Copyright 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include "imx8mn.dtsi" + +/ { + chosen { + stdout-path = &uart4; + }; + + fec_supply: fec-supply-en { + compatible = "regulator-fixed"; + vin-supply = <&buck4_reg>; + regulator-name = "tja1101_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_pwrseq: usdhc2-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwrseq>; + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_espi2>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <&fec_supply>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <2000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + bd71847: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + buck1_reg: BUCK1 { + /* PMIC_BUCK1 - VDD_SOC */ + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + /* PMIC_BUCK2 - VDD_ARM */ + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: BUCK3 { + /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */ + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + /* PMIC_BUCK6 - VDD_3V3 */ + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + /* PMIC_BUCK7 - VDD_1V8 */ + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + /* PMIC_BUCK8 - NVCC_DRAM */ + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + /* PMIC_LDO1 - NVCC_SNVS_1V8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + /* PMIC_LDO2 - VDD_SNVS_0V8 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + /* PMIC_LDO3 - VDDA_1V8 */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + /* PMIC_LDO4 - VDD_MIPI_0V9 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + /* PMIC_LDO6 - VDD_MIPI_1V2 */ + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bluetooth>; + shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + }; +}; + +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + mmc-pwrseq = <&usdhc2_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: bcrmf@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */ + MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */ + MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */ + >; + }; + + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 + MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090 + MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016 + MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090 + MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016 + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */ + MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */ + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */ + MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040 + MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6 + >; + }; + + pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */ + MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */ + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */ + >; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mn-bsh-smm-s2.dts b/dts/src/arm64/freescale/imx8mn-bsh-smm-s2.dts new file mode 100644 index 0000000000..33f98582ea --- /dev/null +++ b/dts/src/arm64/freescale/imx8mn-bsh-smm-s2.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + * Copyright 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include "imx8mn-bsh-smm-s2-common.dtsi" + +/ { + model = "BSH SMM S2"; + compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x10000000>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mn-bsh-smm-s2pro.dts b/dts/src/arm64/freescale/imx8mn-bsh-smm-s2pro.dts new file mode 100644 index 0000000000..c6a8ed6745 --- /dev/null +++ b/dts/src/arm64/freescale/imx8mn-bsh-smm-s2pro.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Collabora Ltd. + * Copyright 2021 BSH Hausgeraete GmbH + */ + +/dts-v1/; + +#include "imx8mn-bsh-smm-s2-common.dtsi" + +/ { + model = "BSH SMM S2 PRO"; + compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x20000000>; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0 + MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0 + MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0 + MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0 + MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0 + MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4 + MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4 + MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4 + MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4 + MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4 + MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6 + MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6 + MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6 + MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6 + MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6 + MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096 + >; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mn-evk.dtsi b/dts/src/arm64/freescale/imx8mn-evk.dtsi index 85e65f8719..c3f15192b7 100644 --- a/dts/src/arm64/freescale/imx8mn-evk.dtsi +++ b/dts/src/arm64/freescale/imx8mn-evk.dtsi @@ -97,6 +97,15 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + qca,disable-smarteee; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; }; diff --git a/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts new file mode 100644 index 0000000000..3f1e49bfe3 --- /dev/null +++ b/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +/dts-v1/; + +#include "imx8mn-tqma8mqnl.dtsi" +#include "mba8mx.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx"; + compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; + + aliases { + eeprom0 = &eeprom3; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +/* Located on TQMa8MxML-ADAP */ +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0hub_sel>; + + sel-usb-hub-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&i2c1 { + expander2: gpio@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander2>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&sai3 { + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; +}; + +&tlv320aic3x04 { + clock-names = "mclk"; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + power-active-high; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = <MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x00000146>, + <MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x00000146>, + <MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x00000146>, + <MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00000146>; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = <MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x00000146>, + <MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x00000146>, + <MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x00000146>, + <MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00000146>; + }; + + pinctrl_expander2: expander2grp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x94>; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = <MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002>, + <MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002>, + <MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14>, + <MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14>, + <MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14>, + <MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14>, + <MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90>, + <MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90>, + <MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90>, + <MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90>, + <MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14>, + <MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90>, + <MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90>, + <MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14>; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x84>, + <MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x84>, + <MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x84>; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x84>, + <MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x84>; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001C4>, + <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001C4>; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001C4>, + <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001C4>; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001C4>, + <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001C4>; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001C4>, + <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001C4>; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x14>; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x14>; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = <MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x94>, + <MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x94>, + <MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x94>, + <MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x94>, + <MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x94>, + <MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x94>, + <MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x94>; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = <MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x16>, + <MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x16>; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = <MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x16>, + <MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x16>; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = <MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x16>, + <MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x16>; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = <MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x16>, + <MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x16>; + }; + + pinctrl_usb0hub_sel: usb0hub-selgrp { + /* SEL_USB_HUB_B */ + fsl,pins = <MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x84>; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>, + <MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>, + <MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x1C4>; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>, + <MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, + <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>, + <MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, + <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x1d4>, + <MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, + <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, + <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = <MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x84>; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi b/dts/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi new file mode 100644 index 0000000000..9ea2894106 --- /dev/null +++ b/dts/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include "imx8mn.dtsi" + +/ { + model = "TQ-Systems i.MX8MN TQMa8MxNL"; + compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXNL_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MXNL_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 .. 0.95 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V9_MIPI */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +/* + * Attention: + * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR + * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. + */ +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi: flexspigrp { + fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x84>, + <MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84>, + <MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84>, + <MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84>, + <MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84>, + <MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84>; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c4>, + <MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c4>; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c4>, + <MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c4>; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, + <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, + <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, + <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, + <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, + <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, + <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, + <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, + <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, + <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, + <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, + <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, + <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, + <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, + <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, + <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, + <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, + <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, + <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, + <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, + <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, + <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, + <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, + <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, + <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, + <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, + <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, + <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, + <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, + <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, + <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, + <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, + <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, + <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mn.dtsi b/dts/src/arm64/freescale/imx8mn.dtsi index da6c942fb7..b8d49d5f26 100644 --- a/dts/src/arm64/freescale/imx8mn.dtsi +++ b/dts/src/arm64/freescale/imx8mn.dtsi @@ -63,6 +63,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; @@ -78,6 +84,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -91,6 +103,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -104,6 +122,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -112,6 +136,10 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; @@ -948,7 +976,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; diff --git a/dts/src/arm64/freescale/imx8mp-evk.dts b/dts/src/arm64/freescale/imx8mp-evk.dts index 7b99fad6e4..2eb9432106 100644 --- a/dts/src/arm64/freescale/imx8mp-evk.dts +++ b/dts/src/arm64/freescale/imx8mp-evk.dts @@ -86,6 +86,9 @@ pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; mdio { @@ -97,6 +100,75 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; eee-broken-1000t; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,clkout-disable; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; }; }; }; @@ -120,6 +192,7 @@ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; + realtek,clkout-disable; }; }; }; diff --git a/dts/src/arm64/freescale/imx8mp.dtsi b/dts/src/arm64/freescale/imx8mp.dtsi index 04d259de56..6b840c05dd 100644 --- a/dts/src/arm64/freescale/imx8mp.dtsi +++ b/dts/src/arm64/freescale/imx8mp.dtsi @@ -51,6 +51,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -62,6 +68,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -73,6 +85,12 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -84,12 +102,22 @@ clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; @@ -369,6 +397,10 @@ eth_mac1: mac-address@90 { reg = <0x90 6>; }; + + eth_mac2: mac-address@96 { + reg = <0x96 6>; + }; }; anatop: anatop@30360000 { @@ -832,7 +864,6 @@ nvmem-cells = <ð_mac1>; nvmem-cell-names = "mac-address"; fsl,stop-mode = <&gpr 0x10 3>; - nvmem_macaddr_swap; status = "disabled"; }; @@ -854,6 +885,8 @@ <&clk IMX8MP_SYS_PLL2_100M>, <&clk IMX8MP_SYS_PLL2_125M>; assigned-clock-rates = <0>, <100000000>, <125000000>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; intf_mode = <&gpr 0x4>; status = "disabled"; }; diff --git a/dts/src/arm64/freescale/imx8mq-evk.dts b/dts/src/arm64/freescale/imx8mq-evk.dts index b83df77195..a1b7582f3e 100644 --- a/dts/src/arm64/freescale/imx8mq-evk.dts +++ b/dts/src/arm64/freescale/imx8mq-evk.dts @@ -169,6 +169,11 @@ reg = <0>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + qca,disable-smarteee; + vddio-supply = <&vddh>; + + vddh: vddh-regulator { + }; }; }; }; @@ -326,6 +331,10 @@ power-supply = <&sw1a_reg>; }; +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + &qspi0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; diff --git a/dts/src/arm64/freescale/imx8mq-librem5-r3.dts b/dts/src/arm64/freescale/imx8mq-librem5-r3.dts index cd3c3edd48..4533a84fb0 100644 --- a/dts/src/arm64/freescale/imx8mq-librem5-r3.dts +++ b/dts/src/arm64/freescale/imx8mq-librem5-r3.dts @@ -1,14 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC <kernel@puri.sm> +// Copyright (C) 2021 Purism SPC <kernel@puri.sm> /dts-v1/; -#include "imx8mq-librem5.dtsi" - -/ { - model = "Purism Librem 5r3"; - compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; -}; +#include "imx8mq-librem5-r3.dtsi" &a53_opp_table { opp-1000000000 { @@ -16,22 +11,6 @@ }; }; -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - &buck3_reg { regulator-always-on; }; - -&proximity { - proximity-near-level = <25>; -}; diff --git a/dts/src/arm64/freescale/imx8mq-librem5-r3.dtsi b/dts/src/arm64/freescale/imx8mq-librem5-r3.dtsi new file mode 100644 index 0000000000..e4f8b47cce --- /dev/null +++ b/dts/src/arm64/freescale/imx8mq-librem5-r3.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2021 Purism SPC <kernel@puri.sm> + +/dts-v1/; + +/* + * This file describes hardware that is shared among r3 ("Dogwood") and + * later revisions of the Librem 5 so it has to be included in dts there. + */ + +#include "imx8mq-librem5.dtsi" + +/ { + model = "Purism Librem 5r3"; + compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; +}; + +&accel_gyro { + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; +}; + +&bq25895 { + ti,battery-regulation-voltage = <4200000>; /* uV */ + ti,charge-current = <1500000>; /* uA */ + ti,termination-current = <144000>; /* uA */ +}; + +&camera_front { + pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>; + shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_r3_camera_pwr: r3camerapwrgrp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83 + >; + }; +}; + +&proximity { + proximity-near-level = <25>; +}; diff --git a/dts/src/arm64/freescale/imx8mq-librem5-r4.dts b/dts/src/arm64/freescale/imx8mq-librem5-r4.dts index cbfb49aa25..30d65bef69 100644 --- a/dts/src/arm64/freescale/imx8mq-librem5-r4.dts +++ b/dts/src/arm64/freescale/imx8mq-librem5-r4.dts @@ -1,31 +1,19 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC <kernel@puri.sm> +// Copyright (C) 2021 Purism SPC <kernel@puri.sm> /dts-v1/; -#include "imx8mq-librem5.dtsi" +#include "imx8mq-librem5-r3.dtsi" / { model = "Purism Librem 5r4"; compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; }; -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - &bat { maxim,rsns-microohm = <1667>; }; -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - &led_backlight { led-max-microamp = <25000>; }; diff --git a/dts/src/arm64/freescale/imx8mq-librem5.dtsi b/dts/src/arm64/freescale/imx8mq-librem5.dtsi index 60d47c7149..f3e3418f7e 100644 --- a/dts/src/arm64/freescale/imx8mq-librem5.dtsi +++ b/dts/src/arm64/freescale/imx8mq-librem5.dtsi @@ -14,6 +14,7 @@ / { model = "Purism Librem 5"; compatible = "purism,librem5", "fsl,imx8mq"; + chassis-type = "handset"; backlight_dsi: backlight-dsi { compatible = "led-backlight"; @@ -62,6 +63,40 @@ enable-active-high; }; + /* + * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC + * since we can't have it twice in the 2 different regulator nodes. + */ + reg_csi_1v8: regulator-csi-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* controlled by the CAMERA_POWER_KEY HKS */ + reg_vcam_1v2: regulator-vcam-1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <®_vdd_1v8>; + enable-active-high; + }; + + reg_vcam_2v8: regulator-vcam-2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDA_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_gnss: regulator-gnss { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -237,6 +272,10 @@ cpu-supply = <&buck2_reg>; }; +&csi1 { + status = "okay"; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; @@ -329,6 +368,20 @@ >; }; + pinctrl_camera_pwr: camerapwrgrp { + fsl,pins = < + /* CAMERA_PWR_EN_3V3 */ + MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + /* CSI1_NRST */ + MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83 + >; + }; + pinctrl_charger_in: chargeringrp { fsl,pins = < /* CHRG_INT */ @@ -725,7 +778,7 @@ compatible = "rohm,bd71837"; reg = <0x4b>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; + pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>; clocks = <&pmic_osc>; clock-names = "osc"; clock-output-names = "pmic_clk"; @@ -958,6 +1011,31 @@ >; }; + camera_front: camera@20 { + compatible = "hynix,hi846"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-rates = <25000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + vdda-supply = <®_vcam_2v8>; + vddd-supply = <®_vcam_1v2>; + vddio-supply = <®_csi_1v8>; + rotation = <90>; + orientation = <0>; + + port { + camera1_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 + <80000000 200000000 300000000>; + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + backlight@36 { compatible = "ti,lm36922"; reg = <0x36>; @@ -1031,6 +1109,23 @@ status = "okay"; }; +&mipi_csi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mipi1_sensor_ep: endpoint { + remote-endpoint = <&camera1_ep>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dsi { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/freescale/imx8mq-mnt-reform2.dts b/dts/src/arm64/freescale/imx8mq-mnt-reform2.dts index 4f2db6197b..fa721a13de 100644 --- a/dts/src/arm64/freescale/imx8mq-mnt-reform2.dts +++ b/dts/src/arm64/freescale/imx8mq-mnt-reform2.dts @@ -12,6 +12,7 @@ / { model = "MNT Reform 2"; compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; + chassis-type = "laptop"; pcie1_refclk: clock-pcie1-refclk { compatible = "fixed-clock"; diff --git a/dts/src/arm64/freescale/imx8mq-nitrogen-som.dtsi b/dts/src/arm64/freescale/imx8mq-nitrogen-som.dtsi index 36fc428ebe..395f77b5ac 100644 --- a/dts/src/arm64/freescale/imx8mq-nitrogen-som.dtsi +++ b/dts/src/arm64/freescale/imx8mq-nitrogen-som.dtsi @@ -69,6 +69,9 @@ reg = <4>; interrupt-parent = <&gpio1>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; }; }; }; @@ -191,20 +194,20 @@ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1 + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022 + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022 >; }; diff --git a/dts/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts b/dts/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts new file mode 100644 index 0000000000..d7660eab68 --- /dev/null +++ b/dts/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2021 TQ-Systems GmbH + */ + +/dts-v1/; + +#include "imx8mq-tqma8mq.dtsi" +#include "mba8mx.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx"; + compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq"; + + aliases { + eeprom0 = &eeprom3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + }; + + extcon_usbotg: extcon-usbotg0 { + compatible = "linux,extcon-usb-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon0>; + id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regotgvbus>; + regulator-name = "MBA8MQ_OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&btn2 { + gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; +}; + +&gpio_leds { + led3 { + label = "led3"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + expander2: gpio@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + mpcie-rst-hog { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "MPCIE_RST#"; + }; + }; +}; + +&irqsteer { + status = "okay"; +}; + +&led2 { + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; +}; + +&pcie0 { + reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + epdev_on-supply = <®_vcc_3v3>; + hard-wired = <1>; + status = "okay"; +}; + +/* + * miniPCIe, also usable for cards with USB. Therefore configure the reset as + * static gpio hog. + */ +&pcie1 { + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + epdev_on-supply = <®_vcc_3v3>; + hard-wired = <1>; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; +}; + +&tlv320aic3x04 { + clock-names = "mclk"; + clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +}; + +&uart2 { + assigned-clocks = <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; +}; + +/* console */ +&uart3 { + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; +}; + +&usb3_phy0 { + vbus-supply = <®_otg_vbus>; + status = "okay"; +}; + +&usb_dwc3_0 { + /* we implement dual role but not full featured OTG */ + extcon = <&extcon_usbotg>; + hnp-disable; + srp-disable; + adp-disable; + /* OC not supported due to non matching active polarity */ + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = <MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x0000004e>, + <MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x0000004e>, + <MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x0000004e>, + <MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0000004e>; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = <MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x0000004e>, + <MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x0000004e>, + <MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x0000004e>, + <MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x0000004e>; + }; + + pinctrl_expander: expandergrp { + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0xd6>; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, + <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23>, + <MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, + <MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, + <MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, + <MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, + <MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, + <MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, + <MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, + <MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, + <MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, + <MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, + <MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, + <MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41>, + <MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41>, + <MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41>; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x41>, + <MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41>, + <MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41>; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067>, + <MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067>; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000067>, + <MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x40000067>; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000067>, + <MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000067>; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000067>, + <MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x40000067>; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x16>; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x16>; + }; + + pinctrl_regotgvbus: reggotgvbusgrp { + /* USB1 OTG PWR as GPIO */ + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x06>; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1>; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = <MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6>, + <MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6>, + <MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6>, + <MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6>, + <MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6>, + <MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6>, + <MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6>; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = <MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79>, + <MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79>; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = <MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79>, + <MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79>; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = <MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79>, + <MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79>; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = <MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79>, + <MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79>; + }; + + pinctrl_usbcon0: usb0congrp { + /* ID: floating / high: device, low: host -> use PU */ + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xe6>; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83>, + <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3>, + <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3>, + <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3>, + <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3>, + <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3>, + <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85>, + <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5>, + <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5>, + <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5>, + <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5>, + <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5>, + <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f>, + <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7>, + <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7>, + <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7>, + <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7>, + <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7>, + <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = <MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41>; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mq-tqma8mq.dtsi b/dts/src/arm64/freescale/imx8mq-tqma8mq.dtsi new file mode 100644 index 0000000000..8aedcddfea --- /dev/null +++ b/dts/src/arm64/freescale/imx8mq-tqma8mq.dtsi @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2021 TQ-Systems GmbH + */ + +#include "imx8mq.dtsi" + +/ { + model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ"; + compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq"; + + memory@40000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MX_VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "TQMA8MX_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vdd_arm: regulator-vdd-arm { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-name = "TQMa8Mx_DVFS"; + regulator-type = "voltage"; + regulator-settling-time-us = <150000>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + states = <900000 0x1 1000000 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 640 MiB */ + size = <0 0x28000000>; + /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&gpu { + status = "okay"; +}; + +&pgc_gpu { + power-supply = <&sw1a_reg>; +}; + +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; + reg = <0x8>; + + regulators { + /* VDD_GPU */ + sw1a_reg: sw1ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + /* VDD_VPU */ + sw1c_reg: sw1c { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + /* NVCC_DRAM */ + sw2_reg: sw2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + /* VDD_DRAM */ + sw3a_reg: sw3ab { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + /* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */ + nvcc_1v8_reg: sw4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + /* not used */ + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + /* VDD_PHY_0V9 */ + vgen2_reg: vgen2 { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <975000>; + regulator-always-on; + }; + + /* VDD_PHY_1V8 */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1675000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + /* VDDA_1V8 */ + vgen4_reg: vgen4 { + regulator-min-microvolt = <1625000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + /* VDD_PHY_3V3 */ + vgen5_reg: vgen5 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3625000>; + regulator-always-on; + }; + + /* not used */ + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + sensor0: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-names = "irq"; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + quartz-load-femtofarads = <7000>; + + clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + eeprom1: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + }; + + eeprom0: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&pcie0 { + /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */ + vph-supply = <&vgen5_reg>; +}; + +&pcie1 { + /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */ + vph-supply = <&vgen5_reg>; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + assigned-clocks = <&clk IMX8MQ_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <84000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +/* Attention: wdog reset forcing POR needs baseboard support */ +&wdog1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_dvfs: dvfsgrp { + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16>; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f>, + <MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f>; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000074>, + <MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000074>; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = <MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x97>, + <MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, + <MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x97>, + <MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x97>, + <MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x97>, + <MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x97>; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41>; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83>, + <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3>, + <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3>, + <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3>, + <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3>, + <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3>, + <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3>, + <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3>, + <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3>, + <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3>, + <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83>, + <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85>, + <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5>, + <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5>, + <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5>, + <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5>, + <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5>, + <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5>, + <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5>, + <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5>, + <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5>, + <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85>, + <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87>, + <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7>, + <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7>, + <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7>, + <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7>, + <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7>, + <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7>, + <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7>, + <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7>, + <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7>, + <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87>, + <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mq.dtsi b/dts/src/arm64/freescale/imx8mq.dtsi index 71bf497f99..2df2510d01 100644 --- a/dts/src/arm64/freescale/imx8mq.dtsi +++ b/dts/src/arm64/freescale/imx8mq.dtsi @@ -102,6 +102,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -116,6 +122,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -128,6 +140,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -140,6 +158,12 @@ clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -147,6 +171,10 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; @@ -429,49 +457,49 @@ clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; little-endian; fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000023 - 0x00000001 0x00000029 - 0x00000002 0x0000002f - 0x00000003 0x00000035 - 0x00000004 0x0000003d - 0x00000005 0x00000043 - 0x00000006 0x0000004b - 0x00000007 0x00000051 - 0x00000008 0x00000057 - 0x00000009 0x0000005f - 0x0000000a 0x00000067 - 0x0000000b 0x0000006f - - 0x00010000 0x0000001b - 0x00010001 0x00000023 - 0x00010002 0x0000002b - 0x00010003 0x00000033 - 0x00010004 0x0000003b - 0x00010005 0x00000043 - 0x00010006 0x0000004b - 0x00010007 0x00000055 - 0x00010008 0x0000005d - 0x00010009 0x00000067 - 0x0001000a 0x00000070 - - 0x00020000 0x00000017 - 0x00020001 0x00000023 - 0x00020002 0x0000002d - 0x00020003 0x00000037 - 0x00020004 0x00000041 - 0x00020005 0x0000004b - 0x00020006 0x00000057 - 0x00020007 0x00000063 - 0x00020008 0x0000006f - - 0x00030000 0x00000015 - 0x00030001 0x00000021 - 0x00030002 0x0000002d - 0x00030003 0x00000039 - 0x00030004 0x00000045 - 0x00030005 0x00000053 - 0x00030006 0x0000005f - 0x00030007 0x00000071>; + fsl,tmu-calibration = <0x00000000 0x00000023>, + <0x00000001 0x00000029>, + <0x00000002 0x0000002f>, + <0x00000003 0x00000035>, + <0x00000004 0x0000003d>, + <0x00000005 0x00000043>, + <0x00000006 0x0000004b>, + <0x00000007 0x00000051>, + <0x00000008 0x00000057>, + <0x00000009 0x0000005f>, + <0x0000000a 0x00000067>, + <0x0000000b 0x0000006f>, + + <0x00010000 0x0000001b>, + <0x00010001 0x00000023>, + <0x00010002 0x0000002b>, + <0x00010003 0x00000033>, + <0x00010004 0x0000003b>, + <0x00010005 0x00000043>, + <0x00010006 0x0000004b>, + <0x00010007 0x00000055>, + <0x00010008 0x0000005d>, + <0x00010009 0x00000067>, + <0x0001000a 0x00000070>, + + <0x00020000 0x00000017>, + <0x00020001 0x00000023>, + <0x00020002 0x0000002d>, + <0x00020003 0x00000037>, + <0x00020004 0x00000041>, + <0x00020005 0x0000004b>, + <0x00020006 0x00000057>, + <0x00020007 0x00000063>, + <0x00020008 0x0000006f>, + + <0x00030000 0x00000015>, + <0x00030001 0x00000021>, + <0x00030002 0x0000002d>, + <0x00030003 0x00000039>, + <0x00030004 0x00000045>, + <0x00030005 0x00000053>, + <0x00030006 0x0000005f>, + <0x00030007 0x00000071>; #thermal-sensor-cells = <1>; }; @@ -1290,7 +1318,6 @@ fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; - nvmem_macaddr_swap; fsl,stop-mode = <&iomuxc_gpr 0x10 3>; status = "disabled"; }; diff --git a/dts/src/arm64/freescale/imx8qm.dtsi b/dts/src/arm64/freescale/imx8qm.dtsi index aebbe2b84a..4a7c017b5f 100644 --- a/dts/src/arm64/freescale/imx8qm.dtsi +++ b/dts/src/arm64/freescale/imx8qm.dtsi @@ -57,6 +57,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -65,6 +71,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -73,6 +85,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -81,6 +99,12 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; }; @@ -89,6 +113,12 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&A72_L2>; }; @@ -102,10 +132,18 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; A72_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; diff --git a/dts/src/arm64/freescale/imx8qxp.dtsi b/dts/src/arm64/freescale/imx8qxp.dtsi index 617618edf7..dbec7c106e 100644 --- a/dts/src/arm64/freescale/imx8qxp.dtsi +++ b/dts/src/arm64/freescale/imx8qxp.dtsi @@ -58,6 +58,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -69,6 +75,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -80,6 +92,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x2>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -91,6 +109,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x3>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -99,6 +123,10 @@ A35_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; diff --git a/dts/src/arm64/freescale/imx8ulp-evk.dts b/dts/src/arm64/freescale/imx8ulp-evk.dts new file mode 100644 index 0000000000..33e84c4e9e --- /dev/null +++ b/dts/src/arm64/freescale/imx8ulp-evk.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8ulp.dtsi" + +/ { + model = "NXP i.MX8ULP EVK"; + compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; + + chosen { + stdout-path = &lpuart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; +}; + +&lpuart5 { + /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart5>; + pinctrl-1 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x3 + MX8ULP_PAD_PTF15__LPUART5_RX 0x3 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 + MX8ULP_PAD_PTD10__SDHC0_D0 0x43 + MX8ULP_PAD_PTD9__SDHC0_D1 0x43 + MX8ULP_PAD_PTD8__SDHC0_D2 0x43 + MX8ULP_PAD_PTD7__SDHC0_D3 0x43 + MX8ULP_PAD_PTD6__SDHC0_D4 0x43 + MX8ULP_PAD_PTD5__SDHC0_D5 0x43 + MX8ULP_PAD_PTD4__SDHC0_D6 0x43 + MX8ULP_PAD_PTD3__SDHC0_D7 0x43 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 + >; + }; +}; diff --git a/dts/src/arm64/freescale/imx8ulp-pinfunc.h b/dts/src/arm64/freescale/imx8ulp-pinfunc.h new file mode 100755 index 0000000000..b204ac79b4 --- /dev/null +++ b/dts/src/arm64/freescale/imx8ulp-pinfunc.h @@ -0,0 +1,978 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Copyright 2021 NXP + */ + +#ifndef __DTS_IMX8ULP_PINFUNC_H +#define __DTS_IMX8ULP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg input_reg mux_mode input_val> + */ +#define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 +#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 +#define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 +#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1 +#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1 0x0004 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX0_1 0x0004 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX1_1 0x0004 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 +#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1 +#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2 0x0008 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX0_2 0x0008 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX1_2 0x0008 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1 +#define MX8ULP_PAD_PTD3__SDHC0_D7 0x000C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA5 0x000C 0x0968 0x9 0x1 +#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3 0x000C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX0_3 0x000C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX1_3 0x000C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD4__PTD4 0x0010 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1 +#define MX8ULP_PAD_PTD4__SDHC0_VS 0x0010 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD4__TPM8_CH5 0x0010 0x0B2C 0x6 0x1 +#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD4__SDHC0_D6 0x0010 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA4 0x0010 0x0964 0x9 0x1 +#define MX8ULP_PAD_PTD4__EPDC0_SDCE0 0x0010 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD4__DPI0_DE 0x0010 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4 0x0010 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD4__DEBUG_MUX0_4 0x0010 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD4__DEBUG_MUX1_4 0x0010 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD5__PTD5 0x0014 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD5__SDHC0_CD 0x0014 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD5__TPM8_CH4 0x0014 0x0B28 0x6 0x1 +#define MX8ULP_PAD_PTD5__I2S6_TX_BCLK 0x0014 0x0B4C 0x7 0x1 +#define MX8ULP_PAD_PTD5__SDHC0_D5 0x0014 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SS0_B 0x0014 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SCLK_B 0x0014 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD5__EPDC0_D0 0x0014 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD5__DPI0_D0 0x0014 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5 0x0014 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD5__DEBUG_MUX0_5 0x0014 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD5__DEBUG_MUX1_5 0x0014 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD6__PTD6 0x0018 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD6__SDHC0_WP 0x0018 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD6__TPM8_CH3 0x0018 0x0B24 0x6 0x1 +#define MX8ULP_PAD_PTD6__I2S6_TX_FS 0x0018 0x0B50 0x7 0x1 +#define MX8ULP_PAD_PTD6__SDHC0_D4 0x0018 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD6__FLEXSPI2_B_SCLK 0x0018 0x0978 0x9 0x1 +#define MX8ULP_PAD_PTD6__EPDC0_D1 0x0018 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD6__DPI0_D1 0x0018 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6 0x0018 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD6__DEBUG_MUX0_6 0x0018 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD6__DEBUG_MUX1_6 0x0018 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD7__PTD7 0x001C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD7__TPM8_CH2 0x001C 0x0B20 0x6 0x1 +#define MX8ULP_PAD_PTD7__I2S6_TXD0 0x001C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD7__SDHC0_D3 0x001C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD7__FLEXSPI2_B_DATA3 0x001C 0x0960 0x9 0x1 +#define MX8ULP_PAD_PTD7__EPDC0_D2 0x001C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD7__DPI0_D2 0x001C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7 0x001C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD7__DEBUG_MUX0_7 0x001C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD7__DEBUG_MUX1_7 0x001C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD8__PTD8 0x0020 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD8__TPM8_CH1 0x0020 0x0B1C 0x6 0x1 +#define MX8ULP_PAD_PTD8__I2S6_TXD1 0x0020 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD8__SDHC0_D2 0x0020 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD8__FLEXSPI2_B_DATA2 0x0020 0x095C 0x9 0x1 +#define MX8ULP_PAD_PTD8__EPDC0_D3 0x0020 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD8__DPI0_D3 0x0020 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD8__LP_APD_DBG_MUX_8 0x0020 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD8__DEBUG_MUX1_8 0x0020 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD9__PTD9 0x0024 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD9__TPM8_CLKIN 0x0024 0x0B30 0x6 0x1 +#define MX8ULP_PAD_PTD9__I2S6_TXD2 0x0024 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD9__SDHC0_D1 0x0024 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD9__FLEXSPI2_B_DATA1 0x0024 0x0958 0x9 0x1 +#define MX8ULP_PAD_PTD9__EPDC0_D4 0x0024 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD9__DPI0_D4 0x0024 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD9__LP_APD_DBG_MUX_9 0x0024 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD9__DEBUG_MUX1_9 0x0024 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD10__PTD10 0x0028 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD10__TPM8_CH0 0x0028 0x0B18 0x6 0x1 +#define MX8ULP_PAD_PTD10__I2S6_TXD3 0x0028 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD10__SDHC0_D0 0x0028 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD10__FLEXSPI2_B_DATA0 0x0028 0x0954 0x9 0x1 +#define MX8ULP_PAD_PTD10__EPDC0_D5 0x0028 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD10__DPI0_D5 0x0028 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD10__LP_APD_DBG_MUX_10 0x0028 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD10__DEBUG_MUX1_10 0x0028 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD11__PTD11 0x002C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD11__TPM8_CH5 0x002C 0x0B2C 0x6 0x2 +#define MX8ULP_PAD_PTD11__I2S6_RXD2 0x002C 0x0B3C 0x7 0x1 +#define MX8ULP_PAD_PTD11__SDHC0_DQS 0x002C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B 0x002C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B 0x002C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD11__EPDC0_D6 0x002C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD11__DPI0_D6 0x002C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD11__LP_APD_DBG_MUX_11 0x002C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD12__PTD12 0x0030 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD12__USB0_ID 0x0030 0x0AC8 0x5 0x1 +#define MX8ULP_PAD_PTD12__SDHC2_D3 0x0030 0x0AA4 0x6 0x1 +#define MX8ULP_PAD_PTD12__I2S7_RX_BCLK 0x0030 0x0B64 0x7 0x1 +#define MX8ULP_PAD_PTD12__SDHC1_DQS 0x0030 0x0A84 0x8 0x1 +#define MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x0030 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B 0x0030 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD12__EPDC0_D7 0x0030 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD12__DPI0_D7 0x0030 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD12__LP_APD_DBG_MUX_12 0x0030 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD13__PTD13 0x0034 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD13__SPDIF_IN3 0x0034 0x0B80 0x4 0x1 +#define MX8ULP_PAD_PTD13__USB0_PWR 0x0034 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD13__SDHC2_D2 0x0034 0x0AA0 0x6 0x1 +#define MX8ULP_PAD_PTD13__I2S7_RX_FS 0x0034 0x0B68 0x7 0x1 +#define MX8ULP_PAD_PTD13__SDHC1_RESET_B 0x0034 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x0034 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD13__CLKOUT2 0x0034 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD13__EPDC0_D8 0x0034 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD13__DPI0_D8 0x0034 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD13__CLKOUT1 0x0034 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD13__LP_APD_DBG_MUX_13 0x0034 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD14__PTD14 0x0038 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD14__SPDIF_OUT3 0x0038 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD14__USB0_OC 0x0038 0x0AC0 0x5 0x1 +#define MX8ULP_PAD_PTD14__SDHC2_D1 0x0038 0x0A9C 0x6 0x1 +#define MX8ULP_PAD_PTD14__I2S7_RXD0 0x0038 0x0B54 0x7 0x1 +#define MX8ULP_PAD_PTD14__SDHC1_D7 0x0038 0x0A80 0x8 0x1 +#define MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x0038 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD14__TRACE0_D7 0x0038 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD14__EPDC0_D9 0x0038 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD14__DPI0_D9 0x0038 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD14__LP_APD_DBG_MUX_14 0x0038 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD15__PTD15 0x003C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD15__SPDIF_IN2 0x003C 0x0B7C 0x4 0x1 +#define MX8ULP_PAD_PTD15__SDHC1_VS 0x003C 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD15__SDHC2_D0 0x003C 0x0A98 0x6 0x1 +#define MX8ULP_PAD_PTD15__I2S7_TX_BCLK 0x003C 0x0B6C 0x7 0x1 +#define MX8ULP_PAD_PTD15__SDHC1_D6 0x003C 0x0A7C 0x8 0x1 +#define MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x003C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD15__TRACE0_D6 0x003C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD15__EPDC0_D10 0x003C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD15__DPI0_D10 0x003C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD15__LP_APD_DBG_MUX_15 0x003C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD16__PTD16 0x0040 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD16__FXIO1_D31 0x0040 0x08A0 0x2 0x1 +#define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1 +#define MX8ULP_PAD_PTD16__SPDIF_OUT2 0x0040 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD16__SDHC1_CD 0x0040 0x0A58 0x5 0x1 +#define MX8ULP_PAD_PTD16__SDHC2_CLK 0x0040 0x0A90 0x6 0x1 +#define MX8ULP_PAD_PTD16__I2S7_TX_FS 0x0040 0x0B70 0x7 0x1 +#define MX8ULP_PAD_PTD16__SDHC1_D5 0x0040 0x0A78 0x8 0x1 +#define MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x0040 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD16__TRACE0_D5 0x0040 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD16__EPDC0_D11 0x0040 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD16__DPI0_D11 0x0040 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD16__LP_APD_DBG_MUX_16 0x0040 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD17__PTD17 0x0044 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD17__FXIO1_D30 0x0044 0x089C 0x2 0x1 +#define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1 +#define MX8ULP_PAD_PTD17__EXT_AUD_MCLK3 0x0044 0x0B14 0x4 0x2 +#define MX8ULP_PAD_PTD17__SDHC1_WP 0x0044 0x0A88 0x5 0x1 +#define MX8ULP_PAD_PTD17__SDHC2_CMD 0x0044 0x0A94 0x6 0x1 +#define MX8ULP_PAD_PTD17__I2S7_TXD0 0x0044 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD17__SDHC1_D4 0x0044 0x0A74 0x8 0x1 +#define MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x0044 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD17__TRACE0_D4 0x0044 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD17__EPDC0_D12 0x0044 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD17__DPI0_D12 0x0044 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD17__LP_APD_DBG_MUX_17 0x0044 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD18__PTD18 0x0048 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD18__FXIO1_D29 0x0048 0x0894 0x2 0x1 +#define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1 +#define MX8ULP_PAD_PTD18__SPDIF_CLK 0x0048 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3 +#define MX8ULP_PAD_PTD18__TPM8_CH0 0x0048 0x0B18 0x6 0x2 +#define MX8ULP_PAD_PTD18__I2S7_MCLK 0x0048 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD18__SDHC1_D3 0x0048 0x0A70 0x8 0x1 +#define MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x0048 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD18__TRACE0_D3 0x0048 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD18__EPDC0_D13 0x0048 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD18__DPI0_D13 0x0048 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD18__LP_APD_DBG_MUX_18 0x0048 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD19__PTD19 0x004C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD19__FXIO1_D28 0x004C 0x0890 0x2 0x1 +#define MX8ULP_PAD_PTD19__SPDIF_IN0 0x004C 0x0B74 0x4 0x1 +#define MX8ULP_PAD_PTD19__TPM8_CH1 0x004C 0x0B1C 0x6 0x2 +#define MX8ULP_PAD_PTD19__I2S6_RXD3 0x004C 0x0B40 0x7 0x1 +#define MX8ULP_PAD_PTD19__SDHC1_D2 0x004C 0x0A6C 0x8 0x1 +#define MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x004C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD19__TRACE0_D2 0x004C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD19__EPDC0_D14 0x004C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD19__DPI0_D14 0x004C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD19__LP_APD_DBG_MUX_19 0x004C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD20__PTD20 0x0050 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD20__FXIO1_D27 0x0050 0x088C 0x2 0x1 +#define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1 +#define MX8ULP_PAD_PTD20__SPDIF_OUT0 0x0050 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD20__TPM8_CLKIN 0x0050 0x0B30 0x6 0x2 +#define MX8ULP_PAD_PTD20__I2S7_RXD1 0x0050 0x0B58 0x7 0x1 +#define MX8ULP_PAD_PTD20__SDHC1_D1 0x0050 0x0A68 0x8 0x1 +#define MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x0050 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD20__TRACE0_D1 0x0050 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD20__EPDC0_D15 0x0050 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD20__DPI0_D15 0x0050 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD20__LP_APD_DBG_MUX_20 0x0050 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD21__PTD21 0x0054 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD21__FXIO1_D26 0x0054 0x0888 0x2 0x1 +#define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1 +#define MX8ULP_PAD_PTD21__SPDIF_IN1 0x0054 0x0B78 0x4 0x1 +#define MX8ULP_PAD_PTD21__USB1_PWR 0x0054 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD21__TPM8_CH2 0x0054 0x0B20 0x6 0x2 +#define MX8ULP_PAD_PTD21__I2S7_TXD1 0x0054 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD21__SDHC1_D0 0x0054 0x0A64 0x8 0x1 +#define MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x0054 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD21__TRACE0_D0 0x0054 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD21__DPI0_D16 0x0054 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD21__WDOG5_RST 0x0054 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD21__LP_APD_DBG_MUX_21 0x0054 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD22__PTD22 0x0058 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD22__FXIO1_D25 0x0058 0x0884 0x2 0x1 +#define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1 +#define MX8ULP_PAD_PTD22__SPDIF_OUT1 0x0058 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD22__USB1_OC 0x0058 0x0AC4 0x5 0x1 +#define MX8ULP_PAD_PTD22__TPM8_CH3 0x0058 0x0B24 0x6 0x2 +#define MX8ULP_PAD_PTD22__I2S7_TXD2 0x0058 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD22__SDHC1_CLK 0x0058 0x0A5C 0x8 0x1 +#define MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x0058 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD22__TRACE0_CLKOUT 0x0058 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD22__DPI0_D17 0x0058 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD22__LP_APD_DBG_MUX_22 0x0058 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD23__PTD23 0x005C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD23__FXIO1_D24 0x005C 0x0880 0x2 0x1 +#define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1 +#define MX8ULP_PAD_PTD23__USB1_ID 0x005C 0x0ACC 0x5 0x1 +#define MX8ULP_PAD_PTD23__TPM8_CH4 0x005C 0x0B28 0x6 0x2 +#define MX8ULP_PAD_PTD23__I2S7_TXD3 0x005C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD23__SDHC1_CMD 0x005C 0x0A60 0x8 0x1 +#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B 0x005C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK_B 0x005C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD23__DPI0_D18 0x005C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD23__LP_APD_DBG_MUX_23 0x005C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE0__PTE0 0x0080 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE0__FXIO1_D23 0x0080 0x087C 0x2 0x1 +#define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2 +#define MX8ULP_PAD_PTE0__LPUART4_CTS_B 0x0080 0x08DC 0x4 0x1 +#define MX8ULP_PAD_PTE0__LPI2C4_SCL 0x0080 0x08C8 0x5 0x1 +#define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3 +#define MX8ULP_PAD_PTE0__I2S7_RXD2 0x0080 0x0B5C 0x7 0x1 +#define MX8ULP_PAD_PTE0__SDHC2_D1 0x0080 0x0A9C 0x8 0x2 +#define MX8ULP_PAD_PTE0__FLEXSPI2_B_DQS 0x0080 0x0974 0x9 0x2 +#define MX8ULP_PAD_PTE0__ENET0_CRS 0x0080 0x0AE8 0xa 0x1 +#define MX8ULP_PAD_PTE0__DBI0_WRX 0x0080 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE0__DPI0_D19 0x0080 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE0__WUU1_P0 0x0080 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE0__DEBUG_MUX0_8 0x0080 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE0__DEBUG_MUX1_11 0x0080 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE1__PTE1 0x0084 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE1__FXIO1_D22 0x0084 0x0878 0x2 0x1 +#define MX8ULP_PAD_PTE1__SPDIF_OUT3 0x0084 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE1__LPUART4_RTS_B 0x0084 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE1__LPI2C4_SDA 0x0084 0x08CC 0x5 0x1 +#define MX8ULP_PAD_PTE1__TPM8_CH0 0x0084 0x0B18 0x6 0x3 +#define MX8ULP_PAD_PTE1__I2S7_RXD3 0x0084 0x0B60 0x7 0x1 +#define MX8ULP_PAD_PTE1__SDHC2_D0 0x0084 0x0A98 0x8 0x2 +#define MX8ULP_PAD_PTE1__FLEXSPI2_B_DATA7 0x0084 0x0970 0x9 0x2 +#define MX8ULP_PAD_PTE1__ENET0_COL 0x0084 0x0AE4 0xa 0x1 +#define MX8ULP_PAD_PTE1__DBI0_CSX 0x0084 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE1__DPI0_D20 0x0084 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE1__WUU1_P1 0x0084 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE1__DEBUG_MUX0_9 0x0084 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE1__DEBUG_MUX1_12 0x0084 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE2__PTE2 0x0088 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE2__FXIO1_D21 0x0088 0x0874 0x2 0x1 +#define MX8ULP_PAD_PTE2__SPDIF_IN2 0x0088 0x0B7C 0x3 0x2 +#define MX8ULP_PAD_PTE2__LPUART4_TX 0x0088 0x08E4 0x4 0x1 +#define MX8ULP_PAD_PTE2__LPI2C4_HREQ 0x0088 0x08C4 0x5 0x1 +#define MX8ULP_PAD_PTE2__TPM8_CH1 0x0088 0x0B1C 0x6 0x3 +#define MX8ULP_PAD_PTE2__EXT_AUD_MCLK3 0x0088 0x0B14 0x7 0x4 +#define MX8ULP_PAD_PTE2__SDHC2_CLK 0x0088 0x0A90 0x8 0x2 +#define MX8ULP_PAD_PTE2__FLEXSPI2_B_DATA6 0x0088 0x096C 0x9 0x2 +#define MX8ULP_PAD_PTE2__ENET0_TXER 0x0088 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE2__DBI0_DCX 0x0088 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE2__DPI0_D21 0x0088 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE2__LP_HV_DBG_MUX_0 0x0088 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE2__DEBUG_MUX0_10 0x0088 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE2__DEBUG_MUX1_13 0x0088 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE3__PTE3 0x008C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE3__FXIO1_D20 0x008C 0x0870 0x2 0x1 +#define MX8ULP_PAD_PTE3__SPDIF_OUT2 0x008C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE3__LPUART4_RX 0x008C 0x08E0 0x4 0x1 +#define MX8ULP_PAD_PTE3__TPM8_CH2 0x008C 0x0B20 0x6 0x3 +#define MX8ULP_PAD_PTE3__I2S6_MCLK 0x008C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE3__SDHC2_CMD 0x008C 0x0A94 0x8 0x2 +#define MX8ULP_PAD_PTE3__FLEXSPI2_B_DATA5 0x008C 0x0968 0x9 0x2 +#define MX8ULP_PAD_PTE3__ENET0_TXCLK 0x008C 0x0B10 0xa 0x1 +#define MX8ULP_PAD_PTE3__DBI0_RWX 0x008C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE3__DPI0_D22 0x008C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE3__WUU1_P2 0x008C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE3__DEBUG_MUX0_11 0x008C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE3__DEBUG_MUX1_14 0x008C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE4__PTE4 0x0090 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE4__FXIO1_D19 0x0090 0x0868 0x2 0x1 +#define MX8ULP_PAD_PTE4__SPDIF_CLK 0x0090 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE4__LPUART5_CTS_B 0x0090 0x08E8 0x4 0x1 +#define MX8ULP_PAD_PTE4__LPI2C5_SCL 0x0090 0x08D4 0x5 0x1 +#define MX8ULP_PAD_PTE4__TPM8_CH3 0x0090 0x0B24 0x6 0x3 +#define MX8ULP_PAD_PTE4__I2S6_RX_BCLK 0x0090 0x0B44 0x7 0x2 +#define MX8ULP_PAD_PTE4__SDHC2_D3 0x0090 0x0AA4 0x8 0x2 +#define MX8ULP_PAD_PTE4__FLEXSPI2_B_DATA4 0x0090 0x0964 0x9 0x2 +#define MX8ULP_PAD_PTE4__ENET0_TXD3 0x0090 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE4__DBI0_E 0x0090 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE4__DPI0_D23 0x0090 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE4__WUU1_P3 0x0090 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE4__DEBUG_MUX0_12 0x0090 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE4__DEBUG_MUX1_15 0x0090 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE5__PTE5 0x0094 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE5__FXIO1_D18 0x0094 0x0864 0x2 0x1 +#define MX8ULP_PAD_PTE5__SPDIF_IN0 0x0094 0x0B74 0x3 0x2 +#define MX8ULP_PAD_PTE5__LPUART5_RTS_B 0x0094 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE5__LPI2C5_SDA 0x0094 0x08D8 0x5 0x1 +#define MX8ULP_PAD_PTE5__TPM8_CH4 0x0094 0x0B28 0x6 0x3 +#define MX8ULP_PAD_PTE5__I2S6_RX_FS 0x0094 0x0B48 0x7 0x2 +#define MX8ULP_PAD_PTE5__SDHC2_D2 0x0094 0x0AA0 0x8 0x2 +#define MX8ULP_PAD_PTE5__FLEXSPI2_B_SS0_B 0x0094 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE5__ENET0_TXD2 0x0094 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE5__DBI0_D0 0x0094 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE5__LP_HV_DBG_MUX_1 0x0094 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE5__DEBUG_MUX0_13 0x0094 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE5__DEBUG_MUX1_16 0x0094 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE6__PTE6 0x0098 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE6__FXIO1_D17 0x0098 0x0860 0x2 0x1 +#define MX8ULP_PAD_PTE6__SPDIF_OUT0 0x0098 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE6__LPUART5_TX 0x0098 0x08F0 0x4 0x1 +#define MX8ULP_PAD_PTE6__LPI2C5_HREQ 0x0098 0x08D0 0x5 0x1 +#define MX8ULP_PAD_PTE6__TPM8_CH5 0x0098 0x0B2C 0x6 0x3 +#define MX8ULP_PAD_PTE6__I2S6_RXD0 0x0098 0x0B34 0x7 0x2 +#define MX8ULP_PAD_PTE6__SDHC2_D4 0x0098 0x0AA8 0x8 0x1 +#define MX8ULP_PAD_PTE6__FLEXSPI2_B_SCLK 0x0098 0x0978 0x9 0x2 +#define MX8ULP_PAD_PTE6__ENET0_RXCLK 0x0098 0x0B0C 0xa 0x1 +#define MX8ULP_PAD_PTE6__DBI0_D1 0x0098 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE6__LP_HV_DBG_MUX_2 0x0098 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE6__WDOG5_RST 0x0098 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE6__DEBUG_MUX0_14 0x0098 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE6__DEBUG_MUX1_17 0x0098 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE7__PTE7 0x009C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE7__FXIO1_D16 0x009C 0x085C 0x2 0x1 +#define MX8ULP_PAD_PTE7__SPDIF_IN1 0x009C 0x0B78 0x3 0x2 +#define MX8ULP_PAD_PTE7__LPUART5_RX 0x009C 0x08EC 0x4 0x1 +#define MX8ULP_PAD_PTE7__LPI2C6_HREQ 0x009C 0x09B4 0x5 0x1 +#define MX8ULP_PAD_PTE7__TPM4_CLKIN 0x009C 0x081C 0x6 0x1 +#define MX8ULP_PAD_PTE7__I2S6_RXD1 0x009C 0x0B38 0x7 0x2 +#define MX8ULP_PAD_PTE7__SDHC2_D5 0x009C 0x0AAC 0x8 0x1 +#define MX8ULP_PAD_PTE7__FLEXSPI2_B_DATA3 0x009C 0x0960 0x9 0x2 +#define MX8ULP_PAD_PTE7__ENET0_RXD3 0x009C 0x0B04 0xa 0x1 +#define MX8ULP_PAD_PTE7__DBI0_D2 0x009C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE7__EPDC0_BDR1 0x009C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE7__WUU1_P4 0x009C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE7__DEBUG_MUX0_15 0x009C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE7__DEBUG_MUX1_18 0x009C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE8__PTE8 0x00A0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE8__FXIO1_D15 0x00A0 0x0858 0x2 0x1 +#define MX8ULP_PAD_PTE8__LPSPI4_PCS1 0x00A0 0x08F8 0x3 0x2 +#define MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x00A0 0x09CC 0x4 0x1 +#define MX8ULP_PAD_PTE8__LPI2C6_SCL 0x00A0 0x09B8 0x5 0x1 +#define MX8ULP_PAD_PTE8__TPM4_CH0 0x00A0 0x0804 0x6 0x1 +#define MX8ULP_PAD_PTE8__I2S6_RXD2 0x00A0 0x0B3C 0x7 0x2 +#define MX8ULP_PAD_PTE8__SDHC2_D6 0x00A0 0x0AB0 0x8 0x1 +#define MX8ULP_PAD_PTE8__FLEXSPI2_B_DATA2 0x00A0 0x095C 0x9 0x2 +#define MX8ULP_PAD_PTE8__ENET0_RXD2 0x00A0 0x0B00 0xa 0x1 +#define MX8ULP_PAD_PTE8__DBI0_D3 0x00A0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE8__EPDC0_BDR0 0x00A0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE8__LP_HV_DBG_MUX_3 0x00A0 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE8__DEBUG_MUX1_19 0x00A0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE9__PTE9 0x00A4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE9__FXIO1_D14 0x00A4 0x0854 0x2 0x1 +#define MX8ULP_PAD_PTE9__LPSPI4_PCS2 0x00A4 0x08FC 0x3 0x2 +#define MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x00A4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE9__LPI2C6_SDA 0x00A4 0x09BC 0x5 0x1 +#define MX8ULP_PAD_PTE9__TPM4_CH1 0x00A4 0x0808 0x6 0x1 +#define MX8ULP_PAD_PTE9__I2S6_RXD3 0x00A4 0x0B40 0x7 0x2 +#define MX8ULP_PAD_PTE9__SDHC2_D7 0x00A4 0x0AB4 0x8 0x1 +#define MX8ULP_PAD_PTE9__FLEXSPI2_B_DATA1 0x00A4 0x0958 0x9 0x2 +#define MX8ULP_PAD_PTE9__ENET0_1588_TMR3 0x00A4 0x0AE0 0xa 0x1 +#define MX8ULP_PAD_PTE9__DBI0_D4 0x00A4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE9__EPDC0_VCOM1 0x00A4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE9__LP_HV_DBG_MUX_4 0x00A4 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE9__DEBUG_MUX1_20 0x00A4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE10__PTE10 0x00A8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE10__FXIO1_D13 0x00A8 0x0850 0x2 0x1 +#define MX8ULP_PAD_PTE10__LPSPI4_PCS3 0x00A8 0x0900 0x3 0x2 +#define MX8ULP_PAD_PTE10__LPUART6_TX 0x00A8 0x09D4 0x4 0x1 +#define MX8ULP_PAD_PTE10__I3C2_SCL 0x00A8 0x08BC 0x5 0x1 +#define MX8ULP_PAD_PTE10__TPM4_CH2 0x00A8 0x080C 0x6 0x1 +#define MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x00A8 0x0B4C 0x7 0x2 +#define MX8ULP_PAD_PTE10__SDHC2_DQS 0x00A8 0x0AB8 0x8 0x1 +#define MX8ULP_PAD_PTE10__FLEXSPI2_B_DATA0 0x00A8 0x0954 0x9 0x2 +#define MX8ULP_PAD_PTE10__ENET0_1588_TMR2 0x00A8 0x0ADC 0xa 0x1 +#define MX8ULP_PAD_PTE10__DBI0_D5 0x00A8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE10__EPDC0_VCOM0 0x00A8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE10__LP_HV_DBG_MUX_5 0x00A8 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE10__DEBUG_MUX1_21 0x00A8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE11__PTE11 0x00AC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE11__FXIO1_D12 0x00AC 0x084C 0x2 0x1 +#define MX8ULP_PAD_PTE11__SPDIF_OUT1 0x00AC 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE11__LPUART6_RX 0x00AC 0x09D0 0x4 0x1 +#define MX8ULP_PAD_PTE11__I3C2_SDA 0x00AC 0x08C0 0x5 0x1 +#define MX8ULP_PAD_PTE11__TPM4_CH3 0x00AC 0x0810 0x6 0x1 +#define MX8ULP_PAD_PTE11__I2S6_TX_FS 0x00AC 0x0B50 0x7 0x2 +#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SCLK_B 0x00AC 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SS0_B 0x00AC 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE11__ENET0_1588_TMR1 0x00AC 0x0AD8 0xa 0x1 +#define MX8ULP_PAD_PTE11__DBI0_D6 0x00AC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE11__EPDC0_PWRCTRL0 0x00AC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE11__LP_HV_DBG_MUX_6 0x00AC 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE12__PTE12 0x00B0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE12__FXIO1_D11 0x00B0 0x0848 0x2 0x1 +#define MX8ULP_PAD_PTE12__LPSPI4_SIN 0x00B0 0x0908 0x3 0x2 +#define MX8ULP_PAD_PTE12__LPUART7_CTS_B 0x00B0 0x09D8 0x4 0x1 +#define MX8ULP_PAD_PTE12__LPI2C7_SCL 0x00B0 0x09C4 0x5 0x1 +#define MX8ULP_PAD_PTE12__TPM4_CH4 0x00B0 0x0814 0x6 0x1 +#define MX8ULP_PAD_PTE12__I2S6_TXD0 0x00B0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE12__SDHC2_RESET_B 0x00B0 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE12__FLEXSPI2_B_SS1_B 0x00B0 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE12__ENET0_1588_TMR0 0x00B0 0x0AD4 0xa 0x1 +#define MX8ULP_PAD_PTE12__DBI0_D7 0x00B0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE12__EPDC0_PWRCTRL1 0x00B0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE12__WUU1_P5 0x00B0 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE13__PTE13 0x00B4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE13__FXIO1_D10 0x00B4 0x0844 0x2 0x1 +#define MX8ULP_PAD_PTE13__LPSPI4_SOUT 0x00B4 0x090C 0x3 0x2 +#define MX8ULP_PAD_PTE13__LPUART7_RTS_B 0x00B4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE13__LPI2C7_SDA 0x00B4 0x09C8 0x5 0x1 +#define MX8ULP_PAD_PTE13__TPM4_CH5 0x00B4 0x0818 0x6 0x1 +#define MX8ULP_PAD_PTE13__I2S6_TXD1 0x00B4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE13__SDHC1_WP 0x00B4 0x0A88 0x8 0x2 +#define MX8ULP_PAD_PTE13__ENET0_1588_CLKIN 0x00B4 0x0AD0 0xa 0x1 +#define MX8ULP_PAD_PTE13__DBI0_D8 0x00B4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE13__EPDC0_PWRCTRL2 0x00B4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE13__LP_HV_DBG_MUX_7 0x00B4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE14__PTE14 0x00B8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE14__FXIO1_D9 0x00B8 0x08B8 0x2 0x1 +#define MX8ULP_PAD_PTE14__LPSPI4_SCK 0x00B8 0x0904 0x3 0x2 +#define MX8ULP_PAD_PTE14__LPUART7_TX 0x00B8 0x09E0 0x4 0x1 +#define MX8ULP_PAD_PTE14__LPI2C7_HREQ 0x00B8 0x09C0 0x5 0x1 +#define MX8ULP_PAD_PTE14__TPM5_CLKIN 0x00B8 0x0838 0x6 0x1 +#define MX8ULP_PAD_PTE14__I2S6_TXD2 0x00B8 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE14__SDHC1_CD 0x00B8 0x0A58 0x8 0x2 +#define MX8ULP_PAD_PTE14__ENET0_MDIO 0x00B8 0x0AF0 0xa 0x1 +#define MX8ULP_PAD_PTE14__DBI0_D9 0x00B8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE14__EPDC0_PWRCTRL3 0x00B8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE14__LP_HV_DBG_MUX_8 0x00B8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE15__PTE15 0x00BC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE15__FXIO1_D8 0x00BC 0x08B4 0x2 0x1 +#define MX8ULP_PAD_PTE15__LPSPI4_PCS0 0x00BC 0x08F4 0x3 0x2 +#define MX8ULP_PAD_PTE15__LPUART7_RX 0x00BC 0x09DC 0x4 0x1 +#define MX8ULP_PAD_PTE15__I3C2_PUR 0x00BC 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTE15__TPM5_CH0 0x00BC 0x0820 0x6 0x1 +#define MX8ULP_PAD_PTE15__I2S6_TXD3 0x00BC 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE15__MQS1_LEFT 0x00BC 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE15__ENET0_MDC 0x00BC 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE15__DBI0_D10 0x00BC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE15__EPDC0_PWRCOM 0x00BC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE15__WUU1_P6 0x00BC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE16__PTE16 0x00C0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE16__FXIO1_D7 0x00C0 0x08B0 0x2 0x1 +#define MX8ULP_PAD_PTE16__LPSPI5_PCS1 0x00C0 0x0914 0x3 0x1 +#define MX8ULP_PAD_PTE16__LPUART4_CTS_B 0x00C0 0x08DC 0x4 0x2 +#define MX8ULP_PAD_PTE16__LPI2C4_SCL 0x00C0 0x08C8 0x5 0x2 +#define MX8ULP_PAD_PTE16__TPM5_CH1 0x00C0 0x0824 0x6 0x1 +#define MX8ULP_PAD_PTE16__MQS1_LEFT 0x00C0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE16__MQS1_RIGHT 0x00C0 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE16__USB0_ID 0x00C0 0x0AC8 0x9 0x2 +#define MX8ULP_PAD_PTE16__ENET0_TXEN 0x00C0 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE16__DBI0_D11 0x00C0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE16__EPDC0_PWRIRQ 0x00C0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE16__WDOG3_RST 0x00C0 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE16__LP_HV_DBG_MUX_9 0x00C0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE17__PTE17 0x00C4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE17__FXIO1_D6 0x00C4 0x08AC 0x2 0x1 +#define MX8ULP_PAD_PTE17__LPSPI5_PCS2 0x00C4 0x0918 0x3 0x1 +#define MX8ULP_PAD_PTE17__LPUART4_RTS_B 0x00C4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE17__LPI2C4_SDA 0x00C4 0x08CC 0x5 0x2 +#define MX8ULP_PAD_PTE17__MQS1_RIGHT 0x00C4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE17__SDHC1_VS 0x00C4 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE17__USB0_PWR 0x00C4 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE17__ENET0_RXER 0x00C4 0x0B08 0xa 0x1 +#define MX8ULP_PAD_PTE17__DBI0_D12 0x00C4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE17__EPDC0_PWRSTAT 0x00C4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE17__LP_HV_DBG_MUX_10 0x00C4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE18__PTE18 0x00C8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE18__FXIO1_D5 0x00C8 0x08A8 0x2 0x1 +#define MX8ULP_PAD_PTE18__LPSPI5_PCS3 0x00C8 0x091C 0x3 0x1 +#define MX8ULP_PAD_PTE18__LPUART4_TX 0x00C8 0x08E4 0x4 0x2 +#define MX8ULP_PAD_PTE18__LPI2C4_HREQ 0x00C8 0x08C4 0x5 0x2 +#define MX8ULP_PAD_PTE18__I2S7_TX_BCLK 0x00C8 0x0B6C 0x7 0x2 +#define MX8ULP_PAD_PTE18__USB0_OC 0x00C8 0x0AC0 0x9 0x2 +#define MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x00C8 0x0AEC 0xa 0x1 +#define MX8ULP_PAD_PTE18__DBI0_D13 0x00C8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x00C8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE18__LP_HV_DBG_MUX_11 0x00C8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE19__PTE19 0x00CC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE19__FXIO1_D4 0x00CC 0x08A4 0x2 0x1 +#define MX8ULP_PAD_PTE19__LPUART4_RX 0x00CC 0x08E0 0x4 0x2 +#define MX8ULP_PAD_PTE19__LPI2C5_HREQ 0x00CC 0x08D0 0x5 0x2 +#define MX8ULP_PAD_PTE19__I3C2_PUR 0x00CC 0x0000 0x6 0x0 +#define MX8ULP_PAD_PTE19__I2S7_TX_FS 0x00CC 0x0B70 0x7 0x2 +#define MX8ULP_PAD_PTE19__USB1_PWR 0x00CC 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE19__ENET0_REFCLK 0x00CC 0x0AF4 0xa 0x1 +#define MX8ULP_PAD_PTE19__DBI0_D14 0x00CC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x00CC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE19__WUU1_P7 0x00CC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE20__PTE20 0x00D0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE20__FXIO1_D3 0x00D0 0x0898 0x2 0x1 +#define MX8ULP_PAD_PTE20__LPSPI5_SIN 0x00D0 0x0924 0x3 0x1 +#define MX8ULP_PAD_PTE20__LPUART5_CTS_B 0x00D0 0x08E8 0x4 0x2 +#define MX8ULP_PAD_PTE20__LPI2C5_SCL 0x00D0 0x08D4 0x5 0x2 +#define MX8ULP_PAD_PTE20__I2S7_TXD0 0x00D0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE20__USB1_OC 0x00D0 0x0AC4 0x9 0x2 +#define MX8ULP_PAD_PTE20__ENET0_RXD1 0x00D0 0x0AFC 0xa 0x1 +#define MX8ULP_PAD_PTE20__DBI0_D15 0x00D0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE20__EPDC0_GDOE 0x00D0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE20__LP_HV_DBG_MUX_12 0x00D0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE21__PTE21 0x00D4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE21__FXIO1_D2 0x00D4 0x086C 0x2 0x1 +#define MX8ULP_PAD_PTE21__LPSPI5_SOUT 0x00D4 0x0928 0x3 0x1 +#define MX8ULP_PAD_PTE21__LPUART5_RTS_B 0x00D4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE21__LPI2C5_SDA 0x00D4 0x08D8 0x5 0x2 +#define MX8ULP_PAD_PTE21__TPM6_CLKIN 0x00D4 0x0994 0x6 0x1 +#define MX8ULP_PAD_PTE21__I2S7_TXD1 0x00D4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE21__USB1_ID 0x00D4 0x0ACC 0x9 0x2 +#define MX8ULP_PAD_PTE21__ENET0_RXD0 0x00D4 0x0AF8 0xa 0x1 +#define MX8ULP_PAD_PTE21__EPDC0_GDRL 0x00D4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE21__WDOG4_RST 0x00D4 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE21__LP_HV_DBG_MUX_13 0x00D4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE22__PTE22 0x00D8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE22__FXIO1_D1 0x00D8 0x0840 0x2 0x1 +#define MX8ULP_PAD_PTE22__LPSPI5_SCK 0x00D8 0x0920 0x3 0x1 +#define MX8ULP_PAD_PTE22__LPUART5_TX 0x00D8 0x08F0 0x4 0x2 +#define MX8ULP_PAD_PTE22__I3C2_SCL 0x00D8 0x08BC 0x5 0x2 +#define MX8ULP_PAD_PTE22__TPM6_CH0 0x00D8 0x097C 0x6 0x1 +#define MX8ULP_PAD_PTE22__I2S7_TXD2 0x00D8 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE22__EXT_AUD_MCLK3 0x00D8 0x0B14 0x9 0x5 +#define MX8ULP_PAD_PTE22__ENET0_TXD1 0x00D8 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE22__EPDC0_SDOED 0x00D8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE22__CLKOUT2 0x00D8 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE22__LP_HV_DBG_MUX_14 0x00D8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE23__PTE23 0x00DC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE23__FXIO1_D0 0x00DC 0x083C 0x2 0x1 +#define MX8ULP_PAD_PTE23__LPSPI5_PCS0 0x00DC 0x0910 0x3 0x1 +#define MX8ULP_PAD_PTE23__LPUART5_RX 0x00DC 0x08EC 0x4 0x2 +#define MX8ULP_PAD_PTE23__I3C2_SDA 0x00DC 0x08C0 0x5 0x2 +#define MX8ULP_PAD_PTE23__TPM6_CH1 0x00DC 0x0980 0x6 0x1 +#define MX8ULP_PAD_PTE23__I2S7_TXD3 0x00DC 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE23__EXT_AUD_MCLK2 0x00DC 0x0800 0x9 0x1 +#define MX8ULP_PAD_PTE23__ENET0_TXD0 0x00DC 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE23__EPDC0_SDOEZ 0x00DC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE23__CLKOUT1 0x00DC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE23__LP_HV_DBG_MUX_15 0x00DC 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF0__PTF0 0x0100 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF0__FXIO1_D0 0x0100 0x083C 0x2 0x2 +#define MX8ULP_PAD_PTF0__LPUART6_CTS_B 0x0100 0x09CC 0x4 0x2 +#define MX8ULP_PAD_PTF0__LPI2C6_SCL 0x0100 0x09B8 0x5 0x2 +#define MX8ULP_PAD_PTF0__I2S7_RX_BCLK 0x0100 0x0B64 0x7 0x2 +#define MX8ULP_PAD_PTF0__SDHC1_D1 0x0100 0x0A68 0x8 0x2 +#define MX8ULP_PAD_PTF0__ENET0_RXD1 0x0100 0x0AFC 0x9 0x2 +#define MX8ULP_PAD_PTF0__USB1_ID 0x0100 0x0ACC 0xa 0x3 +#define MX8ULP_PAD_PTF0__EPDC0_SDOE 0x0100 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF0__DPI0_D23 0x0100 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF0__WUU1_P8 0x0100 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF1__PTF1 0x0104 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF1__FXIO1_D1 0x0104 0x0840 0x2 0x2 +#define MX8ULP_PAD_PTF1__LPUART6_RTS_B 0x0104 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF1__LPI2C6_SDA 0x0104 0x09BC 0x5 0x2 +#define MX8ULP_PAD_PTF1__I2S7_RX_FS 0x0104 0x0B68 0x7 0x2 +#define MX8ULP_PAD_PTF1__SDHC1_D0 0x0104 0x0A64 0x8 0x2 +#define MX8ULP_PAD_PTF1__ENET0_RXD0 0x0104 0x0AF8 0x9 0x2 +#define MX8ULP_PAD_PTF1__LP_HV_DBG_MUX_16 0x0104 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF1__EPDC0_SDSHR 0x0104 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF1__DPI0_D22 0x0104 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF1__WDOG3_RST 0x0104 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF1__DEBUG_MUX0_16 0x0104 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF1__DEBUG_MUX1_22 0x0104 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF2__PTF2 0x0108 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF2__FXIO1_D2 0x0108 0x086C 0x2 0x2 +#define MX8ULP_PAD_PTF2__LPUART6_TX 0x0108 0x09D4 0x4 0x2 +#define MX8ULP_PAD_PTF2__LPI2C6_HREQ 0x0108 0x09B4 0x5 0x2 +#define MX8ULP_PAD_PTF2__I2S7_RXD0 0x0108 0x0B54 0x7 0x2 +#define MX8ULP_PAD_PTF2__SDHC1_CLK 0x0108 0x0A5C 0x8 0x2 +#define MX8ULP_PAD_PTF2__ENET0_TXD1 0x0108 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF2__USB0_ID 0x0108 0x0AC8 0xa 0x3 +#define MX8ULP_PAD_PTF2__EPDC0_SDCE9 0x0108 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF2__DPI0_D21 0x0108 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF2__LP_HV_DBG_MUX_17 0x0108 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF2__DEBUG_MUX0_17 0x0108 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF2__DEBUG_MUX1_23 0x0108 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF3__PTF3 0x010C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF3__FXIO1_D3 0x010C 0x0898 0x2 0x2 +#define MX8ULP_PAD_PTF3__LPUART6_RX 0x010C 0x09D0 0x4 0x2 +#define MX8ULP_PAD_PTF3__LPI2C7_HREQ 0x010C 0x09C0 0x5 0x2 +#define MX8ULP_PAD_PTF3__I2S7_RXD1 0x010C 0x0B58 0x7 0x2 +#define MX8ULP_PAD_PTF3__SDHC1_CMD 0x010C 0x0A60 0x8 0x2 +#define MX8ULP_PAD_PTF3__ENET0_TXD0 0x010C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF3__USB0_PWR 0x010C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF3__EPDC0_SDCE8 0x010C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF3__DPI0_D20 0x010C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF3__WUU1_P9 0x010C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF3__DEBUG_MUX1_24 0x010C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF4__PTF4 0x0110 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF4__FXIO1_D4 0x0110 0x08A4 0x2 0x2 +#define MX8ULP_PAD_PTF4__LPSPI4_PCS1 0x0110 0x08F8 0x3 0x3 +#define MX8ULP_PAD_PTF4__LPUART7_CTS_B 0x0110 0x09D8 0x4 0x2 +#define MX8ULP_PAD_PTF4__LPI2C7_SCL 0x0110 0x09C4 0x5 0x2 +#define MX8ULP_PAD_PTF4__TPM7_CLKIN 0x0110 0x09B0 0x6 0x1 +#define MX8ULP_PAD_PTF4__I2S7_RXD2 0x0110 0x0B5C 0x7 0x2 +#define MX8ULP_PAD_PTF4__SDHC1_D3 0x0110 0x0A70 0x8 0x2 +#define MX8ULP_PAD_PTF4__ENET0_TXEN 0x0110 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF4__USB0_OC 0x0110 0x0AC0 0xa 0x3 +#define MX8ULP_PAD_PTF4__EPDC0_SDCE7 0x0110 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF4__DPI0_D19 0x0110 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF4__WUU1_P10 0x0110 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF4__DEBUG_MUX1_25 0x0110 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF5__PTF5 0x0114 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF5__FXIO1_D5 0x0114 0x08A8 0x2 0x2 +#define MX8ULP_PAD_PTF5__LPSPI4_PCS2 0x0114 0x08FC 0x3 0x3 +#define MX8ULP_PAD_PTF5__LPUART7_RTS_B 0x0114 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF5__LPI2C7_SDA 0x0114 0x09C8 0x5 0x2 +#define MX8ULP_PAD_PTF5__TPM7_CH0 0x0114 0x0998 0x6 0x1 +#define MX8ULP_PAD_PTF5__I2S7_RXD3 0x0114 0x0B60 0x7 0x2 +#define MX8ULP_PAD_PTF5__SDHC1_D2 0x0114 0x0A6C 0x8 0x2 +#define MX8ULP_PAD_PTF5__ENET0_RXER 0x0114 0x0B08 0x9 0x2 +#define MX8ULP_PAD_PTF5__USB1_PWR 0x0114 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF5__EPDC0_SDCE6 0x0114 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF5__DPI0_D18 0x0114 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF5__LP_HV_DBG_MUX_18 0x0114 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF5__DEBUG_MUX0_18 0x0114 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF5__DEBUG_MUX1_26 0x0114 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF6__LP_HV_DBG_MUX_19 0x0118 0x0000 0x0 0x0 +#define MX8ULP_PAD_PTF6__PTF6 0x0118 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF6__FXIO1_D6 0x0118 0x08AC 0x2 0x2 +#define MX8ULP_PAD_PTF6__LPSPI4_PCS3 0x0118 0x0900 0x3 0x3 +#define MX8ULP_PAD_PTF6__LPUART7_TX 0x0118 0x09E0 0x4 0x2 +#define MX8ULP_PAD_PTF6__I3C2_SCL 0x0118 0x08BC 0x5 0x3 +#define MX8ULP_PAD_PTF6__TPM7_CH1 0x0118 0x099C 0x6 0x1 +#define MX8ULP_PAD_PTF6__I2S7_MCLK 0x0118 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF6__SDHC1_D4 0x0118 0x0A74 0x8 0x2 +#define MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x0118 0x0AEC 0x9 0x2 +#define MX8ULP_PAD_PTF6__USB1_OC 0x0118 0x0AC4 0xa 0x3 +#define MX8ULP_PAD_PTF6__EPDC0_SDCE5 0x0118 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF6__DPI0_D17 0x0118 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF6__WDOG4_RST 0x0118 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF6__DEBUG_MUX0_19 0x0118 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF6__DEBUG_MUX1_27 0x0118 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF7__PTF7 0x011C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF7__FXIO1_D7 0x011C 0x08B0 0x2 0x2 +#define MX8ULP_PAD_PTF7__LPUART7_RX 0x011C 0x09DC 0x4 0x2 +#define MX8ULP_PAD_PTF7__I3C2_SDA 0x011C 0x08C0 0x5 0x3 +#define MX8ULP_PAD_PTF7__TPM7_CH2 0x011C 0x09A0 0x6 0x1 +#define MX8ULP_PAD_PTF7__MQS1_LEFT 0x011C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF7__SDHC1_D5 0x011C 0x0A78 0x8 0x2 +#define MX8ULP_PAD_PTF7__ENET0_REFCLK 0x011C 0x0AF4 0x9 0x2 +#define MX8ULP_PAD_PTF7__TRACE0_D15 0x011C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF7__EPDC0_SDCE4 0x011C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF7__DPI0_D16 0x011C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF7__WUU1_P11 0x011C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF7__DEBUG_MUX1_28 0x011C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF8__PTF8 0x0120 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF8__FXIO1_D8 0x0120 0x08B4 0x2 0x2 +#define MX8ULP_PAD_PTF8__LPSPI4_SIN 0x0120 0x0908 0x3 0x3 +#define MX8ULP_PAD_PTF8__LPUART4_CTS_B 0x0120 0x08DC 0x4 0x3 +#define MX8ULP_PAD_PTF8__LPI2C4_SCL 0x0120 0x08C8 0x5 0x3 +#define MX8ULP_PAD_PTF8__TPM7_CH3 0x0120 0x09A4 0x6 0x1 +#define MX8ULP_PAD_PTF8__MQS1_RIGHT 0x0120 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF8__SDHC1_D6 0x0120 0x0A7C 0x8 0x2 +#define MX8ULP_PAD_PTF8__ENET0_MDIO 0x0120 0x0AF0 0x9 0x2 +#define MX8ULP_PAD_PTF8__TRACE0_D14 0x0120 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF8__EPDC0_D15 0x0120 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF8__DPI0_D15 0x0120 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF8__LP_HV_DBG_MUX_24 0x0120 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF8__DEBUG_MUX1_29 0x0120 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF9__PTF9 0x0124 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF9__FXIO1_D9 0x0124 0x08B8 0x2 0x2 +#define MX8ULP_PAD_PTF9__LPSPI4_SOUT 0x0124 0x090C 0x3 0x3 +#define MX8ULP_PAD_PTF9__LPUART4_RTS_B 0x0124 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF9__LPI2C4_SDA 0x0124 0x08CC 0x5 0x3 +#define MX8ULP_PAD_PTF9__TPM7_CH4 0x0124 0x09A8 0x6 0x1 +#define MX8ULP_PAD_PTF9__EXT_AUD_MCLK2 0x0124 0x0800 0x7 0x2 +#define MX8ULP_PAD_PTF9__SDHC1_D7 0x0124 0x0A80 0x8 0x2 +#define MX8ULP_PAD_PTF9__ENET0_MDC 0x0124 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF9__TRACE0_D13 0x0124 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF9__EPDC0_D14 0x0124 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF9__DPI0_D14 0x0124 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF9__LP_HV_DBG_MUX_25 0x0124 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF9__DEBUG_MUX1_30 0x0124 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF10__LP_HV_DBG_MUX_26 0x0128 0x0000 0x0 0x0 +#define MX8ULP_PAD_PTF10__PTF10 0x0128 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF10__FXIO1_D10 0x0128 0x0844 0x2 0x2 +#define MX8ULP_PAD_PTF10__LPSPI4_SCK 0x0128 0x0904 0x3 0x3 +#define MX8ULP_PAD_PTF10__LPUART4_TX 0x0128 0x08E4 0x4 0x3 +#define MX8ULP_PAD_PTF10__LPI2C4_HREQ 0x0128 0x08C4 0x5 0x3 +#define MX8ULP_PAD_PTF10__TPM7_CH5 0x0128 0x09AC 0x6 0x1 +#define MX8ULP_PAD_PTF10__I2S4_RX_BCLK 0x0128 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF10__SDHC1_DQS 0x0128 0x0A84 0x8 0x2 +#define MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x0128 0x0AD0 0x9 0x2 +#define MX8ULP_PAD_PTF10__TRACE0_D12 0x0128 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF10__EPDC0_D13 0x0128 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF10__DPI0_D13 0x0128 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF10__DEBUG_MUX0_20 0x0128 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF10__DEBUG_MUX1_31 0x0128 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF11__PTF11 0x012C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF11__FXIO1_D11 0x012C 0x0848 0x2 0x2 +#define MX8ULP_PAD_PTF11__LPSPI4_PCS0 0x012C 0x08F4 0x3 0x3 +#define MX8ULP_PAD_PTF11__LPUART4_RX 0x012C 0x08E0 0x4 0x3 +#define MX8ULP_PAD_PTF11__TPM4_CLKIN 0x012C 0x081C 0x6 0x2 +#define MX8ULP_PAD_PTF11__I2S4_RX_FS 0x012C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF11__ENET0_1588_TMR0 0x012C 0x0AD4 0x9 0x2 +#define MX8ULP_PAD_PTF11__TRACE0_D11 0x012C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF11__EPDC0_D12 0x012C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF11__DPI0_D12 0x012C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF11__LP_HV_DBG_MUX_27 0x012C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF11__DEBUG_MUX1_32 0x012C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF12__PTF12 0x0130 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF12__FXIO1_D12 0x0130 0x084C 0x2 0x2 +#define MX8ULP_PAD_PTF12__LPSPI5_PCS1 0x0130 0x0914 0x3 0x2 +#define MX8ULP_PAD_PTF12__LPUART5_CTS_B 0x0130 0x08E8 0x4 0x3 +#define MX8ULP_PAD_PTF12__LPI2C5_SCL 0x0130 0x08D4 0x5 0x3 +#define MX8ULP_PAD_PTF12__TPM4_CH0 0x0130 0x0804 0x6 0x2 +#define MX8ULP_PAD_PTF12__I2S4_RXD0 0x0130 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF12__SDHC2_WP 0x0130 0x0ABC 0x8 0x1 +#define MX8ULP_PAD_PTF12__ENET0_1588_TMR1 0x0130 0x0AD8 0x9 0x2 +#define MX8ULP_PAD_PTF12__TRACE0_D10 0x0130 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF12__EPDC0_D11 0x0130 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF12__DPI0_D11 0x0130 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF12__LP_HV_DBG_MUX_28 0x0130 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF12__DEBUG_MUX1_33 0x0130 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF13__PTF13 0x0134 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF13__FXIO1_D13 0x0134 0x0850 0x2 0x2 +#define MX8ULP_PAD_PTF13__LPSPI5_PCS2 0x0134 0x0918 0x3 0x2 +#define MX8ULP_PAD_PTF13__LPUART5_RTS_B 0x0134 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF13__LPI2C5_SDA 0x0134 0x08D8 0x5 0x3 +#define MX8ULP_PAD_PTF13__TPM4_CH1 0x0134 0x0808 0x6 0x2 +#define MX8ULP_PAD_PTF13__I2S4_RXD1 0x0134 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF13__SDHC2_CD 0x0134 0x0A8C 0x8 0x1 +#define MX8ULP_PAD_PTF13__ENET0_1588_TMR2 0x0134 0x0ADC 0x9 0x2 +#define MX8ULP_PAD_PTF13__TRACE0_D9 0x0134 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF13__EPDC0_D10 0x0134 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF13__DPI0_D10 0x0134 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF13__DEBUG_MUX0_21 0x0134 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF13__LP_HV_DBG_MUX_29 0x0134 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF14__PTF14 0x0138 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF14__FXIO1_D14 0x0138 0x0854 0x2 0x2 +#define MX8ULP_PAD_PTF14__LPSPI5_PCS3 0x0138 0x091C 0x3 0x2 +#define MX8ULP_PAD_PTF14__LPUART5_TX 0x0138 0x08F0 0x4 0x3 +#define MX8ULP_PAD_PTF14__LPI2C5_HREQ 0x0138 0x08D0 0x5 0x3 +#define MX8ULP_PAD_PTF14__TPM4_CH2 0x0138 0x080C 0x6 0x2 +#define MX8ULP_PAD_PTF14__I2S4_MCLK 0x0138 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF14__SDHC2_VS 0x0138 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF14__ENET0_1588_TMR3 0x0138 0x0AE0 0x9 0x2 +#define MX8ULP_PAD_PTF14__TRACE0_D8 0x0138 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF14__EPDC0_D9 0x0138 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF14__DPI0_D9 0x0138 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF14__DEBUG_MUX0_22 0x0138 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF14__LP_HV_DBG_MUX_30 0x0138 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF15__PTF15 0x013C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF15__FXIO1_D15 0x013C 0x0858 0x2 0x2 +#define MX8ULP_PAD_PTF15__LPUART5_RX 0x013C 0x08EC 0x4 0x3 +#define MX8ULP_PAD_PTF15__TPM4_CH3 0x013C 0x0810 0x6 0x2 +#define MX8ULP_PAD_PTF15__I2S4_TX_BCLK 0x013C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF15__SDHC2_D1 0x013C 0x0A9C 0x8 0x3 +#define MX8ULP_PAD_PTF15__ENET0_RXD2 0x013C 0x0B00 0x9 0x2 +#define MX8ULP_PAD_PTF15__TRACE0_D7 0x013C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF15__EPDC0_D8 0x013C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF15__DPI0_D8 0x013C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF15__LP_HV_DBG_MUX_31 0x013C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF16__PTF16 0x0140 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF16__FXIO1_D16 0x0140 0x085C 0x2 0x2 +#define MX8ULP_PAD_PTF16__LPSPI5_SIN 0x0140 0x0924 0x3 0x2 +#define MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x0140 0x09CC 0x4 0x3 +#define MX8ULP_PAD_PTF16__LPI2C6_SCL 0x0140 0x09B8 0x5 0x3 +#define MX8ULP_PAD_PTF16__TPM4_CH4 0x0140 0x0814 0x6 0x2 +#define MX8ULP_PAD_PTF16__I2S4_TX_FS 0x0140 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF16__SDHC2_D0 0x0140 0x0A98 0x8 0x3 +#define MX8ULP_PAD_PTF16__ENET0_RXD3 0x0140 0x0B04 0x9 0x2 +#define MX8ULP_PAD_PTF16__TRACE0_D6 0x0140 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF16__EPDC0_D7 0x0140 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF16__DPI0_D7 0x0140 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF16__LP_HV_DBG_MUX_32 0x0140 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF17__PTF17 0x0144 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF17__FXIO1_D17 0x0144 0x0860 0x2 0x2 +#define MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x0144 0x0928 0x3 0x2 +#define MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x0144 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF17__LPI2C6_SDA 0x0144 0x09BC 0x5 0x3 +#define MX8ULP_PAD_PTF17__TPM4_CH5 0x0144 0x0818 0x6 0x2 +#define MX8ULP_PAD_PTF17__I2S4_TXD0 0x0144 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF17__SDHC2_CLK 0x0144 0x0A90 0x8 0x3 +#define MX8ULP_PAD_PTF17__ENET0_RXCLK 0x0144 0x0B0C 0x9 0x2 +#define MX8ULP_PAD_PTF17__TRACE0_D5 0x0144 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF17__EPDC0_D6 0x0144 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF17__DPI0_D6 0x0144 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF17__DEBUG_MUX0_23 0x0144 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF17__LP_HV_DBG_MUX_33 0x0144 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF18__PTF18 0x0148 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF18__FXIO1_D18 0x0148 0x0864 0x2 0x2 +#define MX8ULP_PAD_PTF18__LPSPI5_SCK 0x0148 0x0920 0x3 0x2 +#define MX8ULP_PAD_PTF18__LPUART6_TX 0x0148 0x09D4 0x4 0x3 +#define MX8ULP_PAD_PTF18__LPI2C6_HREQ 0x0148 0x09B4 0x5 0x3 +#define MX8ULP_PAD_PTF18__TPM5_CLKIN 0x0148 0x0838 0x6 0x2 +#define MX8ULP_PAD_PTF18__I2S4_TXD1 0x0148 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF18__SDHC2_CMD 0x0148 0x0A94 0x8 0x3 +#define MX8ULP_PAD_PTF18__ENET0_TXD2 0x0148 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF18__TRACE0_D4 0x0148 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF18__EPDC0_D5 0x0148 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF18__DPI0_D5 0x0148 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF19__PTF19 0x014C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF19__FXIO1_D19 0x014C 0x0868 0x2 0x2 +#define MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x014C 0x0910 0x3 0x2 +#define MX8ULP_PAD_PTF19__LPUART6_RX 0x014C 0x09D0 0x4 0x3 +#define MX8ULP_PAD_PTF19__TPM5_CH0 0x014C 0x0820 0x6 0x2 +#define MX8ULP_PAD_PTF19__I2S5_RX_BCLK 0x014C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF19__SDHC2_D3 0x014C 0x0AA4 0x8 0x3 +#define MX8ULP_PAD_PTF19__ENET0_TXD3 0x014C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF19__TRACE0_D3 0x014C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF19__EPDC0_D4 0x014C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF19__DPI0_D4 0x014C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF20__PTF20 0x0150 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF20__FXIO1_D20 0x0150 0x0870 0x2 0x2 +#define MX8ULP_PAD_PTF20__LPUART7_CTS_B 0x0150 0x09D8 0x4 0x3 +#define MX8ULP_PAD_PTF20__LPI2C7_SCL 0x0150 0x09C4 0x5 0x3 +#define MX8ULP_PAD_PTF20__TPM5_CH1 0x0150 0x0824 0x6 0x2 +#define MX8ULP_PAD_PTF20__I2S5_RX_FS 0x0150 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF20__SDHC2_D2 0x0150 0x0AA0 0x8 0x3 +#define MX8ULP_PAD_PTF20__ENET0_TXCLK 0x0150 0x0B10 0x9 0x2 +#define MX8ULP_PAD_PTF20__TRACE0_D2 0x0150 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF20__EPDC0_D3 0x0150 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF20__DPI0_D3 0x0150 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF21__PTF21 0x0154 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF21__FXIO1_D21 0x0154 0x0874 0x2 0x2 +#define MX8ULP_PAD_PTF21__SPDIF_CLK 0x0154 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF21__LPUART7_RTS_B 0x0154 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF21__LPI2C7_SDA 0x0154 0x09C8 0x5 0x3 +#define MX8ULP_PAD_PTF21__TPM6_CLKIN 0x0154 0x0994 0x6 0x2 +#define MX8ULP_PAD_PTF21__I2S5_RXD0 0x0154 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF21__SDHC2_D4 0x0154 0x0AA8 0x8 0x2 +#define MX8ULP_PAD_PTF21__ENET0_CRS 0x0154 0x0AE8 0x9 0x2 +#define MX8ULP_PAD_PTF21__TRACE0_D1 0x0154 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF21__EPDC0_D2 0x0154 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF21__DPI0_D2 0x0154 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF22__PTF22 0x0158 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF22__FXIO1_D22 0x0158 0x0878 0x2 0x2 +#define MX8ULP_PAD_PTF22__SPDIF_IN0 0x0158 0x0B74 0x3 0x3 +#define MX8ULP_PAD_PTF22__LPUART7_TX 0x0158 0x09E0 0x4 0x3 +#define MX8ULP_PAD_PTF22__LPI2C7_HREQ 0x0158 0x09C0 0x5 0x3 +#define MX8ULP_PAD_PTF22__TPM6_CH0 0x0158 0x097C 0x6 0x2 +#define MX8ULP_PAD_PTF22__I2S5_RXD1 0x0158 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF22__SDHC2_D5 0x0158 0x0AAC 0x8 0x2 +#define MX8ULP_PAD_PTF22__ENET0_COL 0x0158 0x0AE4 0x9 0x2 +#define MX8ULP_PAD_PTF22__TRACE0_D0 0x0158 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF22__EPDC0_D1 0x0158 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF22__DPI0_D1 0x0158 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF23__PTF23 0x015C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF23__FXIO1_D23 0x015C 0x087C 0x2 0x2 +#define MX8ULP_PAD_PTF23__SPDIF_OUT0 0x015C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF23__LPUART7_RX 0x015C 0x09DC 0x4 0x3 +#define MX8ULP_PAD_PTF23__I3C2_PUR 0x015C 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTF23__TPM6_CH1 0x015C 0x0980 0x6 0x2 +#define MX8ULP_PAD_PTF23__I2S5_RXD2 0x015C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF23__SDHC2_D6 0x015C 0x0AB0 0x8 0x2 +#define MX8ULP_PAD_PTF23__ENET0_TXER 0x015C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF23__TRACE0_CLKOUT 0x015C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF23__EPDC0_D0 0x015C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF23__DPI0_D0 0x015C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF24__PTF24 0x0160 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF24__FXIO1_D24 0x0160 0x0880 0x2 0x2 +#define MX8ULP_PAD_PTF24__SPDIF_IN1 0x0160 0x0B78 0x3 0x3 +#define MX8ULP_PAD_PTF24__I3C2_SCL 0x0160 0x08BC 0x5 0x4 +#define MX8ULP_PAD_PTF24__I2S5_RXD3 0x0160 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF24__SDHC2_D7 0x0160 0x0AB4 0x8 0x2 +#define MX8ULP_PAD_PTF24__DBI0_WRX 0x0160 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x0160 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF24__DPI0_PCLK 0x0160 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF24__WUU1_P12 0x0160 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF25__PTF25 0x0164 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF25__FXIO1_D25 0x0164 0x0884 0x2 0x2 +#define MX8ULP_PAD_PTF25__SPDIF_OUT1 0x0164 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF25__I3C2_SDA 0x0164 0x08C0 0x5 0x4 +#define MX8ULP_PAD_PTF25__TPM7_CH5 0x0164 0x09AC 0x6 0x2 +#define MX8ULP_PAD_PTF25__I2S5_MCLK 0x0164 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF25__SDHC2_DQS 0x0164 0x0AB8 0x8 0x2 +#define MX8ULP_PAD_PTF25__EXT_AUD_MCLK2 0x0164 0x0800 0x9 0x3 +#define MX8ULP_PAD_PTF25__EPDC0_GDSP 0x0164 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF25__DPI0_VSYNC 0x0164 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF25__WUU1_P13 0x0164 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF26__PTF26 0x0168 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF26__FXIO1_D26 0x0168 0x0888 0x2 0x2 +#define MX8ULP_PAD_PTF26__SPDIF_IN2 0x0168 0x0B7C 0x3 0x3 +#define MX8ULP_PAD_PTF26__TPM7_CLKIN 0x0168 0x09B0 0x6 0x2 +#define MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x0168 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF26__SDHC2_RESET_B 0x0168 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF26__EPDC0_SDLE 0x0168 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF26__DPI0_HSYNC 0x0168 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF26__WUU1_P14 0x0168 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF27__PTF27 0x016C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF27__FXIO1_D27 0x016C 0x088C 0x2 0x2 +#define MX8ULP_PAD_PTF27__SPDIF_OUT2 0x016C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF27__TPM7_CH0 0x016C 0x0998 0x6 0x2 +#define MX8ULP_PAD_PTF27__I2S5_TX_FS 0x016C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF27__SDHC2_WP 0x016C 0x0ABC 0x8 0x2 +#define MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x016C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF27__DPI0_DE 0x016C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF27__WUU1_P15 0x016C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF28__PTF28 0x0170 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF28__FXIO1_D28 0x0170 0x0890 0x2 0x2 +#define MX8ULP_PAD_PTF28__SPDIF_IN3 0x0170 0x0B80 0x3 0x3 +#define MX8ULP_PAD_PTF28__TPM7_CH1 0x0170 0x099C 0x6 0x2 +#define MX8ULP_PAD_PTF28__I2S5_TXD0 0x0170 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF28__SDHC2_CD 0x0170 0x0A8C 0x8 0x2 +#define MX8ULP_PAD_PTF28__EPDC0_SDCLK_B 0x0170 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF28__LP_HV_DBG_MUX_20 0x0170 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF29__PTF29 0x0174 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF29__FXIO1_D29 0x0174 0x0894 0x2 0x2 +#define MX8ULP_PAD_PTF29__SPDIF_OUT3 0x0174 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF29__TPM7_CH2 0x0174 0x09A0 0x6 0x2 +#define MX8ULP_PAD_PTF29__I2S5_TXD1 0x0174 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF29__SDHC2_VS 0x0174 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF29__EPDC0_SDCE1 0x0174 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF29__WDOG3_RST 0x0174 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF29__LP_HV_DBG_MUX_21 0x0174 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF30__PTF30 0x0178 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF30__FXIO1_D30 0x0178 0x089C 0x2 0x2 +#define MX8ULP_PAD_PTF30__TPM7_CH3 0x0178 0x09A4 0x6 0x2 +#define MX8ULP_PAD_PTF30__I2S5_TXD2 0x0178 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF30__MQS1_LEFT 0x0178 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF30__EPDC0_SDCE2 0x0178 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF30__WDOG4_RST 0x0178 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF30__LP_HV_DBG_MUX_22 0x0178 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF31__PTF31 0x017C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF31__FXIO1_D31 0x017C 0x08A0 0x2 0x2 +#define MX8ULP_PAD_PTF31__TPM7_CH4 0x017C 0x09A8 0x6 0x2 +#define MX8ULP_PAD_PTF31__I2S5_TXD3 0x017C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF31__MQS1_RIGHT 0x017C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF31__EPDC0_SDCE3 0x017C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF31__WDOG5_RST 0x017C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF31__LP_HV_DBG_MUX_23 0x017C 0x0000 0xf 0x0 +#define MX8ULP_PAD_BOOT_MODE0__BOOT_MODE0 0x0400 0x0000 0x0 0x0 +#define MX8ULP_PAD_BOOT_MODE1__BOOT_MODE1 0x0404 0x0000 0x0 0x0 + +#endif /* __DTS_IMX8ULP_PINFUNC_H */ diff --git a/dts/src/arm64/freescale/imx8ulp.dtsi b/dts/src/arm64/freescale/imx8ulp.dtsi new file mode 100644 index 0000000000..a987ff7156 --- /dev/null +++ b/dts/src/arm64/freescale/imx8ulp.dtsi @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + */ + +#include <dt-bindings/clock/imx8ulp-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/imx8ulp-power.h> + +#include "imx8ulp-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpiod; + gpio1 = &gpioe; + gpio2 = &gpiof; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + mmc2 = &usdhc2; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@2d400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ + <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ + }; + + frosc: clock-frosc { + compatible = "fixed-clock"; + clock-frequency = <192000000>; + clock-output-names = "frosc"; + #clock-cells = <0>; + }; + + lposc: clock-lposc { + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "lposc"; + #clock-cells = <0>; + }; + + rosc: clock-rosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "rosc"; + #clock-cells = <0>; + }; + + sosc: clock-sosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "sosc"; + #clock-cells = <0>; + }; + + sram@2201f000 { + compatible = "mmio-sram"; + reg = <0x0 0x2201f000 0x0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x2201f000 0x1000>; + + scmi_buf: scmi-buf@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x400>; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0xc20000fe>; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&scmi_buf>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <0>; + }; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + + per_bridge3: bus@29000000 { + compatible = "simple-bus"; + reg = <0x29000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + wdog3: watchdog@292a0000 { + compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; + reg = <0x292a0000 0x10000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; + assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + timeout-sec = <40>; + }; + + cgc1: clock-controller@292c0000 { + compatible = "fsl,imx8ulp-cgc1"; + reg = <0x292c0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; + clock-names = "rosc", "sosc", "frosc", "lposc"; + #clock-cells = <1>; + }; + + pcc3: clock-controller@292d0000 { + compatible = "fsl,imx8ulp-pcc3"; + reg = <0x292d0000 0x10000>; + #clock-cells = <1>; + }; + + tpm5: tpm@29340000 { + compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; + reg = <0x29340000 0x1000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_TPM5>, + <&pcc3 IMX8ULP_CLK_TPM5>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + lpi2c4: i2c@29370000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29370000 0x10000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, + <&pcc3 IMX8ULP_CLK_LPI2C4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c5: i2c@29380000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29380000 0x10000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, + <&pcc3 IMX8ULP_CLK_LPI2C5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart4: serial@29390000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29390000 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@293a0000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x293a0000 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpspi4: spi@293b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293b0000 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, + <&pcc3 IMX8ULP_CLK_LPSPI4>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <16000000>; + status = "disabled"; + }; + + lpspi5: spi@293c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; + reg = <0x293c0000 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, + <&pcc3 IMX8ULP_CLK_LPSPI5>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <16000000>; + status = "disabled"; + }; + }; + + per_bridge4: bus@29800000 { + compatible = "simple-bus"; + reg = <0x29800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pcc4: clock-controller@29800000 { + compatible = "fsl,imx8ulp-pcc4"; + reg = <0x29800000 0x10000>; + #clock-cells = <1>; + }; + + lpi2c6: i2c@29840000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29840000 0x10000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, + <&pcc4 IMX8ULP_CLK_LPI2C6>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c7: i2c@29850000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29850000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, + <&pcc4 IMX8ULP_CLK_LPI2C7>; + clock-names = "per", "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart6: serial@29860000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29860000 0x1000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart7: serial@29870000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29870000 0x1000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc1: pinctrl@298c0000 { + compatible = "fsl,imx8ulp-iomuxc1"; + reg = <0x298c0000 0x10000>; + }; + + usdhc0: mmc@298d0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298d0000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC0>; + clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc1: mmc@298e0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298e0000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@298f0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298f0000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + }; + + gpioe: gpio@2d000000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, + <&pcc4 IMX8ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 24>; + }; + + gpiof: gpio@2d010000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, + <&pcc4 IMX8ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 32>; + }; + + per_bridge5: bus@2d800000 { + compatible = "simple-bus"; + reg = <0x2d800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cgc2: clock-controller@2da60000 { + compatible = "fsl,imx8ulp-cgc2"; + reg = <0x2da60000 0x10000>; + clocks = <&sosc>, <&frosc>; + clock-names = "sosc", "frosc"; + #clock-cells = <1>; + }; + + pcc5: clock-controller@2da70000 { + compatible = "fsl,imx8ulp-pcc5"; + reg = <0x2da70000 0x10000>; + #clock-cells = <1>; + }; + }; + + gpiod: gpio@2e200000 { + compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; + reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, + <&pcc5 IMX8ULP_CLK_RGPIOD>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 0 24>; + }; + }; +}; diff --git a/dts/src/arm64/freescale/mba8mx.dtsi b/dts/src/arm64/freescale/mba8mx.dtsi new file mode 100644 index 0000000000..f27e3c8de9 --- /dev/null +++ b/dts/src/arm64/freescale/mba8mx.dtsi @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2020-2021 TQ-Systems GmbH + */ + +#include <dt-bindings/net/ti-dp83867.h> + +/* TQ-Systems GmbH MBa8Mx baseboard */ + +/ { + beeper { + compatible = "pwm-beeper"; + pwms = <&pwm4 0 250000 0>; + beeper-hz = <4000>; + amp-supply = <®_vcc_3v3>; + }; + + chosen { + // bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200"; + stdout-path = &uart3; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobutton>; + autorepeat; + + switch1 { + label = "switch1"; + linux,code = <BTN_0>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + btn2: switch2 { + label = "switch2"; + linux,code = <BTN_1>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch3 { + label = "switch3"; + linux,code = <BTN_2>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led1 { + label = "led1"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2: led2 { + label = "led2"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_hub_vbus: regulator-hub-vbus { + compatible = "regulator-fixed"; + regulator-name = "MBA8MX_HUB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_sn65dsi83_1v8: regulator-sn65dsi83-1v8 { + compatible = "regulator-fixed"; + regulator-name = "SN65DSI83_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&expander0 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "MBA8MX_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + ssi-controller = <&sai3>; + audio-codec = <&tlv320aic3x04>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-supply = <®_vcc_3v3>; + fsl,magic-packet; + mac-address = [ 00 00 00 00 00 00 ]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@e { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0xe>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + enet-phy-lane-no-swap; + reset-gpios = <&expander2 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <500>; + }; + }; +}; + +&i2c1 { + expander0: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + sd-mux-oe-hog { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "SD_MUX_EN#"; + }; + + boot-cfg-oe-hog { + gpio-hog; + gpios = <12 0>; + output-high; + line-name = "BOOT_CFG_OE#"; + }; + + rst-usb-hub-hog { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "RST_USB_HUB#"; + }; + }; + + expander1: gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_vcc_3v3>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + reset-gpios = <&expander2 0 GPIO_ACTIVE_LOW>; + iov-supply = <®_vcc_3v3>; + ldoin-supply = <®_vcc_3v3>; + }; + + sensor1: sensor@1f { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1f>; + }; + + eeprom3: eeprom@57 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + #sound-dai-cells = <0>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 is assigned to Cortex-M4 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; |