diff options
Diffstat (limited to 'dts/src/arm64/hisilicon/hi3660.dtsi')
| -rw-r--r-- | dts/src/arm64/hisilicon/hi3660.dtsi | 89 |
1 files changed, 65 insertions, 24 deletions
diff --git a/dts/src/arm64/hisilicon/hi3660.dtsi b/dts/src/arm64/hisilicon/hi3660.dtsi index 253cc345f1..7e137a884a 100644 --- a/dts/src/arm64/hisilicon/hi3660.dtsi +++ b/dts/src/arm64/hisilicon/hi3660.dtsi @@ -2,7 +2,7 @@ /* * dts file for Hisilicon Hi3660 SoC * - * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2016, HiSilicon Ltd. */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -203,14 +203,18 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; A73_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -245,7 +249,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; @@ -479,7 +483,7 @@ reg = <0x0 0xfdf00000 0x0 0x1000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; - dmas = <&dma0 2 &dma0 3>; + dmas = <&dma0 2 &dma0 3>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, <&crg_ctrl HI3660_CLK_GATE_UART1>; clock-names = "uartclk", "apb_pclk"; @@ -493,7 +497,7 @@ reg = <0x0 0xfdf03000 0x0 0x1000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; - dmas = <&dma0 4 &dma0 5>; + dmas = <&dma0 4 &dma0 5>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, <&crg_ctrl HI3660_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -519,7 +523,7 @@ reg = <0x0 0xfdf01000 0x0 0x1000>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; - dmas = <&dma0 6 &dma0 7>; + dmas = <&dma0 6 &dma0 7>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, <&crg_ctrl HI3660_CLK_GATE_UART4>; clock-names = "uartclk", "apb_pclk"; @@ -533,7 +537,7 @@ reg = <0x0 0xfdf05000 0x0 0x1000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; - dmas = <&dma0 8 &dma0 9>; + dmas = <&dma0 8 &dma0 9>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; @@ -971,10 +975,10 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&spi2_pmx_func>; + pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; num-cs = <1>; cs-gpios = <&gpio27 2 0>; status = "disabled"; @@ -986,10 +990,10 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&spi3_pmx_func>; + pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; num-cs = <1>; cs-gpios = <&gpio18 5 0>; status = "disabled"; @@ -1002,7 +1006,7 @@ <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xf5000000 0x0 0x2000>; reg-names = "dbi", "apb", "phy", "config"; - bus-range = <0x0 0x1>; + bus-range = <0x0 0xff>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -1045,7 +1049,8 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; + freq-table-hz = <0 0>, + <0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; @@ -1086,19 +1091,21 @@ }; watchdog0: watchdog@e8a06000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xe8a06000 0x0 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg_ctrl HI3660_OSC32K>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "wdog_clk", "apb_pclk"; }; watchdog1: watchdog@e8a07000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xe8a07000 0x0 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg_ctrl HI3660_OSC32K>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "wdog_clk", "apb_pclk"; }; tsensor: tsensor@fff30000 { @@ -1110,7 +1117,7 @@ thermal-zones { - cls0: cls0 { + cls0: cls0-thermal { polling-delay = <1000>; polling-delay-passive = <100>; sustainable-power = <4500>; @@ -1119,13 +1126,13 @@ thermal-sensors = <&tsensor 1>; trips { - threshold: trip-point@0 { + threshold: trip-point0 { temperature = <65000>; hysteresis = <1000>; type = "passive"; }; - target: trip-point@1 { + target: trip-point1 { temperature = <75000>; hysteresis = <1000>; type = "passive"; @@ -1152,6 +1159,40 @@ }; }; }; + + usb3_otg_bc: usb3_otg_bc@ff200000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0xff200000 0x0 0x1000>; + + usb_phy: usb-phy { + compatible = "hisilicon,hi3660-usb-phy"; + #phy-cells = <0>; + hisilicon,pericrg-syscon = <&crg_ctrl>; + hisilicon,pctrl-syscon = <&pctrl>; + hisilicon,eye-diagram-param = <0x22466e4>; + }; + }; + + dwc3: usb@ff100000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff100000 0x0 0x100000>; + + clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, + <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + clock-names = "ref", "bus_early"; + + assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + assigned-clock-rates = <229000000>; + + resets = <&crg_rst 0x90 8>, + <&crg_rst 0x90 7>, + <&crg_rst 0x90 6>, + <&crg_rst 0x90 5>; + + interrupts = <0 159 4>, <0 161 4>; + phys = <&usb_phy>; + phy-names = "usb3-phy"; + }; }; }; |