summaryrefslogtreecommitdiffstats
path: root/dts/src/arm64/hisilicon/hi3660.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'dts/src/arm64/hisilicon/hi3660.dtsi')
-rw-r--r--dts/src/arm64/hisilicon/hi3660.dtsi16
1 files changed, 14 insertions, 2 deletions
diff --git a/dts/src/arm64/hisilicon/hi3660.dtsi b/dts/src/arm64/hisilicon/hi3660.dtsi
index f432b0a88c..20ae40df61 100644
--- a/dts/src/arm64/hisilicon/hi3660.dtsi
+++ b/dts/src/arm64/hisilicon/hi3660.dtsi
@@ -79,6 +79,7 @@
capacity-dmips-mhz = <592>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
cpu2: cpu@2 {
@@ -91,6 +92,7 @@
capacity-dmips-mhz = <592>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
cpu3: cpu@3 {
@@ -103,6 +105,7 @@
capacity-dmips-mhz = <592>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
cpu4: cpu@100 {
@@ -129,6 +132,7 @@
capacity-dmips-mhz = <1024>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
};
cpu6: cpu@102 {
@@ -141,6 +145,7 @@
capacity-dmips-mhz = <1024>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
};
cpu7: cpu@103 {
@@ -153,6 +158,7 @@
capacity-dmips-mhz = <1024>;
clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
};
idle-states {
@@ -1112,12 +1118,18 @@
map0 {
trip = <&target>;
contribution = <1024>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&target>;
contribution = <512>;
- cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};