diff options
Diffstat (limited to 'dts/src/arm64/mediatek/mt8173.dtsi')
| -rw-r--r-- | dts/src/arm64/mediatek/mt8173.dtsi | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/dts/src/arm64/mediatek/mt8173.dtsi b/dts/src/arm64/mediatek/mt8173.dtsi index cac4cd0a03..3458be7f7f 100644 --- a/dts/src/arm64/mediatek/mt8173.dtsi +++ b/dts/src/arm64/mediatek/mt8173.dtsi @@ -222,14 +222,14 @@ }; }; - pmu_a53 { + pmu-a53 { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; interrupt-affinity = <&cpu0>, <&cpu1>; }; - pmu_a72 { + pmu-a72 { compatible = "arm,cortex-a72-pmu"; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; @@ -286,7 +286,7 @@ type = "passive"; }; - cpu_crit: cpu_crit0 { + cpu_crit: cpu-crit0 { temperature = <115000>; hysteresis = <2000>; type = "critical"; @@ -318,7 +318,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; - vpu_dma_reserved: vpu_dma_mem_region@b7000000 { + vpu_dma_reserved: vpu-dma-mem@b7000000 { compatible = "shared-dma-pool"; reg = <0 0xb7000000 0 0x500000>; alignment = <0x1000>; @@ -366,7 +366,7 @@ #reset-cells = <1>; }; - syscfg_pctl_a: syscfg_pctl_a@10005000 { + syscfg_pctl_a: syscon@10005000 { compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; }; @@ -590,6 +590,15 @@ reg = <0 0x10206000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + socinfo-data1@40 { + reg = <0x040 0x4>; + }; + + socinfo-data2@44 { + reg = <0x044 0x4>; + }; + thermal_calibration: calib@528 { reg = <0x528 0xc>; }; |