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-rw-r--r--dts/src/arm64/mediatek/mt8183.dtsi17
1 files changed, 5 insertions, 12 deletions
diff --git a/dts/src/arm64/mediatek/mt8183.dtsi b/dts/src/arm64/mediatek/mt8183.dtsi
index 4b08691ed3..01e6502519 100644
--- a/dts/src/arm64/mediatek/mt8183.dtsi
+++ b/dts/src/arm64/mediatek/mt8183.dtsi
@@ -197,7 +197,7 @@
};
};
- gpu_opp_table: opp_table0 {
+ gpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -682,8 +682,8 @@
compatible = "mediatek,mt8183-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
- &larb4 &larb5 &larb6>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
+ <&larb4>, <&larb5>, <&larb6>;
#iommu-cells = <1>;
};
@@ -823,7 +823,7 @@
};
thermal_zones: thermal-zones {
- cpu_thermal: cpu_thermal {
+ cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
@@ -1396,7 +1396,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
};
@@ -1407,7 +1406,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
@@ -1418,7 +1416,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
@@ -1429,7 +1426,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <5120>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
@@ -1441,7 +1437,6 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <2048>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
@@ -1466,8 +1461,7 @@
};
aal0: aal@14010000 {
- compatible = "mediatek,mt8183-disp-aal",
- "mediatek,mt8173-disp-aal";
+ compatible = "mediatek,mt8183-disp-aal";
reg = <0 0x14010000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
@@ -1598,7 +1592,6 @@
compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
reg = <0 0x17030000 0 0x1000>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb4>;
iommus = <&iommu M4U_PORT_JPGENC_RDMA>,
<&iommu M4U_PORT_JPGENC_BSDMA>;
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;