diff options
Diffstat (limited to 'dts/src/arm64/mediatek/mt8183.dtsi')
| -rw-r--r-- | dts/src/arm64/mediatek/mt8183.dtsi | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/dts/src/arm64/mediatek/mt8183.dtsi b/dts/src/arm64/mediatek/mt8183.dtsi index 5b782a4769..80519a145f 100644 --- a/dts/src/arm64/mediatek/mt8183.dtsi +++ b/dts/src/arm64/mediatek/mt8183.dtsi @@ -6,7 +6,7 @@ */ #include <dt-bindings/clock/mt8183-clk.h> -#include <dt-bindings/gce/mt8173-gce.h> +#include <dt-bindings/gce/mt8183-gce.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/memory/mt8183-larb-port.h> @@ -360,7 +360,7 @@ #size-cells = <0>; #power-domain-cells = <1>; - power-domain@MT8183_POWER_DOMAIN_MFG { + mfg: power-domain@MT8183_POWER_DOMAIN_MFG { reg = <MT8183_POWER_DOMAIN_MFG>; #address-cells = <1>; #size-cells = <0>; @@ -661,12 +661,27 @@ compatible = "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; #pwm-cells = <2>; clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, <&infracfg CLK_INFRA_DISP_PWM>; clock-names = "main", "mm"; }; + pwm1: pwm@11006000 { + compatible = "mediatek,mt8183-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_PWM>, + <&infracfg CLK_INFRA_PWM_HCLK>, + <&infracfg CLK_INFRA_PWM1>, + <&infracfg CLK_INFRA_PWM2>, + <&infracfg CLK_INFRA_PWM3>, + <&infracfg CLK_INFRA_PWM4>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4"; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8183-i2c"; reg = <0 0x1100f000 0 0x1000>, @@ -1011,7 +1026,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,larb = <&larb0>; - mediatek,rdma_fifo_size = <5120>; + mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; @@ -1023,7 +1038,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,larb = <&larb0>; - mediatek,rdma_fifo_size = <2048>; + mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; @@ -1055,8 +1070,7 @@ }; gamma0: gamma@14011000 { - compatible = "mediatek,mt8183-disp-gamma", - "mediatek,mt8173-disp-gamma"; + compatible = "mediatek,mt8183-disp-gamma"; reg = <0 0x14011000 0 0x1000>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; |