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-rw-r--r--dts/src/arm64/qcom/msm8916.dtsi1099
1 files changed, 922 insertions, 177 deletions
diff --git a/dts/src/arm64/qcom/msm8916.dtsi b/dts/src/arm64/qcom/msm8916.dtsi
index 3f85e34a8c..e423c57ddd 100644
--- a/dts/src/arm64/qcom/msm8916.dtsi
+++ b/dts/src/arm64/qcom/msm8916.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -18,11 +19,6 @@
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
- sdhc2 = &sdhc_2; /* SDC2 SD card slot */
- };
-
chosen { };
memory@80000000 {
@@ -41,9 +37,13 @@
no-map;
};
- smem_mem: smem_region@86300000 {
+ smem@86300000 {
+ compatible = "qcom,smem";
reg = <0x0 0x86300000 0x0 0x100000>;
no-map;
+
+ hwlocks = <&tcsr_mutex 3>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
};
hypervisor@86400000 {
@@ -75,23 +75,43 @@
};
mpss_mem: mpss@86800000 {
- reg = <0x0 0x86800000 0x0 0x2b00000>;
+ /*
+ * The memory region for the mpss firmware is generally
+ * relocatable and could be allocated dynamically.
+ * However, many firmware versions tend to fail when
+ * loaded to some special addresses, so it is hard to
+ * define reliable alloc-ranges.
+ *
+ * alignment = <0x0 0x400000>;
+ * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+ */
+ reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
no-map;
+ status = "disabled";
};
- wcnss_mem: wcnss@89300000 {
- reg = <0x0 0x89300000 0x0 0x600000>;
+ wcnss_mem: wcnss {
+ size = <0x0 0x600000>;
+ alignment = <0x0 0x100000>;
+ alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
no-map;
+ status = "disabled";
};
- venus_mem: venus@89900000 {
- reg = <0x0 0x89900000 0x0 0x600000>;
+ venus_mem: venus {
+ size = <0x0 0x500000>;
+ alignment = <0x0 0x100000>;
+ alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
no-map;
+ status = "disabled";
};
- mba_mem: mba@8ea00000 {
+ mba_mem: mba {
+ size = <0x0 0x100000>;
+ alignment = <0x0 0x100000>;
+ alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
no-map;
- reg = <0 0x8ea00000 0 0x100000>;
+ status = "disabled";
};
};
@@ -124,6 +144,8 @@
#cooling-cells = <2>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,acc = <&cpu0_acc>;
+ qcom,saw = <&cpu0_saw>;
};
CPU1: cpu@1 {
@@ -137,6 +159,8 @@
#cooling-cells = <2>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
+ qcom,acc = <&cpu1_acc>;
+ qcom,saw = <&cpu1_saw>;
};
CPU2: cpu@2 {
@@ -150,6 +174,8 @@
#cooling-cells = <2>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
+ qcom,acc = <&cpu2_acc>;
+ qcom,saw = <&cpu2_saw>;
};
CPU3: cpu@3 {
@@ -163,11 +189,14 @@
#cooling-cells = <2>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
+ qcom,acc = <&cpu3_acc>;
+ qcom,saw = <&cpu3_saw>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
idle-states {
@@ -204,7 +233,7 @@
};
};
- cpu_opp_table: cpu-opp-table {
+ cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
@@ -274,10 +303,10 @@
};
};
- smd {
- compatible = "qcom,smd";
+ rpm: remoteproc {
+ compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
- rpm {
+ smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
@@ -287,8 +316,10 @@
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
- compatible = "qcom,rpmcc-msm8916";
+ compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
#clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
};
rpmpd: power-controller {
@@ -323,15 +354,6 @@
};
};
- smem {
- compatible = "qcom,smem";
-
- memory-region = <&smem_mem>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
-
- hwlocks = <&tcsr_mutex 3>;
- };
-
smp2p-hexagon {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
@@ -414,7 +436,7 @@
};
};
- soc: soc {
+ soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
@@ -433,38 +455,113 @@
};
qfprom: qfprom@5c000 {
- compatible = "qcom,qfprom";
+ compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
reg = <0x0005c000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- tsens_caldata: caldata@d0 {
- reg = <0xd0 0x8>;
+
+ tsens_base1: base1@d0 {
+ reg = <0xd0 0x1>;
+ bits = <0 7>;
+ };
+
+ tsens_s0_p1: s0-p1@d0 {
+ reg = <0xd0 0x2>;
+ bits = <7 5>;
+ };
+
+ tsens_s0_p2: s0-p2@d1 {
+ reg = <0xd1 0x2>;
+ bits = <4 5>;
};
- tsens_calsel: calsel@ec {
- reg = <0xec 0x4>;
+
+ tsens_s1_p1: s1-p1@d2 {
+ reg = <0xd2 0x1>;
+ bits = <1 5>;
+ };
+ tsens_s1_p2: s1-p2@d2 {
+ reg = <0xd2 0x2>;
+ bits = <6 5>;
+ };
+ tsens_s2_p1: s2-p1@d3 {
+ reg = <0xd3 0x1>;
+ bits = <3 5>;
+ };
+
+ tsens_s2_p2: s2-p2@d4 {
+ reg = <0xd4 0x1>;
+ bits = <0 5>;
+ };
+
+ // no tsens with hw_id 3
+
+ tsens_s4_p1: s4-p1@d4 {
+ reg = <0xd4 0x2>;
+ bits = <5 5>;
+ };
+
+ tsens_s4_p2: s4-p2@d5 {
+ reg = <0xd5 0x1>;
+ bits = <2 5>;
+ };
+
+ tsens_s5_p1: s5-p1@d5 {
+ reg = <0xd5 0x2>;
+ bits = <7 5>;
+ };
+
+ tsens_s5_p2: s5-p2@d6 {
+ reg = <0xd6 0x2>;
+ bits = <4 5>;
+ };
+
+ tsens_base2: base2@d7 {
+ reg = <0xd7 0x1>;
+ bits = <1 7>;
+ };
+
+ tsens_mode: mode@ef {
+ reg = <0xef 0x1>;
+ bits = <5 3>;
};
};
- rpm_msg_ram: memory@60000 {
+ rpm_msg_ram: sram@60000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x00060000 0x8000>;
};
+ sram@290000 {
+ compatible = "qcom,msm8916-rpm-stats";
+ reg = <0x00290000 0x10000>;
+ };
+
bimc: interconnect@400000 {
compatible = "qcom,msm8916-bimc";
reg = <0x00400000 0x62000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
- <&rpmcc RPM_SMD_BIMC_A_CLK>;
};
tsens: thermal-sensor@4a9000 {
compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
reg = <0x004a9000 0x1000>, /* TM */
<0x004a8000 0x1000>; /* SROT */
- nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
- nvmem-cell-names = "calib", "calib_sel";
+
+ // no hw_id 3
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base1>, <&tsens_base2>,
+ <&tsens_s0_p1>, <&tsens_s0_p2>,
+ <&tsens_s1_p1>, <&tsens_s1_p2>,
+ <&tsens_s2_p1>, <&tsens_s2_p2>,
+ <&tsens_s4_p1>, <&tsens_s4_p2>,
+ <&tsens_s5_p1>, <&tsens_s5_p2>;
+ nvmem-cell-names = "mode",
+ "base1", "base2",
+ "s0_p1", "s0_p2",
+ "s1_p1", "s1_p2",
+ "s2_p1", "s2_p2",
+ "s4_p1", "s4_p2",
+ "s5_p1", "s5_p2";
#qcom,sensors = <5>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
@@ -475,18 +572,12 @@
compatible = "qcom,msm8916-pcnoc";
reg = <0x00500000 0x11000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
- <&rpmcc RPM_SMD_PCNOC_A_CLK>;
};
snoc: interconnect@580000 {
compatible = "qcom,msm8916-snoc";
reg = <0x00580000 0x14000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
- <&rpmcc RPM_SMD_SNOC_A_CLK>;
};
stm: stm@802000 {
@@ -909,15 +1000,494 @@
};
};
- msmgpio: pinctrl@1000000 {
+ tlmm: pinctrl@1000000 {
compatible = "qcom,msm8916-pinctrl";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
- gpio-ranges = <&msmgpio 0 0 122>;
+ gpio-ranges = <&tlmm 0 0 122>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ blsp_i2c1_default: blsp-i2c1-default-state {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c1_sleep: blsp-i2c1-sleep-state {
+ pins = "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c2_default: blsp-i2c2-default-state {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c2_sleep: blsp-i2c2-sleep-state {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c3_default: blsp-i2c3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c3_sleep: blsp-i2c3-sleep-state {
+ pins = "gpio10", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c4_default: blsp-i2c4-default-state {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c4_sleep: blsp-i2c4-sleep-state {
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c5_default: blsp-i2c5-default-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c5_sleep: blsp-i2c5-sleep-state {
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c6_default: blsp-i2c6-default-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c6_sleep: blsp-i2c6-sleep-state {
+ pins = "gpio22", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_spi1_default: blsp-spi1-default-state {
+ spi-pins {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi1_sleep: blsp-spi1-sleep-state {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi2_default: blsp-spi2-default-state {
+ spi-pins {
+ pins = "gpio4", "gpio5", "gpio7";
+ function = "blsp_spi2";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi2_sleep: blsp-spi2-sleep-state {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi3_default: blsp-spi3-default-state {
+ spi-pins {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "blsp_spi3";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio10";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi3_sleep: blsp-spi3-sleep-state {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi4_default: blsp-spi4-default-state {
+ spi-pins {
+ pins = "gpio12", "gpio13", "gpio15";
+ function = "blsp_spi4";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio14";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi4_sleep: blsp-spi4-sleep-state {
+ pins = "gpio12", "gpio13", "gpio14", "gpio15";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi5_default: blsp-spi5-default-state {
+ spi-pins {
+ pins = "gpio16", "gpio17", "gpio19";
+ function = "blsp_spi5";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi5_sleep: blsp-spi5-sleep-state {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi6_default: blsp-spi6-default-state {
+ spi-pins {
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio22";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi6_sleep: blsp-spi6-sleep-state {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_uart1_default: blsp-uart1-default-state {
+ /* TX, RX, CTS_N, RTS_N */
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "blsp_uart1";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp_uart1_sleep: blsp-uart1-sleep-state {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_uart2_default: blsp-uart2-default-state {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp_uart2_sleep: blsp-uart2-sleep-state {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ camera_front_default: camera-front-default-state {
+ pwdn-pins {
+ pins = "gpio33";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ rst-pins {
+ pins = "gpio28";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ mclk1-pins {
+ pins = "gpio27";
+ function = "cam_mclk1";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_rear_default: camera-rear-default-state {
+ pwdn-pins {
+ pins = "gpio34";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ rst-pins {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ mclk0-pins {
+ pins = "gpio26";
+ function = "cam_mclk0";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ cci0_default: cci0-default-state {
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cdc_dmic_default: cdc-dmic-default-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "dmic0_clk";
+ drive-strength = <8>;
+ };
+ data-pins {
+ pins = "gpio1";
+ function = "dmic0_data";
+ drive-strength = <8>;
+ };
+ };
+
+ cdc_dmic_sleep: cdc-dmic-sleep-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "dmic0_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ data-pins {
+ pins = "gpio1";
+ function = "dmic0_data";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ cdc_pdm_default: cdc-pdm-default-state {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ function = "cdc_pdm0";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cdc_pdm_sleep: cdc-pdm-sleep-state {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ function = "cdc_pdm0";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ pri_mi2s_default: mi2s-pri-default-state {
+ pins = "gpio113", "gpio114", "gpio115", "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pri_mi2s_sleep: mi2s-pri-sleep-state {
+ pins = "gpio113", "gpio114", "gpio115", "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
+ pins = "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
+ pins = "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pri_mi2s_ws_default: mi2s-pri-ws-default-state {
+ pins = "gpio110";
+ function = "pri_mi2s_ws";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
+ pins = "gpio110";
+ function = "pri_mi2s_ws";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sec_mi2s_default: mi2s-sec-default-state {
+ pins = "gpio112", "gpio117", "gpio118", "gpio119";
+ function = "sec_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ sec_mi2s_sleep: mi2s-sec-sleep-state {
+ pins = "gpio112", "gpio117", "gpio118", "gpio119";
+ function = "sec_mi2s";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc1_default: sdc1-default-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc1_sleep: sdc1-sleep-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ wcss_wlan_default: wcss-wlan-default-state {
+ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "wcss_wlan";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
};
gcc: clock-controller@1800000 {
@@ -926,6 +1496,20 @@
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x01800000 0x80000>;
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "xo",
+ "sleep_clk",
+ "dsi0pll",
+ "dsi0pllbyte",
+ "ext_mclk",
+ "ext_pri_i2s",
+ "ext_sec_i2s";
};
tcsr_mutex: hwlock@1905000 {
@@ -939,7 +1523,7 @@
reg = <0x01937000 0x30000>;
};
- mdss: mdss@1a00000 {
+ mdss: display-subsystem@1a00000 {
status = "disabled";
compatible = "qcom,mdss";
reg = <0x01a00000 0x1000>,
@@ -964,8 +1548,8 @@
#size-cells = <1>;
ranges;
- mdp: mdp@1a01000 {
- compatible = "qcom,mdp5";
+ mdss_mdp: display-controller@1a01000 {
+ compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
@@ -989,15 +1573,16 @@
port@0 {
reg = <0>;
- mdp5_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ mdss_mdp_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
};
};
};
};
- dsi0: dsi@1a98000 {
- compatible = "qcom,mdss-dsi-ctrl";
+ mdss_dsi0: dsi@1a98000 {
+ compatible = "qcom,msm8916-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
reg = <0x01a98000 0x25c>;
reg-names = "dsi_ctrl";
@@ -1006,8 +1591,8 @@
assigned-clocks = <&gcc BYTE0_CLK_SRC>,
<&gcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&dsi_phy0 0>,
- <&dsi_phy0 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
@@ -1021,8 +1606,7 @@
"byte",
"pixel",
"core";
- phys = <&dsi_phy0>;
- phy-names = "dsi-phy";
+ phys = <&mdss_dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1033,20 +1617,20 @@
port@0 {
reg = <0>;
- dsi0_in: endpoint {
- remote-endpoint = <&mdp5_intf1_out>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&mdss_mdp_intf1_out>;
};
};
port@1 {
reg = <1>;
- dsi0_out: endpoint {
+ mdss_dsi0_out: endpoint {
};
};
};
};
- dsi_phy0: dsi-phy@1a98300 {
+ mdss_dsi0_phy: phy@1a98300 {
compatible = "qcom,dsi-phy-28nm-lp";
reg = <0x01a98300 0xd4>,
<0x01a98500 0x280>,
@@ -1064,7 +1648,7 @@
};
};
- camss: camss@1b00000 {
+ camss: camss@1b0ac00 {
compatible = "qcom,msm8916-camss";
reg = <0x01b0ac00 0x200>,
<0x01b00030 0x4>,
@@ -1140,11 +1724,19 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
};
};
cci: cci@1b0c000 {
- compatible = "qcom,msm8916-cci";
+ compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01b0c000 0x1000>;
@@ -1170,7 +1762,7 @@
};
};
- gpu@1c00000 {
+ gpu: gpu@1c00000 {
compatible = "qcom,adreno-306.0", "qcom,adreno";
reg = <0x01c00000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
@@ -1193,6 +1785,7 @@
power-domains = <&gcc OXILI_GDSC>;
operating-points-v2 = <&gpu_opp_table>;
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+ status = "disabled";
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -1217,7 +1810,7 @@
clock-names = "core", "iface", "bus";
iommus = <&apps_iommu 5>;
memory-region = <&venus_mem>;
- status = "okay";
+ status = "disabled";
video-decoder {
compatible = "venus-decoder";
@@ -1233,28 +1826,28 @@
#size-cells = <1>;
#iommu-cells = <1>;
compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
- ranges = <0 0x01e20000 0x40000>;
+ ranges = <0 0x01e20000 0x20000>;
reg = <0x01ef0000 0x3000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_CLK>;
clock-names = "iface", "bus";
qcom,iommu-secure-id = <17>;
- // vfe:
+ /* VFE */
iommu-ctx@3000 {
compatible = "qcom,msm-iommu-v1-sec";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
};
- // mdp_0:
+ /* MDP_0 */
iommu-ctx@4000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x4000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
};
- // venus_ns:
+ /* VENUS_NS */
iommu-ctx@5000 {
compatible = "qcom,msm-iommu-v1-sec";
reg = <0x5000 0x1000>;
@@ -1273,14 +1866,14 @@
clock-names = "iface", "bus";
qcom,iommu-secure-id = <18>;
- // gfx3d_user:
+ /* GFX3D_USER */
iommu-ctx@1000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
};
- // gfx3d_priv:
+ /* GFX3D_PRIV */
iommu-ctx@2000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x2000 0x1000>;
@@ -1306,8 +1899,22 @@
#interrupt-cells = <4>;
};
+ bam_dmux_dma: dma-controller@4044000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x04044000 0x19000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+
+ num-channels = <6>;
+ qcom,num-ees = <1>;
+ qcom,powered-remotely;
+
+ status = "disabled";
+ };
+
mpss: remoteproc@4080000 {
- compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
+ compatible = "qcom,msm8916-mss-pil";
reg = <0x04080000 0x100>,
<0x04020000 0x040>;
@@ -1349,6 +1956,22 @@
memory-region = <&mpss_mem>;
};
+ bam_dmux: bam-dmux {
+ compatible = "qcom,bam-dmux";
+
+ interrupt-parent = <&hexagon_smsm>;
+ interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "pc", "pc-ack";
+
+ qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
+ qcom,smem-state-names = "pc", "pc-ack";
+
+ dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
+ dma-names = "tx", "rx";
+
+ status = "disabled";
+ };
+
smd-edge {
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
@@ -1358,10 +1981,59 @@
label = "hexagon";
+ apr: apr {
+ compatible = "qcom,apr-v2";
+ qcom,smd-channels = "apr_audio_svc";
+ qcom,domain = <APR_DOMAIN_ADSP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ q6core: service@3 {
+ compatible = "qcom,q6core";
+ reg = <APR_SVC_ADSP_CORE>;
+ };
+
+ q6afe: service@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6asm: service@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6adm: service@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+
+ q6routing: routing {
+ compatible = "qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
fastrpc {
compatible = "qcom,fastrpc";
qcom,smd-channels = "fastrpcsmd-apps-dsp";
label = "adsp";
+ qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
@@ -1383,22 +2055,28 @@
lpass: audio-controller@7708000 {
status = "disabled";
- compatible = "qcom,lpass-cpu-apq8016";
+ compatible = "qcom,apq8016-lpass-cpu";
+
+ /*
+ * Note: Unlike the name would suggest, the SEC_I2S_CLK
+ * is actually only used by Tertiary MI2S while
+ * Primary/Secondary MI2S both use the PRI_I2S_CLK.
+ */
clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
- <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
- <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
+ <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
- <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
- <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
+ <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
+ <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
+ <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
clock-names = "ahbix-clk",
- "pcnoc-mport-clk",
- "pcnoc-sway-clk",
"mi2s-bit-clk0",
"mi2s-bit-clk1",
"mi2s-bit-clk2",
- "mi2s-bit-clk3";
+ "mi2s-bit-clk3",
+ "pcnoc-mport-clk",
+ "pcnoc-sway-clk";
#sound-dai-cells = <1>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
@@ -1417,38 +2095,45 @@
<&gcc GCC_CODEC_DIGCODEC_CLK>;
clock-names = "ahbix-clk", "mclk";
#sound-dai-cells = <1>;
+ status = "disabled";
};
- sdhc_1: sdhci@7824000 {
- compatible = "qcom,sdhci-msm-v4";
+ sdhc_1: mmc@7824900 {
+ compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
+ pinctrl-0 = <&sdc1_default>;
+ pinctrl-1 = <&sdc1_sleep>;
+ pinctrl-names = "default", "sleep";
mmc-ddr-1_8v;
bus-width = <8>;
non-removable;
status = "disabled";
};
- sdhc_2: sdhci@7864000 {
- compatible = "qcom,sdhci-msm-v4";
+ sdhc_2: mmc@7864900 {
+ compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
+ pinctrl-0 = <&sdc2_default>;
+ pinctrl-1 = <&sdc2_sleep>;
+ pinctrl-names = "default", "sleep";
bus-width = <4>;
status = "disabled";
};
@@ -1461,34 +2146,34 @@
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
- status = "disabled";
+ qcom,controlled-remotely;
};
- blsp1_uart1: serial@78af000 {
+ blsp_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 1>, <&blsp_dma 0>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 0>, <&blsp_dma 1>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart1_default>;
- pinctrl-1 = <&blsp1_uart1_sleep>;
+ pinctrl-0 = <&blsp_uart1_default>;
+ pinctrl-1 = <&blsp_uart1_sleep>;
status = "disabled";
};
- blsp1_uart2: serial@78b0000 {
+ blsp_uart2: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b0000 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 3>, <&blsp_dma 2>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 2>, <&blsp_dma 3>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart2_default>;
- pinctrl-1 = <&blsp1_uart2_sleep>;
+ pinctrl-0 = <&blsp_uart2_default>;
+ pinctrl-1 = <&blsp_uart2_sleep>;
status = "disabled";
};
@@ -1496,12 +2181,14 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c1_default>;
- pinctrl-1 = <&i2c1_sleep>;
+ pinctrl-0 = <&blsp_i2c1_default>;
+ pinctrl-1 = <&blsp_i2c1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1514,11 +2201,11 @@
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 5>, <&blsp_dma 4>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi1_default>;
- pinctrl-1 = <&spi1_sleep>;
+ pinctrl-0 = <&blsp_spi1_default>;
+ pinctrl-1 = <&blsp_spi1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1528,12 +2215,14 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c2_default>;
- pinctrl-1 = <&i2c2_sleep>;
+ pinctrl-0 = <&blsp_i2c2_default>;
+ pinctrl-1 = <&blsp_i2c2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1546,11 +2235,11 @@
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 7>, <&blsp_dma 6>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi2_default>;
- pinctrl-1 = <&spi2_sleep>;
+ pinctrl-0 = <&blsp_spi2_default>;
+ pinctrl-1 = <&blsp_spi2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1560,12 +2249,14 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x500>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c3_default>;
- pinctrl-1 = <&i2c3_sleep>;
+ pinctrl-0 = <&blsp_i2c3_default>;
+ pinctrl-1 = <&blsp_i2c3_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1578,11 +2269,11 @@
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 9>, <&blsp_dma 8>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi3_default>;
- pinctrl-1 = <&spi3_sleep>;
+ pinctrl-0 = <&blsp_spi3_default>;
+ pinctrl-1 = <&blsp_spi3_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1592,12 +2283,14 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c4_default>;
- pinctrl-1 = <&i2c4_sleep>;
+ pinctrl-0 = <&blsp_i2c4_default>;
+ pinctrl-1 = <&blsp_i2c4_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1610,11 +2303,11 @@
clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 11>, <&blsp_dma 10>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi4_default>;
- pinctrl-1 = <&spi4_sleep>;
+ pinctrl-0 = <&blsp_spi4_default>;
+ pinctrl-1 = <&blsp_spi4_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1624,12 +2317,14 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_default>;
- pinctrl-1 = <&i2c5_sleep>;
+ pinctrl-0 = <&blsp_i2c5_default>;
+ pinctrl-1 = <&blsp_i2c5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1642,11 +2337,11 @@
clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 13>, <&blsp_dma 12>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi5_default>;
- pinctrl-1 = <&spi5_sleep>;
+ pinctrl-0 = <&blsp_spi5_default>;
+ pinctrl-1 = <&blsp_spi5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1656,12 +2351,14 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078ba000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c6_default>;
- pinctrl-1 = <&i2c6_sleep>;
+ pinctrl-0 = <&blsp_i2c6_default>;
+ pinctrl-1 = <&blsp_i2c6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1674,11 +2371,11 @@
clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 15>, <&blsp_dma 14>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi6_default>;
- pinctrl-1 = <&spi6_sleep>;
+ pinctrl-0 = <&blsp_spi6_default>;
+ pinctrl-1 = <&blsp_spi6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1717,13 +2414,15 @@
clock-names = "ref", "sleep";
resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
reset-names = "phy", "por";
- qcom,init-seq = /bits/ 8 <0x0 0x44
- 0x1 0x6b 0x2 0x24 0x3 0x13>;
+ qcom,init-seq = /bits/ 8 <0x0 0x44>,
+ <0x1 0x6b>,
+ <0x2 0x24>,
+ <0x3 0x13>;
};
};
};
- pronto: remoteproc@a21b000 {
+ wcnss: remoteproc@a204000 {
compatible = "qcom,pronto-v2-pil", "qcom,pronto";
reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
reg-names = "ccu", "dxe", "pmu";
@@ -1741,17 +2440,16 @@
<&rpmpd MSM8916_VDDMX>;
power-domain-names = "cx", "mx";
- qcom,state = <&wcnss_smp2p_out 0>;
- qcom,state-names = "stop";
+ qcom,smem-states = <&wcnss_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
pinctrl-names = "default";
- pinctrl-0 = <&wcnss_pin_a>;
+ pinctrl-0 = <&wcss_wlan_default>;
status = "disabled";
- iris {
- compatible = "qcom,wcn3620";
-
+ wcnss_iris: iris {
+ /* Separate chip, compatible is board-specific */
clocks = <&rpmcc RPM_SMD_RF_CLK2>;
clock-names = "xo";
};
@@ -1765,17 +2463,17 @@
label = "pronto";
- wcnss {
+ wcnss_ctrl: wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
- qcom,mmio = <&pronto>;
+ qcom,mmio = <&wcnss>;
- bt {
+ wcnss_bt: bluetooth {
compatible = "qcom,wcnss-bt";
};
- wifi {
+ wcnss_wifi: wifi {
compatible = "qcom,wcnss-wlan";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
@@ -1811,6 +2509,8 @@
compatible = "qcom,msm8916-a53pll";
reg = <0x0b016000 0x40>;
#clock-cells = <0>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
};
timer@b020000 {
@@ -1871,6 +2571,54 @@
status = "disabled";
};
};
+
+ cpu0_acc: power-manager@b088000 {
+ compatible = "qcom,msm8916-acc";
+ reg = <0x0b088000 0x1000>;
+ status = "reserved"; /* Controlled by PSCI firmware */
+ };
+
+ cpu0_saw: power-manager@b089000 {
+ compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b089000 0x1000>;
+ status = "reserved"; /* Controlled by PSCI firmware */
+ };
+
+ cpu1_acc: power-manager@b098000 {
+ compatible = "qcom,msm8916-acc";
+ reg = <0x0b098000 0x1000>;
+ status = "reserved"; /* Controlled by PSCI firmware */
+ };
+
+ cpu1_saw: power-manager@b099000 {
+ compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b099000 0x1000>;
+ status = "reserved"; /* Controlled by PSCI firmware */
+ };
+
+ cpu2_acc: power-manager@b0a8000 {
+ compatible = "qcom,msm8916-acc";
+ reg = <0x0b0a8000 0x1000>;
+ status = "reserved"; /* Controlled by PSCI firmware */
+ };
+
+ cpu2_saw: power-manager@b0a9000 {
+ compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b0a9000 0x1000>;
+ status = "reserved"; /* Controlled by PSCI firmware */
+ };
+
+ cpu3_acc: power-manager@b0b8000 {
+ compatible = "qcom,msm8916-acc";
+ reg = <0x0b0b8000 0x1000>;
+ status = "reserved"; /* Controlled by PSCI firmware */
+ };
+
+ cpu3_saw: power-manager@b0b9000 {
+ compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b0b9000 0x1000>;
+ status = "reserved"; /* Controlled by PSCI firmware */
+ };
};
thermal-zones {
@@ -1886,7 +2634,7 @@
hysteresis = <2000>;
type = "passive";
};
- cpu0_1_crit: cpu_crit {
+ cpu0_1_crit: cpu-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -1916,7 +2664,7 @@
hysteresis = <2000>;
type = "passive";
};
- cpu2_3_crit: cpu_crit {
+ cpu2_3_crit: cpu-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -1946,7 +2694,7 @@
hysteresis = <2000>;
type = "passive";
};
- gpu_crit: gpu_crit {
+ gpu_crit: gpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -1983,7 +2731,6 @@
};
};
};
-
};
timer {
@@ -1994,5 +2741,3 @@
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
-
-#include "msm8916-pins.dtsi"
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-16 16:38:44 +0000