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-rw-r--r--dts/src/arm64/qcom/msm8994.dtsi426
1 files changed, 253 insertions, 173 deletions
diff --git a/dts/src/arm64/qcom/msm8994.dtsi b/dts/src/arm64/qcom/msm8994.dtsi
index 986fe60dec..8295bf1b21 100644
--- a/dts/src/arm64/qcom/msm8994.dtsi
+++ b/dts/src/arm64/qcom/msm8994.dtsi
@@ -1,9 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
+#include <dt-bindings/clock/qcom,mmcc-msm8994.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>
/ {
@@ -12,6 +16,11 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ mmc1 = &sdhc1;
+ mmc2 = &sdhc2;
+ };
+
chosen { };
clocks {
@@ -43,6 +52,7 @@
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -79,6 +89,7 @@
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
};
@@ -93,7 +104,7 @@
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a57";
- reg = <0x0 0x101>;
+ reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};
@@ -101,7 +112,7 @@
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a57";
- reg = <0x0 0x101>;
+ reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};
@@ -157,12 +168,6 @@
reg = <0 0x80000000 0 0>;
};
- tcsr_mutex: hwlock {
- compatible = "qcom,tcsr-mutex";
- syscon = <&tcsr_mutex_regs 0 0x80>;
- #hwlock-cells = <1>;
- };
-
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
@@ -173,6 +178,56 @@
method = "hvc";
};
+ rpm: remoteproc {
+ compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc";
+
+ smd-edge {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+ qcom,remote-pid = <6>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-msm8994";
+ qcom,smd-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+
+ rpmpd: power-controller {
+ compatible = "qcom,msm8994-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_ret: opp1 {
+ opp-level = <1>;
+ };
+ rpmpd_opp_svs_krait: opp2 {
+ opp-level = <2>;
+ };
+ rpmpd_opp_svs_soc: opp3 {
+ opp-level = <3>;
+ };
+ rpmpd_opp_nom: opp4 {
+ opp-level = <4>;
+ };
+ rpmpd_opp_turbo: opp5 {
+ opp-level = <5>;
+ };
+ rpmpd_opp_super_turbo: opp6 {
+ opp-level = <6>;
+ };
+ };
+ };
+ };
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -183,8 +238,8 @@
no-map;
};
- cont_splash_mem: memory@3800000 {
- reg = <0 0x03800000 0 0x2400000>;
+ cont_splash_mem: memory@3401000 {
+ reg = <0 0x03401000 0 0x2200000>;
no-map;
};
@@ -225,55 +280,10 @@
reg = <0 0xc9400000 0 0x3f00000>;
no-map;
};
- };
-
- smd {
- compatible = "qcom,smd";
- rpm {
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
- qcom,smd-edge = <15>;
- qcom,local-pid = <0>;
- qcom,remote-pid = <6>;
-
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-msm8994";
- qcom,smd-channels = "rpm_requests";
-
- rpmcc: rpmcc {
- compatible = "qcom,rpmcc-msm8994";
- #clock-cells = <1>;
- };
- rpmpd: power-controller {
- compatible = "qcom,msm8994-rpmpd";
- #power-domain-cells = <1>;
- operating-points-v2 = <&rpmpd_opp_table>;
-
- rpmpd_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- rpmpd_opp_ret: opp1 {
- opp-level = <1>;
- };
- rpmpd_opp_svs_krait: opp2 {
- opp-level = <2>;
- };
- rpmpd_opp_svs_soc: opp3 {
- opp-level = <3>;
- };
- rpmpd_opp_nom: opp4 {
- opp-level = <4>;
- };
- rpmpd_opp_turbo: opp5 {
- opp-level = <5>;
- };
- rpmpd_opp_super_turbo: opp6 {
- opp-level = <6>;
- };
- };
- };
- };
+ res_hyp_mem: reserved@6c00000 {
+ reg = <0 0x06c00000 0 0x400000>;
+ no-map;
};
};
@@ -333,8 +343,7 @@
};
};
- soc: soc {
-
+ soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
@@ -354,6 +363,15 @@
#mbox-cells = <1>;
};
+ watchdog@f9017000 {
+ compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
+ reg = <0xf9017000 0x1000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&sleep_clk>;
+ timeout-sec = <10>;
+ };
+
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -413,7 +431,7 @@
};
usb3: usb@f92f8800 {
- compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
+ compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
reg = <0xf92f8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
@@ -423,7 +441,10 @@
<&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
- clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
+ clock-names = "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
@@ -435,7 +456,7 @@
usb@f9200000 {
compatible = "snps,dwc3";
reg = <0xf9200000 0xcc00>;
- interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
maximum-speed = "high-speed";
@@ -443,19 +464,19 @@
};
};
- sdhc1: sdhci@f9824900 {
- compatible = "qcom,sdhci-msm-v4";
+ sdhc1: mmc@f9824900 {
+ compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
@@ -466,25 +487,25 @@
status = "disabled";
};
- sdhc2: sdhci@f98a4900 {
- compatible = "qcom,sdhci-msm-v4";
+ sdhc2: mmc@f98a4900 {
+ compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>,
- <&xo_board>;
- clock-names = "core", "iface", "xo";
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "core", "xo";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
- cd-gpios = <&tlmm 100 0>;
+ cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "disabled";
};
@@ -498,7 +519,7 @@
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
- num-channels = <18>;
+ num-channels = <24>;
qcom,num-ees = <4>;
};
@@ -519,9 +540,9 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9923000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
@@ -540,7 +561,6 @@
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- spi-max-frequency = <19200000>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
@@ -555,9 +575,9 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
dma-names = "tx", "rx";
@@ -575,9 +595,9 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9926000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
dma-names = "tx", "rx";
@@ -593,9 +613,9 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9927000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
@@ -611,9 +631,9 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9928000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
dma-names = "tx", "rx";
@@ -634,7 +654,7 @@
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
- num-channels = <18>;
+ num-channels = <24>;
qcom,num-ees = <4>;
};
@@ -657,9 +677,9 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9963000 0x500>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
dma-names = "tx", "rx";
@@ -678,7 +698,6 @@
clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
- spi-max-frequency = <19200000>;
dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
@@ -693,9 +712,9 @@
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9967000 0x500>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <355000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
@@ -713,9 +732,12 @@
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
+
+ clock-names = "xo", "sleep";
+ clocks = <&xo_board>, <&sleep_clk>;
};
- rpm_msg_ram: memory@fc428000 {
+ rpm_msg_ram: sram@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
@@ -725,7 +747,7 @@
reg = <0xfc4ab000 0x4>;
};
- spmi_bus: spmi@fc4c0000 {
+ spmi_bus: spmi@fc4cf000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xfc4cf000 0x1000>,
<0xfc4cb000 0x1000>,
@@ -741,9 +763,10 @@
#interrupt-cells = <4>;
};
- tcsr_mutex_regs: syscon@fd484000 {
- compatible = "syscon";
- reg = <0xfd484000 0x2000>;
+ tcsr_mutex: hwlock@fd484000 {
+ compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
+ reg = <0xfd484000 0x1000>;
+ #hwlock-cells = <1>;
};
tlmm: pinctrl@fd510000 {
@@ -756,259 +779,316 @@
interrupt-controller;
#interrupt-cells = <2>;
- blsp1_uart2_default: blsp1-uart2-default {
- function = "blsp_uart2";
+ blsp1_uart2_default: blsp1-uart2-default-state {
pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
drive-strength = <16>;
bias-disable;
};
- blsp1_uart2_sleep: blsp1-uart2-sleep {
- function = "gpio";
+ blsp1_uart2_sleep: blsp1-uart2-sleep-state {
pins = "gpio4", "gpio5";
+ function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- blsp2_uart2_default: blsp2-uart2-default {
+ blsp2_uart2_default: blsp2-uart2-default-state {
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "blsp_uart8";
- pins = "gpio45", "gpio46",
- "gpio47", "gpio48";
drive-strength = <16>;
bias-disable;
};
- blsp2_uart2_sleep: blsp2-uart2-sleep {
+ blsp2_uart2_sleep: blsp2-uart2-sleep-state {
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "gpio";
- pins = "gpio45", "gpio46",
- "gpio47", "gpio48";
drive-strength = <2>;
bias-disable;
};
- i2c1_default: i2c1-default {
- function = "blsp_i2c1";
+ i2c1_default: i2c1-default-state {
pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
- i2c1_sleep: i2c1-sleep {
- function = "gpio";
+ i2c1_sleep: i2c1-sleep-state {
pins = "gpio2", "gpio3";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c2_default: i2c2-default {
- function = "blsp_i2c2";
+ i2c2_default: i2c2-default-state {
pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
- i2c2_sleep: i2c2-sleep {
- function = "gpio";
+ i2c2_sleep: i2c2-sleep-state {
pins = "gpio6", "gpio7";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c4_default: i2c4-default {
- function = "blsp_i2c4";
+ i2c4_default: i2c4-default-state {
pins = "gpio19", "gpio20";
+ function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
- i2c4_sleep: i2c4-sleep {
- function = "gpio";
+ i2c4_sleep: i2c4-sleep-state {
pins = "gpio19", "gpio20";
+ function = "gpio";
drive-strength = <2>;
bias-pull-down;
- input-enable;
};
- i2c5_default: i2c5-default {
- function = "blsp_i2c5";
+ i2c5_default: i2c5-default-state {
pins = "gpio23", "gpio24";
+ function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
- i2c5_sleep: i2c5-sleep {
- function = "gpio";
+ i2c5_sleep: i2c5-sleep-state {
pins = "gpio23", "gpio24";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c6_default: i2c6-default {
- function = "blsp_i2c6";
+ i2c6_default: i2c6-default-state {
pins = "gpio28", "gpio27";
+ function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
- i2c6_sleep: i2c6-sleep {
- function = "gpio";
+ i2c6_sleep: i2c6-sleep-state {
pins = "gpio28", "gpio27";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c7_default: i2c7-default {
- function = "blsp_i2c7";
+ i2c7_default: i2c7-default-state {
pins = "gpio44", "gpio43";
+ function = "blsp_i2c7";
drive-strength = <2>;
bias-disable;
};
- i2c7_sleep: i2c7-sleep {
- function = "gpio";
+ i2c7_sleep: i2c7-sleep-state {
pins = "gpio44", "gpio43";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_spi10_default: blsp2-spi10-default {
- default {
- function = "blsp_spi10";
+ blsp2_spi10_default: blsp2-spi10-default-state {
+ default-pins {
pins = "gpio53", "gpio54", "gpio55";
+ function = "blsp_spi10";
drive-strength = <10>;
bias-pull-down;
};
- cs {
+
+ cs-pins {
+ pins = "gpio67";
function = "gpio";
- pins = "gpio55";
drive-strength = <2>;
bias-disable;
};
};
- blsp2_spi10_sleep: blsp2-spi10-sleep {
+ blsp2_spi10_sleep: blsp2-spi10-sleep-state {
pins = "gpio53", "gpio54", "gpio55";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c11_default: i2c11-default {
- function = "blsp_i2c11";
+ i2c11_default: i2c11-default-state {
pins = "gpio83", "gpio84";
+ function = "blsp_i2c11";
drive-strength = <2>;
bias-disable;
};
- i2c11_sleep: i2c11-sleep {
- function = "gpio";
+ i2c11_sleep: i2c11-sleep-state {
pins = "gpio83", "gpio84";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp1_spi1_default: blsp1-spi1-default {
- default {
- function = "blsp_spi1";
+ blsp1_spi1_default: blsp1-spi1-default-state {
+ default-pins {
pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
drive-strength = <10>;
bias-pull-down;
};
- cs {
- function = "gpio";
+
+ cs-pins {
pins = "gpio8";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
- blsp1_spi1_sleep: blsp1-spi1-sleep {
+ blsp1_spi1_sleep: blsp1-spi1-sleep-state {
pins = "gpio0", "gpio1", "gpio3";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- sdc1_clk_on: clk-on {
+ sdc1_clk_on: clk-on-state {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- sdc1_clk_off: clk-off {
+ sdc1_clk_off: clk-off-state {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- sdc1_cmd_on: cmd-on {
+ sdc1_cmd_on: cmd-on-state {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <8>;
};
- sdc1_cmd_off: cmd-off {
+ sdc1_cmd_off: cmd-off-state {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- sdc1_data_on: data-on {
+ sdc1_data_on: data-on-state {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <8>;
};
- sdc1_data_off: data-off {
+ sdc1_data_off: data-off-state {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- sdc1_rclk_on: rclk-on {
+ sdc1_rclk_on: rclk-on-state {
pins = "sdc1_rclk";
bias-pull-down;
};
- sdc1_rclk_off: rclk-off {
+ sdc1_rclk_off: rclk-off-state {
pins = "sdc1_rclk";
bias-pull-down;
};
- sdc2_clk_on: sdc2-clk-on {
+ sdc2_clk_on: sdc2-clk-on-state {
pins = "sdc2_clk";
bias-disable;
drive-strength = <10>;
};
- sdc2_clk_off: sdc2-clk-off {
+ sdc2_clk_off: sdc2-clk-off-state {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- sdc2_cmd_on: sdc2-cmd-on {
+ sdc2_cmd_on: sdc2-cmd-on-state {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- sdc2_cmd_off: sdc2-cmd-off {
+ sdc2_cmd_off: sdc2-cmd-off-state {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- sdc2_data_on: sdc2-data-on {
+ sdc2_data_on: sdc2-data-on-state {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
- sdc2_data_off: sdc2-data-off {
+ sdc2_data_off: sdc2-data-off-state {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
};
+
+ mmcc: clock-controller@fd8c0000 {
+ compatible = "qcom,mmcc-msm8994";
+ reg = <0xfd8c0000 0x5200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ clock-names = "xo",
+ "gpll0",
+ "mmssnoc_ahb",
+ "oxili_gfx3d_clk_src",
+ "dsi0pll",
+ "dsi0pllbyte",
+ "dsi1pll",
+ "dsi1pllbyte",
+ "hdmipll";
+ clocks = <&xo_board>,
+ <&gcc GPLL0_OUT_MMSSCC>,
+ <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
+ <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+
+ assigned-clocks = <&mmcc MMPLL0_PLL>,
+ <&mmcc MMPLL1_PLL>,
+ <&mmcc MMPLL3_PLL>,
+ <&mmcc MMPLL4_PLL>,
+ <&mmcc MMPLL5_PLL>;
+ assigned-clock-rates = <800000000>,
+ <1167000000>,
+ <1020000000>,
+ <960000000>,
+ <600000000>;
+ };
+
+ ocmem: sram@fdd00000 {
+ compatible = "qcom,msm8974-ocmem";
+ reg = <0xfdd00000 0x2000>,
+ <0xfec00000 0x200000>;
+ reg-names = "ctrl", "mem";
+ ranges = <0 0xfec00000 0x200000>;
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+ <&mmcc OCMEMCX_OCMEMNOC_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gmu_sram: gmu-sram@0 {
+ reg = <0x0 0x180000>;
+ };
+ };
};
timer: timer {
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-18 23:09:21 +0000