diff options
Diffstat (limited to 'dts/src/arm64/qcom/msm8998.dtsi')
-rw-r--r-- | dts/src/arm64/qcom/msm8998.dtsi | 1079 |
1 files changed, 821 insertions, 258 deletions
diff --git a/dts/src/arm64/qcom/msm8998.dtsi b/dts/src/arm64/qcom/msm8998.dtsi index 758c45bbbe..2793cc22d3 100644 --- a/dts/src/arm64/qcom/msm8998.dtsi +++ b/dts/src/arm64/qcom/msm8998.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,gpucc-msm8998.h> #include <dt-bindings/clock/qcom,mmcc-msm8998.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/gpio/gpio.h> @@ -56,7 +57,7 @@ no-map; qcom,client-id = <1>; - qcom,vmid = <15>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; }; spss_mem: memory@8ab00000 { @@ -108,6 +109,12 @@ reg = <0x0 0x95700000 0x0 0x100000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; clocks { @@ -140,6 +147,7 @@ L2_0: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -184,6 +192,7 @@ L2_1: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -308,10 +317,23 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-131250000 { + opp-hz = /bits/ 64 <131250000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-312500000 { + opp-hz = /bits/ 64 <312500000>; + required-opps = <&rpmpd_opp_nom>; + }; }; psci { @@ -319,68 +341,74 @@ method = "smc"; }; - rpm-glink { - compatible = "qcom,glink-rpm"; + rpm: remoteproc { + compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; + glink-edge { + compatible = "qcom,glink-rpm"; - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8998"; - qcom,glink-channels = "rpm_requests"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; - #clock-cells = <1>; - }; + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8998"; + qcom,glink-channels = "rpm_requests"; - rpmpd: power-controller { - compatible = "qcom,msm8998-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; + clocks = <&xo>; + clock-names = "xo"; + #clock-cells = <1>; + }; - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; + rpmpd: power-controller { + compatible = "qcom,msm8998-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; - rpmpd_opp_ret: opp1 { - opp-level = <RPM_SMD_LEVEL_RETENTION>; - }; + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; - rpmpd_opp_ret_plus: opp2 { - opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; - }; + rpmpd_opp_ret: opp1 { + opp-level = <RPM_SMD_LEVEL_RETENTION>; + }; - rpmpd_opp_min_svs: opp3 { - opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - }; + rpmpd_opp_ret_plus: opp2 { + opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; + }; - rpmpd_opp_low_svs: opp4 { - opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - }; + rpmpd_opp_min_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; - rpmpd_opp_svs: opp5 { - opp-level = <RPM_SMD_LEVEL_SVS>; - }; + rpmpd_opp_low_svs: opp4 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; - rpmpd_opp_svs_plus: opp6 { - opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - }; + rpmpd_opp_svs: opp5 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; - rpmpd_opp_nom: opp7 { - opp-level = <RPM_SMD_LEVEL_NOM>; - }; + rpmpd_opp_svs_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; - rpmpd_opp_nom_plus: opp8 { - opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - }; + rpmpd_opp_nom: opp7 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; - rpmpd_opp_turbo: opp9 { - opp-level = <RPM_SMD_LEVEL_TURBO>; - }; + rpmpd_opp_nom_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; - rpmpd_opp_turbo_plus: opp10 { - opp-level = <RPM_SMD_LEVEL_BINNING>; + rpmpd_opp_turbo_plus: opp10 { + opp-level = <RPM_SMD_LEVEL_BINNING>; + }; }; }; }; @@ -471,7 +499,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -492,7 +520,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -513,7 +541,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -534,7 +562,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -555,7 +583,7 @@ type = "passive"; }; - cpu4_crit: cpu_crit { + cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -576,7 +604,7 @@ type = "passive"; }; - cpu5_crit: cpu_crit { + cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -597,7 +625,7 @@ type = "passive"; }; - cpu6_crit: cpu_crit { + cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -618,7 +646,7 @@ type = "passive"; }; - cpu7_crit: cpu_crit { + cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -800,7 +828,7 @@ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; }; - soc: soc { + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; @@ -814,7 +842,7 @@ reg = <0x00100000 0xb0000>; clock-names = "xo", "sleep_clk"; - clocks = <&xo>, <&sleep_clk>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; /* * The hypervisor typically configures the memory region where these clocks @@ -838,7 +866,7 @@ }; qfprom: qfprom@784000 { - compatible = "qcom,qfprom"; + compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; reg = <0x00784000 0x621c>; #address-cells = <1>; #size-cells = <1>; @@ -905,12 +933,12 @@ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; }; - pcie0: pci@1c00000 { - compatible = "qcom,pcie-msm8996"; - reg = <0x01c00000 0x2000>, - <0x1b000000 0xf1d>, - <0x1b000f20 0xa8>, - <0x1b100000 0x100000>; + pcie0: pcie@1c00000 { + compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; + reg = <0x01c00000 0x2000>, + <0x1b000000 0xf1d>, + <0x1b000f20 0xa8>, + <0x1b100000 0x100000>; reg-names = "parf", "dbi", "elbi", "config"; device_type = "pci"; linux,pci-domain = <0>; @@ -918,28 +946,28 @@ #address-cells = <3>; #size-cells = <2>; num-lanes = <1>; - phys = <&pciephy>; + phys = <&pcie_phy>; phy-names = "pciephy"; status = "disabled"; - ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; #interrupt-cells = <1>; interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, + interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>; - clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; @@ -948,39 +976,35 @@ pcie_phy: phy@1c06000 { compatible = "qcom,msm8998-qmp-pcie-phy"; - reg = <0x01c06000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x01c06000 0x1000>; status = "disabled"; - ranges; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; + <&gcc GCC_PCIE_CLKREF_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk_src"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy", "common"; vdda-phy-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l2a_1p2>; - - pciephy: phy@1c06800 { - reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk_src"; - #clock-cells = <0>; - }; }; ufshc: ufshc@1da4000 { compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x01da4000 0x2500>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; - phys = <&ufsphy_lanes>; + phys = <&ufsphy>; phy-names = "ufsphy"; lanes-per-direction = <2>; power-domains = <&gcc UFS_GDSC>; @@ -1021,11 +1045,7 @@ ufsphy: phy@1da7000 { compatible = "qcom,msm8998-qmp-ufs-phy"; - reg = <0x01da7000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges; + reg = <0x01da7000 0x1000>; clock-names = "ref", @@ -1037,127 +1057,101 @@ reset-names = "ufsphy"; resets = <&ufshc 0>; - ufsphy_lanes: phy@1da7400 { - reg = <0x01da7400 0x128>, - <0x01da7600 0x1fc>, - <0x01da7c00 0x1dc>, - <0x01da7800 0x128>, - <0x01da7a00 0x1fc>; - #phy-cells = <0>; - }; + #phy-cells = <0>; + status = "disabled"; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x01f40000 0x40000>; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,msm8998-tcsr", "syscon"; + reg = <0x01f60000 0x20000>; }; tlmm: pinctrl@3400000 { compatible = "qcom,msm8998-pinctrl"; reg = <0x03400000 0xc00000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&tlmm 0 0 150>; gpio-controller; - #gpio-cells = <0x2>; + #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <0x2>; + #interrupt-cells = <2>; - sdc2_clk_on: sdc2_clk_on { - config { + sdc2_on: sdc2-on-state { + clk-pins { pins = "sdc2_clk"; - bias-disable; drive-strength = <16>; - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; bias-disable; - drive-strength = <2>; }; - }; - sdc2_cmd_on: sdc2_cmd_on { - config { + cmd-pins { pins = "sdc2_cmd"; - bias-pull-up; drive-strength = <10>; - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; bias-pull-up; - drive-strength = <2>; }; - }; - sdc2_data_on: sdc2_data_on { - config { + data-pins { pins = "sdc2_data"; - bias-pull-up; drive-strength = <10>; + bias-pull-up; }; }; - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; + sdc2_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; drive-strength = <2>; + bias-disable; }; - }; - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio95"; - function = "gpio"; + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; }; - config { - pins = "gpio95"; - bias-pull-up; + data-pins { + pins = "sdc2_data"; drive-strength = <2>; + bias-pull-up; }; }; - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio95"; - function = "gpio"; - }; - - config { - pins = "gpio95"; - bias-pull-up; - drive-strength = <2>; - }; + sdc2_cd: sdc2-cd-state { + pins = "gpio95"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; }; - blsp1_uart3_on: blsp1_uart3_on { - tx { + blsp1_uart3_on: blsp1-uart3-on-state { + tx-pins { pins = "gpio45"; function = "blsp_uart3_a"; drive-strength = <2>; bias-disable; }; - rx { + rx-pins { pins = "gpio46"; function = "blsp_uart3_a"; drive-strength = <2>; bias-disable; }; - cts { + cts-pins { pins = "gpio47"; function = "blsp_uart3_a"; drive-strength = <2>; bias-disable; }; - rfr { + rfr-pins { pins = "gpio48"; function = "blsp_uart3_a"; drive-strength = <2>; @@ -1165,173 +1159,266 @@ }; }; - blsp1_i2c1_default: blsp1-i2c1-default { + blsp1_i2c1_default: blsp1-i2c1-default-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-disable; }; - blsp1_i2c1_sleep: blsp1-i2c1-sleep { + blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c2_default: blsp1-i2c2-default { + blsp1_i2c2_default: blsp1-i2c2-default-state { pins = "gpio32", "gpio33"; function = "blsp_i2c2"; drive-strength = <2>; bias-disable; }; - blsp1_i2c2_sleep: blsp1-i2c2-sleep { + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { pins = "gpio32", "gpio33"; function = "blsp_i2c2"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c3_default: blsp1-i2c3-default { + blsp1_i2c3_default: blsp1-i2c3-default-state { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; drive-strength = <2>; bias-disable; }; - blsp1_i2c3_sleep: blsp1-i2c3-sleep { + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c4_default: blsp1-i2c4-default { + blsp1_i2c4_default: blsp1-i2c4-default-state { pins = "gpio10", "gpio11"; function = "blsp_i2c4"; drive-strength = <2>; bias-disable; }; - blsp1_i2c4_sleep: blsp1-i2c4-sleep { + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { pins = "gpio10", "gpio11"; function = "blsp_i2c4"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c5_default: blsp1-i2c5-default { + blsp1_i2c5_default: blsp1-i2c5-default-state { pins = "gpio87", "gpio88"; function = "blsp_i2c5"; drive-strength = <2>; bias-disable; }; - blsp1_i2c5_sleep: blsp1-i2c5-sleep { + blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { pins = "gpio87", "gpio88"; function = "blsp_i2c5"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c6_default: blsp1-i2c6-default { + blsp1_i2c6_default: blsp1-i2c6-default-state { pins = "gpio43", "gpio44"; function = "blsp_i2c6"; drive-strength = <2>; bias-disable; }; - blsp1_i2c6_sleep: blsp1-i2c6-sleep { + blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { pins = "gpio43", "gpio44"; function = "blsp_i2c6"; drive-strength = <2>; bias-pull-up; }; + + blsp1_spi_b_default: blsp1-spi-b-default-state { + pins = "gpio23", "gpio28"; + function = "blsp1_spi_b"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi1_default: blsp1-spi1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_spi1"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi2_default: blsp1-spi2-default-state { + pins = "gpio31", "gpio34", "gpio32", "gpio33"; + function = "blsp_spi2"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "blsp_spi2"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi4_default: blsp1-spi4-default-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "blsp_spi4"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi5_default: blsp1-spi5-default-state { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + function = "blsp_spi5"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi6_default: blsp1-spi6-default-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "blsp_spi6"; + drive-strength = <6>; + bias-disable; + }; + + /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ - blsp2_i2c1_default: blsp2-i2c1-default { + blsp2_i2c1_default: blsp2-i2c1-default-state { pins = "gpio55", "gpio56"; function = "blsp_i2c7"; drive-strength = <2>; bias-disable; }; - blsp2_i2c1_sleep: blsp2-i2c1-sleep { + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { pins = "gpio55", "gpio56"; function = "blsp_i2c7"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c2_default: blsp2-i2c2-default { + blsp2_i2c2_default: blsp2-i2c2-default-state { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; drive-strength = <2>; bias-disable; }; - blsp2_i2c2_sleep: blsp2-i2c2-sleep { + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c3_default: blsp2-i2c3-default { + blsp2_i2c3_default: blsp2-i2c3-default-state { pins = "gpio51", "gpio52"; function = "blsp_i2c9"; drive-strength = <2>; bias-disable; }; - blsp2_i2c3_sleep: blsp2-i2c3-sleep { + blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { pins = "gpio51", "gpio52"; function = "blsp_i2c9"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c4_default: blsp2-i2c4-default { + blsp2_i2c4_default: blsp2-i2c4-default-state { pins = "gpio67", "gpio68"; function = "blsp_i2c10"; drive-strength = <2>; bias-disable; }; - blsp2_i2c4_sleep: blsp2-i2c4-sleep { + blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { pins = "gpio67", "gpio68"; function = "blsp_i2c10"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c5_default: blsp2-i2c5-default { + blsp2_i2c5_default: blsp2-i2c5-default-state { pins = "gpio60", "gpio61"; function = "blsp_i2c11"; drive-strength = <2>; bias-disable; }; - blsp2_i2c5_sleep: blsp2-i2c5-sleep { + blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { pins = "gpio60", "gpio61"; function = "blsp_i2c11"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c6_default: blsp2-i2c6-default { + blsp2_i2c6_default: blsp2-i2c6-default-state { pins = "gpio83", "gpio84"; function = "blsp_i2c12"; drive-strength = <2>; bias-disable; }; - blsp2_i2c6_sleep: blsp2-i2c6-sleep { + blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { pins = "gpio83", "gpio84"; function = "blsp_i2c12"; drive-strength = <2>; bias-pull-up; }; + + blsp2_spi1_default: blsp2-spi1-default-state { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "blsp_spi7"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_spi8"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi3_default: blsp2-spi3-default-state { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_spi9"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi4_default: blsp2-spi4-default-state { + pins = "gpio65", "gpio66", "gpio67", "gpio68"; + function = "blsp_spi10"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi5_default: blsp2-spi5-default-state { + pins = "gpio58", "gpio59", "gpio60", "gpio61"; + function = "blsp_spi11"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi6_default: blsp2-spi6-default-state { + pins = "gpio81", "gpio82", "gpio83", "gpio84"; + function = "blsp_spi12"; + drive-strength = <6>; + bias-disable; + }; }; remoteproc_mss: remoteproc@4080000 { @@ -1367,7 +1454,7 @@ resets = <&gcc GCC_MSS_RESTART>; reset-names = "mss_restart"; - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; power-domains = <&rpmpd MSM8998_VDDCX>, <&rpmpd MSM8998_VDDMX>; @@ -1383,6 +1470,10 @@ memory-region = <&mpss_mem>; }; + metadata { + memory-region = <&mdata_mem>; + }; + glink-edge { interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; label = "modem"; @@ -1409,54 +1500,54 @@ "rbcpr", "core"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; power-domains = <&rpmpd MSM8998_VDDMX>; status = "disabled"; gpu_opp_table: opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2"; opp-710000097 { opp-hz = /bits/ 64 <710000097>; opp-level = <RPM_SMD_LEVEL_TURBO>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-670000048 { opp-hz = /bits/ 64 <670000048>; opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-596000097 { opp-hz = /bits/ 64 <596000097>; opp-level = <RPM_SMD_LEVEL_NOM>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-515000097 { opp-hz = /bits/ 64 <515000097>; opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; opp-level = <RPM_SMD_LEVEL_SVS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; }; }; @@ -1495,7 +1586,7 @@ reg = <0x05065000 0x9000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GPLL0_OUT_MAIN>; + <&gcc GCC_GPU_GPLL0_CLK>; clock-names = "xo", "gpll0"; }; @@ -1514,9 +1605,8 @@ px-supply = <&vreg_lvs2a_1p8>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; - clock-names = "xo", "aggre2"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; memory-region = <&slpi_mem>; @@ -1540,7 +1630,7 @@ compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x06002000 0x1000>, <0x16280000 0x180000>; - reg-names = "stm-base", "stm-data-base"; + reg-names = "stm-base", "stm-stimulus-base"; status = "disabled"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; @@ -1930,9 +2020,11 @@ cpu = <&CPU4>; - port{ - etm4_out: endpoint { - remote-endpoint = <&apss_funnel_in4>; + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; }; }; }; @@ -1947,9 +2039,11 @@ cpu = <&CPU5>; - port{ - etm5_out: endpoint { - remote-endpoint = <&apss_funnel_in5>; + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; }; }; }; @@ -1964,9 +2058,11 @@ cpu = <&CPU6>; - port{ - etm6_out: endpoint { - remote-endpoint = <&apss_funnel_in6>; + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; }; }; }; @@ -1981,9 +2077,11 @@ cpu = <&CPU7>; - port{ - etm7_out: endpoint { - remote-endpoint = <&apss_funnel_in7>; + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; }; }; }; @@ -1995,11 +2093,11 @@ spmi_bus: spmi@800f000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; + reg = <0x0800f000 0x1000>, + <0x08400000 0x1000000>, + <0x09400000 0x1000000>, + <0x0a400000 0x220000>, + <0x0800a000 0x3000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; @@ -2009,7 +2107,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; usb3: usb@a8f8800 { @@ -2049,7 +2146,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&qusb2phy>, <&usb1_ssphy>; + phys = <&qusb2phy>, <&usb3phy>; phy-names = "usb2-phy", "usb3-phy"; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; @@ -2058,33 +2155,26 @@ usb3phy: phy@c010000 { compatible = "qcom,msm8998-qmp-usb3-phy"; - reg = <0x0c010000 0x18c>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x0c010000 0x1000>; clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3_phy_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; resets = <&gcc GCC_USB3_PHY_BCR>, <&gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "phy", "common"; + reset-names = "phy", + "phy_phy"; - usb1_ssphy: phy@c010200 { - reg = <0xc010200 0x128>, - <0xc010400 0x200>, - <0xc010c00 0x20c>, - <0xc010600 0x128>, - <0xc010800 0x200>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + status = "disabled"; }; qusb2phy: phy@c012000 { @@ -2102,10 +2192,10 @@ nvmem-cells = <&qusb2_hstx_trim>; }; - sdhc2: sdhci@c0a4900 { - compatible = "qcom,sdhci-msm-v4"; + sdhc2: mmc@c0a4900 { + compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; @@ -2114,7 +2204,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; bus-width = <4>; status = "disabled"; }; @@ -2266,6 +2356,114 @@ #size-cells = <0>; }; + blsp1_spi1: spi@c175000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c175000 0x600>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi1_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi2: spi@c176000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c176000 0x600>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi2_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi3: spi@c177000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c177000 0x600>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi3_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi4: spi@c178000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c178000 0x600>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi4_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi5: spi@c179000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c179000 0x600>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi5_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi6: spi@c17a000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c17a000 0x600>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi6_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + blsp2_dma: dma-controller@c184000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c184000 0x25000>; @@ -2409,13 +2607,120 @@ #size-cells = <0>; }; + blsp2_spi1: spi@c1b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b5000 0x600>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi1_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi2: spi@c1b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b6000 0x600>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi2_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi3: spi@c1b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b7000 0x600>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi3_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi4: spi@c1b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b8000 0x600>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi4_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi5: spi@c1b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b9000 0x600>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi5_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi6: spi@c1ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1ba000 0x600>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi6_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + mmcc: clock-controller@c8c0000 { compatible = "qcom,mmcc-msm8998"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xc8c0000 0x40000>; - status = "disabled"; clock-names = "xo", "gpll0", @@ -2426,17 +2731,273 @@ "hdmipll", "dplink", "dpvco", - "core_bi_pll_test_se"; + "gpll0_div"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, <0>, <0>, <0>, - <0>, - <0>, - <0>, - <0>, - <0>; + <&gcc GCC_MMSS_GPLL0_DIV_CLK>; + }; + + mdss: display-subsystem@c900000 { + compatible = "qcom,msm8998-mdss"; + reg = <0x0c900000 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "core"; + + power-domains = <&mmcc MDSS_GDSC>; + iommus = <&mmss_smmu 0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@c901000 { + compatible = "qcom,msm8998-dpu"; + reg = <0x0c901000 0x8f000>, + <0x0c9a8e00 0xf0>, + <0x0c9b0000 0x2008>, + <0x0c9b8000 0x1040>; + reg-names = "mdp", + "regdma", + "vbif", + "vbif_nrt"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "mnoc", + "core", + "vsync"; + + assigned-clocks = <&mmcc MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd MSM8998_VDDMX>; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-171430000 { + opp-hz = /bits/ 64 <171430000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-330000000 { + opp-hz = /bits/ 64 <330000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-412500000 { + opp-hz = /bits/ 64 <412500000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@c994000 { + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0c994000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_BYTE0_INTF_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@c994400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c994400 0x200>, + <0x0c994600 0x280>, + <0x0c994a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@c996000 { + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0c996000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_BYTE1_INTF_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@c996400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c996400 0x200>, + <0x0c996600 0x280>, + <0x0c996a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; }; mmss_smmu: iommu@cd00000 { @@ -2446,11 +3007,10 @@ clocks = <&mmcc MNOC_AHB_CLK>, <&mmcc BIMC_SMMU_AHB_CLK>, - <&rpmcc RPM_SMD_MMAXI_CLK>, <&mmcc BIMC_SMMU_AXI_CLK>; - clock-names = "iface-mm", "iface-smmu", - "bus-mm", "bus-smmu"; - status = "disabled"; + clock-names = "iface-mm", + "iface-smmu", + "bus-smmu"; #global-interrupts = <0>; interrupts = @@ -2474,6 +3034,8 @@ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&mmcc BIMC_SMMU_GDSC>; }; remoteproc_adsp: remoteproc@17300000 { @@ -2510,7 +3072,8 @@ }; apcs_glb: mailbox@17911000 { - compatible = "qcom,msm8998-apcs-hmss-global"; + compatible = "qcom,msm8998-apcs-hmss-global", + "qcom,msm8994-apcs-kpss-global"; reg = <0x17911000 0x1000>; #mbox-cells = <1>; |