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-rw-r--r--dts/src/arm64/qcom/sc7180.dtsi1493
1 files changed, 911 insertions, 582 deletions
diff --git a/dts/src/arm64/qcom/sc7180.dtsi b/dts/src/arm64/qcom/sc7180.dtsi
index 5dcaac23a1..4dcaa15cae 100644
--- a/dts/src/arm64/qcom/sc7180.dtsi
+++ b/dts/src/arm64/qcom/sc7180.dtsi
@@ -11,14 +11,19 @@
#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7180.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -27,8 +32,6 @@
#address-cells = <2>;
#size-cells = <2>;
- chosen { };
-
aliases {
mmc1 = &sdhc_1;
mmc2 = &sdhc_2;
@@ -54,6 +57,8 @@
spi11 = &spi11;
};
+ chosen { };
+
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
@@ -68,62 +73,6 @@
};
};
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- hyp_mem: memory@80000000 {
- reg = <0x0 0x80000000 0x0 0x600000>;
- no-map;
- };
-
- xbl_mem: memory@80600000 {
- reg = <0x0 0x80600000 0x0 0x200000>;
- no-map;
- };
-
- aop_mem: memory@80800000 {
- reg = <0x0 0x80800000 0x0 0x20000>;
- no-map;
- };
-
- aop_cmd_db_mem: memory@80820000 {
- reg = <0x0 0x80820000 0x0 0x20000>;
- compatible = "qcom,cmd-db";
- no-map;
- };
-
- sec_apps_mem: memory@808ff000 {
- reg = <0x0 0x808ff000 0x0 0x1000>;
- no-map;
- };
-
- smem_mem: memory@80900000 {
- reg = <0x0 0x80900000 0x0 0x200000>;
- no-map;
- };
-
- tz_mem: memory@80b00000 {
- reg = <0x0 0x80b00000 0x0 0x3900000>;
- no-map;
- };
-
- ipa_fw_mem: memory@8b700000 {
- reg = <0 0x8b700000 0 0x10000>;
- no-map;
- };
-
- rmtfs_mem: memory@94600000 {
- compatible = "qcom,rmtfs-mem";
- reg = <0x0 0x94600000 0x0 0x200000>;
- no-map;
-
- qcom,client-id = <1>;
- qcom,vmid = <15>;
- };
- };
-
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -132,10 +81,10 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x0>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
operating-points-v2 = <&cpu0_opp_table>;
@@ -146,9 +95,13 @@
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
};
};
};
@@ -157,10 +110,10 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x100>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_100>;
@@ -171,6 +124,8 @@
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -179,10 +134,10 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x200>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_200>;
@@ -193,6 +148,8 @@
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -201,10 +158,10 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x300>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_300>;
@@ -215,6 +172,8 @@
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -223,10 +182,10 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x400>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_400>;
@@ -237,6 +196,8 @@
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -245,10 +206,10 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x500>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
- cpu-idle-states = <&LITTLE_CPU_SLEEP_0
- &LITTLE_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_500>;
@@ -259,6 +220,8 @@
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -267,10 +230,10 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x600>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
- cpu-idle-states = <&BIG_CPU_SLEEP_0
- &BIG_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_600>;
@@ -281,6 +244,8 @@
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -289,10 +254,10 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x700>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
- cpu-idle-states = <&BIG_CPU_SLEEP_0
- &BIG_CPU_SLEEP_1
- &CLUSTER_SLEEP_0>;
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_700>;
@@ -303,6 +268,8 @@
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
next-level-cache = <&L3_0>;
};
};
@@ -343,7 +310,7 @@
};
};
- idle-states {
+ idle_states: idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
@@ -385,20 +352,51 @@
min-residency-us = <5555>;
local-timer-stop;
};
+ };
- CLUSTER_SLEEP_0: cluster-sleep-0 {
- compatible = "arm,idle-state";
+ domain_idle_states: domain-idle-states {
+ CLUSTER_SLEEP_PC: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ idle-state-name = "cluster-l3-power-collapse";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <2752>;
+ exit-latency-us = <3048>;
+ min-residency-us = <6118>;
+ };
+
+ CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ idle-state-name = "cluster-cx-retention";
+ arm,psci-suspend-param = <0x41001244>;
+ entry-latency-us = <3638>;
+ exit-latency-us = <4562>;
+ min-residency-us = <8467>;
+ };
+
+ CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
+ compatible = "domain-idle-state";
idle-state-name = "cluster-power-down";
- arm,psci-suspend-param = <0x40003444>;
+ arm,psci-suspend-param = <0x4100b244>;
entry-latency-us = <3263>;
exit-latency-us = <6562>;
- min-residency-us = <9926>;
- local-timer-stop;
+ min-residency-us = <9826>;
};
};
};
- cpu0_opp_table: cpu0_opp_table {
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sc7180", "qcom,scm";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0>;
+ };
+
+ cpu0_opp_table: opp-table-cpu0 {
compatible = "operating-points-v2";
opp-shared;
@@ -453,7 +451,7 @@
};
};
- cpu6_opp_table: cpu6_opp_table {
+ cpu6_opp_table: opp-table-cpu6 {
compatible = "operating-points-v2";
opp-shared;
@@ -538,10 +536,42 @@
};
};
- memory@80000000 {
- device_type = "memory";
- /* We expect the bootloader to fill in the size */
- reg = <0 0x80000000 0 0>;
+ qspi_opp_table: opp-table-qspi {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
+ qup_opp_table: opp-table-qup {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
};
pmu {
@@ -549,16 +579,120 @@
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
- firmware {
- scm {
- compatible = "qcom,scm-sc7180", "qcom,scm";
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD1: cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD2: cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD3: cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD4: cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD5: cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
+ };
+
+ CPU_PD6: cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+ };
+
+ CPU_PD7: cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
+ };
+
+ CLUSTER_PD: cpu-cluster0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_PC
+ &CLUSTER_SLEEP_CX_RET
+ &CLUSTER_AOSS_SLEEP>;
};
};
- tcsr_mutex: hwlock {
- compatible = "qcom,tcsr-mutex";
- syscon = <&tcsr_mutex_regs 0 0x1000>;
- #hwlock-cells = <1>;
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@80000000 {
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_mem: memory@80600000 {
+ reg = <0x0 0x80600000 0x0 0x200000>;
+ no-map;
+ };
+
+ aop_mem: memory@80800000 {
+ reg = <0x0 0x80800000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: memory@80820000 {
+ reg = <0x0 0x80820000 0x0 0x20000>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+
+ sec_apps_mem: memory@808ff000 {
+ reg = <0x0 0x808ff000 0x0 0x1000>;
+ no-map;
+ };
+
+ smem_mem: memory@80900000 {
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ no-map;
+ };
+
+ tz_mem: memory@80b00000 {
+ reg = <0x0 0x80b00000 0x0 0x3900000>;
+ no-map;
+ };
+
+ ipa_fw_mem: memory@8b700000 {
+ reg = <0 0x8b700000 0 0x10000>;
+ no-map;
+ };
+
+ rmtfs_mem: memory@94600000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0x94600000 0x0 0x200000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+ };
};
smem {
@@ -646,11 +780,6 @@
};
};
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@@ -668,6 +797,7 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ power-domains = <&rpmhpd SC7180_CX>;
};
qfprom: efuse@784000 {
@@ -693,10 +823,10 @@
};
};
- sdhc_1: sdhci@7c4000 {
+ sdhc_1: mmc@7c4000 {
compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
- reg = <0 0x7c4000 0 0x1000>,
- <0 0x07c5000 0 0x1000>;
+ reg = <0 0x007c4000 0 0x1000>,
+ <0 0x007c5000 0 0x1000>;
reg-names = "hc", "cqhci";
iommus = <&apps_smmu 0x60 0x0>;
@@ -704,10 +834,10 @@
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -725,7 +855,7 @@
status = "disabled";
- sdhc1_opp_table: sdhc1-opp-table {
+ sdhc1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
@@ -744,25 +874,6 @@
};
};
- qup_opp_table: qup-opp-table {
- compatible = "operating-points-v2";
-
- opp-75000000 {
- opp-hz = /bits/ 64 <75000000>;
- required-opps = <&rpmhpd_opp_low_svs>;
- };
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- required-opps = <&rpmhpd_opp_svs>;
- };
-
- opp-128000000 {
- opp-hz = /bits/ 64 <128000000>;
- required-opps = <&rpmhpd_opp_nom>;
- };
- };
-
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x008c0000 0 0x6000>;
@@ -801,7 +912,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi0_default>;
+ pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -855,7 +966,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi1_default>;
+ pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -945,7 +1056,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi3_default>;
+ pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1035,7 +1146,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi5_default>;
+ pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1102,7 +1213,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi6_default>;
+ pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1192,7 +1303,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi8_default>;
+ pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1282,7 +1393,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi10_default>;
+ pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1336,7 +1447,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi11_default>;
+ pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1426,9 +1537,9 @@
iommus = <&apps_smmu 0x440 0x0>,
<&apps_smmu 0x442 0x0>;
- reg = <0 0x1e40000 0 0x7000>,
- <0 0x1e47000 0 0x2000>,
- <0 0x1e04000 0 0x2c000>;
+ reg = <0 0x01e40000 0 0x7000>,
+ <0 0x01e47000 0 0x2000>,
+ <0 0x01e04000 0 0x2c000>;
reg-names = "ipa-reg",
"ipa-shared",
"gsi";
@@ -1462,13 +1573,19 @@
status = "disabled";
};
- tcsr_mutex_regs: syscon@1f40000 {
- compatible = "syscon";
- reg = <0 0x01f40000 0 0x40000>;
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0 0x01f40000 0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr_regs_1: syscon@1f60000 {
+ compatible = "qcom,sc7180-tcsr", "syscon";
+ reg = <0 0x01f60000 0 0x20000>;
};
- tcsr_regs: syscon@1fc0000 {
- compatible = "syscon";
+ tcsr_regs_2: syscon@1fc0000 {
+ compatible = "qcom,sc7180-tcsr", "syscon";
reg = <0 0x01fc0000 0 0x40000>;
};
@@ -1486,417 +1603,459 @@
gpio-ranges = <&tlmm 0 0 120>;
wakeup-parent = <&pdc>;
- dp_hot_plug_det: dp-hot-plug-det {
- pinmux {
- pins = "gpio117";
- function = "dp_hot";
- };
+ dp_hot_plug_det: dp-hot-plug-det-state {
+ pins = "gpio117";
+ function = "dp_hot";
};
- qspi_clk: qspi-clk {
- pinmux {
- pins = "gpio63";
- function = "qspi_clk";
- };
+ qspi_clk: qspi-clk-state {
+ pins = "gpio63";
+ function = "qspi_clk";
};
- qspi_cs0: qspi-cs0 {
- pinmux {
- pins = "gpio68";
- function = "qspi_cs";
- };
+ qspi_cs0: qspi-cs0-state {
+ pins = "gpio68";
+ function = "qspi_cs";
};
- qspi_cs1: qspi-cs1 {
- pinmux {
- pins = "gpio72";
- function = "qspi_cs";
- };
+ qspi_cs1: qspi-cs1-state {
+ pins = "gpio72";
+ function = "qspi_cs";
};
- qspi_data01: qspi-data01 {
- pinmux-data {
- pins = "gpio64", "gpio65";
- function = "qspi_data";
- };
+ qspi_data0: qspi-data0-state {
+ pins = "gpio64";
+ function = "qspi_data";
};
- qspi_data12: qspi-data12 {
- pinmux-data {
- pins = "gpio66", "gpio67";
- function = "qspi_data";
- };
+ qspi_data1: qspi-data1-state {
+ pins = "gpio65";
+ function = "qspi_data";
};
- qup_i2c0_default: qup-i2c0-default {
- pinmux {
- pins = "gpio34", "gpio35";
- function = "qup00";
- };
+ qspi_data23: qspi-data23-state {
+ pins = "gpio66", "gpio67";
+ function = "qspi_data";
};
- qup_i2c1_default: qup-i2c1-default {
- pinmux {
- pins = "gpio0", "gpio1";
- function = "qup01";
- };
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio34", "gpio35";
+ function = "qup00";
};
- qup_i2c2_default: qup-i2c2-default {
- pinmux {
- pins = "gpio15", "gpio16";
- function = "qup02_i2c";
- };
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup01";
};
- qup_i2c3_default: qup-i2c3-default {
- pinmux {
- pins = "gpio38", "gpio39";
- function = "qup03";
- };
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio15", "gpio16";
+ function = "qup02_i2c";
};
- qup_i2c4_default: qup-i2c4-default {
- pinmux {
- pins = "gpio115", "gpio116";
- function = "qup04_i2c";
- };
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio38", "gpio39";
+ function = "qup03";
};
- qup_i2c5_default: qup-i2c5-default {
- pinmux {
- pins = "gpio25", "gpio26";
- function = "qup05";
- };
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio115", "gpio116";
+ function = "qup04_i2c";
};
- qup_i2c6_default: qup-i2c6-default {
- pinmux {
- pins = "gpio59", "gpio60";
- function = "qup10";
- };
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio25", "gpio26";
+ function = "qup05";
};
- qup_i2c7_default: qup-i2c7-default {
- pinmux {
- pins = "gpio6", "gpio7";
- function = "qup11_i2c";
- };
+ qup_i2c6_default: qup-i2c6-default-state {
+ pins = "gpio59", "gpio60";
+ function = "qup10";
};
- qup_i2c8_default: qup-i2c8-default {
- pinmux {
- pins = "gpio42", "gpio43";
- function = "qup12";
- };
+ qup_i2c7_default: qup-i2c7-default-state {
+ pins = "gpio6", "gpio7";
+ function = "qup11_i2c";
};
- qup_i2c9_default: qup-i2c9-default {
- pinmux {
- pins = "gpio46", "gpio47";
- function = "qup13_i2c";
- };
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio42", "gpio43";
+ function = "qup12";
};
- qup_i2c10_default: qup-i2c10-default {
- pinmux {
- pins = "gpio86", "gpio87";
- function = "qup14";
- };
+ qup_i2c9_default: qup-i2c9-default-state {
+ pins = "gpio46", "gpio47";
+ function = "qup13_i2c";
};
- qup_i2c11_default: qup-i2c11-default {
- pinmux {
- pins = "gpio53", "gpio54";
- function = "qup15";
- };
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio86", "gpio87";
+ function = "qup14";
+ };
+
+ qup_i2c11_default: qup-i2c11-default-state {
+ pins = "gpio53", "gpio54";
+ function = "qup15";
+ };
+
+ qup_spi0_spi: qup-spi0-spi-state {
+ pins = "gpio34", "gpio35", "gpio36";
+ function = "qup00";
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio37";
+ function = "qup00";
+ };
+
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
+ pins = "gpio37";
+ function = "gpio";
+ };
+
+ qup_spi1_spi: qup-spi1-spi-state {
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup01";
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio3";
+ function = "qup01";
+ };
+
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ qup_spi3_spi: qup-spi3-spi-state {
+ pins = "gpio38", "gpio39", "gpio40";
+ function = "qup03";
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio41";
+ function = "qup03";
+ };
+
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
+ pins = "gpio41";
+ function = "gpio";
+ };
+
+ qup_spi5_spi: qup-spi5-spi-state {
+ pins = "gpio25", "gpio26", "gpio27";
+ function = "qup05";
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio28";
+ function = "qup05";
+ };
+
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
+ pins = "gpio28";
+ function = "gpio";
};
- qup_spi0_default: qup-spi0-default {
- pinmux {
- pins = "gpio34", "gpio35",
- "gpio36", "gpio37";
+ qup_spi6_spi: qup-spi6-spi-state {
+ pins = "gpio59", "gpio60", "gpio61";
+ function = "qup10";
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio62";
+ function = "qup10";
+ };
+
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
+ pins = "gpio62";
+ function = "gpio";
+ };
+
+ qup_spi8_spi: qup-spi8-spi-state {
+ pins = "gpio42", "gpio43", "gpio44";
+ function = "qup12";
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio45";
+ function = "qup12";
+ };
+
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
+ pins = "gpio45";
+ function = "gpio";
+ };
+
+ qup_spi10_spi: qup-spi10-spi-state {
+ pins = "gpio86", "gpio87", "gpio88";
+ function = "qup14";
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio89";
+ function = "qup14";
+ };
+
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
+ pins = "gpio89";
+ function = "gpio";
+ };
+
+ qup_spi11_spi: qup-spi11-spi-state {
+ pins = "gpio53", "gpio54", "gpio55";
+ function = "qup15";
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio56";
+ function = "qup15";
+ };
+
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
+ pins = "gpio56";
+ function = "gpio";
+ };
+
+ qup_uart0_default: qup-uart0-default-state {
+ qup_uart0_cts: cts-pins {
+ pins = "gpio34";
+ function = "qup00";
+ };
+
+ qup_uart0_rts: rts-pins {
+ pins = "gpio35";
function = "qup00";
};
- };
- qup_spi0_cs_gpio: qup-spi0-cs-gpio {
- pinmux {
- pins = "gpio34", "gpio35",
- "gpio36";
+ qup_uart0_tx: tx-pins {
+ pins = "gpio36";
function = "qup00";
};
- pinmux-cs {
+ qup_uart0_rx: rx-pins {
pins = "gpio37";
- function = "gpio";
+ function = "qup00";
};
};
- qup_spi1_default: qup-spi1-default {
- pinmux {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
+ qup_uart1_default: qup-uart1-default-state {
+ qup_uart1_cts: cts-pins {
+ pins = "gpio0";
function = "qup01";
};
- };
- qup_spi1_cs_gpio: qup-spi1-cs-gpio {
- pinmux {
- pins = "gpio0", "gpio1",
- "gpio2";
+ qup_uart1_rts: rts-pins {
+ pins = "gpio1";
function = "qup01";
};
- pinmux-cs {
- pins = "gpio3";
- function = "gpio";
+ qup_uart1_tx: tx-pins {
+ pins = "gpio2";
+ function = "qup01";
};
- };
- qup_spi3_default: qup-spi3-default {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "qup03";
+ qup_uart1_rx: rx-pins {
+ pins = "gpio3";
+ function = "qup01";
};
};
- qup_spi3_cs_gpio: qup-spi3-cs-gpio {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40";
- function = "qup03";
+ qup_uart2_default: qup-uart2-default-state {
+ qup_uart2_tx: tx-pins {
+ pins = "gpio15";
+ function = "qup02_uart";
};
- pinmux-cs {
- pins = "gpio41";
- function = "gpio";
+ qup_uart2_rx: rx-pins {
+ pins = "gpio16";
+ function = "qup02_uart";
};
};
- qup_spi5_default: qup-spi5-default {
- pinmux {
- pins = "gpio25", "gpio26",
- "gpio27", "gpio28";
- function = "qup05";
+ qup_uart3_default: qup-uart3-default-state {
+ qup_uart3_cts: cts-pins {
+ pins = "gpio38";
+ function = "qup03";
};
- };
- qup_spi5_cs_gpio: qup-spi5-cs-gpio {
- pinmux {
- pins = "gpio25", "gpio26",
- "gpio27";
- function = "qup05";
+ qup_uart3_rts: rts-pins {
+ pins = "gpio39";
+ function = "qup03";
};
- pinmux-cs {
- pins = "gpio28";
- function = "gpio";
+ qup_uart3_tx: tx-pins {
+ pins = "gpio40";
+ function = "qup03";
};
- };
- qup_spi6_default: qup-spi6-default {
- pinmux {
- pins = "gpio59", "gpio60",
- "gpio61", "gpio62";
- function = "qup10";
+ qup_uart3_rx: rx-pins {
+ pins = "gpio41";
+ function = "qup03";
};
};
- qup_spi6_cs_gpio: qup-spi6-cs-gpio {
- pinmux {
- pins = "gpio59", "gpio60",
- "gpio61";
- function = "qup10";
+ qup_uart4_default: qup-uart4-default-state {
+ qup_uart4_tx: tx-pins {
+ pins = "gpio115";
+ function = "qup04_uart";
};
- pinmux-cs {
- pins = "gpio62";
- function = "gpio";
+ qup_uart4_rx: rx-pins {
+ pins = "gpio116";
+ function = "qup04_uart";
};
};
- qup_spi8_default: qup-spi8-default {
- pinmux {
- pins = "gpio42", "gpio43",
- "gpio44", "gpio45";
- function = "qup12";
+ qup_uart5_default: qup-uart5-default-state {
+ qup_uart5_cts: cts-pins {
+ pins = "gpio25";
+ function = "qup05";
};
- };
- qup_spi8_cs_gpio: qup-spi8-cs-gpio {
- pinmux {
- pins = "gpio42", "gpio43",
- "gpio44";
- function = "qup12";
+ qup_uart5_rts: rts-pins {
+ pins = "gpio26";
+ function = "qup05";
};
- pinmux-cs {
- pins = "gpio45";
- function = "gpio";
+ qup_uart5_tx: tx-pins {
+ pins = "gpio27";
+ function = "qup05";
};
- };
- qup_spi10_default: qup-spi10-default {
- pinmux {
- pins = "gpio86", "gpio87",
- "gpio88", "gpio89";
- function = "qup14";
+ qup_uart5_rx: rx-pins {
+ pins = "gpio28";
+ function = "qup05";
};
};
- qup_spi10_cs_gpio: qup-spi10-cs-gpio {
- pinmux {
- pins = "gpio86", "gpio87",
- "gpio88";
- function = "qup14";
+ qup_uart6_default: qup-uart6-default-state {
+ qup_uart6_cts: cts-pins {
+ pins = "gpio59";
+ function = "qup10";
};
- pinmux-cs {
- pins = "gpio89";
- function = "gpio";
+ qup_uart6_rts: rts-pins {
+ pins = "gpio60";
+ function = "qup10";
};
- };
- qup_spi11_default: qup-spi11-default {
- pinmux {
- pins = "gpio53", "gpio54",
- "gpio55", "gpio56";
- function = "qup15";
+ qup_uart6_tx: tx-pins {
+ pins = "gpio61";
+ function = "qup10";
+ };
+
+ qup_uart6_rx: rx-pins {
+ pins = "gpio62";
+ function = "qup10";
};
};
- qup_spi11_cs_gpio: qup-spi11-cs-gpio {
- pinmux {
- pins = "gpio53", "gpio54",
- "gpio55";
- function = "qup15";
+ qup_uart7_default: qup-uart7-default-state {
+ qup_uart7_tx: tx-pins {
+ pins = "gpio6";
+ function = "qup11_uart";
};
- pinmux-cs {
- pins = "gpio56";
- function = "gpio";
+ qup_uart7_rx: rx-pins {
+ pins = "gpio7";
+ function = "qup11_uart";
};
};
- qup_uart0_default: qup-uart0-default {
- pinmux {
- pins = "gpio34", "gpio35",
- "gpio36", "gpio37";
- function = "qup00";
+ qup_uart8_default: qup-uart8-default-state {
+ qup_uart8_tx: tx-pins {
+ pins = "gpio44";
+ function = "qup12";
};
- };
- qup_uart1_default: qup-uart1-default {
- pinmux {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- function = "qup01";
+ qup_uart8_rx: rx-pins {
+ pins = "gpio45";
+ function = "qup12";
};
};
- qup_uart2_default: qup-uart2-default {
- pinmux {
- pins = "gpio15", "gpio16";
- function = "qup02_uart";
+ qup_uart9_default: qup-uart9-default-state {
+ qup_uart9_tx: tx-pins {
+ pins = "gpio46";
+ function = "qup13_uart";
};
- };
- qup_uart3_default: qup-uart3-default {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "qup03";
+ qup_uart9_rx: rx-pins {
+ pins = "gpio47";
+ function = "qup13_uart";
};
};
- qup_uart4_default: qup-uart4-default {
- pinmux {
- pins = "gpio115", "gpio116";
- function = "qup04_uart";
+ qup_uart10_default: qup-uart10-default-state {
+ qup_uart10_cts: cts-pins {
+ pins = "gpio86";
+ function = "qup14";
};
- };
- qup_uart5_default: qup-uart5-default {
- pinmux {
- pins = "gpio25", "gpio26",
- "gpio27", "gpio28";
- function = "qup05";
+ qup_uart10_rts: rts-pins {
+ pins = "gpio87";
+ function = "qup14";
};
- };
- qup_uart6_default: qup-uart6-default {
- pinmux {
- pins = "gpio59", "gpio60",
- "gpio61", "gpio62";
- function = "qup10";
+ qup_uart10_tx: tx-pins {
+ pins = "gpio88";
+ function = "qup14";
};
- };
- qup_uart7_default: qup-uart7-default {
- pinmux {
- pins = "gpio6", "gpio7";
- function = "qup11_uart";
+ qup_uart10_rx: rx-pins {
+ pins = "gpio89";
+ function = "qup14";
};
};
- qup_uart8_default: qup-uart8-default {
- pinmux {
- pins = "gpio44", "gpio45";
- function = "qup12";
+ qup_uart11_default: qup-uart11-default-state {
+ qup_uart11_cts: cts-pins {
+ pins = "gpio53";
+ function = "qup15";
};
- };
- qup_uart9_default: qup-uart9-default {
- pinmux {
- pins = "gpio46", "gpio47";
- function = "qup13_uart";
+ qup_uart11_rts: rts-pins {
+ pins = "gpio54";
+ function = "qup15";
};
- };
- qup_uart10_default: qup-uart10-default {
- pinmux {
- pins = "gpio86", "gpio87",
- "gpio88", "gpio89";
- function = "qup14";
+ qup_uart11_tx: tx-pins {
+ pins = "gpio55";
+ function = "qup15";
};
- };
- qup_uart11_default: qup-uart11-default {
- pinmux {
- pins = "gpio53", "gpio54",
- "gpio55", "gpio56";
+ qup_uart11_rx: rx-pins {
+ pins = "gpio56";
function = "qup15";
};
};
- sec_mi2s_active: sec-mi2s-active {
- pinmux {
- pins = "gpio49", "gpio50", "gpio51";
- function = "mi2s_1";
- };
+ sec_mi2s_active: sec-mi2s-active-state {
+ pins = "gpio49", "gpio50", "gpio51";
+ function = "mi2s_1";
};
- pri_mi2s_active: pri-mi2s-active {
- pinmux {
- pins = "gpio53", "gpio54", "gpio55", "gpio56";
- function = "mi2s_0";
- };
+ pri_mi2s_active: pri-mi2s-active-state {
+ pins = "gpio53", "gpio54", "gpio55", "gpio56";
+ function = "mi2s_0";
};
- pri_mi2s_mclk_active: pri-mi2s-mclk-active {
- pinmux {
- pins = "gpio57";
- function = "lpass_ext";
- };
+ pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
+ pins = "gpio57";
+ function = "lpass_ext";
+ };
+
+ ter_mi2s_active: ter-mi2s-active-state {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66";
+ function = "mi2s_2";
};
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7180-mpss-pas";
- reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
- reg-names = "qdsp6", "rmb";
+ reg = <0 0x04080000 0 0x4040>;
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1907,14 +2066,8 @@
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
- clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
- <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
- <&gcc GCC_MSS_NAV_AXI_CLK>,
- <&gcc GCC_MSS_SNOC_AXI_CLK>,
- <&gcc GCC_MSS_MFAB_AXIS_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "bus", "nav", "snoc_axi",
- "mnoc_axi", "xo";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
power-domains = <&rpmhpd SC7180_CX>,
<&rpmhpd SC7180_MX>,
@@ -1928,13 +2081,6 @@
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
- resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
- <&pdc_reset PDC_MODEM_SYNC_RESET>;
- reset-names = "mss_restart", "pdc_reset";
-
- qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
- qcom,spare-regs = <&tcsr_regs 0xb3e4>;
-
status = "disabled";
glink-edge {
@@ -2048,7 +2194,7 @@
};
gmu: gmu@506a000 {
- compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
+ compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
<0 0x0b490000 0 0x10000>;
reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
@@ -2089,6 +2235,12 @@
#power-domain-cells = <1>;
};
+ dma@10a2000 {
+ compatible = "qcom,sc7180-dcc", "qcom,dcc";
+ reg = <0x0 0x010a2000 0x0 0x1000>,
+ <0x0 0x010ae000 0x0 0x2000>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
@@ -2578,7 +2730,7 @@
};
};
- sdhc_2: sdhci@8804000 {
+ sdhc_2: mmc@8804000 {
compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@@ -2587,10 +2739,10 @@
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>,
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
- clock-names = "core", "iface", "xo";
+ clock-names = "iface", "core", "xo";
interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
@@ -2602,7 +2754,7 @@
status = "disabled";
- sdhc2_opp_table: sdhc2-opp-table {
+ sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
@@ -2621,28 +2773,10 @@
};
};
- qspi_opp_table: qspi-opp-table {
- compatible = "operating-points-v2";
-
- opp-75000000 {
- opp-hz = /bits/ 64 <75000000>;
- required-opps = <&rpmhpd_opp_low_svs>;
- };
-
- opp-150000000 {
- opp-hz = /bits/ 64 <150000000>;
- required-opps = <&rpmhpd_opp_svs>;
- };
-
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- required-opps = <&rpmhpd_opp_nom>;
- };
- };
-
qspi: spi@88dc000 {
compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
reg = <0 0x088dc000 0 0x600>;
+ iommus = <&apps_smmu 0x20 0x0>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
@@ -2670,48 +2804,111 @@
nvmem-cells = <&qusb2p_hstx_trim>;
};
- usb_1_qmpphy: phy-wrapper@88e9000 {
+ usb_1_qmpphy: phy@88e8000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
- reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x3c>,
- <0 0x088ea000 0 0x18c>;
+ reg = <0 0x088e8000 0 0x3000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe",
+ "cfg_ahb";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
- usb_1_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088e9200 0 0x128>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x218>,
- <0 0x088e9600 0 0x128>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x18>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+ };
+
+ pmu@90b6300 {
+ compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0 0x090b6300 0 0x600>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <2288000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <4577000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <7110000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <9155000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <12298000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <14236000>;
+ };
};
+ };
- dp_phy: dp-phy@88ea200 {
- reg = <0 0x088ea200 0 0x200>,
- <0 0x088ea400 0 0x200>,
- <0 0x088eaa00 0 0x200>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
+ pmu@90cd000 {
+ compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0 0x090cd000 0 0x1000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+ llcc_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <1144000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <1720000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <2086000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <2929000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <3879000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <5931000>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <6881000>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <8137000>;
+ };
};
};
@@ -2725,7 +2922,7 @@
system-cache-controller@9200000 {
compatible = "qcom,sc7180-llcc";
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
- reg-names = "llcc_base", "llcc_broadcast_base";
+ reg-names = "llcc0_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -2769,12 +2966,13 @@
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
+ <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
@@ -2782,6 +2980,8 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
interconnect-names = "usb-ddr", "apps-usb";
+ wakeup-source;
+
usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xe000>;
@@ -2789,7 +2989,7 @@
iommus = <&apps_smmu 0x540 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
};
@@ -2825,7 +3025,7 @@
compatible = "venus-encoder";
};
- venus_opp_table: venus-opp-table {
+ venus_opp_table: opp-table {
compatible = "operating-points-v2";
opp-150000000 {
@@ -2884,7 +3084,7 @@
#power-domain-cells = <1>;
};
- mdss: mdss@ae00000 {
+ mdss: display-subsystem@ae00000 {
compatible = "qcom,sc7180-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
@@ -2896,15 +3096,16 @@
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "ahb", "core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
- assigned-clock-rates = <300000000>;
-
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
- interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
- interconnect-names = "mdp0-mem";
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
iommus = <&apps_smmu 0x800 0x2>;
@@ -2914,7 +3115,7 @@
status = "disabled";
- mdp: mdp@ae01000 {
+ mdp: display-controller@ae01000 {
compatible = "qcom,sc7180-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x2008>;
@@ -2928,12 +3129,10 @@
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus", "iface", "rot", "lut", "core",
"vsync";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
- <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>;
- assigned-clock-rates = <300000000>,
- <19200000>,
+ assigned-clock-rates = <19200000>,
<19200000>,
<19200000>;
operating-points-v2 = <&mdp_opp_table>;
@@ -2942,8 +3141,6 @@
interrupt-parent = <&mdss>;
interrupts = <0>;
- status = "disabled";
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2951,7 +3148,7 @@
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ remote-endpoint = <&mdss_dsi0_in>;
};
};
@@ -2963,7 +3160,7 @@
};
};
- mdp_opp_table: mdp-opp-table {
+ mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
@@ -2986,11 +3183,11 @@
required-opps = <&rpmhpd_opp_nom>;
};
};
-
};
- dsi0: dsi@ae94000 {
- compatible = "qcom,mdss-dsi-ctrl";
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,sc7180-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
@@ -3011,13 +3208,12 @@
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
- assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC7180_CX>;
- phys = <&dsi_phy>;
- phy-names = "dsi";
+ phys = <&mdss_dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
@@ -3030,19 +3226,19 @@
port@0 {
reg = <0>;
- dsi0_in: endpoint {
+ mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
- dsi0_out: endpoint {
+ mdss_dsi0_out: endpoint {
};
};
};
- dsi_opp_table: dsi-opp-table {
+ dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-187500000 {
@@ -3062,7 +3258,7 @@
};
};
- dsi_phy: dsi-phy@ae94400 {
+ mdss_dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
@@ -3085,7 +3281,11 @@
compatible = "qcom,sc7180-dp";
status = "disabled";
- reg = <0 0x0ae90000 0 0x1400>;
+ reg = <0 0x0ae90000 0 0x200>,
+ <0 0x0ae90200 0 0x200>,
+ <0 0x0ae90400 0 0xc00>,
+ <0 0x0ae91000 0 0x400>,
+ <0 0x0ae91400 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <12>;
@@ -3097,11 +3297,11 @@
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
clock-names = "core_iface", "core_aux", "ctrl_link",
"ctrl_link_iface", "stream_pixel";
- #clock-cells = <1>;
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
- phys = <&dp_phy>;
+ assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+ phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
@@ -3121,7 +3321,7 @@
port@1 {
reg = <1>;
- dp_out: endpoint { };
+ mdss_dp_out: endpoint { };
};
};
@@ -3156,10 +3356,10 @@
reg = <0 0x0af00000 0 0x200000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
- <&dsi_phy 0>,
- <&dsi_phy 1>,
- <&dp_phy 0>,
- <&dp_phy 1>;
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"dsi0_phy_pll_out_byteclk",
@@ -3214,8 +3414,8 @@
#reset-cells = <1>;
};
- aoss_qmp: power-controller@c300000 {
- compatible = "qcom,sc7180-aoss-qmp";
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
@@ -3240,15 +3440,14 @@
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
- cell-index = <0>;
};
- imem@146aa000 {
- compatible = "simple-mfd";
+ sram@146aa000 {
+ compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
reg = <0 0x146aa000 0 0x2000>;
#address-cells = <1>;
@@ -3371,7 +3570,8 @@
};
apss_shared: mailbox@17c00000 {
- compatible = "qcom,sc7180-apss-shared";
+ compatible = "qcom,sc7180-apss-shared",
+ "qcom,sdm845-apss-shared";
reg = <0 0x17c00000 0 0x10000>;
#mbox-cells = <1>;
};
@@ -3380,13 +3580,13 @@
compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
- timer@17c20000{
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ timer@17c20000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x20000000>;
compatible = "arm,armv7-timer-mem";
reg = <0 0x17c20000 0 0x1000>;
@@ -3394,49 +3594,49 @@
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0 0x17c21000 0 0x1000>,
- <0 0x17c22000 0 0x1000>;
+ reg = <0x17c21000 0x1000>,
+ <0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0 0x17c23000 0 0x1000>;
+ reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0 0x17c25000 0 0x1000>;
+ reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0 0x17c27000 0 0x1000>;
+ reg = <0x17c27000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0 0x17c29000 0 0x1000>;
+ reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0 0x17c2b000 0 0x1000>;
+ reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0 0x17c2d000 0 0x1000>;
+ reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
@@ -3456,6 +3656,7 @@
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+ power-domains = <&CLUSTER_PD>;
rpmhcc: clock-controller {
compatible = "qcom,sc7180-rpmh-clk";
@@ -3524,7 +3725,7 @@
};
osm_l3: interconnect@18321000 {
- compatible = "qcom,sc7180-osm-l3";
+ compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
reg = <0 0x18321000 0 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
@@ -3534,7 +3735,7 @@
};
cpufreq_hw: cpufreq@18323000 {
- compatible = "qcom,cpufreq-hw";
+ compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
@@ -3542,6 +3743,7 @@
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
+ #clock-cells = <1>;
};
wifi: wifi@18800000 {
@@ -3567,6 +3769,126 @@
status = "disabled";
};
+ remoteproc_adsp: remoteproc@62400000 {
+ compatible = "qcom,sc7180-adsp-pas";
+ reg = <0 0x62400000 0 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SC7180_LCX>,
+ <&rpmhpd SC7180_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ qcom,qmp = <&aoss_qmp>;
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ mboxes = <&apss_shared 8>;
+
+ apr {
+ compatible = "qcom,apr-v2";
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,domain = <APR_DOMAIN_ADSP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ service@3 {
+ compatible = "qcom,q6core";
+ reg = <APR_SVC_ADSP_CORE>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+ };
+
+ q6afe: service@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ q6afecc: clock-controller {
+ compatible = "qcom,q6afe-clocks";
+ #clock-cells = <2>;
+ };
+ };
+
+ q6asm: service@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ iommus = <&apps_smmu 0x1001 0x0>;
+ };
+ };
+
+ q6adm: service@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6routing: routing {
+ compatible = "qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1003 0x0>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1004 0x0>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1005 0x0>;
+ qcom,nsessions = <5>;
+ };
+ };
+ };
+ };
+
lpasscc: clock-controller@62d00000 {
compatible = "qcom,sc7180-lpasscorecc";
reg = <0 0x62d00000 0 0x50000>,
@@ -3578,19 +3900,22 @@
power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
#clock-cells = <1>;
#power-domain-cells = <1>;
+
+ status = "reserved"; /* Controlled by ADSP */
};
lpass_cpu: lpass@62d87000 {
compatible = "qcom,sc7180-lpass-cpu";
reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
- reg-names = "lpass-hdmiif", "lpass-lpaif";
+ reg-names = "lpass-hdmiif", "lpass-lpaif";
iommus = <&apps_smmu 0x1020 0>,
<&apps_smmu 0x1021 0>,
<&apps_smmu 0x1032 0>;
power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
+ required-opps = <&rpmhpd_opp_nom>;
status = "disabled";
@@ -3621,8 +3946,12 @@
clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "bi_tcxo";
+ power-domains = <&rpmhpd SC7180_CX>;
+
#clock-cells = <1>;
#power-domain-cells = <1>;
+
+ status = "reserved"; /* Controlled by ADSP */
};
};
@@ -3647,7 +3976,7 @@
type = "passive";
};
- cpu0_crit: cpu_crit {
+ cpu0_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -3696,7 +4025,7 @@
type = "passive";
};
- cpu1_crit: cpu_crit {
+ cpu1_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -3745,7 +4074,7 @@
type = "passive";
};
- cpu2_crit: cpu_crit {
+ cpu2_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -3794,7 +4123,7 @@
type = "passive";
};
- cpu3_crit: cpu_crit {
+ cpu3_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -3843,7 +4172,7 @@
type = "passive";
};
- cpu4_crit: cpu_crit {
+ cpu4_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -3892,7 +4221,7 @@
type = "passive";
};
- cpu5_crit: cpu_crit {
+ cpu5_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -3941,7 +4270,7 @@
type = "passive";
};
- cpu6_crit: cpu_crit {
+ cpu6_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -3982,7 +4311,7 @@
type = "passive";
};
- cpu7_crit: cpu_crit {
+ cpu7_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4023,7 +4352,7 @@
type = "passive";
};
- cpu8_crit: cpu_crit {
+ cpu8_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4064,7 +4393,7 @@
type = "passive";
};
- cpu9_crit: cpu_crit {
+ cpu9_crit: cpu-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -4098,7 +4427,7 @@
type = "hot";
};
- aoss0_crit: aoss0_crit {
+ aoss0_crit: aoss0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4118,7 +4447,7 @@
hysteresis = <2000>;
type = "hot";
};
- cpuss0_crit: cluster0_crit {
+ cpuss0_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4138,7 +4467,7 @@
hysteresis = <2000>;
type = "hot";
};
- cpuss1_crit: cluster0_crit {
+ cpuss1_crit: cluster0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4159,7 +4488,7 @@
type = "passive";
};
- gpuss0_crit: gpuss0_crit {
+ gpuss0_crit: gpuss0-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4187,7 +4516,7 @@
type = "passive";
};
- gpuss1_crit: gpuss1_crit {
+ gpuss1_crit: gpuss1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4215,7 +4544,7 @@
type = "hot";
};
- aoss1_crit: aoss1_crit {
+ aoss1_crit: aoss1-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4236,7 +4565,7 @@
type = "hot";
};
- cwlan_crit: cwlan_crit {
+ cwlan_crit: cwlan-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4257,7 +4586,7 @@
type = "hot";
};
- audio_crit: audio_crit {
+ audio_crit: audio-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4278,7 +4607,7 @@
type = "hot";
};
- ddr_crit: ddr_crit {
+ ddr_crit: ddr-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4299,7 +4628,7 @@
type = "hot";
};
- q6_hvx_crit: q6_hvx_crit {
+ q6_hvx_crit: q6-hvx-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4320,7 +4649,7 @@
type = "hot";
};
- camera_crit: camera_crit {
+ camera_crit: camera-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4341,7 +4670,7 @@
type = "hot";
};
- mdm_crit: mdm_crit {
+ mdm_crit: mdm-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4362,7 +4691,7 @@
type = "hot";
};
- mdm_dsp_crit: mdm_dsp_crit {
+ mdm_dsp_crit: mdm-dsp-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4383,7 +4712,7 @@
type = "hot";
};
- npu_crit: npu_crit {
+ npu_crit: npu-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -4404,7 +4733,7 @@
type = "hot";
};
- video_crit: video_crit {
+ video_crit: video-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-18 12:23:20 +0000