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-rw-r--r--dts/src/arm64/qcom/sc7180.dtsi126
1 files changed, 119 insertions, 7 deletions
diff --git a/dts/src/arm64/qcom/sc7180.dtsi b/dts/src/arm64/qcom/sc7180.dtsi
index a9a052f8c6..c8921e2d64 100644
--- a/dts/src/arm64/qcom/sc7180.dtsi
+++ b/dts/src/arm64/qcom/sc7180.dtsi
@@ -110,6 +110,11 @@
no-map;
};
+ ipa_fw_mem: memory@8b700000 {
+ reg = <0 0x8b700000 0 0x10000>;
+ no-map;
+ };
+
rmtfs_mem: memory@94600000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x94600000 0x0 0x200000>;
@@ -668,7 +673,7 @@
qfprom: efuse@784000 {
compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
- reg = <0 0x00784000 0 0x8ff>,
+ reg = <0 0x00784000 0 0x7a0>,
<0 0x00780000 0 0x7a0>,
<0 0x00782000 0 0x100>,
<0 0x00786000 0 0x1fff>;
@@ -786,6 +791,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -838,6 +845,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -890,6 +899,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -924,6 +935,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -976,6 +989,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -1010,6 +1025,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -1075,6 +1092,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -1127,6 +1146,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -1161,6 +1182,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -1213,6 +1236,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -1247,6 +1272,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -1299,6 +1326,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
status = "disabled";
};
@@ -2928,6 +2957,13 @@
remote-endpoint = <&dsi0_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
+ };
+ };
};
mdp_opp_table: mdp-opp-table {
@@ -2977,6 +3013,9 @@
"iface",
"bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
+
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC7180_CX>;
@@ -3044,6 +3083,75 @@
status = "disabled";
};
+
+ mdss_dp: displayport-controller@ae90000 {
+ compatible = "qcom,sc7180-dp";
+ status = "disabled";
+
+ reg = <0 0x0ae90000 0 0x1400>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface", "core_aux", "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SC7180_CX>;
+
+ #sound-dai-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
};
dispcc: clock-controller@af00000 {
@@ -3456,17 +3564,20 @@
#power-domain-cells = <1>;
};
- lpass_cpu: lpass@62f00000 {
+ lpass_cpu: lpass@62d87000 {
compatible = "qcom,sc7180-lpass-cpu";
- reg = <0 0x62f00000 0 0x29000>;
- reg-names = "lpass-lpaif";
+ reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
+ reg-names = "lpass-hdmiif", "lpass-lpaif";
iommus = <&apps_smmu 0x1020 0>,
- <&apps_smmu 0x1021 0>;
+ <&apps_smmu 0x1021 0>,
+ <&apps_smmu 0x1032 0>;
power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
+ status = "disabled";
+
clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
<&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
<&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
@@ -3483,8 +3594,9 @@
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "lpass-irq-lpaif";
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
};
lpass_hm: clock-controller@63000000 {
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-24 11:56:30 +0000