diff options
Diffstat (limited to 'dts/src/arm64/qcom/sc7180.dtsi')
| -rw-r--r-- | dts/src/arm64/qcom/sc7180.dtsi | 58 |
1 files changed, 25 insertions, 33 deletions
diff --git a/dts/src/arm64/qcom/sc7180.dtsi b/dts/src/arm64/qcom/sc7180.dtsi index 1ea3344ab6..6228ba2d85 100644 --- a/dts/src/arm64/qcom/sc7180.dtsi +++ b/dts/src/arm64/qcom/sc7180.dtsi @@ -110,9 +110,9 @@ no-map; }; - rmtfs_mem: memory@84400000 { + rmtfs_mem: memory@94600000 { compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x84400000 0x0 0x200000>; + reg = <0x0 0x94600000 0x0 0x200000>; no-map; qcom,client-id = <1>; @@ -1856,12 +1856,6 @@ pins = "gpio49", "gpio50", "gpio51"; function = "mi2s_1"; }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51"; - drive-strength = <8>; - bias-pull-up; - }; }; pri_mi2s_active: pri-mi2s-active { @@ -1869,12 +1863,6 @@ pins = "gpio53", "gpio54", "gpio55", "gpio56"; function = "mi2s_0"; }; - - pinconf { - pins = "gpio53", "gpio54", "gpio55", "gpio56"; - drive-strength = <8>; - bias-pull-up; - }; }; pri_mi2s_mclk_active: pri-mi2s-mclk-active { @@ -1882,12 +1870,6 @@ pins = "gpio57"; function = "lpass_ext"; }; - - pinconf { - pins = "gpio57"; - drive-strength = <8>; - bias-pull-up; - }; }; sdc1_on: sdc1-on { @@ -2770,12 +2752,11 @@ }; usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sc7180-qmp-usb3-phy"; + compatible = "qcom,sc7180-qmp-usb3-dp-phy"; reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x38>; - reg-names = "reg-base", "dp_com"; + <0 0x088e8000 0 0x38>, + <0 0x088ea000 0 0x40>; status = "disabled"; - #clock-cells = <1>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -2790,7 +2771,7 @@ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: phy@88e9200 { + usb_1_ssphy: usb3-phy@88e9200 { reg = <0 0x088e9200 0 0x128>, <0 0x088e9400 0 0x200>, <0 0x088e9c00 0 0x218>, @@ -2803,6 +2784,16 @@ clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; }; + + dp_phy: dp-phy@88ea200 { + reg = <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eaa00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; }; dc_noc: interconnect@9160000 { @@ -2854,10 +2845,10 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; @@ -3166,8 +3157,8 @@ <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, <&dsi_phy 1>, - <0>, - <0>; + <&dp_phy 0>, + <&dp_phy 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "dsi0_phy_pll_out_byteclk", @@ -3222,7 +3213,7 @@ #reset-cells = <1>; }; - aoss_qmp: qmp@c300000 { + aoss_qmp: power-controller@c300000 { compatible = "qcom,sc7180-aoss-qmp"; reg = <0 0x0c300000 0 0x100000>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; @@ -3575,7 +3566,8 @@ reg = <0 0x62f00000 0 0x29000>; reg-names = "lpass-lpaif"; - iommus = <&apps_smmu 0x1020 0>; + iommus = <&apps_smmu 0x1020 0>, + <&apps_smmu 0x1021 0>; power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; |