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-rw-r--r--dts/src/arm64/qcom/sdm845-mtp.dts259
1 files changed, 164 insertions, 95 deletions
diff --git a/dts/src/arm64/qcom/sdm845-mtp.dts b/dts/src/arm64/qcom/sdm845-mtp.dts
index 7713e8060c..76bfa78661 100644
--- a/dts/src/arm64/qcom/sdm845-mtp.dts
+++ b/dts/src/arm64/qcom/sdm845-mtp.dts
@@ -15,6 +15,7 @@
/ {
model = "Qualcomm Technologies, Inc. SDM845 MTP";
compatible = "qcom,sdm845-mtp", "qcom,sdm845";
+ chassis-type = "handset";
aliases {
serial0 = &uart9;
@@ -113,11 +114,11 @@
&adsp_pas {
status = "okay";
- firmware-name = "qcom/sdm845/adsp.mdt";
+ firmware-name = "qcom/sdm845/adsp.mbn";
};
&apps_rsc {
- pm8998-rpmh-regulators {
+ regulators-0 {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
@@ -382,7 +383,7 @@
};
};
- pmi8998-rpmh-regulators {
+ regulators-1 {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
@@ -396,7 +397,7 @@
};
};
- pm8005-rpmh-regulators {
+ regulators-2 {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";
@@ -414,10 +415,46 @@
&cdsp_pas {
status = "okay";
- firmware-name = "qcom/sdm845/cdsp.mdt";
+ firmware-name = "qcom/sdm845/cdsp.mbn";
};
-&dsi0 {
+&gcc {
+ protected-clocks = <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_LPASS_Q6_AXI_CLK>,
+ <GCC_LPASS_SWAY_CLK>;
+};
+
+&gmu {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ firmware-name = "qcom/sdm845/a630_zap.mbn";
+ };
+};
+
+&i2c10 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
@@ -448,33 +485,33 @@
port@0 {
reg = <0>;
truly_in_0: endpoint {
- remote-endpoint = <&dsi0_out>;
+ remote-endpoint = <&mdss_dsi0_out>;
};
};
port@1 {
reg = <1>;
truly_in_1: endpoint {
- remote-endpoint = <&dsi1_out>;
+ remote-endpoint = <&mdss_dsi1_out>;
};
};
};
};
};
-&dsi0_phy {
+&mdss_dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
-&dsi1 {
+&mdss_dsi1 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi1_1p2>;
qcom,dual-dsi-mode;
/* DSI1 is slave, so use DSI0 clocks */
- assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
ports {
port@1 {
@@ -486,92 +523,89 @@
};
};
-&dsi1_phy {
+&mdss_dsi1_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi1_pll>;
};
-&gcc {
- protected-clocks = <GCC_QSPI_CORE_CLK>,
- <GCC_QSPI_CORE_CLK_SRC>,
- <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
- <GCC_LPASS_Q6_AXI_CLK>,
- <GCC_LPASS_SWAY_CLK>;
-};
-
-&gmu {
+&mss_pil {
status = "okay";
+ firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
};
-&gpu {
- status = "okay";
+&pcie0 {
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- zap-shader {
- memory-region = <&gpu_mem>;
- firmware-name = "qcom/sdm845/a630_zap.mbn";
- };
-};
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
-&i2c10 {
status = "okay";
- clock-frequency = <400000>;
};
-&ipa {
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l26a_1p2>;
+
status = "okay";
- memory-region = <&ipa_fw_mem>;
};
-&mdss {
+&pcie1 {
+ perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
status = "okay";
};
-&mss_pil {
+&pcie1_phy {
status = "okay";
- firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
+
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l26a_1p2>;
};
&pm8998_adc {
- adc-chan@4c {
+ channel@4c {
reg = <ADC5_XO_THERM_100K_PU>;
label = "xo_therm";
qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
+ qcom,hw-settle-time = <200>;
};
- adc-chan@4d {
+ channel@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
label = "msm_therm";
qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
+ qcom,hw-settle-time = <200>;
};
- adc-chan@4f {
+ channel@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
label = "pa_therm1";
qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
+ qcom,hw-settle-time = <200>;
};
- adc-chan@51 {
+ channel@51 {
reg = <ADC5_AMUX_THM5_100K_PU>;
label = "quiet_therm";
qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
+ qcom,hw-settle-time = <200>;
};
- adc-chan@83 {
+ channel@83 {
reg = <ADC5_VPH_PWR>;
label = "vph_pwr";
qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
+ qcom,hw-settle-time = <200>;
};
- adc-chan@85 {
+ channel@85 {
reg = <ADC5_VCOIN>;
label = "vcoin";
qcom,ratiometric;
- qcom,hw-settle-time-us = <200>;
+ qcom,hw-settle-time = <200>;
};
};
@@ -607,6 +641,11 @@
};
};
+&pm8998_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
&qupv3_id_1 {
status = "okay";
};
@@ -623,6 +662,52 @@
cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
};
+&tlmm {
+ pcie0_default_state: pcie0-default-state {
+ clkreq-pins {
+ pins = "gpio36";
+ function = "pci_e0";
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio37";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_state: pcie1-default-state {
+ clkreq-pins {
+ pins = "gpio103";
+ function = "pci_e1";
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio102";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
&uart9 {
status = "okay";
};
@@ -714,73 +799,57 @@
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
+
+ qcom,snoc-host-cap-8bit-quirk;
+ qcom,ath10k-calibration-variant = "Qualcomm_sdm845mtp";
};
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
&qup_i2c10_default {
- pinconf {
- pins = "gpio55", "gpio56";
- drive-strength = <2>;
- bias-disable;
- };
+ drive-strength = <2>;
+ bias-disable;
};
-&qup_uart9_default {
- pinconf-tx {
- pins = "gpio4";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart9_rx {
+ drive-strength = <2>;
+ bias-pull-up;
+};
- pinconf-rx {
- pins = "gpio5";
- drive-strength = <2>;
- bias-pull-up;
- };
+&qup_uart9_tx {
+ drive-strength = <2>;
+ bias-disable;
};
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
- sdc2_clk: sdc2-clk {
- pinconf {
- pins = "sdc2_clk";
- bias-disable;
+ sdc2_clk: sdc2-clk-state {
+ pins = "sdc2_clk";
+ bias-disable;
- /*
- * It seems that mmc_test reports errors if drive
- * strength is not 16 on clk, cmd, and data pins.
- */
- drive-strength = <16>;
- };
+ /*
+ * It seems that mmc_test reports errors if drive
+ * strength is not 16 on clk, cmd, and data pins.
+ */
+ drive-strength = <16>;
};
- sdc2_cmd: sdc2-cmd {
- pinconf {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <16>;
- };
+ sdc2_cmd: sdc2-cmd-state {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <16>;
};
- sdc2_data: sdc2-data {
- pinconf {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <16>;
- };
+ sdc2_data: sdc2-data-state {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <16>;
};
- sd_card_det_n: sd-card-det-n {
- pinmux {
- pins = "gpio126";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio126";
- bias-pull-up;
- };
+ sd_card_det_n: sd-card-det-n-state {
+ pins = "gpio126";
+ function = "gpio";
+ bias-pull-up;
};
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-25 17:01:48 +0000