diff options
Diffstat (limited to 'dts/src/arm64/qcom')
94 files changed, 3638 insertions, 985 deletions
diff --git a/dts/src/arm64/qcom/apq8096-db820c.dts b/dts/src/arm64/qcom/apq8096-db820c.dts index c1cb1ba517..5cdc7ac1a9 100644 --- a/dts/src/arm64/qcom/apq8096-db820c.dts +++ b/dts/src/arm64/qcom/apq8096-db820c.dts @@ -14,6 +14,7 @@ #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> +#include <dt-bindings/sound/qcom,wcd9335.h> /* * GPIO name legend: proper name = the GPIO line is used as GPIO @@ -502,20 +503,20 @@ &pcie0 { status = "okay"; - perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; }; &pcie1 { status = "okay"; - perst-gpio = <&tlmm 130 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; &pcie2 { status = "okay"; - perst-gpio = <&tlmm 114 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; @@ -1064,7 +1065,7 @@ }; codec { - sound-dai = <&wcd9335 6>; + sound-dai = <&wcd9335 AIF4_PB>; }; }; @@ -1079,7 +1080,7 @@ }; codec { - sound-dai = <&wcd9335 1>; + sound-dai = <&wcd9335 AIF1_CAP>; }; }; }; diff --git a/dts/src/arm64/qcom/apq8096-ifc6640.dts b/dts/src/arm64/qcom/apq8096-ifc6640.dts index 567b331065..92f264891d 100644 --- a/dts/src/arm64/qcom/apq8096-ifc6640.dts +++ b/dts/src/arm64/qcom/apq8096-ifc6640.dts @@ -368,7 +368,7 @@ bus-width = <4>; - cd-gpios = <&tlmm 38 0x1>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; vmmc-supply = <&vreg_l21a_2p95>; vqmmc-supply = <&vreg_l13a_2p95>; diff --git a/dts/src/arm64/qcom/ipq6018.dtsi b/dts/src/arm64/qcom/ipq6018.dtsi index aaad7d9059..a7c7ca980a 100644 --- a/dts/src/arm64/qcom/ipq6018.dtsi +++ b/dts/src/arm64/qcom/ipq6018.dtsi @@ -129,12 +129,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; - #hwlock-cells = <1>; - }; - pmuv8: pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | @@ -252,13 +246,14 @@ #reset-cells = <1>; }; - tcsr_mutex_regs: syscon@1905000 { - compatible = "syscon"; - reg = <0x0 0x01905000 0x0 0x8000>; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; + reg = <0x0 0x01905000 0x0 0x1000>; + #hwlock-cells = <1>; }; tcsr: syscon@1937000 { - compatible = "syscon"; + compatible = "qcom,tcsr-ipq6018", "syscon"; reg = <0x0 0x01937000 0x0 0x21000>; }; diff --git a/dts/src/arm64/qcom/ipq8074-hk01.dts b/dts/src/arm64/qcom/ipq8074-hk01.dts index 81dc3a0bcd..7143c936de 100644 --- a/dts/src/arm64/qcom/ipq8074-hk01.dts +++ b/dts/src/arm64/qcom/ipq8074-hk01.dts @@ -51,12 +51,12 @@ &pcie0 { status = "okay"; - perst-gpio = <&tlmm 61 0x1>; + perst-gpios = <&tlmm 61 0x1>; }; &pcie1 { status = "okay"; - perst-gpio = <&tlmm 58 0x1>; + perst-gpios = <&tlmm 58 0x1>; }; &pcie_phy0 { diff --git a/dts/src/arm64/qcom/ipq8074-hk10.dtsi b/dts/src/arm64/qcom/ipq8074-hk10.dtsi index 40415d988e..db4b87944c 100644 --- a/dts/src/arm64/qcom/ipq8074-hk10.dtsi +++ b/dts/src/arm64/qcom/ipq8074-hk10.dtsi @@ -39,12 +39,12 @@ &pcie0 { status = "ok"; - perst-gpio = <&tlmm 58 0x1>; + perst-gpios = <&tlmm 58 0x1>; }; &pcie1 { status = "ok"; - perst-gpio = <&tlmm 61 0x1>; + perst-gpios = <&tlmm 61 0x1>; }; &pcie_phy0 { diff --git a/dts/src/arm64/qcom/ipq8074.dtsi b/dts/src/arm64/qcom/ipq8074.dtsi index d53675fc15..a47acf9bdf 100644 --- a/dts/src/arm64/qcom/ipq8074.dtsi +++ b/dts/src/arm64/qcom/ipq8074.dtsi @@ -199,7 +199,7 @@ pcie_qmp0: phy@86000 { compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x00086000 0x1000>; + reg = <0x00086000 0x1c4>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -227,7 +227,7 @@ pcie_qmp1: phy@8e000 { compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x0008e000 0x1000>; + reg = <0x0008e000 0x1c4>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -383,7 +383,7 @@ sdhc_1: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi index 10f6509a87..3255bd3fcb 100644 --- a/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi +++ b/dts/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi @@ -61,9 +61,9 @@ }; }; - reg_vdd_tsp: regulator-vdd-tsp { + reg_vdd_tsp_a: regulator-vdd-tsp-a { compatible = "regulator-fixed"; - regulator-name = "vdd_tsp"; + regulator-name = "vdd_tsp_a"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts b/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts index bc198a2eea..6db5f78ca2 100644 --- a/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts +++ b/dts/src/arm64/qcom/msm8916-samsung-a3u-eur.dts @@ -73,8 +73,8 @@ touchscreen-size-x = <540>; touchscreen-size-y = <960>; - vdd-supply = <®_vdd_tsp>; - vddo-supply = <&pm8916_l6>; + vcca-supply = <®_vdd_tsp_a>; + vdd-supply = <&pm8916_l6>; pinctrl-names = "default"; pinctrl-0 = <&ts_int_default>; diff --git a/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts b/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts index 7f2ab1891d..5fb8ecd0c9 100644 --- a/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts +++ b/dts/src/arm64/qcom/msm8916-samsung-a5u-eur.dts @@ -42,7 +42,7 @@ touchscreen-size-x = <720>; touchscreen-size-y = <1280>; - avdd-supply = <®_vdd_tsp>; + avdd-supply = <®_vdd_tsp_a>; vdd-supply = <&pm8916_l6>; pinctrl-names = "default"; diff --git a/dts/src/arm64/qcom/msm8916-samsung-e2015-common.dtsi b/dts/src/arm64/qcom/msm8916-samsung-e2015-common.dtsi new file mode 100644 index 0000000000..542010fdfb --- /dev/null +++ b/dts/src/arm64/qcom/msm8916-samsung-e2015-common.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-samsung-a2015-common.dtsi" + +/ { + haptic { + compatible = "regulator-haptic"; + haptic-supply = <®_motor_vdd>; + min-microvolt = <3300000>; + max-microvolt = <3300000>; + }; + + i2c-muic { + /* SM5504 MUIC instead of SM5502 */ + /delete-node/ extcon@25; + + muic: extcon@14 { + compatible = "siliconmitus,sm5504-muic"; + reg = <0x14>; + + interrupt-parent = <&msmgpio>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_int_default>; + }; + }; + + reg_motor_vdd: regulator-motor-vdd { + compatible = "regulator-fixed"; + regulator-name = "motor_vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&motor_en_default>; + }; + + reg_touch_key: regulator-touch-key { + compatible = "regulator-fixed"; + regulator-name = "touch_key"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_en_default>; + }; +}; + +&blsp_i2c2 { + /* lis2hh12 accelerometer instead of BMC150 */ + status = "disabled"; + + /delete-node/ accelerometer@10; + /delete-node/ magnetometer@12; +}; + +&touchkey { + vcc-supply = <®_touch_key>; + vdd-supply = <®_touch_key>; +}; + +&msmgpio { + motor_en_default: motor-en-default { + pins = "gpio76"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_en_default: tkey-en-default { + pins = "gpio97"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/dts/src/arm64/qcom/msm8916-samsung-e5.dts b/dts/src/arm64/qcom/msm8916-samsung-e5.dts new file mode 100644 index 0000000000..777eb934eb --- /dev/null +++ b/dts/src/arm64/qcom/msm8916-samsung-e5.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-e2015-common.dtsi" + +/* + * NOTE: The original firmware from Samsung can only boot ARM32 kernels on some + * variants. + * Unfortunately, the firmware is signed and cannot be replaced easily. + * There seems to be no way to boot ARM64 kernels on 32-bit devices at the + * moment, even though the hardware would support it. + * + * However, it is possible to use this device tree by compiling an ARM32 kernel + * instead. For clarity and build testing this device tree is maintained next + * to the other MSM8916 device trees. However, it is actually used through + * arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts + */ + +/ { + model = "Samsung Galaxy E5"; + compatible = "samsung,e5", "qcom,msm8916"; + chassis-type = "handset"; +}; diff --git a/dts/src/arm64/qcom/msm8916-samsung-e7.dts b/dts/src/arm64/qcom/msm8916-samsung-e7.dts new file mode 100644 index 0000000000..b412b61ca2 --- /dev/null +++ b/dts/src/arm64/qcom/msm8916-samsung-e7.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-e2015-common.dtsi" + +/* + * NOTE: The original firmware from Samsung can only boot ARM32 kernels on some + * variants. + * Unfortunately, the firmware is signed and cannot be replaced easily. + * There seems to be no way to boot ARM64 kernels on 32-bit devices at the + * moment, even though the hardware would support it. + * + * However, it is possible to use this device tree by compiling an ARM32 kernel + * instead. For clarity and build testing this device tree is maintained next + * to the other MSM8916 device trees. However, it is actually used through + * arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts + */ + +/ { + model = "Samsung Galaxy E7"; + compatible = "samsung,e7", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&pm8916_l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; diff --git a/dts/src/arm64/qcom/msm8916-samsung-grandmax.dts b/dts/src/arm64/qcom/msm8916-samsung-grandmax.dts new file mode 100644 index 0000000000..bc71346989 --- /dev/null +++ b/dts/src/arm64/qcom/msm8916-samsung-grandmax.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-e2015-common.dtsi" +#include <dt-bindings/leds/common.h> + +/* + * NOTE: The original firmware from Samsung can only boot ARM32 kernels on some + * variants. + * Unfortunately, the firmware is signed and cannot be replaced easily. + * There seems to be no way to boot ARM64 kernels on 32-bit devices at the + * moment, even though the hardware would support it. + * + * However, it is possible to use this device tree by compiling an ARM32 kernel + * instead. For clarity and build testing this device tree is maintained next + * to the other MSM8916 device trees. However, it is actually used through + * arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts + */ + +/ { + model = "Samsung Galaxy Grand Max"; + compatible = "samsung,grandmax", "qcom,msm8916"; + chassis-type = "handset"; + + /delete-node/ gpio-hall-sensor; + /delete-node/ i2c-nfc; + /delete-node/ i2c-tkey; + + gpio-leds { + compatible = "gpio-leds"; + keyled { + gpios = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds_default>; + }; + }; +}; + +®_motor_vdd { + gpio = <&msmgpio 72 GPIO_ACTIVE_HIGH>; +}; + +®_touch_key { + status = "disabled"; +}; + +&msmgpio { + gpio_leds_default: gpio-led-default { + pins = "gpio60"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; +}; + +&motor_en_default { + pins = "gpio72"; +}; diff --git a/dts/src/arm64/qcom/msm8916-samsung-serranove.dts b/dts/src/arm64/qcom/msm8916-samsung-serranove.dts index 439e89cf78..bbd6bb3f4f 100644 --- a/dts/src/arm64/qcom/msm8916-samsung-serranove.dts +++ b/dts/src/arm64/qcom/msm8916-samsung-serranove.dts @@ -210,6 +210,15 @@ pinctrl-names = "default"; pinctrl-0 = <&imu_irq_default>; }; + + magnetometer@2e { + compatible = "yamaha,yas537"; + reg = <0x2e>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + }; }; &blsp_i2c4 { diff --git a/dts/src/arm64/qcom/msm8916.dtsi b/dts/src/arm64/qcom/msm8916.dtsi index 48bc2e0912..a831064700 100644 --- a/dts/src/arm64/qcom/msm8916.dtsi +++ b/dts/src/arm64/qcom/msm8916.dtsi @@ -936,6 +936,20 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0x01800000 0x80000>; + clocks = <&xo_board>, + <&sleep_clk>, + <&dsi_phy0 1>, + <&dsi_phy0 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep_clk", + "dsi0pll", + "dsi0pllbyte", + "ext_mclk", + "ext_pri_i2s", + "ext_sec_i2s"; }; tcsr_mutex: hwlock@1905000 { @@ -1469,7 +1483,7 @@ sdhc_1: mmc@7824000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -1487,7 +1501,7 @@ sdhc_2: mmc@7864000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm64/qcom/msm8953.dtsi b/dts/src/arm64/qcom/msm8953.dtsi index 8416a45ca4..6b992a6d56 100644 --- a/dts/src/arm64/qcom/msm8953.dtsi +++ b/dts/src/arm64/qcom/msm8953.dtsi @@ -722,7 +722,7 @@ }; tcsr_phy_clk_scheme_sel: syscon@193f044 { - compatible = "syscon"; + compatible = "qcom,tcsr-msm8953", "syscon"; reg = <0x193f044 0x4>; }; @@ -799,7 +799,7 @@ compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -859,7 +859,7 @@ compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7864900 0x500>, <0x7864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm64/qcom/msm8992-xiaomi-libra.dts b/dts/src/arm64/qcom/msm8992-xiaomi-libra.dts index cbe11c060d..c4e87d0aec 100644 --- a/dts/src/arm64/qcom/msm8992-xiaomi-libra.dts +++ b/dts/src/arm64/qcom/msm8992-xiaomi-libra.dts @@ -17,7 +17,7 @@ chassis-type = "handset"; /* required for bootloader to select correct board */ - qcom,msm-id = <251 0 252 0>; + qcom,msm-id = <251 0>, <252 0>; qcom,pmic-id = <65545 65546 0 0>; qcom,board-id = <12 0>; diff --git a/dts/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi b/dts/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi index 61ec905025..f9d8bd09e0 100644 --- a/dts/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/dts/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi @@ -499,7 +499,7 @@ linux,code = <KEY_POWER>; }; - volwnkey { + resin { compatible = "qcom,pm8941-resin"; interrupts = <0 8 1 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; diff --git a/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi b/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi index f430d79719..ff60b7004d 100644 --- a/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -471,7 +471,7 @@ &sdhc2 { status = "okay"; - cd-gpios = <&tlmm 100 0>; + cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; vmmc-supply = <&pm8994_l21>; vqmmc-supply = <&pm8994_l13>; }; diff --git a/dts/src/arm64/qcom/msm8994.dtsi b/dts/src/arm64/qcom/msm8994.dtsi index 8bc6c070e3..ded5b7ceea 100644 --- a/dts/src/arm64/qcom/msm8994.dtsi +++ b/dts/src/arm64/qcom/msm8994.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,gcc-msm8994.h> #include <dt-bindings/clock/qcom,mmcc-msm8994.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power/qcom-rpmpd.h> / { @@ -164,12 +165,6 @@ reg = <0 0x80000000 0 0>; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; - #hwlock-cells = <1>; - }; - pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; @@ -464,7 +459,7 @@ sdhc1: mmc@f9824900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -487,7 +482,7 @@ sdhc2: mmc@f98a4900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; @@ -502,7 +497,7 @@ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - cd-gpios = <&tlmm 100 0>; + cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "disabled"; }; @@ -762,9 +757,10 @@ #interrupt-cells = <4>; }; - tcsr_mutex_regs: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; + tcsr_mutex: hwlock@fd484000 { + compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex"; + reg = <0xfd484000 0x1000>; + #hwlock-cells = <1>; }; tlmm: pinctrl@fd510000 { diff --git a/dts/src/arm64/qcom/msm8996-sony-xperia-tone.dtsi b/dts/src/arm64/qcom/msm8996-sony-xperia-tone.dtsi index e165b5e890..ca7c8d2e1d 100644 --- a/dts/src/arm64/qcom/msm8996-sony-xperia-tone.dtsi +++ b/dts/src/arm64/qcom/msm8996-sony-xperia-tone.dtsi @@ -196,8 +196,8 @@ &pcie0 { status = "okay"; - perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&pm8994_l28>; }; diff --git a/dts/src/arm64/qcom/msm8996-xiaomi-common.dtsi b/dts/src/arm64/qcom/msm8996-xiaomi-common.dtsi index 6276499798..7781918608 100644 --- a/dts/src/arm64/qcom/msm8996-xiaomi-common.dtsi +++ b/dts/src/arm64/qcom/msm8996-xiaomi-common.dtsi @@ -58,6 +58,14 @@ }; }; + irled { + compatible = "pwm-ir-tx"; + pwms = <&pm8994_lpg 1 1000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&irled_default>; + }; + reserved-memory { memory@88800000 { reg = <0x0 0x88800000 0x0 0x1400000>; @@ -297,6 +305,41 @@ linux,code = <KEY_VOLUMEDOWN>; }; +&pm8994_lpg { + status = "okay"; + + qcom,power-source = <1>; +}; + +&pmi8994_lpg { + status = "okay"; + + qcom,power-source = <1>; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + &slpi_pil { status = "okay"; @@ -608,6 +651,15 @@ }; &pm8994_gpios { + irled_default: irled-default-state { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_FUNC1; + output-low; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + power-source = <PM8994_GPIO_S4>; + bias-disable; + }; + wlan_en_default: wlan-en-state { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; diff --git a/dts/src/arm64/qcom/msm8996-xiaomi-gemini.dts b/dts/src/arm64/qcom/msm8996-xiaomi-gemini.dts index 25f30ec277..4e5264f411 100644 --- a/dts/src/arm64/qcom/msm8996-xiaomi-gemini.dts +++ b/dts/src/arm64/qcom/msm8996-xiaomi-gemini.dts @@ -8,6 +8,7 @@ #include "msm8996-xiaomi-common.dtsi" #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> +#include <dt-bindings/sound/qcom,wcd9335.h> #include <dt-bindings/input/ti-drv260x.h> / { @@ -193,7 +194,7 @@ }; codec { - sound-dai = <&wcd9335 6>; + sound-dai = <&wcd9335 AIF4_PB>; }; }; @@ -208,7 +209,7 @@ }; codec { - sound-dai = <&wcd9335 1>; + sound-dai = <&wcd9335 AIF1_CAP>; }; }; }; diff --git a/dts/src/arm64/qcom/msm8996-xiaomi-scorpio.dts b/dts/src/arm64/qcom/msm8996-xiaomi-scorpio.dts index 30a9e4bed4..79be5fb129 100644 --- a/dts/src/arm64/qcom/msm8996-xiaomi-scorpio.dts +++ b/dts/src/arm64/qcom/msm8996-xiaomi-scorpio.dts @@ -9,6 +9,7 @@ #include "pmi8996.dtsi" #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> +#include <dt-bindings/sound/qcom,wcd9335.h> / { model = "Xiaomi Mi Note 2"; @@ -116,6 +117,25 @@ "qcom/msm8996/scorpio/modem.mbn"; }; +&pm8994_lpg { + pinctrl-names = "default"; + pinctrl-0 = <&keypad_default>; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; + function-enumerator = <1>; + }; + + led@6 { + reg = <6>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; + function-enumerator = <0>; + }; +}; + &q6asmdai { dai@0 { reg = <0>; @@ -171,7 +191,7 @@ }; codec { - sound-dai = <&wcd9335 6>; + sound-dai = <&wcd9335 AIF4_PB>; }; }; @@ -186,7 +206,7 @@ }; codec { - sound-dai = <&wcd9335 1>; + sound-dai = <&wcd9335 AIF1_CAP>; }; }; }; @@ -258,6 +278,15 @@ "PMIC_SLB", /* GPIO_20 */ "UIM_BATT_ALARM", /* GPIO_21 */ "NC"; /* GPIO_22 */ + + keypad_default: keypad-default-state { + pins = "gpio7", "gpio10"; + function = PMIC_GPIO_FUNC_FUNC1; + output-low; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <PM8994_GPIO_S4>; + bias-disable; + }; }; &pm8994_mpps { diff --git a/dts/src/arm64/qcom/msm8996.dtsi b/dts/src/arm64/qcom/msm8996.dtsi index 742eac4ce9..c0a2baffa4 100644 --- a/dts/src/arm64/qcom/msm8996.dtsi +++ b/dts/src/arm64/qcom/msm8996.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/qcom,mmcc-msm8996.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/interconnect/qcom,msm8996.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/thermal/thermal.h> @@ -359,16 +360,10 @@ firmware { scm { compatible = "qcom,scm-msm8996", "qcom,scm"; - qcom,dload-mode = <&tcsr 0x13000>; + qcom,dload-mode = <&tcsr_2 0x13000>; }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ @@ -838,12 +833,18 @@ <&rpmcc RPM_SMD_PCNOC_A_CLK>; }; - tcsr_mutex_regs: syscon@740000 { - compatible = "syscon"; - reg = <0x00740000 0x40000>; + tcsr_mutex: hwlock@740000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x00740000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_1: syscon@760000 { + compatible = "qcom,tcsr-msm8996", "syscon"; + reg = <0x00760000 0x20000>; }; - tcsr: syscon@7a0000 { + tcsr_2: syscon@7a0000 { compatible = "qcom,tcsr-msm8996", "syscon"; reg = <0x007a0000 0x18000>; }; @@ -1161,9 +1162,13 @@ "hdmi_phy"; clocks = <&mmcc MDSS_AHB_CLK>, - <&gcc GCC_HDMI_CLKREF_CLK>; + <&gcc GCC_HDMI_CLKREF_CLK>, + <&xo_board>; clock-names = "iface", - "ref"; + "ref", + "xo"; + + #clock-cells = <0>; status = "disabled"; }; @@ -2413,7 +2418,7 @@ qcom,smem-states = <&mpss_smp2p_out 0>; qcom,smem-state-names = "stop"; - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; status = "disabled"; @@ -3018,7 +3023,7 @@ sdhc1: mmc@7464900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07464900 0x11c>, <0x07464000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; @@ -3042,7 +3047,7 @@ sdhc2: mmc@74a4900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; @@ -3337,7 +3342,7 @@ interrupt-names = "intr1", "intr2"; interrupt-controller; #interrupt-cells = <1>; - reset-gpios = <&tlmm 64 0>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; slim-ifc-dev = <&tasha_ifd>; @@ -3499,7 +3504,7 @@ }; saw3: syscon@9a10000 { - compatible = "syscon"; + compatible = "qcom,tcsr-msm8996", "syscon"; reg = <0x09a10000 0x1000>; }; diff --git a/dts/src/arm64/qcom/msm8998.dtsi b/dts/src/arm64/qcom/msm8998.dtsi index 02d21bff21..f05f16ac5c 100644 --- a/dts/src/arm64/qcom/msm8998.dtsi +++ b/dts/src/arm64/qcom/msm8998.dtsi @@ -308,12 +308,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1047,9 +1041,15 @@ }; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x01f40000 0x40000>; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,msm8998-tcsr", "syscon"; + reg = <0x01f60000 0x20000>; }; tlmm: pinctrl@3400000 { @@ -1340,7 +1340,7 @@ resets = <&gcc GCC_MSS_RESTART>; reset-names = "mss_restart"; - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; power-domains = <&rpmpd MSM8998_VDDCX>, <&rpmpd MSM8998_VDDMX>; @@ -2076,9 +2076,9 @@ }; sdhc2: mmc@c0a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm64/qcom/pm6150l.dtsi b/dts/src/arm64/qcom/pm6150l.dtsi index 7aa2ef90cb..f02c223ef4 100644 --- a/dts/src/arm64/qcom/pm6150l.dtsi +++ b/dts/src/arm64/qcom/pm6150l.dtsi @@ -20,10 +20,29 @@ #size-cells = <0>; #io-channel-cells = <1>; + adc-chan@0 { + reg = <ADC5_REF_GND>; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + adc-chan@1 { + reg = <ADC5_1P25VREF>; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + adc-chan@6 { reg = <ADC5_DIE_TEMP>; + qcom,pre-scaling = <1 1>; label = "die_temp"; }; + + adc-chan@83 { + reg = <ADC5_VPH_PWR>; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; }; pm6150l_adc_tm: adc-tm@3500 { diff --git a/dts/src/arm64/qcom/pm660.dtsi b/dts/src/arm64/qcom/pm660.dtsi index d0eefbb516..e1622b16c0 100644 --- a/dts/src/arm64/qcom/pm660.dtsi +++ b/dts/src/arm64/qcom/pm660.dtsi @@ -187,7 +187,7 @@ #address-cells = <1>; #size-cells = <0>; - pm660_spmi_regulators: pm660-regulators { + pm660_spmi_regulators: regulators { compatible = "qcom,pm660-regulators"; }; }; diff --git a/dts/src/arm64/qcom/pm660l.dtsi b/dts/src/arm64/qcom/pm660l.dtsi index c7945470ff..8aa0a50787 100644 --- a/dts/src/arm64/qcom/pm660l.dtsi +++ b/dts/src/arm64/qcom/pm660l.dtsi @@ -65,7 +65,7 @@ #address-cells = <1>; #size-cells = <0>; - pm660l_lpg: lpg@b100 { + pm660l_lpg: pwm { compatible = "qcom,pm660l-lpg"; status = "disabled"; @@ -81,7 +81,7 @@ status = "disabled"; }; - pm660l_spmi_regulators: pm660l-regulators { + pm660l_spmi_regulators: regulators { compatible = "qcom,pm660l-regulators"; }; }; diff --git a/dts/src/arm64/qcom/pm7250b.dtsi b/dts/src/arm64/qcom/pm7250b.dtsi new file mode 100644 index 0000000000..61f7a63451 --- /dev/null +++ b/dts/src/arm64/qcom/pm7250b.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm7250b-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm7250b_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@2 { + compatible = "qcom,pm7250b", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7250b_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm7250b_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm7250b_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + adc-chan@0 { + reg = <ADC5_REF_GND>; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + adc-chan@1 { + reg = <ADC5_1P25VREF>; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + adc-chan@2 { + reg = <ADC5_DIE_TEMP>; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + + adc-chan@7 { + reg = <ADC5_USB_IN_I>; + qcom,pre-scaling = <1 1>; + label = "usb_in_i_uv"; + }; + + adc-chan@8 { + reg = <ADC5_USB_IN_V_16>; + qcom,pre-scaling = <1 16>; + label = "usb_in_v_div_16"; + }; + + adc-chan@9 { + reg = <ADC5_CHG_TEMP>; + qcom,pre-scaling = <1 1>; + label = "chg_temp"; + }; + + adc-chan@e { + reg = <ADC5_AMUX_THM2>; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "smb1390_therm"; + }; + + adc-chan@1e { + reg = <ADC5_MID_CHG_DIV6>; + qcom,pre-scaling = <1 6>; + label = "chg_mid"; + }; + + adc-chan@83 { + reg = <ADC5_VPH_PWR>; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + + adc-chan@84 { + reg = <ADC5_VBAT_SNS>; + qcom,pre-scaling = <1 3>; + label = "vbat_sns"; + }; + + adc-chan@99 { + reg = <ADC5_SBUx>; + qcom,pre-scaling = <1 3>; + label = "chg_sbux"; + }; + }; + + pm7250b_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + pmic@3 { + compatible = "qcom,pm7250b", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/dts/src/arm64/qcom/pm8150.dtsi b/dts/src/arm64/qcom/pm8150.dtsi index fd84342159..574fa95a28 100644 --- a/dts/src/arm64/qcom/pm8150.dtsi +++ b/dts/src/arm64/qcom/pm8150.dtsi @@ -47,7 +47,7 @@ #address-cells = <1>; #size-cells = <0>; - pon: power-on@800 { + pon: pon@800 { compatible = "qcom,pm8998-pon"; reg = <0x0800>; mode-bootloader = <0x2>; diff --git a/dts/src/arm64/qcom/pm8150b.dtsi b/dts/src/arm64/qcom/pm8150b.dtsi index 5d1ec3a6cc..cdded791d9 100644 --- a/dts/src/arm64/qcom/pm8150b.dtsi +++ b/dts/src/arm64/qcom/pm8150b.dtsi @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <0>; - power-on@800 { + pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; @@ -128,7 +128,7 @@ #address-cells = <1>; #size-cells = <0>; - pm8150b_lpg: lpg { + pm8150b_lpg: pwm { compatible = "qcom,pm8150b-lpg"; #address-cells = <1>; diff --git a/dts/src/arm64/qcom/pm8150l.dtsi b/dts/src/arm64/qcom/pm8150l.dtsi index c62d023b39..135bfb8d62 100644 --- a/dts/src/arm64/qcom/pm8150l.dtsi +++ b/dts/src/arm64/qcom/pm8150l.dtsi @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <0>; - power-on@800 { + pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; @@ -116,7 +116,7 @@ #address-cells = <1>; #size-cells = <0>; - pm8150l_lpg: lpg { + pm8150l_lpg: pwm { compatible = "qcom,pm8150l-lpg"; #address-cells = <1>; diff --git a/dts/src/arm64/qcom/pm8350c.dtsi b/dts/src/arm64/qcom/pm8350c.dtsi index e0bbb67717..f28e71487d 100644 --- a/dts/src/arm64/qcom/pm8350c.dtsi +++ b/dts/src/arm64/qcom/pm8350c.dtsi @@ -30,9 +30,8 @@ #interrupt-cells = <2>; }; - pm8350c_pwm: pwm@e800 { + pm8350c_pwm: pwm { compatible = "qcom,pm8350c-pwm"; - reg = <0xe800>; #pwm-cells = <2>; status = "disabled"; }; diff --git a/dts/src/arm64/qcom/pm8953.dtsi b/dts/src/arm64/qcom/pm8953.dtsi index 741c538a9c..a1d36f9ebb 100644 --- a/dts/src/arm64/qcom/pm8953.dtsi +++ b/dts/src/arm64/qcom/pm8953.dtsi @@ -45,7 +45,7 @@ #thermal-sensor-cells = <0>; }; - pm8953_vadc: vadc@3100 { + pm8953_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; interrupts = <0x00 0x31 0x00 0x01>; diff --git a/dts/src/arm64/qcom/pm8994.dtsi b/dts/src/arm64/qcom/pm8994.dtsi index ab342397fc..e92e5ac414 100644 --- a/dts/src/arm64/qcom/pm8994.dtsi +++ b/dts/src/arm64/qcom/pm8994.dtsi @@ -135,7 +135,7 @@ #address-cells = <1>; #size-cells = <0>; - pm8994_lpg: lpg { + pm8994_lpg: pwm { compatible = "qcom,pm8994-lpg"; #address-cells = <1>; diff --git a/dts/src/arm64/qcom/pmi8994.dtsi b/dts/src/arm64/qcom/pmi8994.dtsi index 84c44912ec..542c215dde 100644 --- a/dts/src/arm64/qcom/pmi8994.dtsi +++ b/dts/src/arm64/qcom/pmi8994.dtsi @@ -21,7 +21,7 @@ }; pmi8994_mpps: mpps@a000 { - compatible = "qcom,pmi8994-mpp"; + compatible = "qcom,pmi8994-mpp", "qcom,spmi-mpp"; reg = <0xa000>; gpio-controller; gpio-ranges = <&pmi8994_mpps 0 0 4>; @@ -37,7 +37,7 @@ #address-cells = <1>; #size-cells = <0>; - pmi8994_lpg: lpg { + pmi8994_lpg: pwm { compatible = "qcom,pmi8994-lpg"; #address-cells = <1>; diff --git a/dts/src/arm64/qcom/pmi8998.dtsi b/dts/src/arm64/qcom/pmi8998.dtsi index 6d3d212560..3852a012bb 100644 --- a/dts/src/arm64/qcom/pmi8998.dtsi +++ b/dts/src/arm64/qcom/pmi8998.dtsi @@ -42,7 +42,7 @@ }; }; - pmi8998_lpg: lpg { + pmi8998_lpg: pwm { compatible = "qcom,pmi8998-lpg"; #address-cells = <1>; diff --git a/dts/src/arm64/qcom/pmk8350.dtsi b/dts/src/arm64/qcom/pmk8350.dtsi index 0f94c46a14..a7ec9d1194 100644 --- a/dts/src/arm64/qcom/pmk8350.dtsi +++ b/dts/src/arm64/qcom/pmk8350.dtsi @@ -39,16 +39,13 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eoc-int-en-set"; #io-channel-cells = <1>; - io-channel-ranges; }; pmk8350_adc_tm: adc-tm@3400 { compatible = "qcom,adc-tm7"; reg = <0x3400>; interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "threshold"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; diff --git a/dts/src/arm64/qcom/pmm8155au_1.dtsi b/dts/src/arm64/qcom/pmm8155au_1.dtsi index 68e9122363..20c5d60c8c 100644 --- a/dts/src/arm64/qcom/pmm8155au_1.dtsi +++ b/dts/src/arm64/qcom/pmm8155au_1.dtsi @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <0>; - pon: power-on@800 { + pon: pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; pwrkey { diff --git a/dts/src/arm64/qcom/pmm8155au_2.dtsi b/dts/src/arm64/qcom/pmm8155au_2.dtsi index c307fc6625..1da4606e8e 100644 --- a/dts/src/arm64/qcom/pmm8155au_2.dtsi +++ b/dts/src/arm64/qcom/pmm8155au_2.dtsi @@ -45,7 +45,7 @@ #address-cells = <1>; #size-cells = <0>; - power-on@800 { + pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; diff --git a/dts/src/arm64/qcom/qcs404-evb.dtsi b/dts/src/arm64/qcom/qcs404-evb.dtsi index 1721ebe575..1678ef0f86 100644 --- a/dts/src/arm64/qcom/qcs404-evb.dtsi +++ b/dts/src/arm64/qcom/qcs404-evb.dtsi @@ -99,7 +99,7 @@ &pcie { status = "okay"; - perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&perst_state>; diff --git a/dts/src/arm64/qcom/qcs404.dtsi b/dts/src/arm64/qcom/qcs404.dtsi index 9ab9900615..80f2d05595 100644 --- a/dts/src/arm64/qcom/qcs404.dtsi +++ b/dts/src/arm64/qcom/qcs404.dtsi @@ -295,12 +295,6 @@ hwlocks = <&tcsr_mutex 3>; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - soc: soc@0 { #address-cells = <1>; #size-cells = <1>; @@ -726,13 +720,14 @@ assigned-clock-rates = <19200000>; }; - tcsr_mutex_regs: syscon@1905000 { - compatible = "syscon"; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; }; tcsr: syscon@1937000 { - compatible = "syscon"; + compatible = "qcom,qcs404-tcsr", "syscon"; reg = <0x01937000 0x25000>; }; @@ -1297,7 +1292,7 @@ }; pcie: pci@10000000 { - compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; + compatible = "qcom,pcie-qcs404"; reg = <0x10000000 0xf1d>, <0x10000f20 0xa8>, <0x07780000 0x2000>, diff --git a/dts/src/arm64/qcom/sa8155p-adp.dts b/dts/src/arm64/qcom/sa8155p-adp.dts index ba547ca9fc..87ab0e1ecd 100644 --- a/dts/src/arm64/qcom/sa8155p-adp.dts +++ b/dts/src/arm64/qcom/sa8155p-adp.dts @@ -333,9 +333,6 @@ snps,reset-active-low; snps,reset-delays-us = <0 11000 70000>; - snps,ptp-ref-clk-rate = <250000000>; - snps,ptp-req-clk-rate = <96000000>; - snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; diff --git a/dts/src/arm64/qcom/sa8295p-adp.dts b/dts/src/arm64/qcom/sa8295p-adp.dts index 9398f03499..b608b82dff 100644 --- a/dts/src/arm64/qcom/sa8295p-adp.dts +++ b/dts/src/arm64/qcom/sa8295p-adp.dts @@ -35,7 +35,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1208000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l5a: ldo5 { @@ -43,7 +42,6 @@ regulator-min-microvolt = <912000>; regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l7a: ldo7 { @@ -51,7 +49,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l13a: ldo13 { @@ -59,7 +56,6 @@ regulator-min-microvolt = <3072000>; regulator-max-microvolt = <3072000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; }; @@ -72,7 +68,6 @@ regulator-min-microvolt = <912000>; regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l2c: ldo2 { @@ -80,7 +75,6 @@ regulator-min-microvolt = <3072000>; regulator-max-microvolt = <3072000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l3c: ldo3 { @@ -96,7 +90,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1208000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l6c: ldo6 { @@ -112,7 +105,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l10c: ldo10 { @@ -141,7 +133,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l7g: ldo7 { @@ -149,7 +140,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l8g: ldo8 { @@ -157,7 +147,6 @@ regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; }; }; @@ -194,9 +183,10 @@ #size-cells = <0>; pm8450a_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio"; + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8450a_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -210,9 +200,10 @@ #size-cells = <0>; pm8450c_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio"; + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8450c_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -226,9 +217,10 @@ #size-cells = <0>; pm8450e_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio"; + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8450e_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -242,9 +234,10 @@ #size-cells = <0>; pm8450g_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio"; + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8450g_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts index 8290d03604..edfcd47e1a 100644 --- a/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts +++ b/dts/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts @@ -24,8 +24,6 @@ }; &pm6150_adc { - status = "disabled"; - /delete-node/ skin-temp-thermistor@4e; /delete-node/ charger-thermistor@4f; }; diff --git a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts index bfbf26fd2c..d49de65aa9 100644 --- a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts +++ b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts @@ -16,17 +16,6 @@ compatible = "google,lazor-rev0", "qcom,sc7180"; }; -&pp3300_hub { - /* pp3300_l7c is used to power the USB hub */ - /delete-property/regulator-always-on; - /delete-property/regulator-boot-on; -}; - -&pp3300_l7c { - regulator-always-on; - regulator-boot-on; -}; - &sn65dsi86_out { /* * Lane 0 was incorrectly mapped on the cable, but we've now decided @@ -35,3 +24,11 @@ */ lane-polarities = <1 0>; }; + +&usb_hub_2_x { + vdd-supply = <&pp3300_l7c>; +}; + +&usb_hub_3_x { + vdd-supply = <&pp3300_l7c>; +}; diff --git a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts index d45a59afd7..80c7108bc5 100644 --- a/dts/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts +++ b/dts/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts @@ -16,13 +16,11 @@ compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180"; }; -&pp3300_hub { - /* pp3300_l7c is used to power the USB hub */ - /delete-property/regulator-always-on; - /delete-property/regulator-boot-on; + +&usb_hub_2_x { + vdd-supply = <&pp3300_l7c>; }; -&pp3300_l7c { - regulator-always-on; - regulator-boot-on; +&usb_hub_3_x { + vdd-supply = <&pp3300_l7c>; }; diff --git a/dts/src/arm64/qcom/sc7180-trogdor-lazor.dtsi b/dts/src/arm64/qcom/sc7180-trogdor-lazor.dtsi index 2cf7d5212c..002663d752 100644 --- a/dts/src/arm64/qcom/sc7180-trogdor-lazor.dtsi +++ b/dts/src/arm64/qcom/sc7180-trogdor-lazor.dtsi @@ -55,8 +55,6 @@ ap_ts_pen_1v8: &i2c4 { }; &pm6150_adc { - status = "disabled"; - /delete-node/ charger-thermistor@4f; }; diff --git a/dts/src/arm64/qcom/sc7180-trogdor-pazquel-lte-parade.dts b/dts/src/arm64/qcom/sc7180-trogdor-pazquel-lte-parade.dts index 764c451c1a..767cb7450c 100644 --- a/dts/src/arm64/qcom/sc7180-trogdor-pazquel-lte-parade.dts +++ b/dts/src/arm64/qcom/sc7180-trogdor-pazquel-lte-parade.dts @@ -14,7 +14,7 @@ / { model = "Google Pazquel (Parade,LTE)"; - compatible = "google,pazquel-sku4", "qcom,sc7180"; + compatible = "google,pazquel-sku6", "google,pazquel-sku4", "qcom,sc7180"; }; &ap_sar_sensor_i2c { diff --git a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts index 76a130bad6..8467ff41e6 100644 --- a/dts/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts +++ b/dts/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts @@ -34,13 +34,10 @@ /delete-node/ charger-thermistor@0; }; -&pp3300_hub { - /* pp3300_l7c is used to power the USB hub */ - /delete-property/regulator-always-on; - /delete-property/regulator-boot-on; +&usb_hub_2_x { + vdd-supply = <&pp3300_l7c>; }; -&pp3300_l7c { - regulator-always-on; - regulator-boot-on; +&usb_hub_3_x { + vdd-supply = <&pp3300_l7c>; }; diff --git a/dts/src/arm64/qcom/sc7180-trogdor-r1.dts b/dts/src/arm64/qcom/sc7180-trogdor-r1.dts index 59a23d0e96..bc097d1b1b 100644 --- a/dts/src/arm64/qcom/sc7180-trogdor-r1.dts +++ b/dts/src/arm64/qcom/sc7180-trogdor-r1.dts @@ -44,17 +44,6 @@ ap_ts_pen_1v8: &i2c4 { compatible = "auo,b116xa01"; }; -&pp3300_hub { - /* pp3300_l7c is used to power the USB hub */ - /delete-property/regulator-always-on; - /delete-property/regulator-boot-on; -}; - -&pp3300_l7c { - regulator-always-on; - regulator-boot-on; -}; - &sdhc_2 { status = "okay"; }; @@ -63,6 +52,14 @@ ap_ts_pen_1v8: &i2c4 { interrupts = <58 IRQ_TYPE_EDGE_FALLING>; }; +&usb_hub_2_x { + vdd-supply = <&pp3300_l7c>; +}; + +&usb_hub_3_x { + vdd-supply = <&pp3300_l7c>; +}; + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ &trackpad_int_1v8_odl { diff --git a/dts/src/arm64/qcom/sc7180-trogdor.dtsi b/dts/src/arm64/qcom/sc7180-trogdor.dtsi index b5f534db13..eae22e6e97 100644 --- a/dts/src/arm64/qcom/sc7180-trogdor.dtsi +++ b/dts/src/arm64/qcom/sc7180-trogdor.dtsi @@ -299,7 +299,7 @@ pinctrl-names = "default"; pinctrl-0 = <&en_pp3300_hub>; - regulator-always-on; + /* The BIOS leaves this regulator on */ regulator-boot-on; vin-supply = <&pp3300_a>; @@ -936,6 +936,24 @@ ap_spi_fp: &spi10 { &usb_1_dwc3 { dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.x hub on port 1 */ + usb_hub_2_x: hub@1 { + compatible = "usbbda,5411"; + reg = <1>; + vdd-supply = <&pp3300_hub>; + peer-hub = <&usb_hub_3_x>; + }; + + /* 3.x hub on port 2 */ + usb_hub_3_x: hub@2 { + compatible = "usbbda,411"; + reg = <2>; + vdd-supply = <&pp3300_hub>; + peer-hub = <&usb_hub_2_x>; + }; }; &usb_1_hsphy { diff --git a/dts/src/arm64/qcom/sc7180.dtsi b/dts/src/arm64/qcom/sc7180.dtsi index b82c335c25..58976a1ba0 100644 --- a/dts/src/arm64/qcom/sc7180.dtsi +++ b/dts/src/arm64/qcom/sc7180.dtsi @@ -555,12 +555,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; @@ -1462,13 +1456,19 @@ status = "disabled"; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0 0x01f40000 0 0x40000>; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,sc7180-tcsr", "syscon"; + reg = <0 0x01f60000 0 0x20000>; }; - tcsr_regs: syscon@1fc0000 { - compatible = "syscon"; + tcsr_regs_2: syscon@1fc0000 { + compatible = "qcom,sc7180-tcsr", "syscon"; reg = <0 0x01fc0000 0 0x40000>; }; @@ -1932,8 +1932,8 @@ <&pdc_reset PDC_MODEM_SYNC_RESET>; reset-names = "mss_restart", "pdc_reset"; - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; - qcom,spare-regs = <&tcsr_regs 0xb3e4>; + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; status = "disabled"; diff --git a/dts/src/arm64/qcom/sc7280-chrome-common.dtsi b/dts/src/arm64/qcom/sc7280-chrome-common.dtsi index cfe2741456..25f31c81b2 100644 --- a/dts/src/arm64/qcom/sc7280-chrome-common.dtsi +++ b/dts/src/arm64/qcom/sc7280-chrome-common.dtsi @@ -83,17 +83,6 @@ }; }; -/* Modem setup is different on Chrome setups than typical Qualcomm setup */ -&remoteproc_mpss { - status = "okay"; - compatible = "qcom,sc7280-mss-pil"; - iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; - interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; - memory-region = <&mba_mem>, <&mpss_mem>; - firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn", - "qcom/sc7280-herobrine/modem/qdsp6sw.mbn"; -}; - &remoteproc_wpss { status = "okay"; firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; diff --git a/dts/src/arm64/qcom/sc7280-crd-r3.dts b/dts/src/arm64/qcom/sc7280-crd-r3.dts index 344338ad8a..dddb505e22 100644 --- a/dts/src/arm64/qcom/sc7280-crd-r3.dts +++ b/dts/src/arm64/qcom/sc7280-crd-r3.dts @@ -87,6 +87,36 @@ ap_ts_pen_1v8: &i2c13 { pins = "gpio51"; }; +&sound { + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "VA DMIC3", "MIC BIAS3", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; +}; + +&wcd9385 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>; + pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>; + us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + &tlmm { tp_int_odl: tp-int-odl { pins = "gpio7"; @@ -105,4 +135,11 @@ ap_ts_pen_1v8: &i2c13 { function = "gpio"; bias-disable; }; + + us_euro_hs_sel: us-euro-hs-sel { + pins = "gpio81"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + }; }; diff --git a/dts/src/arm64/qcom/sc7280-herobrine-audio-wcd9385.dtsi b/dts/src/arm64/qcom/sc7280-herobrine-audio-wcd9385.dtsi index 859faaa8b7..c72e53aaf9 100644 --- a/dts/src/arm64/qcom/sc7280-herobrine-audio-wcd9385.dtsi +++ b/dts/src/arm64/qcom/sc7280-herobrine-audio-wcd9385.dtsi @@ -5,6 +5,161 @@ * Copyright (c) 2022, The Linux Foundation. All rights reserved. */ +/ { + /* BOARD-SPECIFIC TOP LEVEL NODES */ + sound: sound { + compatible = "google,sc7280-herobrine"; + model = "sc7280-wcd938x-max98360a-1mic"; + + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "VA DMIC3", "MIC BIAS3", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + + dai-link@0 { + link-name = "MAX98360A"; + reg = <0>; + + cpu { + sound-dai = <&lpass_cpu MI2S_SECONDARY>; + }; + + codec { + sound-dai = <&max98360a>; + }; + }; + + dai-link@1 { + link-name = "DisplayPort"; + reg = <1>; + + cpu { + sound-dai = <&lpass_cpu LPASS_DP_RX>; + }; + + codec { + sound-dai = <&mdss_dp>; + }; + }; + + dai-link@2 { + link-name = "WCD9385 Playback"; + reg = <2>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>; + }; + + codec { + sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + }; + + dai-link@3 { + link-name = "WCD9385 Capture"; + reg = <3>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>; + }; + + codec { + sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + }; + + dai-link@4 { + link-name = "DMIC"; + reg = <4>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>; + }; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + }; + }; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&lpass_cpu { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; + + dai-link@1 { + reg = <MI2S_SECONDARY>; + qcom,playback-sd-lines = <0>; + }; + + dai-link@5 { + reg = <LPASS_DP_RX>; + }; + + dai-link@6 { + reg = <LPASS_CDC_DMA_RX0>; + }; + + dai-link@19 { + reg = <LPASS_CDC_DMA_TX3>; + }; + + dai-link@25 { + reg = <LPASS_CDC_DMA_VA_TX0>; + }; +}; + +&lpass_rx_macro { + status = "okay"; +}; + +&lpass_tx_macro { + status = "okay"; +}; + +&lpass_va_macro { + status = "okay"; +}; + +&swr0 { + status = "okay"; +}; + +&swr1 { + status = "okay"; +}; + +&wcd9385 { + status = "okay"; +}; + /* PINCTRL */ &lpass_dmic01_clk { diff --git a/dts/src/arm64/qcom/sc7280-herobrine-crd.dts b/dts/src/arm64/qcom/sc7280-herobrine-crd.dts index 7881bbc641..f0f26af1e4 100644 --- a/dts/src/arm64/qcom/sc7280-herobrine-crd.dts +++ b/dts/src/arm64/qcom/sc7280-herobrine-crd.dts @@ -9,10 +9,11 @@ #include "sc7280-herobrine.dtsi" #include "sc7280-herobrine-audio-wcd9385.dtsi" +#include "sc7280-herobrine-lte-sku.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; - compatible = "google,hoglin", "qcom,sc7280"; + compatible = "google,zoglin", "google,hoglin", "qcom,sc7280"; /* FIXED REGULATORS */ @@ -167,7 +168,7 @@ ap_ts_pen_1v8: &i2c13 { "PMIC_EDP_BL_PWM", ""; - edp_bl_reg_en: edp-bl-reg-en { + edp_bl_reg_en: edp-bl-reg-en-state { pins = "gpio6"; function = "normal"; bias-disable; @@ -371,7 +372,5 @@ ap_ts_pen_1v8: &i2c13 { "", /* 170 */ "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", - "", - "", ""; }; diff --git a/dts/src/arm64/qcom/sc7280-herobrine-evoker-r0.dts b/dts/src/arm64/qcom/sc7280-herobrine-evoker-r0.dts new file mode 100644 index 0000000000..ccbe50b624 --- /dev/null +++ b/dts/src/arm64/qcom/sc7280-herobrine-evoker-r0.dts @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Evoker board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine.dtsi" + +/ { + model = "Google Evoker"; + compatible = "google,evoker", "qcom,sc7280"; +}; + +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_codec { + status = "okay"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + hid-descr-addr = <0x20>; + vcc-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +ts_i2c: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth6915"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + + vcc33-supply = <&ts_avdd>; + }; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + +&ap_sar_sensor0 { + status = "okay"; +}; + +&ap_sar_sensor1 { + status = "okay"; +}; + +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_phy { + status = "okay"; +}; + +/* For nvme */ +&pcie1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status = "okay"; +}; + +&pwmleds { + status = "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status = "okay"; +}; + +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&ts_rst_conn { + bias-disable; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to herobrine board and is named it gets that name. + * - If a pin goes to herobrine board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names = "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "SSD_RST_L", + "PE_WAKE_ODL", + "AP_SAR_SDA", + "AP_SAR_SCL", + "PRB_SC_GPIO_6", + "TP_INT_ODL", + "HP_I2C_SDA", + "HP_I2C_SCL", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "SPI_AP_MOSI", + "SPI_AP_MISO", + "SPI_AP_CLK", + "SPI_AP_CS0_L", + /* + * AP_FLASH_WP is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_OD. + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_L", + "", + + "UF_CAM_RST_L", /* 20 */ + "WF_CAM_RST_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "PRB_SC_GPIO_32", + "HUB_RST_L", + "", + "", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + + "AP_EC_SPI_MISO", /* 40 */ + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "LCM_RST_L", + "EARLY_EUD_N", + "", + "DP_HOT_PLUG_DET", + "IO_BRD_MLB_ID0", + "IO_BRD_MLB_ID1", + + "IO_BRD_MLB_ID2", /* 50 */ + "SSD_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "PRB_SC_GPIO_58", + "PRB_SC_GPIO_59", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "FP_TO_AP_IRQ_L", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "WF_CAM_MCLK", + "PRB_SC_GPIO_67", + "FPMCU_BOOT0", + "UF_CAM_SDA", + + "UF_CAM_SCL", /* 70 */ + "", + "", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "EN_FP_RAILS", + "FP_RST_L", + "PCIE1_CLKREQ_ODL", + + "EN_PP3300_DX_EDP", /* 80 */ + "SC_GPIO_81", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CD_ODL", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "HP_MCLK", + "HP_BCLK", + "HP_DOUT", + "HP_DIN", + + "HP_LRCLK", /* 100 */ + "HP_IRQ", + "", + "", + "GSC_AP_INT_ODL", + "EN_PP3300_CODEC", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "PRB_SC_GPIO_112", + "UIM0_DATA", + "UIM0_CLK", + "UIM0_RST", + "UIM0_PRESENT_ODL", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "WF_CAM_EN", + + "FASTBOOT_SEL_0", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "PRB_SC_GPIO_129", + + "LCM_ID0", /* 130 */ + "LCM_ID1", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "PRB_SC_GPIO_139", + + "SAR1_IRQ_ODL", /* 140 */ + "SAR0_IRQ_ODL", + "PRB_SC_GPIO_142", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_ODL", + "HUB_EN", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +}; diff --git a/dts/src/arm64/qcom/sc7280-herobrine-herobrine-r1.dts b/dts/src/arm64/qcom/sc7280-herobrine-herobrine-r1.dts index c1647a85a3..c1a6719687 100644 --- a/dts/src/arm64/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/dts/src/arm64/qcom/sc7280-herobrine-herobrine-r1.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280-herobrine.dtsi" +#include "sc7280-herobrine-lte-sku.dtsi" / { model = "Google Herobrine (rev1+)"; diff --git a/dts/src/arm64/qcom/sc7280-herobrine-lte-sku.dtsi b/dts/src/arm64/qcom/sc7280-herobrine-lte-sku.dtsi new file mode 100644 index 0000000000..a92eeccd2b --- /dev/null +++ b/dts/src/arm64/qcom/sc7280-herobrine-lte-sku.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine dts fragment for LTE SKUs + * + * Copyright 2022 Google LLC. + */ +/* Modem setup is different on Chrome setups than typical Qualcomm setup */ + +&remoteproc_mpss { + compatible = "qcom,sc7280-mss-pil"; + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + memory-region = <&mba_mem>, <&mpss_mem>; + firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn", + "qcom/sc7280-herobrine/modem/qdsp6sw.mbn"; + status = "okay"; +}; diff --git a/dts/src/arm64/qcom/sc7280-herobrine-villager-r0.dts b/dts/src/arm64/qcom/sc7280-herobrine-villager-r0.dts index 2cacafd8fa..73e24cc55a 100644 --- a/dts/src/arm64/qcom/sc7280-herobrine-villager-r0.dts +++ b/dts/src/arm64/qcom/sc7280-herobrine-villager-r0.dts @@ -7,327 +7,10 @@ /dts-v1/; -#include "sc7280-herobrine.dtsi" +#include "sc7280-herobrine-villager.dtsi" +#include "sc7280-herobrine-lte-sku.dtsi" / { - model = "Google Villager (rev0+)"; - compatible = "google,villager", "qcom,sc7280"; -}; - -/* - * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES - * - * Sort order matches the order in the parent files (parents before children). - */ - -&pp3300_codec { - status = "okay"; -}; - -/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ - -ap_tp_i2c: &i2c0 { - status = "okay"; - clock-frequency = <400000>; - - trackpad: trackpad@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; - pinctrl-names = "default"; - pinctrl-0 = <&tp_int_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - - hid-descr-addr = <0x20>; - vcc-supply = <&pp3300_z1>; - - wakeup-source; - }; -}; - -ts_i2c: &i2c13 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@10 { - compatible = "elan,ekth6915"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; - - interrupt-parent = <&tlmm>; - interrupts = <55 IRQ_TYPE_LEVEL_LOW>; - - reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; - - vcc33-supply = <&ts_avdd>; - }; -}; - -&ap_sar_sensor_i2c { - status = "okay"; -}; - -&ap_sar_sensor0 { - status = "okay"; -}; - -&ap_sar_sensor1 { - status = "okay"; -}; - -&mdss_edp { - status = "okay"; -}; - -&mdss_edp_phy { - status = "okay"; -}; - -/* For nvme */ -&pcie1 { - status = "okay"; -}; - -/* For nvme */ -&pcie1_phy { - status = "okay"; -}; - -&pwmleds { - status = "okay"; -}; - -/* For eMMC */ -&sdhc_1 { - status = "okay"; -}; - -/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ - -&ts_rst_conn { - bias-disable; -}; - -/* PINCTRL - BOARD-SPECIFIC */ - -/* - * Methodology for gpio-line-names: - * - If a pin goes to herobrine board and is named it gets that name. - * - If a pin goes to herobrine board and is not named, it gets no name. - * - If a pin is totally internal to Qcard then it gets Qcard name. - * - If a pin is not hooked up on Qcard, it gets no name. - */ - -&pm8350c_gpios { - gpio-line-names = "FLASH_STROBE_1", /* 1 */ - "AP_SUSPEND", - "PM8008_1_RST_N", - "", - "", - "", - "PMIC_EDP_BL_EN", - "PMIC_EDP_BL_PWM", - ""; -}; - -&tlmm { - gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ - "AP_TP_I2C_SCL", - "SSD_RST_L", - "PE_WAKE_ODL", - "AP_SAR_SDA", - "AP_SAR_SCL", - "PRB_SC_GPIO_6", - "TP_INT_ODL", - "HP_I2C_SDA", - "HP_I2C_SCL", - - "GNSS_L1_EN", /* 10 */ - "GNSS_L5_EN", - "SPI_AP_MOSI", - "SPI_AP_MISO", - "SPI_AP_CLK", - "SPI_AP_CS0_L", - /* - * AP_FLASH_WP is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_OD. - */ - "AP_FLASH_WP", - "", - "AP_EC_INT_L", - "", - - "UF_CAM_RST_L", /* 20 */ - "WF_CAM_RST_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "", - "PM8008_IRQ_1", - "HOST2WLAN_SOL", - "WLAN2HOST_SOL", - "MOS_BT_UART_CTS", - "MOS_BT_UART_RFR", - - "MOS_BT_UART_TX", /* 30 */ - "MOS_BT_UART_RX", - "PRB_SC_GPIO_32", - "HUB_RST_L", - "", - "", - "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - - "AP_EC_SPI_MISO", /* 40 */ - "AP_EC_SPI_MOSI", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "LCM_RST_L", - "EARLY_EUD_N", - "", - "DP_HOT_PLUG_DET", - "IO_BRD_MLB_ID0", - "IO_BRD_MLB_ID1", - - "IO_BRD_MLB_ID2", /* 50 */ - "SSD_EN", - "TS_I2C_SDA_CONN", - "TS_I2C_CLK_CONN", - "TS_RST_CONN", - "TS_INT_CONN", - "AP_I2C_TPM_SDA", - "AP_I2C_TPM_SCL", - "PRB_SC_GPIO_58", - "PRB_SC_GPIO_59", - - "EDP_HOT_PLUG_DET_N", /* 60 */ - "FP_TO_AP_IRQ_L", - "", - "AMP_EN", - "CAM0_MCLK_GPIO_64", - "CAM1_MCLK_GPIO_65", - "WF_CAM_MCLK", - "PRB_SC_GPIO_67", - "FPMCU_BOOT0", - "UF_CAM_SDA", - - "UF_CAM_SCL", /* 70 */ - "", - "", - "WF_CAM_SDA", - "WF_CAM_SCL", - "", - "", - "EN_FP_RAILS", - "FP_RST_L", - "PCIE1_CLKREQ_ODL", - - "EN_PP3300_DX_EDP", /* 80 */ - "SC_GPIO_81", - "FORCED_USB_BOOT", - "WCD_RESET_N", - "MOS_WLAN_EN", - "MOS_BT_EN", - "MOS_SW_CTRL", - "MOS_PCIE0_RST", - "MOS_PCIE0_CLKREQ_N", - "MOS_PCIE0_WAKE_N", - - "MOS_LAA_AS_EN", /* 90 */ - "SD_CD_ODL", - "", - "", - "MOS_BT_WLAN_SLIMBUS_CLK", - "MOS_BT_WLAN_SLIMBUS_DAT0", - "HP_MCLK", - "HP_BCLK", - "HP_DOUT", - "HP_DIN", - - "HP_LRCLK", /* 100 */ - "HP_IRQ", - "", - "", - "GSC_AP_INT_ODL", - "EN_PP3300_CODEC", - "AMP_BCLK", - "AMP_DIN", - "AMP_LRCLK", - "UIM1_DATA_GPIO_109", - - "UIM1_CLK_GPIO_110", /* 110 */ - "UIM1_RESET_GPIO_111", - "PRB_SC_GPIO_112", - "UIM0_DATA", - "UIM0_CLK", - "UIM0_RST", - "UIM0_PRESENT_ODL", - "SDM_RFFE0_CLK", - "SDM_RFFE0_DATA", - "WF_CAM_EN", - - "FASTBOOT_SEL_0", /* 120 */ - "SC_GPIO_121", - "FASTBOOT_SEL_1", - "SC_GPIO_123", - "FASTBOOT_SEL_2", - "SM_RFFE4_CLK_GRFC_8", - "SM_RFFE4_DATA_GRFC_9", - "WLAN_COEX_UART1_RX", - "WLAN_COEX_UART1_TX", - "PRB_SC_GPIO_129", - - "LCM_ID0", /* 130 */ - "LCM_ID1", - "", - "SDR_QLINK_REQ", - "SDR_QLINK_EN", - "QLINK0_WMSS_RESET_N", - "SMR526_QLINK1_REQ", - "SMR526_QLINK1_EN", - "SMR526_QLINK1_WMSS_RESET_N", - "PRB_SC_GPIO_139", - - "SAR1_IRQ_ODL", /* 140 */ - "SAR0_IRQ_ODL", - "PRB_SC_GPIO_142", - "", - "WCD_SWR_TX_CLK", - "WCD_SWR_TX_DATA0", - "WCD_SWR_TX_DATA1", - "WCD_SWR_RX_CLK", - "WCD_SWR_RX_DATA0", - "WCD_SWR_RX_DATA1", - - "DMIC01_CLK", /* 150 */ - "DMIC01_DATA", - "DMIC23_CLK", - "DMIC23_DATA", - "", - "", - "EC_IN_RW_ODL", - "HUB_EN", - "WCD_SWR_TX_DATA2", - "", - - "", /* 160 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - - "", /* 170 */ - "MOS_BLE_UART_TX", - "MOS_BLE_UART_RX", - "", - "", - ""; + model = "Google Villager (rev0)"; + compatible = "google,villager-rev0", "qcom,sc7280"; }; diff --git a/dts/src/arm64/qcom/sc7280-herobrine-villager-r1-lte.dts b/dts/src/arm64/qcom/sc7280-herobrine-villager-r1-lte.dts new file mode 100644 index 0000000000..f1017809e5 --- /dev/null +++ b/dts/src/arm64/qcom/sc7280-herobrine-villager-r1-lte.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Villager board device tree source + * + * Copyright 2022 Google LLC. + */ + +#include "sc7280-herobrine-villager-r1.dts" +#include "sc7280-herobrine-lte-sku.dtsi" + +/ { + model = "Google Villager (rev1+) with LTE"; + compatible = "google,villager-sku512", "qcom,sc7280"; +}; diff --git a/dts/src/arm64/qcom/sc7280-herobrine-villager-r1.dts b/dts/src/arm64/qcom/sc7280-herobrine-villager-r1.dts new file mode 100644 index 0000000000..cfc6487269 --- /dev/null +++ b/dts/src/arm64/qcom/sc7280-herobrine-villager-r1.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Villager board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine-villager.dtsi" +#include "sc7280-herobrine-audio-wcd9385.dtsi" + +/ { + model = "Google Villager (rev1+)"; + compatible = "google,villager", "qcom,sc7280"; +}; + +&lpass_va_macro { + vdd-micb-supply = <&pp1800_l2c>; +}; + +&sound { + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; +}; diff --git a/dts/src/arm64/qcom/sc7280-herobrine-villager.dtsi b/dts/src/arm64/qcom/sc7280-herobrine-villager.dtsi new file mode 100644 index 0000000000..4566722bf4 --- /dev/null +++ b/dts/src/arm64/qcom/sc7280-herobrine-villager.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Villager board device tree source + * + * Copyright 2022 Google LLC. + */ + +#include "sc7280-herobrine.dtsi" + +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_codec { + status = "okay"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + hid-descr-addr = <0x20>; + vcc-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +ts_i2c: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth6915"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + + vcc33-supply = <&ts_avdd>; + }; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + +&ap_sar_sensor0 { + status = "okay"; +}; + +&ap_sar_sensor1 { + status = "okay"; +}; + +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_phy { + status = "okay"; +}; + +/* For nvme */ +&pcie1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status = "okay"; +}; + +&pwmleds { + status = "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status = "okay"; +}; + +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&ts_rst_conn { + bias-disable; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to herobrine board and is named it gets that name. + * - If a pin goes to herobrine board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names = "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "SSD_RST_L", + "PE_WAKE_ODL", + "AP_SAR_SDA", + "AP_SAR_SCL", + "PRB_SC_GPIO_6", + "TP_INT_ODL", + "HP_I2C_SDA", + "HP_I2C_SCL", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "SPI_AP_MOSI", + "SPI_AP_MISO", + "SPI_AP_CLK", + "SPI_AP_CS0_L", + /* + * AP_FLASH_WP is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_OD. + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_L", + "", + + "UF_CAM_RST_L", /* 20 */ + "WF_CAM_RST_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "PRB_SC_GPIO_32", + "HUB_RST_L", + "", + "", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + + "AP_EC_SPI_MISO", /* 40 */ + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "LCM_RST_L", + "EARLY_EUD_N", + "", + "DP_HOT_PLUG_DET", + "IO_BRD_MLB_ID0", + "IO_BRD_MLB_ID1", + + "IO_BRD_MLB_ID2", /* 50 */ + "SSD_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "PRB_SC_GPIO_58", + "PRB_SC_GPIO_59", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "FP_TO_AP_IRQ_L", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "WF_CAM_MCLK", + "PRB_SC_GPIO_67", + "FPMCU_BOOT0", + "UF_CAM_SDA", + + "UF_CAM_SCL", /* 70 */ + "", + "", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "EN_FP_RAILS", + "FP_RST_L", + "PCIE1_CLKREQ_ODL", + + "EN_PP3300_DX_EDP", /* 80 */ + "SC_GPIO_81", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CD_ODL", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "HP_MCLK", + "HP_BCLK", + "HP_DOUT", + "HP_DIN", + + "HP_LRCLK", /* 100 */ + "HP_IRQ", + "", + "", + "GSC_AP_INT_ODL", + "EN_PP3300_CODEC", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "PRB_SC_GPIO_112", + "UIM0_DATA", + "UIM0_CLK", + "UIM0_RST", + "UIM0_PRESENT_ODL", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "WF_CAM_EN", + + "FASTBOOT_SEL_0", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "PRB_SC_GPIO_129", + + "LCM_ID0", /* 130 */ + "LCM_ID1", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "PRB_SC_GPIO_139", + + "SAR1_IRQ_ODL", /* 140 */ + "SAR0_IRQ_ODL", + "PRB_SC_GPIO_142", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_ODL", + "HUB_EN", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +}; diff --git a/dts/src/arm64/qcom/sc7280-herobrine.dtsi b/dts/src/arm64/qcom/sc7280-herobrine.dtsi index 3f8996c00b..c11e37160f 100644 --- a/dts/src/arm64/qcom/sc7280-herobrine.dtsi +++ b/dts/src/arm64/qcom/sc7280-herobrine.dtsi @@ -144,8 +144,8 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + /* The BIOS leaves this regulator on */ regulator-boot-on; - regulator-always-on; gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>; enable-active-high; @@ -296,6 +296,14 @@ /* BOARD-SPECIFIC TOP LEVEL NODES */ + max98360a: audio-codec-0 { + compatible = "maxim,max98360a"; + pinctrl-names = "default"; + pinctrl-0 = <&_en>; + sdmode-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + pwmleds: pwmleds { compatible = "pwm-leds"; status = "disabled"; @@ -446,7 +454,7 @@ ap_i2c_tpm: &i2c14 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; - perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pp3300_ssd>; }; @@ -596,25 +604,32 @@ ap_ec_spi: &spi10 { &usb_1_dwc3 { dr_mode = "host"; -}; -&usb_1_hsphy { - status = "okay"; -}; + #address-cells = <1>; + #size-cells = <0>; -&usb_1_qmpphy { - status = "okay"; -}; + /* 2.x hub on port 1 */ + usb_hub_2_x: hub@1 { + compatible = "usbbda,5411"; + reg = <1>; + vdd-supply = <&pp3300_hub>; + peer-hub = <&usb_hub_3_x>; + }; -&usb_2 { - status = "okay"; + /* 3.x hub on port 2 */ + usb_hub_3_x: hub@2 { + compatible = "usbbda,411"; + reg = <2>; + vdd-supply = <&pp3300_hub>; + peer-hub = <&usb_hub_2_x>; + }; }; -&usb_2_dwc3 { - dr_mode = "host"; +&usb_1_hsphy { + status = "okay"; }; -&usb_2_hsphy { +&usb_1_qmpphy { status = "okay"; }; @@ -729,27 +744,27 @@ ap_ec_spi: &spi10 { pinctrl-names = "default"; pinctrl-0 = <&bios_flash_wp_od>; - amp_en: amp-en { + amp_en: amp-en-pins { pins = "gpio63"; function = "gpio"; bias-disable; drive-strength = <2>; }; - ap_ec_int_l: ap-ec-int-l { + ap_ec_int_l: ap-ec-int-l-pins { pins = "gpio18"; function = "gpio"; bias-pull-up; }; - bios_flash_wp_od: bios-flash-wp-od { + bios_flash_wp_od: bios-flash-wp-od-pins { pins = "gpio16"; function = "gpio"; /* Has external pull */ bias-disable; }; - en_fp_rails: en-fp-rails { + en_fp_rails: en-fp-rails-pins { pins = "gpio77"; function = "gpio"; bias-disable; @@ -757,60 +772,60 @@ ap_ec_spi: &spi10 { output-high; }; - en_pp3300_codec: en-pp3300-codec { + en_pp3300_codec: en-pp3300-codec-pins { pins = "gpio105"; function = "gpio"; bias-disable; drive-strength = <2>; }; - en_pp3300_dx_edp: en-pp3300-dx-edp { + en_pp3300_dx_edp: en-pp3300-dx-edp-pins { pins = "gpio80"; function = "gpio"; bias-disable; drive-strength = <2>; }; - fp_rst_l: fp-rst-l { + fp_rst_l: fp-rst-l-pins { pins = "gpio78"; function = "gpio"; bias-disable; drive-strength = <2>; }; - fp_to_ap_irq_l: fp-to-ap-irq-l { + fp_to_ap_irq_l: fp-to-ap-irq-l-pins { pins = "gpio61"; function = "gpio"; /* Has external pullup */ bias-disable; }; - fpmcu_boot0: fpmcu-boot0 { + fpmcu_boot0: fpmcu-boot0-pins { pins = "gpio68"; function = "gpio"; bias-disable; }; - gsc_ap_int_odl: gsc-ap-int-odl { + gsc_ap_int_odl: gsc-ap-int-odl-pins { pins = "gpio104"; function = "gpio"; bias-pull-up; }; - hp_irq: hp-irq { + hp_irq: hp-irq-pins { pins = "gpio101"; function = "gpio"; bias-pull-up; }; - hub_en: hub-en { + hub_en: hub-en-pins { pins = "gpio157"; function = "gpio"; bias-disable; drive-strength = <2>; }; - pe_wake_odl: pe-wake-odl { + pe_wake_odl: pe-wake-odl-pins { pins = "gpio3"; function = "gpio"; /* Has external pull */ @@ -819,45 +834,45 @@ ap_ec_spi: &spi10 { }; /* For ap_spi_fp */ - qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high { + qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-pins { pins = "gpio39"; function = "gpio"; output-high; }; /* For ap_ec_spi */ - qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins { pins = "gpio43"; function = "gpio"; output-high; }; - sar0_irq_odl: sar0-irq-odl { + sar0_irq_odl: sar0-irq-odl-pins { pins = "gpio141"; function = "gpio"; bias-pull-up; }; - sar1_irq_odl: sar1-irq-odl { + sar1_irq_odl: sar1-irq-odl-pins { pins = "gpio140"; function = "gpio"; bias-pull-up; }; - sd_cd_odl: sd-cd-odl { + sd_cd_odl: sd-cd-odl-pins { pins = "gpio91"; function = "gpio"; bias-pull-up; }; - ssd_en: ssd-en { + ssd_en: ssd-en-pins { pins = "gpio51"; function = "gpio"; bias-disable; drive-strength = <2>; }; - ssd_rst_l: ssd-rst-l { + ssd_rst_l: ssd-rst-l-pins { pins = "gpio2"; function = "gpio"; bias-disable; @@ -865,14 +880,14 @@ ap_ec_spi: &spi10 { output-low; }; - tp_int_odl: tp-int-odl { + tp_int_odl: tp-int-odl-pins { pins = "gpio7"; function = "gpio"; /* Has external pullup */ bias-disable; }; - wf_cam_en: wf-cam-en { + wf_cam_en: wf-cam-en-pins { pins = "gpio119"; function = "gpio"; /* Has external pulldown */ diff --git a/dts/src/arm64/qcom/sc7280-idp-ec-h1.dtsi b/dts/src/arm64/qcom/sc7280-idp-ec-h1.dtsi index a7c346aa3b..7f5143e9bb 100644 --- a/dts/src/arm64/qcom/sc7280-idp-ec-h1.dtsi +++ b/dts/src/arm64/qcom/sc7280-idp-ec-h1.dtsi @@ -79,26 +79,26 @@ ap_h1_spi: &spi14 { }; &tlmm { - ap_ec_int_l: ap-ec-int-l { + ap_ec_int_l: ap-ec-int-l-pins { pins = "gpio18"; function = "gpio"; input-enable; bias-pull-up; }; - h1_ap_int_odl: h1-ap-int-odl { + h1_ap_int_odl: h1-ap-int-odl-pins { pins = "gpio104"; function = "gpio"; input-enable; bias-pull-up; }; - qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins { pins = "gpio43"; output-high; }; - qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high { + qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-pins { pins = "gpio59"; output-high; }; diff --git a/dts/src/arm64/qcom/sc7280-idp.dts b/dts/src/arm64/qcom/sc7280-idp.dts index 6d3ff80582..7559164cdd 100644 --- a/dts/src/arm64/qcom/sc7280-idp.dts +++ b/dts/src/arm64/qcom/sc7280-idp.dts @@ -10,6 +10,7 @@ #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> #include "sc7280-idp.dtsi" #include "pmr735a.dtsi" +#include "sc7280-herobrine-lte-sku.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform"; @@ -78,7 +79,7 @@ }; &pmk8350_vadc { - pmr735a_die_temp { + pmr735a-die-temp@403 { reg = <PMR735A_ADC7_DIE_TEMP>; label = "pmr735a_die_temp"; qcom,pre-scaling = <1 1>; diff --git a/dts/src/arm64/qcom/sc7280-idp.dtsi b/dts/src/arm64/qcom/sc7280-idp.dtsi index a74e0b730d..cd432a2856 100644 --- a/dts/src/arm64/qcom/sc7280-idp.dtsi +++ b/dts/src/arm64/qcom/sc7280-idp.dtsi @@ -20,6 +20,42 @@ serial1 = &uart7; }; + max98360a: audio-codec-0 { + compatible = "maxim,max98360a"; + pinctrl-names = "default"; + pinctrl-0 = <&_en>; + sdmode-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + + wcd9385: audio-codec-1 { + compatible = "qcom,wcd9385-codec"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&wcd_reset_n>; + pinctrl-1 = <&wcd_reset_n_sleep>; + + reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; + + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + vdd-rxtx-supply = <&vreg_l18b_1p8>; + vdd-io-supply = <&vreg_l18b_1p8>; + vdd-buck-supply = <&vreg_l17b_1p8>; + vdd-mic-bias-supply = <&vreg_bob>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 + 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + #sound-dai-cells = <1>; + }; + gpio-keys { compatible = "gpio-keys"; label = "gpio-keys"; @@ -49,6 +85,104 @@ pinctrl-names = "default"; pinctrl-0 = <&nvme_pwren>; }; + + sound: sound { + compatible = "google,sc7280-herobrine"; + model = "sc7280-wcd938x-max98360a-1mic"; + + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + + dai-link@0 { + link-name = "MAX98360A"; + reg = <0>; + + cpu { + sound-dai = <&lpass_cpu MI2S_SECONDARY>; + }; + + codec { + sound-dai = <&max98360a>; + }; + }; + + dai-link@1 { + link-name = "DisplayPort"; + reg = <1>; + + cpu { + sound-dai = <&lpass_cpu LPASS_DP_RX>; + }; + + codec { + sound-dai = <&mdss_dp>; + }; + }; + + dai-link@2 { + link-name = "WCD9385 Playback"; + reg = <2>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>; + }; + + codec { + sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + }; + + dai-link@3 { + link-name = "WCD9385 Capture"; + reg = <3>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>; + }; + + codec { + sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + }; + + dai-link@4 { + link-name = "DMIC"; + reg = <4>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>; + }; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + }; + }; }; &apps_rsc { @@ -246,9 +380,50 @@ modem-init; }; +&lpass_cpu { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; + + dai-link@1 { + reg = <MI2S_SECONDARY>; + qcom,playback-sd-lines = <0>; + }; + + dai-link@5 { + reg = <LPASS_DP_RX>; + }; + + dai-link@6 { + reg = <LPASS_CDC_DMA_RX0>; + }; + + dai-link@19 { + reg = <LPASS_CDC_DMA_TX3>; + }; + + dai-link@25 { + reg = <LPASS_CDC_DMA_VA_TX0>; + }; +}; + +&lpass_rx_macro { + status = "okay"; +}; + +&lpass_tx_macro { + status = "okay"; +}; + +&lpass_va_macro { + status = "okay"; + vdd-micb-supply = <&vreg_bob>; +}; + &pcie1 { status = "okay"; - perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&nvme_3v3_regulator>; @@ -264,7 +439,7 @@ }; &pmk8350_vadc { - pmk8350_die_temp { + pmk8350-die-temp@3 { reg = <PMK8350_ADC7_DIE_TEMP>; label = "pmk8350_die_temp"; qcom,pre-scaling = <1 1>; @@ -306,6 +481,28 @@ cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; }; +&swr0 { + status = "okay"; + + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + #sound-dai-cells = <1>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr1 { + status = "okay"; + + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + #sound-dai-cells = <1>; + qcom,tx-port-mapping = <1 2 3 4>; + }; +}; + &uart5 { compatible = "qcom,geni-debug-uart"; status = "okay"; @@ -550,18 +747,24 @@ }; &tlmm { - bt_en: bt-en { + amp_en: amp-en { + pins = "gpio63"; + bias-pull-down; + drive-strength = <2>; + }; + + bt_en: bt-en-pins { pins = "gpio85"; function = "gpio"; output-low; bias-disable; }; - nvme_pwren: nvme-pwren { + nvme_pwren: nvme-pwren-pins { function = "gpio"; }; - pcie1_reset_n: pcie1-reset-n { + pcie1_reset_n: pcie1-reset-n-pins { pins = "gpio2"; function = "gpio"; @@ -570,7 +773,7 @@ bias-disable; }; - pcie1_wake_n: pcie1-wake-n { + pcie1_wake_n: pcie1-wake-n-pins { pins = "gpio3"; function = "gpio"; @@ -578,7 +781,7 @@ bias-pull-up; }; - qup_uart7_sleep_cts: qup-uart7-sleep-cts { + qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { pins = "gpio28"; function = "gpio"; /* @@ -591,7 +794,7 @@ bias-bus-hold; }; - qup_uart7_sleep_rts: qup-uart7-sleep-rts { + qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { pins = "gpio29"; function = "gpio"; /* @@ -603,7 +806,7 @@ bias-pull-down; }; - qup_uart7_sleep_tx: qup-uart7-sleep-tx { + qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { pins = "gpio30"; function = "gpio"; /* @@ -613,7 +816,7 @@ bias-pull-up; }; - qup_uart7_sleep_rx: qup-uart7-sleep-rx { + qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { pins = "gpio31"; function = "gpio"; /* @@ -624,15 +827,28 @@ bias-pull-up; }; - sd_cd: sd-cd { + sd_cd: sd-cd-pins { pins = "gpio91"; function = "gpio"; bias-pull-up; }; - sw_ctrl: sw-ctrl { + sw_ctrl: sw-ctrl-pins { pins = "gpio86"; function = "gpio"; bias-pull-down; }; + + wcd_reset_n: wcd-reset-n { + pins = "gpio83"; + function = "gpio"; + drive-strength = <8>; + }; + + wcd_reset_n_sleep: wcd-reset-n-sleep { + pins = "gpio83"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; }; diff --git a/dts/src/arm64/qcom/sc7280-qcard.dtsi b/dts/src/arm64/qcom/sc7280-qcard.dtsi index 7adf31bb98..4b8c676b0b 100644 --- a/dts/src/arm64/qcom/sc7280-qcard.dtsi +++ b/dts/src/arm64/qcom/sc7280-qcard.dtsi @@ -28,6 +28,38 @@ bluetooth0 = &bluetooth; serial0 = &uart5; serial1 = &uart7; + wifi0 = &wifi; + }; + + wcd9385: audio-codec-1 { + compatible = "qcom,wcd9385-codec"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>; + pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>; + + reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; + us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + vdd-rxtx-supply = <&vreg_l18b_1p8>; + vdd-io-supply = <&vreg_l18b_1p8>; + vdd-buck-supply = <&vreg_l17b_1p8>; + vdd-mic-bias-supply = <&vreg_bob>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 + 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + #sound-dai-cells = <1>; + + status = "disabled"; }; pm8350c_pwm_backlight: backlight { @@ -309,6 +341,10 @@ modem-init; }; +&lpass_va_macro { + vdd-micb-supply = <&vreg_bob>; +}; + /* NOTE: Not all Qcards have eDP connector stuffed */ &mdss_edp { aux-bus { @@ -378,6 +414,24 @@ no-sdio; }; +&swr0 { + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + #sound-dai-cells = <1>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr1 { + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + #sound-dai-cells = <1>; + qcom,tx-port-mapping = <1 2 3 4>; + }; +}; + uart_dbg: &uart5 { compatible = "qcom,geni-debug-uart"; status = "okay"; @@ -541,7 +595,7 @@ mos_bt_uart: &uart7 { }; &tlmm { - mos_bt_en: mos-bt-en { + mos_bt_en: mos-bt-en-pins { pins = "gpio85"; function = "gpio"; drive-strength = <2>; @@ -549,7 +603,7 @@ mos_bt_uart: &uart7 { }; /* For mos_bt_uart */ - qup_uart7_sleep_cts: qup-uart7-sleep-cts { + qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { pins = "gpio28"; function = "gpio"; /* @@ -563,7 +617,7 @@ mos_bt_uart: &uart7 { }; /* For mos_bt_uart */ - qup_uart7_sleep_rts: qup-uart7-sleep-rts { + qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { pins = "gpio29"; function = "gpio"; /* @@ -576,7 +630,7 @@ mos_bt_uart: &uart7 { }; /* For mos_bt_uart */ - qup_uart7_sleep_rx: qup-uart7-sleep-rx { + qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { pins = "gpio31"; function = "gpio"; /* @@ -588,7 +642,7 @@ mos_bt_uart: &uart7 { }; /* For mos_bt_uart */ - qup_uart7_sleep_tx: qup-uart7-sleep-tx { + qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { pins = "gpio30"; function = "gpio"; /* @@ -598,15 +652,35 @@ mos_bt_uart: &uart7 { bias-pull-up; }; - ts_int_conn: ts-int-conn { + ts_int_conn: ts-int-conn-pins { pins = "gpio55"; function = "gpio"; bias-pull-up; }; - ts_rst_conn: ts-rst-conn { + ts_rst_conn: ts-rst-conn-pins { pins = "gpio54"; function = "gpio"; drive-strength = <2>; }; + + us_euro_hs_sel: us-euro-hs-sel { + pins = "gpio81"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + }; + + wcd_reset_n: wcd-reset-n { + pins = "gpio83"; + function = "gpio"; + drive-strength = <8>; + }; + + wcd_reset_n_sleep: wcd-reset-n-sleep { + pins = "gpio83"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; }; diff --git a/dts/src/arm64/qcom/sc7280.dtsi b/dts/src/arm64/qcom/sc7280.dtsi index dac3b69e31..212580316d 100644 --- a/dts/src/arm64/qcom/sc7280.dtsi +++ b/dts/src/arm64/qcom/sc7280.dtsi @@ -22,6 +22,7 @@ #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/reset/qcom,sdm845-pdc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/sound/qcom,lpass.h> #include <dt-bindings/thermal/thermal.h> / { @@ -828,6 +829,7 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SC7280_CX>; }; ipcc: mailbox@408000 { @@ -2043,7 +2045,9 @@ <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_CLK>; + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; clock-names = "pipe", "pipe_mux", @@ -2055,7 +2059,9 @@ "bus_slave", "slave_q2a", "tbu", - "ddrss_sf_tbu"; + "ddrss_sf_tbu", + "aggre0", + "aggre1"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; @@ -2155,12 +2161,17 @@ }; tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex", "syscon"; - reg = <0 0x01f40000 0 0x40000>; + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; #hwlock-cells = <1>; }; - tcsr: syscon@1fc0000 { + tcsr_1: syscon@1f60000 { + compatible = "qcom,sc7280-tcsr", "syscon"; + reg = <0 0x01f60000 0 0x20000>; + }; + + tcsr_2: syscon@1fc0000 { compatible = "qcom,sc7280-tcsr", "syscon"; reg = <0 0x01fc0000 0 0x30000>; }; @@ -2168,14 +2179,121 @@ lpasscc: lpasscc@3000000 { compatible = "qcom,sc7280-lpasscc"; reg = <0 0x03000000 0 0x40>, - <0 0x03c04000 0 0x4>, - <0 0x03389000 0 0x24>; - reg-names = "qdsp6ss", "top_cc", "cc"; + <0 0x03c04000 0 0x4>; + reg-names = "qdsp6ss", "top_cc"; clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "iface"; #clock-cells = <1>; }; + lpass_rx_macro: codec@3200000 { + compatible = "qcom,sc7280-lpass-rx-macro"; + reg = <0 0x03200000 0 0x1000>; + + pinctrl-names = "default"; + pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&lpass_va_macro>; + clock-names = "mclk", "npl", "fsgen"; + + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names = "macro", "dcodec"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + swr0: soundwire@3210000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03210000 0 0x2000>; + + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&lpass_rx_macro>; + clock-names = "iface"; + + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + + status = "disabled"; + }; + + lpass_tx_macro: codec@3220000 { + compatible = "qcom,sc7280-lpass-tx-macro"; + reg = <0 0x03220000 0 0x1000>; + + pinctrl-names = "default"; + pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&lpass_va_macro>; + clock-names = "mclk", "npl", "fsgen"; + + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names = "macro", "dcodec"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + swr1: soundwire@3230000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03230000 0 0x2000>; + + interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&lpass_tx_macro>; + clock-names = "iface"; + + qcom,din-ports = <3>; + qcom,dout-ports = <0>; + + resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; + qcom,port-offset = <1>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + + status = "disabled"; + }; + lpass_audiocc: clock-controller@3300000 { compatible = "qcom,sc7280-lpassaudiocc"; reg = <0 0x03300000 0 0x30000>; @@ -2185,6 +2303,27 @@ power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; #clock-cells = <1>; #power-domain-cells = <1>; + #reset-cells = <1>; + }; + + lpass_va_macro: codec@3370000 { + compatible = "qcom,sc7280-lpass-va-macro"; + reg = <0 0x03370000 0 0x1000>; + + pinctrl-names = "default"; + pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; + clock-names = "mclk"; + + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names = "macro", "dcodec"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; }; lpass_aon: clock-controller@3380000 { @@ -2192,13 +2331,13 @@ reg = <0 0x03380000 0 0x30000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, - <&lpasscore LPASS_CORE_CC_CORE_CLK>; + <&lpass_core LPASS_CORE_CC_CORE_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; #clock-cells = <1>; #power-domain-cells = <1>; }; - lpasscore: clock-controller@3900000 { + lpass_core: clock-controller@3900000 { compatible = "qcom,sc7280-lpasscorecc"; reg = <0 0x03900000 0 0x50000>; clocks = <&rpmhcc RPMH_CXO_CLK>; @@ -2208,6 +2347,67 @@ #power-domain-cells = <1>; }; + lpass_cpu: audio@3987000 { + compatible = "qcom,sc7280-lpass-cpu"; + + reg = <0 0x03987000 0 0x68000>, + <0 0x03b00000 0 0x29000>, + <0 0x03260000 0 0xc000>, + <0 0x03280000 0 0x29000>, + <0 0x03340000 0 0x29000>, + <0 0x0336c000 0 0x3000>; + reg-names = "lpass-hdmiif", + "lpass-lpaif", + "lpass-rxtx-cdc-dma-lpm", + "lpass-rxtx-lpaif", + "lpass-va-lpaif", + "lpass-va-cdc-dma-lpm"; + + iommus = <&apps_smmu 0x1820 0>, + <&apps_smmu 0x1821 0>, + <&apps_smmu 0x1832 0>; + + power-domains = <&rpmhpd SC7280_LCX>; + power-domain-names = "lcx"; + required-opps = <&rpmhpd_opp_nom>; + + clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, + <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, + <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, + <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, + <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, + <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; + clock-names = "aon_cc_audio_hm_h", + "audio_cc_ext_mclk0", + "core_cc_sysnoc_mport_core", + "core_cc_ext_if0_ibit", + "core_cc_ext_if1_ibit", + "audio_cc_codec_mem", + "audio_cc_codec_mem0", + "audio_cc_codec_mem1", + "audio_cc_codec_mem2", + "aon_cc_va_mem0"; + + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpass-irq-lpaif", + "lpass-irq-hdmi", + "lpass-irq-vaif", + "lpass-irq-rxtxif"; + + status = "disabled"; + }; + lpass_hm: clock-controller@3c00000 { compatible = "qcom,sc7280-lpasshm"; reg = <0 0x3c00000 0 0x28>; @@ -2352,11 +2552,19 @@ opp-supported-hw = <0x03>; }; - opp-550000000 { + /* Only applicable for SKUs which has 550Mhz as Fmax */ + opp-550000000-0 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <8368000>; + opp-supported-hw = <0x01>; + }; + + opp-550000000-1 { opp-hz = /bits/ 64 <550000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; opp-peak-kBps = <6832000>; - opp-supported-hw = <0x03>; + opp-supported-hw = <0x02>; }; opp-608000000 { @@ -2522,9 +2730,9 @@ <&pdc_reset PDC_MODEM_SYNC_RESET>; reset-names = "mss_restart", "pdc_reset"; - qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; - qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; - qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; + qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; + qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; + qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; status = "disabled"; @@ -3181,6 +3389,7 @@ "dm_hs_phy_irq"; power-domains = <&gcc GCC_USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_SEC_BCR>; @@ -3259,7 +3468,7 @@ <&pdc_reset PDC_WPSS_SYNC_RESET>; reset-names = "restart", "pdc_sync"; - qcom,halt-regs = <&tcsr_mutex 0x37000>; + qcom,halt-regs = <&tcsr_1 0x17000>; status = "disabled"; @@ -3275,6 +3484,82 @@ }; }; + pmu@9091000 { + compatible = "qcom,sc7280-llcc-bwmon"; + reg = <0 0x9091000 0 0x1000>; + + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <800000>; + }; + opp-1 { + opp-peak-kBps = <1804000>; + }; + opp-2 { + opp-peak-kBps = <2188000>; + }; + opp-3 { + opp-peak-kBps = <3072000>; + }; + opp-4 { + opp-peak-kBps = <4068000>; + }; + opp-5 { + opp-peak-kBps = <6220000>; + }; + opp-6 { + opp-peak-kBps = <6832000>; + }; + opp-7 { + opp-peak-kBps = <8532000>; + }; + }; + }; + + pmu@90b6400 { + compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; + reg = <0 0x090b6400 0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2400000>; + }; + opp-1 { + opp-peak-kBps = <4800000>; + }; + opp-2 { + opp-peak-kBps = <7456000>; + }; + opp-3 { + opp-peak-kBps = <9600000>; + }; + opp-4 { + opp-peak-kBps = <12896000>; + }; + opp-5 { + opp-peak-kBps = <14928000>; + }; + opp-6 { + opp-peak-kBps = <17056000>; + }; + }; + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc"; @@ -3367,6 +3652,7 @@ "ss_phy_irq"; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; @@ -3972,791 +4258,791 @@ gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; - dp_hot_plug_det: dp-hot-plug-det { + dp_hot_plug_det: dp-hot-plug-det-pins { pins = "gpio47"; function = "dp_hot"; }; - edp_hot_plug_det: edp-hot-plug-det { + edp_hot_plug_det: edp-hot-plug-det-pins { pins = "gpio60"; function = "edp_hot"; }; - mi2s0_data0: mi2s0-data0 { + mi2s0_data0: mi2s0-data0-pins { pins = "gpio98"; function = "mi2s0_data0"; }; - mi2s0_data1: mi2s0-data1 { + mi2s0_data1: mi2s0-data1-pins { pins = "gpio99"; function = "mi2s0_data1"; }; - mi2s0_mclk: mi2s0-mclk { + mi2s0_mclk: mi2s0-mclk-pins { pins = "gpio96"; function = "pri_mi2s"; }; - mi2s0_sclk: mi2s0-sclk { + mi2s0_sclk: mi2s0-sclk-pins { pins = "gpio97"; function = "mi2s0_sck"; }; - mi2s0_ws: mi2s0-ws { + mi2s0_ws: mi2s0-ws-pins { pins = "gpio100"; function = "mi2s0_ws"; }; - mi2s1_data0: mi2s1-data0 { + mi2s1_data0: mi2s1-data0-pins { pins = "gpio107"; function = "mi2s1_data0"; }; - mi2s1_sclk: mi2s1-sclk { + mi2s1_sclk: mi2s1-sclk-pins { pins = "gpio106"; function = "mi2s1_sck"; }; - mi2s1_ws: mi2s1-ws { + mi2s1_ws: mi2s1-ws-pins { pins = "gpio108"; function = "mi2s1_ws"; }; - pcie1_clkreq_n: pcie1-clkreq-n { + pcie1_clkreq_n: pcie1-clkreq-n-pins { pins = "gpio79"; function = "pcie1_clkreqn"; }; - qspi_clk: qspi-clk { + qspi_clk: qspi-clk-pins { pins = "gpio14"; function = "qspi_clk"; }; - qspi_cs0: qspi-cs0 { + qspi_cs0: qspi-cs0-pins { pins = "gpio15"; function = "qspi_cs"; }; - qspi_cs1: qspi-cs1 { + qspi_cs1: qspi-cs1-pins { pins = "gpio19"; function = "qspi_cs"; }; - qspi_data01: qspi-data01 { + qspi_data01: qspi-data01-pins { pins = "gpio12", "gpio13"; function = "qspi_data"; }; - qspi_data12: qspi-data12 { + qspi_data12: qspi-data12-pins { pins = "gpio16", "gpio17"; function = "qspi_data"; }; - qup_i2c0_data_clk: qup-i2c0-data-clk { + qup_i2c0_data_clk: qup-i2c0-data-clk-pins { pins = "gpio0", "gpio1"; function = "qup00"; }; - qup_i2c1_data_clk: qup-i2c1-data-clk { + qup_i2c1_data_clk: qup-i2c1-data-clk-pins { pins = "gpio4", "gpio5"; function = "qup01"; }; - qup_i2c2_data_clk: qup-i2c2-data-clk { + qup_i2c2_data_clk: qup-i2c2-data-clk-pins { pins = "gpio8", "gpio9"; function = "qup02"; }; - qup_i2c3_data_clk: qup-i2c3-data-clk { + qup_i2c3_data_clk: qup-i2c3-data-clk-pins { pins = "gpio12", "gpio13"; function = "qup03"; }; - qup_i2c4_data_clk: qup-i2c4-data-clk { + qup_i2c4_data_clk: qup-i2c4-data-clk-pins { pins = "gpio16", "gpio17"; function = "qup04"; }; - qup_i2c5_data_clk: qup-i2c5-data-clk { + qup_i2c5_data_clk: qup-i2c5-data-clk-pins { pins = "gpio20", "gpio21"; function = "qup05"; }; - qup_i2c6_data_clk: qup-i2c6-data-clk { + qup_i2c6_data_clk: qup-i2c6-data-clk-pins { pins = "gpio24", "gpio25"; function = "qup06"; }; - qup_i2c7_data_clk: qup-i2c7-data-clk { + qup_i2c7_data_clk: qup-i2c7-data-clk-pins { pins = "gpio28", "gpio29"; function = "qup07"; }; - qup_i2c8_data_clk: qup-i2c8-data-clk { + qup_i2c8_data_clk: qup-i2c8-data-clk-pins { pins = "gpio32", "gpio33"; function = "qup10"; }; - qup_i2c9_data_clk: qup-i2c9-data-clk { + qup_i2c9_data_clk: qup-i2c9-data-clk-pins { pins = "gpio36", "gpio37"; function = "qup11"; }; - qup_i2c10_data_clk: qup-i2c10-data-clk { + qup_i2c10_data_clk: qup-i2c10-data-clk-pins { pins = "gpio40", "gpio41"; function = "qup12"; }; - qup_i2c11_data_clk: qup-i2c11-data-clk { + qup_i2c11_data_clk: qup-i2c11-data-clk-pins { pins = "gpio44", "gpio45"; function = "qup13"; }; - qup_i2c12_data_clk: qup-i2c12-data-clk { + qup_i2c12_data_clk: qup-i2c12-data-clk-pins { pins = "gpio48", "gpio49"; function = "qup14"; }; - qup_i2c13_data_clk: qup-i2c13-data-clk { + qup_i2c13_data_clk: qup-i2c13-data-clk-pins { pins = "gpio52", "gpio53"; function = "qup15"; }; - qup_i2c14_data_clk: qup-i2c14-data-clk { + qup_i2c14_data_clk: qup-i2c14-data-clk-pins { pins = "gpio56", "gpio57"; function = "qup16"; }; - qup_i2c15_data_clk: qup-i2c15-data-clk { + qup_i2c15_data_clk: qup-i2c15-data-clk-pins { pins = "gpio60", "gpio61"; function = "qup17"; }; - qup_spi0_data_clk: qup-spi0-data-clk { + qup_spi0_data_clk: qup-spi0-data-clk-pins { pins = "gpio0", "gpio1", "gpio2"; function = "qup00"; }; - qup_spi0_cs: qup-spi0-cs { + qup_spi0_cs: qup-spi0-cs-pins { pins = "gpio3"; function = "qup00"; }; - qup_spi0_cs_gpio: qup-spi0-cs-gpio { + qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins { pins = "gpio3"; function = "gpio"; }; - qup_spi1_data_clk: qup-spi1-data-clk { + qup_spi1_data_clk: qup-spi1-data-clk-pins { pins = "gpio4", "gpio5", "gpio6"; function = "qup01"; }; - qup_spi1_cs: qup-spi1-cs { + qup_spi1_cs: qup-spi1-cs-pins { pins = "gpio7"; function = "qup01"; }; - qup_spi1_cs_gpio: qup-spi1-cs-gpio { + qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins { pins = "gpio7"; function = "gpio"; }; - qup_spi2_data_clk: qup-spi2-data-clk { + qup_spi2_data_clk: qup-spi2-data-clk-pins { pins = "gpio8", "gpio9", "gpio10"; function = "qup02"; }; - qup_spi2_cs: qup-spi2-cs { + qup_spi2_cs: qup-spi2-cs-pins { pins = "gpio11"; function = "qup02"; }; - qup_spi2_cs_gpio: qup-spi2-cs-gpio { + qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins { pins = "gpio11"; function = "gpio"; }; - qup_spi3_data_clk: qup-spi3-data-clk { + qup_spi3_data_clk: qup-spi3-data-clk-pins { pins = "gpio12", "gpio13", "gpio14"; function = "qup03"; }; - qup_spi3_cs: qup-spi3-cs { + qup_spi3_cs: qup-spi3-cs-pins { pins = "gpio15"; function = "qup03"; }; - qup_spi3_cs_gpio: qup-spi3-cs-gpio { + qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins { pins = "gpio15"; function = "gpio"; }; - qup_spi4_data_clk: qup-spi4-data-clk { + qup_spi4_data_clk: qup-spi4-data-clk-pins { pins = "gpio16", "gpio17", "gpio18"; function = "qup04"; }; - qup_spi4_cs: qup-spi4-cs { + qup_spi4_cs: qup-spi4-cs-pins { pins = "gpio19"; function = "qup04"; }; - qup_spi4_cs_gpio: qup-spi4-cs-gpio { + qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins { pins = "gpio19"; function = "gpio"; }; - qup_spi5_data_clk: qup-spi5-data-clk { + qup_spi5_data_clk: qup-spi5-data-clk-pins { pins = "gpio20", "gpio21", "gpio22"; function = "qup05"; }; - qup_spi5_cs: qup-spi5-cs { + qup_spi5_cs: qup-spi5-cs-pins { pins = "gpio23"; function = "qup05"; }; - qup_spi5_cs_gpio: qup-spi5-cs-gpio { + qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins { pins = "gpio23"; function = "gpio"; }; - qup_spi6_data_clk: qup-spi6-data-clk { + qup_spi6_data_clk: qup-spi6-data-clk-pins { pins = "gpio24", "gpio25", "gpio26"; function = "qup06"; }; - qup_spi6_cs: qup-spi6-cs { + qup_spi6_cs: qup-spi6-cs-pins { pins = "gpio27"; function = "qup06"; }; - qup_spi6_cs_gpio: qup-spi6-cs-gpio { + qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins { pins = "gpio27"; function = "gpio"; }; - qup_spi7_data_clk: qup-spi7-data-clk { + qup_spi7_data_clk: qup-spi7-data-clk-pins { pins = "gpio28", "gpio29", "gpio30"; function = "qup07"; }; - qup_spi7_cs: qup-spi7-cs { + qup_spi7_cs: qup-spi7-cs-pins { pins = "gpio31"; function = "qup07"; }; - qup_spi7_cs_gpio: qup-spi7-cs-gpio { + qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins { pins = "gpio31"; function = "gpio"; }; - qup_spi8_data_clk: qup-spi8-data-clk { + qup_spi8_data_clk: qup-spi8-data-clk-pins { pins = "gpio32", "gpio33", "gpio34"; function = "qup10"; }; - qup_spi8_cs: qup-spi8-cs { + qup_spi8_cs: qup-spi8-cs-pins { pins = "gpio35"; function = "qup10"; }; - qup_spi8_cs_gpio: qup-spi8-cs-gpio { + qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins { pins = "gpio35"; function = "gpio"; }; - qup_spi9_data_clk: qup-spi9-data-clk { + qup_spi9_data_clk: qup-spi9-data-clk-pins { pins = "gpio36", "gpio37", "gpio38"; function = "qup11"; }; - qup_spi9_cs: qup-spi9-cs { + qup_spi9_cs: qup-spi9-cs-pins { pins = "gpio39"; function = "qup11"; }; - qup_spi9_cs_gpio: qup-spi9-cs-gpio { + qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins { pins = "gpio39"; function = "gpio"; }; - qup_spi10_data_clk: qup-spi10-data-clk { + qup_spi10_data_clk: qup-spi10-data-clk-pins { pins = "gpio40", "gpio41", "gpio42"; function = "qup12"; }; - qup_spi10_cs: qup-spi10-cs { + qup_spi10_cs: qup-spi10-cs-pins { pins = "gpio43"; function = "qup12"; }; - qup_spi10_cs_gpio: qup-spi10-cs-gpio { + qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins { pins = "gpio43"; function = "gpio"; }; - qup_spi11_data_clk: qup-spi11-data-clk { + qup_spi11_data_clk: qup-spi11-data-clk-pins { pins = "gpio44", "gpio45", "gpio46"; function = "qup13"; }; - qup_spi11_cs: qup-spi11-cs { + qup_spi11_cs: qup-spi11-cs-pins { pins = "gpio47"; function = "qup13"; }; - qup_spi11_cs_gpio: qup-spi11-cs-gpio { + qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins { pins = "gpio47"; function = "gpio"; }; - qup_spi12_data_clk: qup-spi12-data-clk { + qup_spi12_data_clk: qup-spi12-data-clk-pins { pins = "gpio48", "gpio49", "gpio50"; function = "qup14"; }; - qup_spi12_cs: qup-spi12-cs { + qup_spi12_cs: qup-spi12-cs-pins { pins = "gpio51"; function = "qup14"; }; - qup_spi12_cs_gpio: qup-spi12-cs-gpio { + qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins { pins = "gpio51"; function = "gpio"; }; - qup_spi13_data_clk: qup-spi13-data-clk { + qup_spi13_data_clk: qup-spi13-data-clk-pins { pins = "gpio52", "gpio53", "gpio54"; function = "qup15"; }; - qup_spi13_cs: qup-spi13-cs { + qup_spi13_cs: qup-spi13-cs-pins { pins = "gpio55"; function = "qup15"; }; - qup_spi13_cs_gpio: qup-spi13-cs-gpio { + qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins { pins = "gpio55"; function = "gpio"; }; - qup_spi14_data_clk: qup-spi14-data-clk { + qup_spi14_data_clk: qup-spi14-data-clk-pins { pins = "gpio56", "gpio57", "gpio58"; function = "qup16"; }; - qup_spi14_cs: qup-spi14-cs { + qup_spi14_cs: qup-spi14-cs-pins { pins = "gpio59"; function = "qup16"; }; - qup_spi14_cs_gpio: qup-spi14-cs-gpio { + qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins { pins = "gpio59"; function = "gpio"; }; - qup_spi15_data_clk: qup-spi15-data-clk { + qup_spi15_data_clk: qup-spi15-data-clk-pins { pins = "gpio60", "gpio61", "gpio62"; function = "qup17"; }; - qup_spi15_cs: qup-spi15-cs { + qup_spi15_cs: qup-spi15-cs-pins { pins = "gpio63"; function = "qup17"; }; - qup_spi15_cs_gpio: qup-spi15-cs-gpio { + qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins { pins = "gpio63"; function = "gpio"; }; - qup_uart0_cts: qup-uart0-cts { + qup_uart0_cts: qup-uart0-cts-pins { pins = "gpio0"; function = "qup00"; }; - qup_uart0_rts: qup-uart0-rts { + qup_uart0_rts: qup-uart0-rts-pins { pins = "gpio1"; function = "qup00"; }; - qup_uart0_tx: qup-uart0-tx { + qup_uart0_tx: qup-uart0-tx-pins { pins = "gpio2"; function = "qup00"; }; - qup_uart0_rx: qup-uart0-rx { + qup_uart0_rx: qup-uart0-rx-pins { pins = "gpio3"; function = "qup00"; }; - qup_uart1_cts: qup-uart1-cts { + qup_uart1_cts: qup-uart1-cts-pins { pins = "gpio4"; function = "qup01"; }; - qup_uart1_rts: qup-uart1-rts { + qup_uart1_rts: qup-uart1-rts-pins { pins = "gpio5"; function = "qup01"; }; - qup_uart1_tx: qup-uart1-tx { + qup_uart1_tx: qup-uart1-tx-pins { pins = "gpio6"; function = "qup01"; }; - qup_uart1_rx: qup-uart1-rx { + qup_uart1_rx: qup-uart1-rx-pins { pins = "gpio7"; function = "qup01"; }; - qup_uart2_cts: qup-uart2-cts { + qup_uart2_cts: qup-uart2-cts-pins { pins = "gpio8"; function = "qup02"; }; - qup_uart2_rts: qup-uart2-rts { + qup_uart2_rts: qup-uart2-rts-pins { pins = "gpio9"; function = "qup02"; }; - qup_uart2_tx: qup-uart2-tx { + qup_uart2_tx: qup-uart2-tx-pins { pins = "gpio10"; function = "qup02"; }; - qup_uart2_rx: qup-uart2-rx { + qup_uart2_rx: qup-uart2-rx-pins { pins = "gpio11"; function = "qup02"; }; - qup_uart3_cts: qup-uart3-cts { + qup_uart3_cts: qup-uart3-cts-pins { pins = "gpio12"; function = "qup03"; }; - qup_uart3_rts: qup-uart3-rts { + qup_uart3_rts: qup-uart3-rts-pins { pins = "gpio13"; function = "qup03"; }; - qup_uart3_tx: qup-uart3-tx { + qup_uart3_tx: qup-uart3-tx-pins { pins = "gpio14"; function = "qup03"; }; - qup_uart3_rx: qup-uart3-rx { + qup_uart3_rx: qup-uart3-rx-pins { pins = "gpio15"; function = "qup03"; }; - qup_uart4_cts: qup-uart4-cts { + qup_uart4_cts: qup-uart4-cts-pins { pins = "gpio16"; function = "qup04"; }; - qup_uart4_rts: qup-uart4-rts { + qup_uart4_rts: qup-uart4-rts-pins { pins = "gpio17"; function = "qup04"; }; - qup_uart4_tx: qup-uart4-tx { + qup_uart4_tx: qup-uart4-tx-pins { pins = "gpio18"; function = "qup04"; }; - qup_uart4_rx: qup-uart4-rx { + qup_uart4_rx: qup-uart4-rx-pins { pins = "gpio19"; function = "qup04"; }; - qup_uart5_cts: qup-uart5-cts { + qup_uart5_cts: qup-uart5-cts-pins { pins = "gpio20"; function = "qup05"; }; - qup_uart5_rts: qup-uart5-rts { + qup_uart5_rts: qup-uart5-rts-pins { pins = "gpio21"; function = "qup05"; }; - qup_uart5_tx: qup-uart5-tx { + qup_uart5_tx: qup-uart5-tx-pins { pins = "gpio22"; function = "qup05"; }; - qup_uart5_rx: qup-uart5-rx { + qup_uart5_rx: qup-uart5-rx-pins { pins = "gpio23"; function = "qup05"; }; - qup_uart6_cts: qup-uart6-cts { + qup_uart6_cts: qup-uart6-cts-pins { pins = "gpio24"; function = "qup06"; }; - qup_uart6_rts: qup-uart6-rts { + qup_uart6_rts: qup-uart6-rts-pins { pins = "gpio25"; function = "qup06"; }; - qup_uart6_tx: qup-uart6-tx { + qup_uart6_tx: qup-uart6-tx-pins { pins = "gpio26"; function = "qup06"; }; - qup_uart6_rx: qup-uart6-rx { + qup_uart6_rx: qup-uart6-rx-pins { pins = "gpio27"; function = "qup06"; }; - qup_uart7_cts: qup-uart7-cts { + qup_uart7_cts: qup-uart7-cts-pins { pins = "gpio28"; function = "qup07"; }; - qup_uart7_rts: qup-uart7-rts { + qup_uart7_rts: qup-uart7-rts-pins { pins = "gpio29"; function = "qup07"; }; - qup_uart7_tx: qup-uart7-tx { + qup_uart7_tx: qup-uart7-tx-pins { pins = "gpio30"; function = "qup07"; }; - qup_uart7_rx: qup-uart7-rx { + qup_uart7_rx: qup-uart7-rx-pins { pins = "gpio31"; function = "qup07"; }; - qup_uart8_cts: qup-uart8-cts { + qup_uart8_cts: qup-uart8-cts-pins { pins = "gpio32"; function = "qup10"; }; - qup_uart8_rts: qup-uart8-rts { + qup_uart8_rts: qup-uart8-rts-pins { pins = "gpio33"; function = "qup10"; }; - qup_uart8_tx: qup-uart8-tx { + qup_uart8_tx: qup-uart8-tx-pins { pins = "gpio34"; function = "qup10"; }; - qup_uart8_rx: qup-uart8-rx { + qup_uart8_rx: qup-uart8-rx-pins { pins = "gpio35"; function = "qup10"; }; - qup_uart9_cts: qup-uart9-cts { + qup_uart9_cts: qup-uart9-cts-pins { pins = "gpio36"; function = "qup11"; }; - qup_uart9_rts: qup-uart9-rts { + qup_uart9_rts: qup-uart9-rts-pins { pins = "gpio37"; function = "qup11"; }; - qup_uart9_tx: qup-uart9-tx { + qup_uart9_tx: qup-uart9-tx-pins { pins = "gpio38"; function = "qup11"; }; - qup_uart9_rx: qup-uart9-rx { + qup_uart9_rx: qup-uart9-rx-pins { pins = "gpio39"; function = "qup11"; }; - qup_uart10_cts: qup-uart10-cts { + qup_uart10_cts: qup-uart10-cts-pins { pins = "gpio40"; function = "qup12"; }; - qup_uart10_rts: qup-uart10-rts { + qup_uart10_rts: qup-uart10-rts-pins { pins = "gpio41"; function = "qup12"; }; - qup_uart10_tx: qup-uart10-tx { + qup_uart10_tx: qup-uart10-tx-pins { pins = "gpio42"; function = "qup12"; }; - qup_uart10_rx: qup-uart10-rx { + qup_uart10_rx: qup-uart10-rx-pins { pins = "gpio43"; function = "qup12"; }; - qup_uart11_cts: qup-uart11-cts { + qup_uart11_cts: qup-uart11-cts-pins { pins = "gpio44"; function = "qup13"; }; - qup_uart11_rts: qup-uart11-rts { + qup_uart11_rts: qup-uart11-rts-pins { pins = "gpio45"; function = "qup13"; }; - qup_uart11_tx: qup-uart11-tx { + qup_uart11_tx: qup-uart11-tx-pins { pins = "gpio46"; function = "qup13"; }; - qup_uart11_rx: qup-uart11-rx { + qup_uart11_rx: qup-uart11-rx-pins { pins = "gpio47"; function = "qup13"; }; - qup_uart12_cts: qup-uart12-cts { + qup_uart12_cts: qup-uart12-cts-pins { pins = "gpio48"; function = "qup14"; }; - qup_uart12_rts: qup-uart12-rts { + qup_uart12_rts: qup-uart12-rts-pins { pins = "gpio49"; function = "qup14"; }; - qup_uart12_tx: qup-uart12-tx { + qup_uart12_tx: qup-uart12-tx-pins { pins = "gpio50"; function = "qup14"; }; - qup_uart12_rx: qup-uart12-rx { + qup_uart12_rx: qup-uart12-rx-pins { pins = "gpio51"; function = "qup14"; }; - qup_uart13_cts: qup-uart13-cts { + qup_uart13_cts: qup-uart13-cts-pins { pins = "gpio52"; function = "qup15"; }; - qup_uart13_rts: qup-uart13-rts { + qup_uart13_rts: qup-uart13-rts-pins { pins = "gpio53"; function = "qup15"; }; - qup_uart13_tx: qup-uart13-tx { + qup_uart13_tx: qup-uart13-tx-pins { pins = "gpio54"; function = "qup15"; }; - qup_uart13_rx: qup-uart13-rx { + qup_uart13_rx: qup-uart13-rx-pins { pins = "gpio55"; function = "qup15"; }; - qup_uart14_cts: qup-uart14-cts { + qup_uart14_cts: qup-uart14-cts-pins { pins = "gpio56"; function = "qup16"; }; - qup_uart14_rts: qup-uart14-rts { + qup_uart14_rts: qup-uart14-rts-pins { pins = "gpio57"; function = "qup16"; }; - qup_uart14_tx: qup-uart14-tx { + qup_uart14_tx: qup-uart14-tx-pins { pins = "gpio58"; function = "qup16"; }; - qup_uart14_rx: qup-uart14-rx { + qup_uart14_rx: qup-uart14-rx-pins { pins = "gpio59"; function = "qup16"; }; - qup_uart15_cts: qup-uart15-cts { + qup_uart15_cts: qup-uart15-cts-pins { pins = "gpio60"; function = "qup17"; }; - qup_uart15_rts: qup-uart15-rts { + qup_uart15_rts: qup-uart15-rts-pins { pins = "gpio61"; function = "qup17"; }; - qup_uart15_tx: qup-uart15-tx { + qup_uart15_tx: qup-uart15-tx-pins { pins = "gpio62"; function = "qup17"; }; - qup_uart15_rx: qup-uart15-rx { + qup_uart15_rx: qup-uart15-rx-pins { pins = "gpio63"; function = "qup17"; }; - sdc1_clk: sdc1-clk { + sdc1_clk: sdc1-clk-pins { pins = "sdc1_clk"; }; - sdc1_cmd: sdc1-cmd { + sdc1_cmd: sdc1-cmd-pins { pins = "sdc1_cmd"; }; - sdc1_data: sdc1-data { + sdc1_data: sdc1-data-pins { pins = "sdc1_data"; }; - sdc1_rclk: sdc1-rclk { + sdc1_rclk: sdc1-rclk-pins { pins = "sdc1_rclk"; }; - sdc1_clk_sleep: sdc1-clk-sleep { + sdc1_clk_sleep: sdc1-clk-sleep-pins { pins = "sdc1_clk"; drive-strength = <2>; bias-bus-hold; }; - sdc1_cmd_sleep: sdc1-cmd-sleep { + sdc1_cmd_sleep: sdc1-cmd-sleep-pins { pins = "sdc1_cmd"; drive-strength = <2>; bias-bus-hold; }; - sdc1_data_sleep: sdc1-data-sleep { + sdc1_data_sleep: sdc1-data-sleep-pins { pins = "sdc1_data"; drive-strength = <2>; bias-bus-hold; }; - sdc1_rclk_sleep: sdc1-rclk-sleep { + sdc1_rclk_sleep: sdc1-rclk-sleep-pins { pins = "sdc1_rclk"; drive-strength = <2>; bias-bus-hold; }; - sdc2_clk: sdc2-clk { + sdc2_clk: sdc2-clk-pins { pins = "sdc2_clk"; }; - sdc2_cmd: sdc2-cmd { + sdc2_cmd: sdc2-cmd-pins { pins = "sdc2_cmd"; }; - sdc2_data: sdc2-data { + sdc2_data: sdc2-data-pins { pins = "sdc2_data"; }; - sdc2_clk_sleep: sdc2-clk-sleep { + sdc2_clk_sleep: sdc2-clk-sleep-pins { pins = "sdc2_clk"; drive-strength = <2>; bias-bus-hold; }; - sdc2_cmd_sleep: sdc2-cmd-sleep { + sdc2_cmd_sleep: sdc2-cmd-sleep-pins { pins = "sdc2_cmd"; drive-strength = <2>; bias-bus-hold; }; - sdc2_data_sleep: sdc2-data-sleep { + sdc2_data_sleep: sdc2-data-sleep-pins { pins = "sdc2_data"; drive-strength = <2>; bias-bus-hold; diff --git a/dts/src/arm64/qcom/sc8280xp-crd.dts b/dts/src/arm64/qcom/sc8280xp-crd.dts index 45058ad0a1..fea7d8273c 100644 --- a/dts/src/arm64/qcom/sc8280xp-crd.dts +++ b/dts/src/arm64/qcom/sc8280xp-crd.dts @@ -87,7 +87,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; regulator-boot-on; regulator-always-on; }; @@ -97,7 +96,6 @@ regulator-min-microvolt = <912000>; regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l6b: ldo6 { @@ -105,7 +103,6 @@ regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; regulator-boot-on; }; }; @@ -119,7 +116,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l7c: ldo7 { @@ -135,7 +131,6 @@ regulator-min-microvolt = <3072000>; regulator-max-microvolt = <3072000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; }; @@ -158,7 +153,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l6d: ldo6 { @@ -166,7 +160,6 @@ regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l7d: ldo7 { @@ -174,7 +167,6 @@ regulator-min-microvolt = <3072000>; regulator-max-microvolt = <3072000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l9d: ldo9 { @@ -182,7 +174,6 @@ regulator-min-microvolt = <912000>; regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; }; }; @@ -203,16 +194,20 @@ clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; + pinctrl-0 = <&qup0_i2c4_default>; status = "okay"; touchscreen@10 { compatible = "hid-over-i2c"; reg = <0x10>; + hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts0_default>; }; }; @@ -228,24 +223,36 @@ clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; + pinctrl-0 = <&qup2_i2c5_default>; status = "okay"; touchpad@15 { compatible = "hid-over-i2c"; reg = <0x15>; + hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&tpad_default>; + + wakeup-source; }; keyboard@68 { compatible = "hid-over-i2c"; reg = <0x68>; + hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&kybd_default>; + + wakeup-source; }; }; @@ -414,7 +421,7 @@ int-n { pins = "gpio175"; function = "gpio"; - bias-pull-up; + bias-disable; }; reset-n { diff --git a/dts/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/dts/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 4c404e2eaf..b2b744bb8a 100644 --- a/dts/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/dts/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -79,7 +79,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; regulator-boot-on; }; @@ -88,7 +87,6 @@ regulator-min-microvolt = <912000>; regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l6b: ldo6 { @@ -96,7 +94,6 @@ regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; regulator-boot-on; regulator-always-on; // FIXME: VDD_A_EDP_0_0P9 }; @@ -111,7 +108,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l12c: ldo12 { @@ -119,7 +115,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l13c: ldo13 { @@ -127,7 +122,6 @@ regulator-min-microvolt = <3072000>; regulator-max-microvolt = <3072000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; }; @@ -142,7 +136,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l4d: ldo4 { @@ -150,7 +143,6 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l7d: ldo7 { @@ -158,7 +150,6 @@ regulator-min-microvolt = <3072000>; regulator-max-microvolt = <3072000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; vreg_l9d: ldo9 { @@ -166,7 +157,6 @@ regulator-min-microvolt = <912000>; regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; }; }; }; @@ -187,7 +177,7 @@ clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; + pinctrl-0 = <&qup0_i2c4_default>; status = "okay"; @@ -195,9 +185,13 @@ touchscreen@10 { compatible = "hid-over-i2c"; reg = <0x10>; + hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts0_default>; }; }; @@ -213,24 +207,52 @@ clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; + pinctrl-0 = <&qup2_i2c5_default>; status = "okay"; + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&tpad_default>; + + wakeup-source; + + status = "disabled"; + }; + touchpad@2c { compatible = "hid-over-i2c"; reg = <0x2c>; + hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&tpad_default>; + + wakeup-source; }; keyboard@68 { compatible = "hid-over-i2c"; reg = <0x68>; + hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&kybd_default>; + + wakeup-source; }; }; @@ -373,7 +395,7 @@ int-n { pins = "gpio175"; function = "gpio"; - bias-pull-up; + bias-disable; }; reset-n { diff --git a/dts/src/arm64/qcom/sc8280xp-pmics.dtsi b/dts/src/arm64/qcom/sc8280xp-pmics.dtsi index ae90b97aec..24836b6b9b 100644 --- a/dts/src/arm64/qcom/sc8280xp-pmics.dtsi +++ b/dts/src/arm64/qcom/sc8280xp-pmics.dtsi @@ -60,9 +60,8 @@ #interrupt-cells = <2>; }; - pmc8280c_lpg: lpg@e800 { + pmc8280c_lpg: pwm { compatible = "qcom,pm8350c-pwm"; - reg = <0xe800>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm64/qcom/sc8280xp.dtsi b/dts/src/arm64/qcom/sc8280xp.dtsi index 49ea8b5612..c32bcded2a 100644 --- a/dts/src/arm64/qcom/sc8280xp.dtsi +++ b/dts/src/arm64/qcom/sc8280xp.dtsi @@ -1312,6 +1312,8 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; interconnect-names = "usb-ddr", "apps-usb"; + wakeup-source; + status = "disabled"; usb_0_dwc3: usb@a600000 { @@ -1364,6 +1366,8 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; interconnect-names = "usb-ddr", "apps-usb"; + wakeup-source; + status = "disabled"; usb_1_dwc3: usb@a800000 { diff --git a/dts/src/arm64/qcom/sdm630.dtsi b/dts/src/arm64/qcom/sdm630.dtsi index 1bc9091cad..b51b85f583 100644 --- a/dts/src/arm64/qcom/sdm630.dtsi +++ b/dts/src/arm64/qcom/sdm630.dtsi @@ -697,9 +697,15 @@ #thermal-sensor-cells = <1>; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x01f40000 0x40000>; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,sdm630-tcsr", "syscon"; + reg = <0x01f60000 0x20000>; }; tlmm: pinctrl@3100000 { @@ -2351,12 +2357,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - sound: sound { }; diff --git a/dts/src/arm64/qcom/sdm845-db845c.dts b/dts/src/arm64/qcom/sdm845-db845c.dts index c6e2c571b4..132417e2d1 100644 --- a/dts/src/arm64/qcom/sdm845-db845c.dts +++ b/dts/src/arm64/qcom/sdm845-db845c.dts @@ -522,7 +522,7 @@ &pcie0 { status = "okay"; - perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>; vddpe-3v3-supply = <&pcie0_3p3v_dual>; @@ -540,7 +540,7 @@ &pcie1 { status = "okay"; - perst-gpio = <&tlmm 102 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; @@ -1081,7 +1081,7 @@ pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - reset-gpios = <&tlmm 64 0>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>; @@ -1214,8 +1214,6 @@ reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&cam0_default>; - gpios = <&tlmm 13 0>, - <&tlmm 9 GPIO_ACTIVE_LOW>; clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; clock-names = "xvclk"; @@ -1228,8 +1226,6 @@ * both have to be enabled through the power management * gpios. */ - power-domains = <&clock_camcc TITAN_TOP_GDSC>; - dovdd-supply = <&vreg_lvs1a_1p8>; avdd-supply = <&cam0_avdd_2v8>; dvdd-supply = <&cam0_dvdd_1v2>; @@ -1255,11 +1251,9 @@ reg = <0x60>; // CAM3_RST_N - enable-gpios = <&tlmm 21 0>; + enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cam3_default>; - gpios = <&tlmm 16 0>, - <&tlmm 21 0>; clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; clock-names = "xclk"; @@ -1273,8 +1267,6 @@ * * No 1.2V vddd-supply regulator is used. */ - power-domains = <&clock_camcc TITAN_TOP_GDSC>; - vdddo-supply = <&vreg_lvs1a_1p8>; vdda-supply = <&cam3_avdd_2v8>; diff --git a/dts/src/arm64/qcom/sdm845-mtp.dts b/dts/src/arm64/qcom/sdm845-mtp.dts index 7713e8060c..de2d10e031 100644 --- a/dts/src/arm64/qcom/sdm845-mtp.dts +++ b/dts/src/arm64/qcom/sdm845-mtp.dts @@ -536,42 +536,42 @@ reg = <ADC5_XO_THERM_100K_PU>; label = "xo_therm"; qcom,ratiometric; - qcom,hw-settle-time-us = <200>; + qcom,hw-settle-time = <200>; }; adc-chan@4d { reg = <ADC5_AMUX_THM1_100K_PU>; label = "msm_therm"; qcom,ratiometric; - qcom,hw-settle-time-us = <200>; + qcom,hw-settle-time = <200>; }; adc-chan@4f { reg = <ADC5_AMUX_THM3_100K_PU>; label = "pa_therm1"; qcom,ratiometric; - qcom,hw-settle-time-us = <200>; + qcom,hw-settle-time = <200>; }; adc-chan@51 { reg = <ADC5_AMUX_THM5_100K_PU>; label = "quiet_therm"; qcom,ratiometric; - qcom,hw-settle-time-us = <200>; + qcom,hw-settle-time = <200>; }; adc-chan@83 { reg = <ADC5_VPH_PWR>; label = "vph_pwr"; qcom,ratiometric; - qcom,hw-settle-time-us = <200>; + qcom,hw-settle-time = <200>; }; adc-chan@85 { reg = <ADC5_VCOIN>; label = "vcoin"; qcom,ratiometric; - qcom,hw-settle-time-us = <200>; + qcom,hw-settle-time = <200>; }; }; diff --git a/dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts b/dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts index 82c27f90d3..0f470cf1ed 100644 --- a/dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts +++ b/dts/src/arm64/qcom/sdm845-xiaomi-beryllium.dts @@ -546,7 +546,7 @@ pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - reset-gpios = <&tlmm 64 0>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>; diff --git a/dts/src/arm64/qcom/sdm845-xiaomi-polaris.dts b/dts/src/arm64/qcom/sdm845-xiaomi-polaris.dts index 7747081b98..afc17e4d40 100644 --- a/dts/src/arm64/qcom/sdm845-xiaomi-polaris.dts +++ b/dts/src/arm64/qcom/sdm845-xiaomi-polaris.dts @@ -126,7 +126,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - gpio = <&tlmm 23 0>; + gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; regulator-always-on; regulator-boot-on; enable-active-high; @@ -522,7 +522,7 @@ }; &pm8998_gpio { - volume_up_gpio: pm8998_gpio6 { + volume_up_gpio: pm8998-gpio6-state { pinconf { qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; function = "normal"; @@ -617,7 +617,7 @@ pins = "gpio6", "gpio10"; function = "gpio"; drive-strength = <8>; - bias-disable = <0>; + bias-disable; }; sde_dsi_suspend: sde-dsi-suspend { @@ -712,7 +712,7 @@ pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - reset-gpios = <&tlmm 64 0>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>; diff --git a/dts/src/arm64/qcom/sdm845.dtsi b/dts/src/arm64/qcom/sdm845.dtsi index f0e286715d..d761da4722 100644 --- a/dts/src/arm64/qcom/sdm845.dtsi +++ b/dts/src/arm64/qcom/sdm845.dtsi @@ -919,12 +919,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; @@ -2138,11 +2132,48 @@ llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; + reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + pmu@114a000 { + compatible = "qcom,sdm845-llcc-bwmon"; + reg = <0 0x0114a000 0 0x1000>; + interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* + * The interconnect path bandwidth taken from + * cpu4_opp_table bandwidth for gladiator_noc-mem_noc + * interconnect. This also matches the + * bandwidth table of qcom,llccbw (qcom,bw-tbl, + * bus width: 4 bytes) from msm-4.9 downstream + * kernel. + */ + opp-0 { + opp-peak-kBps = <800000>; + }; + opp-1 { + opp-peak-kBps = <1804000>; + }; + opp-2 { + opp-peak-kBps = <3072000>; + }; + opp-3 { + opp-peak-kBps = <5412000>; + }; + opp-4 { + opp-peak-kBps = <7216000>; + }; + }; + }; + pmu@1436400 { compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; reg = <0 0x01436400 0 0x600>; @@ -2588,9 +2619,15 @@ status = "disabled"; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0 0x01f40000 0 0x40000>; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,sdm845-tcsr", "syscon"; + reg = <0 0x01f60000 0 0x20000>; }; tlmm: pinctrl@3400000 { @@ -3207,7 +3244,7 @@ <&pdc_reset PDC_MODEM_SYNC_RESET>; reset-names = "mss_restart", "pdc_reset"; - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; power-domains = <&rpmhpd SDM845_CX>, <&rpmhpd SDM845_MX>, @@ -4836,7 +4873,7 @@ aoss_qmp: power-controller@c300000 { compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x100000>; + reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 0>; @@ -4851,6 +4888,11 @@ }; }; + sram@c3f0000 { + compatible = "qcom,sdm845-rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, diff --git a/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts index a7af1bed43..be59a8ba9c 100644 --- a/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts +++ b/dts/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts @@ -772,7 +772,7 @@ pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - reset-gpios = <&tlmm 64 0>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>; diff --git a/dts/src/arm64/qcom/sdm850-samsung-w737.dts b/dts/src/arm64/qcom/sdm850-samsung-w737.dts index b0315eeb13..f954fe5cb6 100644 --- a/dts/src/arm64/qcom/sdm850-samsung-w737.dts +++ b/dts/src/arm64/qcom/sdm850-samsung-w737.dts @@ -704,7 +704,7 @@ pinctrl-names = "default"; clock-names = "extclk"; clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - reset-gpios = <&tlmm 64 0>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-tx-supply = <&vreg_s4a_1p8>; diff --git a/dts/src/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts b/dts/src/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts index 0aad2e94e7..6a8b88cc43 100644 --- a/dts/src/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/dts/src/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -87,7 +87,7 @@ }; &sdc2_off_state { - sd-cd { + sd-cd-pins { pins = "gpio98"; drive-strength = <2>; bias-disable; @@ -95,7 +95,7 @@ }; &sdc2_on_state { - sd-cd { + sd-cd-pins { pins = "gpio98"; drive-strength = <2>; bias-pull-up; diff --git a/dts/src/arm64/qcom/sm6125.dtsi b/dts/src/arm64/qcom/sm6125.dtsi index 8c582a9e4a..1fe3fa3ad8 100644 --- a/dts/src/arm64/qcom/sm6125.dtsi +++ b/dts/src/arm64/qcom/sm6125.dtsi @@ -387,19 +387,19 @@ #interrupt-cells = <2>; sdc2_off_state: sdc2-off-state { - clk { + clk-pins { pins = "sdc2_clk"; drive-strength = <2>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <2>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <2>; bias-pull-up; @@ -413,13 +413,13 @@ bias-disable; }; - cmd { + cmd-pins-pins { pins = "sdc2_cmd"; drive-strength = <10>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <10>; bias-pull-up; diff --git a/dts/src/arm64/qcom/sm6350.dtsi b/dts/src/arm64/qcom/sm6350.dtsi index d06aefdf3d..c39de7d3ac 100644 --- a/dts/src/arm64/qcom/sm6350.dtsi +++ b/dts/src/arm64/qcom/sm6350.dtsi @@ -1,11 +1,14 @@ // SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> */ #include <dt-bindings/clock/qcom,gcc-sm6350.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,sm6350.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -517,6 +520,26 @@ }; }; + gpi_dma0: dma-controller@800000 { + compatible = "qcom,sm6350-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x56 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x8c0000 0x0 0x2000>; @@ -537,8 +560,15 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -550,12 +580,39 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; }; + gpi_dma1: dma-controller@900000 { + compatible = "qcom,sm6350-gpi-dma"; + reg = <0 0x00900000 0 0x60000>; + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <10>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x4d6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x9c0000 0x0 0x2000>; @@ -576,8 +633,15 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -589,8 +653,15 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -602,8 +673,15 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -615,6 +693,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart9_default>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -626,13 +707,67 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sm6350-config-noc"; + reg = <0 0x01500000 0 0x28000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm6350-system-noc"; + reg = <0 0x01620000 0 0x17080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + + clk_virt: interconnect-clk-virt { + compatible = "qcom,sm6350-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm6350-aggre1-noc"; + reg = <0 0x016e0000 0 0x15080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm6350-aggre2-noc"; + reg = <0 0x01700000 0 0x1f880>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + + compute_noc: interconnect-compute-noc { + compatible = "qcom,sm6350-compute-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sm6350-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufs@1d84000 { compatible = "qcom,sm6350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -933,6 +1068,10 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd SM6350_CX>; @@ -947,11 +1086,15 @@ opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <790000 131000>; + opp-avg-kBps = <50000 50000>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3190000 294000>; + opp-avg-kBps = <261438 300000>; }; }; }; @@ -1017,12 +1160,33 @@ }; }; + dc_noc: interconnect@9160000 { + compatible = "qcom,sm6350-dc-noc"; + reg = <0 0x09160000 0 0x3200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; }; + gem_noc: interconnect@9680000 { + compatible = "qcom,sm6350-gem-noc"; + reg = <0 0x09680000 0 0x3e200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + npu_noc: interconnect@9990000 { + compatible = "qcom,sm6350-npu-noc"; + reg = <0 0x09990000 0 0x1600>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; @@ -1054,6 +1218,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -1146,49 +1314,49 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; - qup_uart9_default: qup-uart9-default { + qup_uart9_default: qup-uart9-default-state { pins = "gpio25", "gpio26"; function = "qup13_f2"; drive-strength = <2>; bias-disable; }; - qup_i2c0_default: qup-i2c0-default { + qup_i2c0_default: qup-i2c0-default-state { pins = "gpio0", "gpio1"; function = "qup00"; drive-strength = <2>; bias-pull-up; }; - qup_i2c2_default: qup-i2c2-default { + qup_i2c2_default: qup-i2c2-default-state { pins = "gpio45", "gpio46"; function = "qup02"; drive-strength = <2>; bias-pull-up; }; - qup_i2c6_default: qup-i2c6-default { + qup_i2c6_default: qup-i2c6-default-state { pins = "gpio13", "gpio14"; function = "qup10"; drive-strength = <2>; bias-pull-up; }; - qup_i2c7_default: qup-i2c7-default { + qup_i2c7_default: qup-i2c7-default-state { pins = "gpio27", "gpio28"; function = "qup11"; drive-strength = <2>; bias-pull-up; }; - qup_i2c8_default: qup-i2c8-default { + qup_i2c8_default: qup-i2c8-default-state { pins = "gpio19", "gpio20"; function = "qup12"; drive-strength = <2>; bias-pull-up; }; - qup_i2c10_default: qup-i2c10-default { + qup_i2c10_default: qup-i2c10-default-state { pins = "gpio4", "gpio5"; function = "qup14"; drive-strength = <2>; diff --git a/dts/src/arm64/qcom/sm7225-fairphone-fp4.dts b/dts/src/arm64/qcom/sm7225-fairphone-fp4.dts index c76abe7587..30c94fd4fe 100644 --- a/dts/src/arm64/qcom/sm7225-fairphone-fp4.dts +++ b/dts/src/arm64/qcom/sm7225-fairphone-fp4.dts @@ -12,6 +12,7 @@ #include "sm7225.dtsi" #include "pm6150l.dtsi" #include "pm6350.dtsi" +#include "pm7250b.dtsi" / { model = "Fairphone 4"; @@ -70,6 +71,36 @@ qcom,vmid = <15>; }; }; + + thermal-zones { + chg-skin-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; }; &adsp { @@ -353,6 +384,42 @@ linux,code = <KEY_VOLUMEDOWN>; }; +&pm7250b_adc { + adc-chan@4d { + reg = <ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "charger_skin_therm"; + }; + + adc-chan@4f { + reg = <ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "conn_therm"; + }; +}; + +&pm7250b_adc_tm { + status = "okay"; + + charger-skin-therm@0 { + reg = <0>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + conn-therm@1 { + reg = <1>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &qupv3_id_1 { status = "okay"; }; diff --git a/dts/src/arm64/qcom/sm8150.dtsi b/dts/src/arm64/qcom/sm8150.dtsi index 916f12b799..cef8c4f4f0 100644 --- a/dts/src/arm64/qcom/sm8150.dtsi +++ b/dts/src/arm64/qcom/sm8150.dtsi @@ -585,12 +585,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -2054,9 +2048,15 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs_1: syscon@1f60000 { + compatible = "qcom,sm8150-tcsr", "syscon"; + reg = <0x0 0x01f60000 0x0 0x20000>; }; remoteproc_slpi: remoteproc@2400000 { diff --git a/dts/src/arm64/qcom/sm8250-mtp.dts b/dts/src/arm64/qcom/sm8250-mtp.dts index 7ab3627cc3..a102aa5efa 100644 --- a/dts/src/arm64/qcom/sm8250-mtp.dts +++ b/dts/src/arm64/qcom/sm8250-mtp.dts @@ -635,7 +635,7 @@ wcd938x: codec { compatible = "qcom,wcd9380-codec"; #sound-dai-cells = <1>; - reset-gpios = <&tlmm 32 0>; + reset-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-rxtx-supply = <&vreg_s4a_1p8>; vdd-io-supply = <&vreg_s4a_1p8>; diff --git a/dts/src/arm64/qcom/sm8250.dtsi b/dts/src/arm64/qcom/sm8250.dtsi index bc773e2100..a5b62cadb1 100644 --- a/dts/src/arm64/qcom/sm8250.dtsi +++ b/dts/src/arm64/qcom/sm8250.dtsi @@ -1792,7 +1792,7 @@ }; pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8250"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, @@ -1810,8 +1810,16 @@ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1893,7 +1901,7 @@ }; pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8250"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, @@ -2001,7 +2009,7 @@ }; pcie2: pci@1c10000 { - compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8250"; reg = <0 0x01c10000 0 0x3000>, <0 0x64000000 0 0xf1d>, <0 0x64000f20 0 0xa8>, @@ -3571,6 +3579,25 @@ }; }; }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; }; dsi0_phy: dsi-phy@ae94400 { @@ -3663,25 +3690,6 @@ clock-names = "iface", "ref"; status = "disabled"; - - dsi_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-187500000 { - opp-hz = /bits/ 64 <187500000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; }; }; diff --git a/dts/src/arm64/qcom/sm8350-sony-xperia-sagami.dtsi b/dts/src/arm64/qcom/sm8350-sony-xperia-sagami.dtsi index cb9bbd234b..b3c9952ac1 100644 --- a/dts/src/arm64/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/dts/src/arm64/qcom/sm8350-sony-xperia-sagami.dtsi @@ -222,8 +222,8 @@ &tlmm { gpio-reserved-ranges = <44 4>; - ts_int_default: ts-int-default { - pin = "gpio23"; + ts_int_default: ts-int-default-state { + pins = "gpio23"; function = "gpio"; drive-strength = <2>; bias-disable; diff --git a/dts/src/arm64/qcom/sm8350.dtsi b/dts/src/arm64/qcom/sm8350.dtsi index d9b08dfc29..a86d9ea93b 100644 --- a/dts/src/arm64/qcom/sm8350.dtsi +++ b/dts/src/arm64/qcom/sm8350.dtsi @@ -1762,150 +1762,150 @@ wakeup-parent = <&pdc>; qup_uart3_default_state: qup-uart3-default-state { - rx { + rx-pins { pins = "gpio18"; function = "qup3"; }; - tx { + tx-pins { pins = "gpio19"; function = "qup3"; }; }; - qup_uart6_default: qup-uart6-default { + qup_uart6_default: qup-uart6-default-state { pins = "gpio30", "gpio31"; function = "qup6"; drive-strength = <2>; bias-disable; }; - qup_uart18_default: qup-uart18-default { + qup_uart18_default: qup-uart18-default-state { pins = "gpio58", "gpio59"; function = "qup18"; drive-strength = <2>; bias-disable; }; - qup_i2c0_default: qup-i2c0-default { + qup_i2c0_default: qup-i2c0-default-state { pins = "gpio4", "gpio5"; function = "qup0"; drive-strength = <2>; bias-pull-up; }; - qup_i2c1_default: qup-i2c1-default { + qup_i2c1_default: qup-i2c1-default-state { pins = "gpio8", "gpio9"; function = "qup1"; drive-strength = <2>; bias-pull-up; }; - qup_i2c2_default: qup-i2c2-default { + qup_i2c2_default: qup-i2c2-default-state { pins = "gpio12", "gpio13"; function = "qup2"; drive-strength = <2>; bias-pull-up; }; - qup_i2c4_default: qup-i2c4-default { + qup_i2c4_default: qup-i2c4-default-state { pins = "gpio20", "gpio21"; function = "qup4"; drive-strength = <2>; bias-pull-up; }; - qup_i2c5_default: qup-i2c5-default { + qup_i2c5_default: qup-i2c5-default-state { pins = "gpio24", "gpio25"; function = "qup5"; drive-strength = <2>; bias-pull-up; }; - qup_i2c6_default: qup-i2c6-default { + qup_i2c6_default: qup-i2c6-default-state { pins = "gpio28", "gpio29"; function = "qup6"; drive-strength = <2>; bias-pull-up; }; - qup_i2c7_default: qup-i2c7-default { + qup_i2c7_default: qup-i2c7-default-state { pins = "gpio32", "gpio33"; function = "qup7"; drive-strength = <2>; bias-disable; }; - qup_i2c8_default: qup-i2c8-default { + qup_i2c8_default: qup-i2c8-default-state { pins = "gpio36", "gpio37"; function = "qup8"; drive-strength = <2>; bias-pull-up; }; - qup_i2c9_default: qup-i2c9-default { + qup_i2c9_default: qup-i2c9-default-state { pins = "gpio40", "gpio41"; function = "qup9"; drive-strength = <2>; bias-pull-up; }; - qup_i2c10_default: qup-i2c10-default { + qup_i2c10_default: qup-i2c10-default-state { pins = "gpio44", "gpio45"; function = "qup10"; drive-strength = <2>; bias-pull-up; }; - qup_i2c11_default: qup-i2c11-default { + qup_i2c11_default: qup-i2c11-default-state { pins = "gpio48", "gpio49"; function = "qup11"; drive-strength = <2>; bias-pull-up; }; - qup_i2c12_default: qup-i2c12-default { + qup_i2c12_default: qup-i2c12-default-state { pins = "gpio52", "gpio53"; function = "qup12"; drive-strength = <2>; bias-pull-up; }; - qup_i2c13_default: qup-i2c13-default { + qup_i2c13_default: qup-i2c13-default-state { pins = "gpio0", "gpio1"; function = "qup13"; drive-strength = <2>; bias-pull-up; }; - qup_i2c14_default: qup-i2c14-default { + qup_i2c14_default: qup-i2c14-default-state { pins = "gpio56", "gpio57"; function = "qup14"; drive-strength = <2>; bias-disable; }; - qup_i2c15_default: qup-i2c15-default { + qup_i2c15_default: qup-i2c15-default-state { pins = "gpio60", "gpio61"; function = "qup15"; drive-strength = <2>; bias-disable; }; - qup_i2c16_default: qup-i2c16-default { + qup_i2c16_default: qup-i2c16-default-state { pins = "gpio64", "gpio65"; function = "qup16"; drive-strength = <2>; bias-disable; }; - qup_i2c17_default: qup-i2c17-default { + qup_i2c17_default: qup-i2c17-default-state { pins = "gpio72", "gpio73"; function = "qup17"; drive-strength = <2>; bias-disable; }; - qup_i2c19_default: qup-i2c19-default { + qup_i2c19_default: qup-i2c19-default-state { pins = "gpio76", "gpio77"; function = "qup19"; drive-strength = <2>; diff --git a/dts/src/arm64/qcom/sm8450-sony-xperia-nagara-pdx223.dts b/dts/src/arm64/qcom/sm8450-sony-xperia-nagara-pdx223.dts new file mode 100644 index 0000000000..d68765eb6d --- /dev/null +++ b/dts/src/arm64/qcom/sm8450-sony-xperia-nagara-pdx223.dts @@ -0,0 +1,634 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8450.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; + +/ { + model = "Sony Xperia 1 IV"; + compatible = "sony,pdx223", "qcom,sm8450"; + chassis-type = "handset"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + adsp_mem: memory@85700000 { + reg = <0x0 0x85700000 0x0 0x2800000>; + no-map; + }; + + video_mem: memory@9fd00000 { + reg = <0x0 0x9fd00000 0x0 0x700000>; + no-map; + }; + + rmtfs_mem: memory@f3300000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf3300000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0 0xffc00000 0 0x200000>; + console-size = <0x40000>; + record-size = <0x1000>; + ecc-size = <16>; + no-map; + }; + }; + + /* Sadly, the voltages for these GPIO regulators are unknown. */ + imx650_vana_vreg: imx650-vana-regulator { + compatible = "regulator-fixed"; + regulator-name = "imx650_vana_vreg"; + gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&pm8350_s11>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&pm8350_s12>; + + /* + * ARC regulators: + * s5 - gfx.lvl + * l8 - lcx.lvl + */ + + pm8350_s10: smps10 { + regulator-name = "pm8350_s10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8350_s11: smps11 { + regulator-name = "pm8350_s11"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + pm8350_s12: smps12 { + regulator-name = "pm8350_s12"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1400000>; + }; + + pm8350_l1: ldo1 { + regulator-name = "pm8350_l1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350_l2: ldo2 { + regulator-name = "pm8350_l2"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350_l3: ldo3 { + regulator-name = "pm8350_l3"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350_l5: ldo5 { + regulator-name = "pm8350_l5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350_l6: ldo6 { + regulator-name = "pm8350_l6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350_l7: ldo7 { + regulator-name = "pm8350_l7"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350_l9: ldo9 { + regulator-name = "pm8350_l9"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&pm8350_s12>; + + vdd-bob-supply = <&vph_pwr>; + + /* + * ARC regulators: + * s2 - mxc.lvl + * s4 - mss.lvl + * s6 - cx.lvl + */ + + pm8350c_s1: smps1 { + regulator-name = "pm8350c_s1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + pm8350c_s10: smps10 { + regulator-name = "pm8350c_s10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + + pm8350c_l1: ldo1 { + regulator-name = "pm8350c_l1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l2: ldo2 { + regulator-name = "pm8350c_l2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l3: ldo3 { + regulator-name = "pm8350c_l3"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l4: ldo4 { + regulator-name = "pm8350c_l4"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l5: ldo5 { + regulator-name = "pm8350c_l5"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l6: ldo6 { + regulator-name = "pm8350c_l6"; + regulator-min-microvolt = <2960000>; + /* Originally max = 3008000 but SDHCI expects 2960000 */ + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l7: ldo7 { + regulator-name = "pm8350c_l7"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l8: ldo8 { + regulator-name = "pm8350c_l8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l9: ldo9 { + regulator-name = "pm8350c_l9"; + regulator-min-microvolt = <2960000>; + /* Originally max = 3008000 but SDHCI expects 2960000 */ + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l10: ldo10 { + regulator-name = "pm8350c_l10"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l12: ldo12 { + regulator-name = "pm8350c_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1968000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8350c_l13: ldo13 { + regulator-name = "pm8350c_l13"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pm8450-rpmh-regulators { + compatible = "qcom,pm8450-rpmh-regulators"; + qcom,pmic-id = "h"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l2-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_bob>; + vdd-l4-supply = <&vreg_bob>; + + /* + * ARC regulators: + * S2 - ebi.lvl + * S4 - mmcx.lvl + * S6 - mx.lvl + * L1 - lmx.lvl + */ + + pm8450_s3: smps3 { + regulator-name = "pm8450_s3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <600000>; + }; + + pm8450_l2: ldo2 { + regulator-name = "pm8450_l2"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + pm8450_l3: ldo3 { + regulator-name = "pm8450_l3"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pmr735a-rpmh-regulators { + compatible = "qcom,pmr735a-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + + vdd-l1-l2-supply = <&pmr735a_s2>; + vdd-l3-supply = <&pmr735a_s1>; + vdd-l4-supply = <&pm8350c_s1>; + vdd-l5-l6-supply = <&pm8350c_s1>; + vdd-l7-bob-supply = <&vreg_bob>; + + pmr735a_s1: smps1 { + regulator-name = "pmr735a_s1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1296000>; + }; + + pmr735a_s2: smps2 { + regulator-name = "pmr735a_s2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + pmr735a_s3: smps3 { + regulator-name = "pmr735a_s3"; + regulator-min-microvolt = <435000>; + regulator-max-microvolt = <2352000>; + }; + + pmr735a_l1: ldo1 { + regulator-name = "pmr735a_l1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + pmr735a_l2: ldo2 { + regulator-name = "pmr735a_l2"; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <912000>; + }; + + pmr735a_l3: ldo3 { + regulator-name = "pmr735a_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l4: ldo4 { + regulator-name = "pmr735a_l4"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + }; + + pmr735a_l5: ldo5 { + regulator-name = "pmr735a_l5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + pmr735a_l6: ldo6 { + regulator-name = "pmr735a_l6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l7: ldo7 { + regulator-name = "pmr735a_l7"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +/* I2C4 is used, it hosts a Samsung touchscreen, but GPI DMA is broken.. */ + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + /* Dialog SLG51000 CMIC @ 75 */ +}; + +&i2c9 { + clock-frequency = <400000>; + status = "okay"; + + /* NXP SN1X0 NFC @ 28 */ +}; + +&i2c13 { + clock-frequency = <400000>; + status = "okay"; + + /* Richwave RTC6226 FM Radio Receiver @ 64 */ +}; + +&i2c14 { + clock-frequency = <1000000>; + status = "okay"; + + cs35l41_l: speaker-amp@40 { + compatible = "cirrus,cs35l41"; + reg = <0x40>; + interrupt-parent = <&tlmm>; + interrupts = <182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + cirrus,asp-sdout-hiz = <3>; + #sound-dai-cells = <1>; + }; + + cs35l41_r: speaker-amp@41 { + compatible = "cirrus,cs35l41"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + cirrus,asp-sdout-hiz = <3>; + #sound-dai-cells = <1>; + }; +}; + +&i2c15 { + clock-frequency = <400000>; + status = "okay"; + + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&i2c19 { + clock-frequency = <1000000>; + status = "okay"; + + /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ +}; + +&pcie0 { + max-link-speed = <2>; + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&pm8350_l5>; + vdda-pll-supply = <&pm8350_l6>; + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_slpi { + firmware-name = "qcom/slpi.mbn"; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; + vmmc-supply = <&pm8350c_l9>; + vqmmc-supply = <&pm8350c_l6>; + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0x0>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&spi10 { + status = "okay"; + + /* NXP SN1X0 NFC Secure Element @ 0 */ +}; + +&tlmm { + gpio-reserved-ranges = <28 4>; + + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&pm8350_l5>; + vdda18-supply = <&pm8350c_l1>; + vdda33-supply = <&pm8350_l2>; + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&pm8350_l6>; + vdda-pll-supply = <&pm8350_l1>; + status = "okay"; +}; diff --git a/dts/src/arm64/qcom/sm8450.dtsi b/dts/src/arm64/qcom/sm8450.dtsi index 4978c5ba5d..d32f08df74 100644 --- a/dts/src/arm64/qcom/sm8450.dtsi +++ b/dts/src/arm64/qcom/sm8450.dtsi @@ -438,11 +438,6 @@ no-map; }; - camera_mem: memory@85200000 { - reg = <0x0 0x85200000 0x0 0x500000>; - no-map; - }; - video_mem: memory@85700000 { reg = <0x0 0x85700000 0x0 0x700000>; no-map; @@ -505,6 +500,11 @@ no-map; }; + camera_mem: memory@9f500000 { + reg = <0x0 0x9f500000 0x0 0x800000>; + no-map; + }; + rmtfs_mem: memory@9fd00000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0x9fd00000 0x0 0x280000>; @@ -514,6 +514,11 @@ qcom,vmid = <15>; }; + xbl_sc_mem2: memory@a6e00000 { + reg = <0x0 0xa6e00000 0x0 0x40000>; + no-map; + }; + global_sync_mem: memory@a6f00000 { reg = <0x0 0xa6f00000 0x0 0x100000>; no-map; @@ -2379,22 +2384,42 @@ gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie0_default_state: pcie0-default-state { - perst { + perst-pins { pins = "gpio94"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio95"; function = "pcie0_clkreqn"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio96"; function = "gpio"; drive-strength = <2>; @@ -2403,21 +2428,21 @@ }; pcie1_default_state: pcie1-default-state { - perst { + perst-pins { pins = "gpio97"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio98"; function = "pcie1_clkreqn"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio99"; function = "gpio"; drive-strength = <2>; @@ -2425,350 +2450,350 @@ }; }; - qup_i2c0_data_clk: qup-i2c0-data-clk { + qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins = "gpio0", "gpio1"; function = "qup0"; }; - qup_i2c1_data_clk: qup-i2c1-data-clk { + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup1"; }; - qup_i2c2_data_clk: qup-i2c2-data-clk { + qup_i2c2_data_clk: qup-i2c2-data-clk-state { pins = "gpio8", "gpio9"; function = "qup2"; }; - qup_i2c3_data_clk: qup-i2c3-data-clk { + qup_i2c3_data_clk: qup-i2c3-data-clk-state { pins = "gpio12", "gpio13"; function = "qup3"; }; - qup_i2c4_data_clk: qup-i2c4-data-clk { + qup_i2c4_data_clk: qup-i2c4-data-clk-state { pins = "gpio16", "gpio17"; function = "qup4"; }; - qup_i2c5_data_clk: qup-i2c5-data-clk { + qup_i2c5_data_clk: qup-i2c5-data-clk-state { pins = "gpio206", "gpio207"; function = "qup5"; }; - qup_i2c6_data_clk: qup-i2c6-data-clk { + qup_i2c6_data_clk: qup-i2c6-data-clk-state { pins = "gpio20", "gpio21"; function = "qup6"; }; - qup_i2c8_data_clk: qup-i2c8-data-clk { + qup_i2c8_data_clk: qup-i2c8-data-clk-state { pins = "gpio28", "gpio29"; function = "qup8"; }; - qup_i2c9_data_clk: qup-i2c9-data-clk { + qup_i2c9_data_clk: qup-i2c9-data-clk-state { pins = "gpio32", "gpio33"; function = "qup9"; }; - qup_i2c10_data_clk: qup-i2c10-data-clk { + qup_i2c10_data_clk: qup-i2c10-data-clk-state { pins = "gpio36", "gpio37"; function = "qup10"; }; - qup_i2c11_data_clk: qup-i2c11-data-clk { + qup_i2c11_data_clk: qup-i2c11-data-clk-state { pins = "gpio40", "gpio41"; function = "qup11"; }; - qup_i2c12_data_clk: qup-i2c12-data-clk { + qup_i2c12_data_clk: qup-i2c12-data-clk-state { pins = "gpio44", "gpio45"; function = "qup12"; }; - qup_i2c13_data_clk: qup-i2c13-data-clk { + qup_i2c13_data_clk: qup-i2c13-data-clk-state { pins = "gpio48", "gpio49"; function = "qup13"; drive-strength = <2>; bias-pull-up; }; - qup_i2c14_data_clk: qup-i2c14-data-clk { + qup_i2c14_data_clk: qup-i2c14-data-clk-state { pins = "gpio52", "gpio53"; function = "qup14"; drive-strength = <2>; bias-pull-up; }; - qup_i2c15_data_clk: qup-i2c15-data-clk { + qup_i2c15_data_clk: qup-i2c15-data-clk-state { pins = "gpio56", "gpio57"; function = "qup15"; }; - qup_i2c16_data_clk: qup-i2c16-data-clk { + qup_i2c16_data_clk: qup-i2c16-data-clk-state { pins = "gpio60", "gpio61"; function = "qup16"; }; - qup_i2c17_data_clk: qup-i2c17-data-clk { + qup_i2c17_data_clk: qup-i2c17-data-clk-state { pins = "gpio64", "gpio65"; function = "qup17"; }; - qup_i2c18_data_clk: qup-i2c18-data-clk { + qup_i2c18_data_clk: qup-i2c18-data-clk-state { pins = "gpio68", "gpio69"; function = "qup18"; }; - qup_i2c19_data_clk: qup-i2c19-data-clk { + qup_i2c19_data_clk: qup-i2c19-data-clk-state { pins = "gpio72", "gpio73"; function = "qup19"; }; - qup_i2c20_data_clk: qup-i2c20-data-clk { + qup_i2c20_data_clk: qup-i2c20-data-clk-state { pins = "gpio76", "gpio77"; function = "qup20"; }; - qup_i2c21_data_clk: qup-i2c21-data-clk { + qup_i2c21_data_clk: qup-i2c21-data-clk-state { pins = "gpio80", "gpio81"; function = "qup21"; }; - qup_spi0_cs: qup-spi0-cs { + qup_spi0_cs: qup-spi0-cs-state { pins = "gpio3"; function = "qup0"; }; - qup_spi0_data_clk: qup-spi0-data-clk { + qup_spi0_data_clk: qup-spi0-data-clk-state { pins = "gpio0", "gpio1", "gpio2"; function = "qup0"; }; - qup_spi1_cs: qup-spi1-cs { + qup_spi1_cs: qup-spi1-cs-state { pins = "gpio7"; function = "qup1"; }; - qup_spi1_data_clk: qup-spi1-data-clk { + qup_spi1_data_clk: qup-spi1-data-clk-state { pins = "gpio4", "gpio5", "gpio6"; function = "qup1"; }; - qup_spi2_cs: qup-spi2-cs { + qup_spi2_cs: qup-spi2-cs-state { pins = "gpio11"; function = "qup2"; }; - qup_spi2_data_clk: qup-spi2-data-clk { + qup_spi2_data_clk: qup-spi2-data-clk-state { pins = "gpio8", "gpio9", "gpio10"; function = "qup2"; }; - qup_spi3_cs: qup-spi3-cs { + qup_spi3_cs: qup-spi3-cs-state { pins = "gpio15"; function = "qup3"; }; - qup_spi3_data_clk: qup-spi3-data-clk { + qup_spi3_data_clk: qup-spi3-data-clk-state { pins = "gpio12", "gpio13", "gpio14"; function = "qup3"; }; - qup_spi4_cs: qup-spi4-cs { + qup_spi4_cs: qup-spi4-cs-state { pins = "gpio19"; function = "qup4"; drive-strength = <6>; bias-disable; }; - qup_spi4_data_clk: qup-spi4-data-clk { + qup_spi4_data_clk: qup-spi4-data-clk-state { pins = "gpio16", "gpio17", "gpio18"; function = "qup4"; }; - qup_spi5_cs: qup-spi5-cs { + qup_spi5_cs: qup-spi5-cs-state { pins = "gpio85"; function = "qup5"; }; - qup_spi5_data_clk: qup-spi5-data-clk { + qup_spi5_data_clk: qup-spi5-data-clk-state { pins = "gpio206", "gpio207", "gpio84"; function = "qup5"; }; - qup_spi6_cs: qup-spi6-cs { + qup_spi6_cs: qup-spi6-cs-state { pins = "gpio23"; function = "qup6"; }; - qup_spi6_data_clk: qup-spi6-data-clk { + qup_spi6_data_clk: qup-spi6-data-clk-state { pins = "gpio20", "gpio21", "gpio22"; function = "qup6"; }; - qup_spi8_cs: qup-spi8-cs { + qup_spi8_cs: qup-spi8-cs-state { pins = "gpio31"; function = "qup8"; }; - qup_spi8_data_clk: qup-spi8-data-clk { + qup_spi8_data_clk: qup-spi8-data-clk-state { pins = "gpio28", "gpio29", "gpio30"; function = "qup8"; }; - qup_spi9_cs: qup-spi9-cs { + qup_spi9_cs: qup-spi9-cs-state { pins = "gpio35"; function = "qup9"; }; - qup_spi9_data_clk: qup-spi9-data-clk { + qup_spi9_data_clk: qup-spi9-data-clk-state { pins = "gpio32", "gpio33", "gpio34"; function = "qup9"; }; - qup_spi10_cs: qup-spi10-cs { + qup_spi10_cs: qup-spi10-cs-state { pins = "gpio39"; function = "qup10"; }; - qup_spi10_data_clk: qup-spi10-data-clk { + qup_spi10_data_clk: qup-spi10-data-clk-state { pins = "gpio36", "gpio37", "gpio38"; function = "qup10"; }; - qup_spi11_cs: qup-spi11-cs { + qup_spi11_cs: qup-spi11-cs-state { pins = "gpio43"; function = "qup11"; }; - qup_spi11_data_clk: qup-spi11-data-clk { + qup_spi11_data_clk: qup-spi11-data-clk-state { pins = "gpio40", "gpio41", "gpio42"; function = "qup11"; }; - qup_spi12_cs: qup-spi12-cs { + qup_spi12_cs: qup-spi12-cs-state { pins = "gpio47"; function = "qup12"; }; - qup_spi12_data_clk: qup-spi12-data-clk { + qup_spi12_data_clk: qup-spi12-data-clk-state { pins = "gpio44", "gpio45", "gpio46"; function = "qup12"; }; - qup_spi13_cs: qup-spi13-cs { + qup_spi13_cs: qup-spi13-cs-state { pins = "gpio51"; function = "qup13"; }; - qup_spi13_data_clk: qup-spi13-data-clk { + qup_spi13_data_clk: qup-spi13-data-clk-state { pins = "gpio48", "gpio49", "gpio50"; function = "qup13"; }; - qup_spi14_cs: qup-spi14-cs { + qup_spi14_cs: qup-spi14-cs-state { pins = "gpio55"; function = "qup14"; }; - qup_spi14_data_clk: qup-spi14-data-clk { + qup_spi14_data_clk: qup-spi14-data-clk-state { pins = "gpio52", "gpio53", "gpio54"; function = "qup14"; }; - qup_spi15_cs: qup-spi15-cs { + qup_spi15_cs: qup-spi15-cs-state { pins = "gpio59"; function = "qup15"; }; - qup_spi15_data_clk: qup-spi15-data-clk { + qup_spi15_data_clk: qup-spi15-data-clk-state { pins = "gpio56", "gpio57", "gpio58"; function = "qup15"; }; - qup_spi16_cs: qup-spi16-cs { + qup_spi16_cs: qup-spi16-cs-state { pins = "gpio63"; function = "qup16"; }; - qup_spi16_data_clk: qup-spi16-data-clk { + qup_spi16_data_clk: qup-spi16-data-clk-state { pins = "gpio60", "gpio61", "gpio62"; function = "qup16"; }; - qup_spi17_cs: qup-spi17-cs { + qup_spi17_cs: qup-spi17-cs-state { pins = "gpio67"; function = "qup17"; }; - qup_spi17_data_clk: qup-spi17-data-clk { + qup_spi17_data_clk: qup-spi17-data-clk-state { pins = "gpio64", "gpio65", "gpio66"; function = "qup17"; }; - qup_spi18_cs: qup-spi18-cs { + qup_spi18_cs: qup-spi18-cs-state { pins = "gpio71"; function = "qup18"; drive-strength = <6>; bias-disable; }; - qup_spi18_data_clk: qup-spi18-data-clk { + qup_spi18_data_clk: qup-spi18-data-clk-state { pins = "gpio68", "gpio69", "gpio70"; function = "qup18"; drive-strength = <6>; bias-disable; }; - qup_spi19_cs: qup-spi19-cs { + qup_spi19_cs: qup-spi19-cs-state { pins = "gpio75"; function = "qup19"; drive-strength = <6>; bias-disable; }; - qup_spi19_data_clk: qup-spi19-data-clk { + qup_spi19_data_clk: qup-spi19-data-clk-state { pins = "gpio72", "gpio73", "gpio74"; function = "qup19"; drive-strength = <6>; bias-disable; }; - qup_spi20_cs: qup-spi20-cs { + qup_spi20_cs: qup-spi20-cs-state { pins = "gpio79"; function = "qup20"; }; - qup_spi20_data_clk: qup-spi20-data-clk { + qup_spi20_data_clk: qup-spi20-data-clk-state { pins = "gpio76", "gpio77", "gpio78"; function = "qup20"; }; - qup_spi21_cs: qup-spi21-cs { + qup_spi21_cs: qup-spi21-cs-state { pins = "gpio83"; function = "qup21"; }; - qup_spi21_data_clk: qup-spi21-data-clk { + qup_spi21_data_clk: qup-spi21-data-clk-state { pins = "gpio80", "gpio81", "gpio82"; function = "qup21"; }; - qup_uart7_rx: qup-uart7-rx { + qup_uart7_rx: qup-uart7-rx-state { pins = "gpio26"; function = "qup7"; drive-strength = <2>; bias-disable; }; - qup_uart7_tx: qup-uart7-tx { + qup_uart7_tx: qup-uart7-tx-state { pins = "gpio27"; function = "qup7"; drive-strength = <2>; bias-disable; }; - qup_uart20_default: qup-uart20-default { + qup_uart20_default: qup-uart20-default-state { pins = "gpio76", "gpio77", "gpio78", "gpio79"; function = "qup20"; }; @@ -3069,7 +3094,9 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; + reg = <0 0x01d84000 0 0x3000>, + <0 0x01d88000 0 0x8000>; + reg-names = "std", "ice"; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -3093,7 +3120,8 @@ "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; + "rx_lane1_sync_clk", + "ice_core_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -3102,7 +3130,8 @@ <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; freq-table-hz = <75000000 300000000>, <0 0>, @@ -3111,13 +3140,14 @@ <75000000 300000000>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>; status = "disabled"; }; ufs_mem_phy: phy@1d87000 { compatible = "qcom,sm8450-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0xe10>; + reg = <0 0x01d87000 0 0x1c4>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -3140,6 +3170,45 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + iommus = <&apps_smmu 0x4a0 0x0>; + power-domains = <&rpmhpd SM8450_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; |