diff options
Diffstat (limited to 'dts/src/arm64/renesas/r8a774c0.dtsi')
| -rw-r--r-- | dts/src/arm64/renesas/r8a774c0.dtsi | 44 |
1 files changed, 36 insertions, 8 deletions
diff --git a/dts/src/arm64/renesas/r8a774c0.dtsi b/dts/src/arm64/renesas/r8a774c0.dtsi index 1ea684af99..3f86db199d 100644 --- a/dts/src/arm64/renesas/r8a774c0.dtsi +++ b/dts/src/arm64/renesas/r8a774c0.dtsi @@ -76,7 +76,7 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -87,7 +87,7 @@ power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -969,8 +969,10 @@ "renesas,rcar-gen3-can"; reg = <0 0xe6c30000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 916>, <&can_clk>; - clock-names = "clkp1", "can_clk"; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774C0_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 916>; status = "disabled"; @@ -981,13 +983,40 @@ "renesas,rcar-gen3-can"; reg = <0 0xe6c38000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 915>, <&can_clk>; - clock-names = "clkp1", "can_clk"; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774C0_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 915>; status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a774c0-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774C0_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; @@ -1740,8 +1769,7 @@ }; csi40: csi2@feaa0000 { - compatible = "renesas,r8a774c0-csi2", - "renesas,rcar-gen3-csi2"; + compatible = "renesas,r8a774c0-csi2"; reg = <0 0xfeaa0000 0 0x10000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 716>; |