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Diffstat (limited to 'dts/src/arm64/renesas/r8a77961.dtsi')
-rw-r--r--dts/src/arm64/renesas/r8a77961.dtsi47
1 files changed, 43 insertions, 4 deletions
diff --git a/dts/src/arm64/renesas/r8a77961.dtsi b/dts/src/arm64/renesas/r8a77961.dtsi
index 68cbbb322a..3c744b7d0d 100644
--- a/dts/src/arm64/renesas/r8a77961.dtsi
+++ b/dts/src/arm64/renesas/r8a77961.dtsi
@@ -323,6 +323,7 @@
compatible = "renesas,r8a77961-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 402>;
@@ -1222,6 +1223,32 @@
status = "disabled";
};
+ canfd: can@e66c0000 {
+ compatible = "renesas,r8a77961-canfd",
+ "renesas,rcar-gen3-canfd";
+ reg = <0 0xe66c0000 0 0x8000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch_int", "g_int";
+ clocks = <&cpg CPG_MOD 914>,
+ <&cpg CPG_CORE R8A77961_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
+ resets = <&cpg 914>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+ };
+
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
@@ -2375,6 +2402,22 @@
status = "disabled";
};
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a77961-rpc-if",
+ "renesas,rcar-gen3-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x04000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -2722,8 +2765,6 @@
port@0 {
reg = <0>;
- du_out_rgb: endpoint {
- };
};
port@1 {
reg = <1>;
@@ -2760,8 +2801,6 @@
};
port@1 {
reg = <1>;
- lvds0_out: endpoint {
- };
};
};
};