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Diffstat (limited to 'dts/src/arm64/renesas/r9a09g011.dtsi')
-rw-r--r--dts/src/arm64/renesas/r9a09g011.dtsi238
1 files changed, 235 insertions, 3 deletions
diff --git a/dts/src/arm64/renesas/r9a09g011.dtsi b/dts/src/arm64/renesas/r9a09g011.dtsi
index d4cc5459fb..50ed66d42a 100644
--- a/dts/src/arm64/renesas/r9a09g011.dtsi
+++ b/dts/src/arm64/renesas/r9a09g011.dtsi
@@ -37,8 +37,15 @@
compatible = "arm,cortex-a53";
reg = <0>;
device_type = "cpu";
+ next-level-cache = <&L2_CA53>;
clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
};
+
+ L2_CA53: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
};
soc: soc {
@@ -48,7 +55,7 @@
#size-cells = <2>;
ranges;
- gic: interrupt-controller@82000000 {
+ gic: interrupt-controller@82010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
@@ -62,8 +69,101 @@
clock-names = "clk";
};
+ sdhi0: mmc@85000000 {
+ compatible = "renesas,sdhi-r9a09g011",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x85000000 0 0x2000>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
+ <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
+ <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
+ <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A09G011_SDI0_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sdhi1: mmc@85010000 {
+ compatible = "renesas,sdhi-r9a09g011",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x85010000 0 0x2000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
+ <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>,
+ <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>,
+ <&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A09G011_SDI1_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ emmc: mmc@85020000 {
+ compatible = "renesas,sdhi-r9a09g011",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0x0 0x85020000 0 0x2000>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>,
+ <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>,
+ <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>,
+ <&cpg CPG_MOD R9A09G011_EMM_ACLK>;
+ clock-names = "core", "clkh", "cd", "aclk";
+ resets = <&cpg R9A09G011_EMM_IXRST>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb3drd: usb3drd@85070400 {
+ compatible = "renesas,r9a09g011-usb3drd",
+ "renesas,rzv2m-usb3drd";
+ reg = <0x0 0x85070400 0x0 0x100>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "drd", "bc", "gpi";
+ clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
+ <&cpg CPG_MOD R9A09G011_USB_PCLK>;
+ clock-names = "axi", "reg";
+ resets = <&cpg R9A09G011_USB_DRD_RESET>;
+ power-domains = <&cpg>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ usb3host: usb@85060000 {
+ compatible = "renesas,r9a09g011-xhci",
+ "renesas,rzv2m-xhci";
+ reg = <0 0x85060000 0 0x2000>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
+ <&cpg CPG_MOD R9A09G011_USB_PCLK>;
+ clock-names = "axi", "reg";
+ resets = <&cpg R9A09G011_USB_ARESETN_H>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb3peri: usb3peri@85070000 {
+ compatible = "renesas,r9a09g011-usb3-peri",
+ "renesas,rzv2m-usb3-peri";
+ reg = <0x0 0x85070000 0x0 0x400>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
+ <&cpg CPG_MOD R9A09G011_USB_PCLK>;
+ clock-names = "axi", "reg";
+ resets = <&cpg R9A09G011_USB_ARESETN_P>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+ };
+
avb: ethernet@a3300000 {
- compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
+ compatible = "renesas,etheravb-r9a09g011", "renesas,etheravb-rzv2m";
reg = <0 0xa3300000 0 0x800>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
@@ -110,7 +210,7 @@
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disable";
+ status = "disabled";
};
cpg: clock-controller@a3500000 {
@@ -123,6 +223,75 @@
#power-domain-cells = <0>;
};
+ pwc: pwc@a3700000 {
+ compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc";
+ reg = <0 0xa3700000 0 0x800>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ sys: system-controller@a3f03000 {
+ compatible = "renesas,r9a09g011-sys";
+ reg = <0 0xa3f03000 0 0x400>;
+ };
+
+ csi0: spi@a4020000 {
+ compatible = "renesas,rzv2m-csi";
+ reg = <0 0xa4020000 0 0x80>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>,
+ <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>;
+ clock-names = "csiclk", "pclk";
+ resets = <&cpg R9A09G011_CSI_GPG_PRESETN>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ csi4: spi@a4020200 {
+ compatible = "renesas,rzv2m-csi";
+ reg = <0 0xa4020200 0 0x80>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
+ <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
+ clock-names = "csiclk", "pclk";
+ resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@a4030000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
+ reg = <0 0xa4030000 0 0x80>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tia", "tis";
+ clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
+ resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@a4030100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
+ reg = <0 0xa4030100 0 0x80>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tia", "tis";
+ clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>;
+ resets = <&cpg R9A09G011_IIC_GPB_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
uart0: serial@a4040000 {
compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
reg = <0 0xa4040000 0 0x80>;
@@ -132,6 +301,69 @@
clock-names = "sclk", "pclk";
status = "disabled";
};
+
+ wdt0: watchdog@a4050000 {
+ compatible = "renesas,r9a09g011-wdt",
+ "renesas,rzv2m-wdt";
+ reg = <0 0xa4050000 0 0x80>;
+ clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>,
+ <&cpg CPG_MOD R9A09G011_WDT0_CLK>;
+ clock-names = "pclk", "oscclk";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cpg R9A09G011_WDT0_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@b6250000 {
+ compatible = "renesas,r9a09g011-pinctrl";
+ reg = <0 0xb6250000 0 0x800>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 352>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A09G011_PFC_PRESETN>;
+ };
};
timer {