diff options
Diffstat (limited to 'dts/src/arm64/renesas')
120 files changed, 12714 insertions, 1836 deletions
diff --git a/dts/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi b/dts/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi index 7ce986f0a0..7cb5c958ae 100644 --- a/dts/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi +++ b/dts/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi @@ -65,7 +65,6 @@ ov5645: ov5645@3c { compatible = "ovti,ov5645"; reg = <0x3c>; - clock-names = "xclk"; clocks = <&osc25250_clk>; clock-frequency = <24000000>; vdddo-supply = <&ov5645_vdddo_1v8>; diff --git a/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi b/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi index 5ad6cd1864..5a14f116f7 100644 --- a/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi +++ b/dts/src/arm64/renesas/beacon-renesom-baseboard.dtsi @@ -5,7 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/clk/versaclock.h> +#include <dt-bindings/clock/versaclock.h> / { backlight_lvds: backlight-lvds { @@ -146,7 +146,7 @@ }; }; - reg_audio: regulator_audio { + reg_audio: regulator-audio { compatible = "regulator-fixed"; regulator-name = "audio-1.8V"; regulator-min-microvolt = <1800000>; @@ -174,7 +174,7 @@ vin-supply = <®_lcd>; }; - reg_cam0: regulator_camera { + reg_cam0: regulator-cam0 { compatible = "regulator-fixed"; regulator-name = "reg_cam0"; regulator-min-microvolt = <1800000>; @@ -183,7 +183,7 @@ enable-active-high; }; - reg_cam1: regulator_camera { + reg_cam1: regulator-cam1 { compatible = "regulator-fixed"; regulator-name = "reg_cam1"; regulator-min-microvolt = <1800000>; @@ -272,8 +272,14 @@ status = "okay"; }; -&du_out_rgb { - remote-endpoint = <&rgb_panel>; +&du { + ports { + port@0 { + du_out_rgb: endpoint { + remote-endpoint = <&rgb_panel>; + }; + }; + }; }; &ehci0 { @@ -361,7 +367,7 @@ assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>, <&versaclock6_bb 3>, <&versaclock6_bb 4>; - assigned-clock-rates = <24000000>, <24000000>, <24000000>, + assigned-clock-rates = <24000000>, <24000000>, <24576000>, <24576000>; OUT1 { @@ -431,20 +437,6 @@ }; }; - /* 0 - lcd_reset */ - /* 1 - lcd_pwr */ - /* 2 - lcd_select */ - /* 3 - backlight-enable */ - /* 4 - Touch_shdwn */ - /* 5 - LCD_H_pol */ - /* 6 - lcd_V_pol */ - gpio_exp1: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - touchscreen@26 { compatible = "ilitek,ili2117"; reg = <0x26>; @@ -476,6 +468,16 @@ }; }; }; + + gpio_exp1: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "lcd_reset", "lcd_pwr", "lcd_select", + "backlight-enable", "Touch_shdwn", + "LCD_H_pol", "lcd_V_pol"; + }; }; &lvds0 { @@ -632,6 +634,25 @@ #clock-cells = <1>; clock-frequency = <11289600>; + /* Reference versaclock instead of audio_clk_a */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&versaclock6_bb 4>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_MOD 922>; + status = "okay"; ports { diff --git a/dts/src/arm64/renesas/beacon-renesom-som.dtsi b/dts/src/arm64/renesas/beacon-renesom-som.dtsi index 877d076ffc..68b04e56ae 100644 --- a/dts/src/arm64/renesas/beacon-renesom-som.dtsi +++ b/dts/src/arm64/renesas/beacon-renesom-som.dtsi @@ -4,7 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clk/versaclock.h> +#include <dt-bindings/clock/versaclock.h> / { memory@48000000 { @@ -20,7 +20,7 @@ clock-output-names = "osc_32k"; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -29,7 +29,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -59,7 +59,7 @@ status = "okay"; phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id004d.d074", + compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <0>; interrupt-parent = <&gpio2>; diff --git a/dts/src/arm64/renesas/condor-common.dtsi b/dts/src/arm64/renesas/condor-common.dtsi new file mode 100644 index 0000000000..7c34d14dcd --- /dev/null +++ b/dts/src/arm64/renesas/condor-common.dtsi @@ -0,0 +1,549 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Condor board with R-Car V3H + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &scif0; + ethernet0 = &gether; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; + + d1_8v: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "D1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + d3_3v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + vcc-supply = <&d3_3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0 0x48000000 0 0x78000000>; + }; + + vddq_vin01: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VDDQ_VIN01"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + x1_clk: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; +}; + +&canfd { + pinctrl-0 = <&canfd0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out0>; + }; + }; + }; +}; + +&csi41 { + status = "okay"; + + ports { + port@0 { + csi41_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out1>; + }; + }; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&x1_clk>; + clock-names = "du.0", "dclkin.0"; + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&gether { + pinctrl-0 = <&gether_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + renesas,no-ether-link; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander0: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + io_expander1: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + avdd-supply = <&d1_8v>; + dvdd-supply = <&d1_8v>; + pvdd-supply = <&d1_8v>; + bgvdd-supply = <&d1_8v>; + dvdd-3v-supply = <&d3_3v>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gmsl0: gmsl-deserializer@48 { + compatible = "maxim,max9286"; + reg = <0x48>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out0: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; + + gmsl1: gmsl-deserializer@4a { + compatible = "maxim,max9286"; + reg = <0x4a>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out1: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi41_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&d3_3v>; + vqmmc-supply = <&vddq_vin01>; + mmc-hs200-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&pciec { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pcie_phy { + status = "okay"; +}; + +&pfc { + canfd0_pins: canfd0 { + groups = "canfd0_data_a"; + function = "canfd0"; + }; + + gether_pins: gether { + groups = "gether_mdio_a", "gether_rgmii", + "gether_txcrefclk", "gether_txcrefclk_mega"; + function = "gether"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + cr7@40000 { + reg = <0x00040000 0x080000>; + read-only; + }; + cert_header_sa3@c0000 { + reg = <0x000c0000 0x080000>; + read-only; + }; + bl2@140000 { + reg = <0x00140000 0x040000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x460000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x0c0000>; + read-only; + }; + uboot-env@700000 { + reg = <0x00700000 0x040000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; diff --git a/dts/src/arm64/renesas/draak-ebisu-panel-aa104xd12.dtso b/dts/src/arm64/renesas/draak-ebisu-panel-aa104xd12.dtso new file mode 100644 index 0000000000..258f8668ca --- /dev/null +++ b/dts/src/arm64/renesas/draak-ebisu-panel-aa104xd12.dtso @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree overlay for the AA104XD12 panel connected to LVDS1 on a Draak or + * Ebisu board + * + * Copyright 2021 Ideas on Board Oy + */ + +/dts-v1/; +/plugin/; + +&{/} { +#include "panel-aa104xd12.dtsi" +}; + +&{/panel} { + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; +}; + +&lvds1 { + status = "okay"; + + ports { + port@1 { + lvds1_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/draak.dtsi b/dts/src/arm64/renesas/draak.dtsi index eb0327c0df..6f133f54de 100644 --- a/dts/src/arm64/renesas/draak.dtsi +++ b/dts/src/arm64/renesas/draak.dtsi @@ -285,7 +285,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&adv7123_in>; }; }; @@ -356,12 +356,9 @@ * CVBS and HDMI inputs through SW[49-53] * switches. * - * CVBS is the default selection, link it to - * VIN4 here. + * HDMI is the default selection, leave CVBS + * not connected here. */ - adv7180_out: endpoint { - remote-endpoint = <&vin4_in>; - }; }; }; @@ -374,6 +371,12 @@ interrupt-parent = <&gpio1>; interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + dvdd-3v-supply = <®_3p3v>; + bgvdd-supply = <®_1p8v>; + adi,input-depth = <8>; adi,input-colorspace = "rgb"; adi,input-clock = "1x"; @@ -423,13 +426,11 @@ * CVBS and HDMI inputs through SW[49-53] * switches. * - * CVBS is the default selection, leave HDMI - * not connected here. + * HDMI is the default selection, link it to + * VIN4 here. */ adv7612_out: endpoint { - pclk-sample = <0>; - hsync-active = <0>; - vsync-active = <0>; + remote-endpoint = <&vin4_in>; }; }; }; @@ -541,6 +542,12 @@ function = "pwm1"; }; + rpc_pins: rpc { + groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", + "rpc_int"; + function = "rpc"; + }; + scif2_pins: scif2 { groups = "scif2_data"; function = "scif2"; @@ -574,8 +581,8 @@ function = "usb0"; }; - vin4_pins_cvbs: vin4 { - groups = "vin4_data8", "vin4_sync", "vin4_clk"; + vin4_pins: vin4 { + groups = "vin4_data24", "vin4_sync", "vin4_clk"; function = "vin4"; }; }; @@ -624,7 +631,59 @@ bitclock-master = <&rsnd_for_ak4613>; frame-master = <&rsnd_for_ak4613>; playback = <&ssi3>, <&src5>, <&dvc0>; - capture = <&ssi4>, <&src6>, <&dvc1>; + capture = <&ssi4>, <&src6>, <&dvc1>; + }; + }; + }; +}; + +&rpc { + pinctrl-0 = <&rpc_pins>; + pinctrl-names = "default"; + + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; }; }; }; @@ -671,7 +730,7 @@ }; &vin4 { - pinctrl-0 = <&vin4_pins_cvbs>; + pinctrl-0 = <&vin4_pins>; pinctrl-names = "default"; status = "okay"; @@ -679,7 +738,10 @@ ports { port { vin4_in: endpoint { - remote-endpoint = <&adv7180_out>; + pclk-sample = <0>; + hsync-active = <0>; + vsync-active = <0>; + remote-endpoint = <&adv7612_out>; }; }; }; diff --git a/dts/src/arm64/renesas/ebisu.dtsi b/dts/src/arm64/renesas/ebisu.dtsi index 67231c8576..cba2fde9dd 100644 --- a/dts/src/arm64/renesas/ebisu.dtsi +++ b/dts/src/arm64/renesas/ebisu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the Ebisu board + * Device Tree Source for the Ebisu/Ebisu-4D board * * Copyright (C) 2018 Renesas Electronics Corp. */ @@ -13,6 +13,14 @@ compatible = "renesas,ebisu"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; serial0 = &scif2; ethernet0 = &avb; mmc0 = &sdhi3; @@ -145,7 +153,7 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -154,7 +162,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -163,7 +171,7 @@ regulator-always-on; }; - reg_12p0v: regulator2 { + reg_12p0v: regulator-12p0v { compatible = "regulator-fixed"; regulator-name = "D12.0V"; regulator-min-microvolt = <12000000>; @@ -356,7 +364,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&adv7123_in>; }; }; @@ -395,6 +403,12 @@ interrupt-parent = <&gpio1>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + dvdd-3v-supply = <®_3p3v>; + bgvdd-supply = <®_1p8v>; + adi,input-depth = <8>; adi,input-colorspace = "rgb"; adi,input-clock = "1x"; @@ -600,6 +614,12 @@ function = "pwm5"; }; + rpc_pins: rpc { + groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", + "rpc_int"; + function = "rpc"; + }; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; @@ -705,12 +725,64 @@ rcar_sound,dai { dai0 { playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; + capture = <&ssi1>, <&src1>, <&dvc1>; }; }; }; +&rpc { + pinctrl-0 = <&rpc_pins>; + pinctrl-names = "default"; + + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; diff --git a/dts/src/arm64/renesas/gmsl-cameras.dtsi b/dts/src/arm64/renesas/gmsl-cameras.dtsi index d45f072f8c..e0930d1ba3 100644 --- a/dts/src/arm64/renesas/gmsl-cameras.dtsi +++ b/dts/src/arm64/renesas/gmsl-cameras.dtsi @@ -100,7 +100,7 @@ #ifdef GMSL_CAMERA_1 port@1 { - max9286_in1: endpoint{ + max9286_in1: endpoint { remote-endpoint = <&fakra_con1>; }; @@ -233,7 +233,7 @@ #ifdef GMSL_CAMERA_5 port@1 { - max9286_in5: endpoint{ + max9286_in5: endpoint { remote-endpoint = <&fakra_con5>; }; diff --git a/dts/src/arm64/renesas/hihope-common.dtsi b/dts/src/arm64/renesas/hihope-common.dtsi index 935d06515a..83104af281 100644 --- a/dts/src/arm64/renesas/hihope-common.dtsi +++ b/dts/src/arm64/renesas/hihope-common.dtsi @@ -10,6 +10,14 @@ / { aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &iic_pmic; serial0 = &scif2; serial1 = &hscif0; mmc0 = &sdhi3; @@ -53,7 +61,7 @@ }; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -62,7 +70,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/renesas/hihope-rev4.dtsi b/dts/src/arm64/renesas/hihope-rev4.dtsi index 7fc0339a3a..66f3affe04 100644 --- a/dts/src/arm64/renesas/hihope-rev4.dtsi +++ b/dts/src/arm64/renesas/hihope-rev4.dtsi @@ -112,7 +112,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + <&cpg CPG_MOD 922>; rsnd_port: port { rsnd_endpoint: endpoint { diff --git a/dts/src/arm64/renesas/panel-aa104xd12.dtsi b/dts/src/arm64/renesas/panel-aa104xd12.dtsi new file mode 100644 index 0000000000..4b1f0982b9 --- /dev/null +++ b/dts/src/arm64/renesas/panel-aa104xd12.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common file for the AA104XD12 panel connected to Renesas R-Car Gen3 boards. + * + * Copyright (C) 2014 Renesas Electronics Corp. + */ + +panel { + compatible = "mitsubishi,aa104xd12", "panel-lvds"; + + width-mm = <210>; + height-mm = <158>; + data-mapping = "jeida-18"; + + panel-timing { + /* 1024x768 @65Hz */ + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hsync-len = <136>; + hfront-porch = <20>; + hback-porch = <160>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + }; + + port { + }; +}; diff --git a/dts/src/arm64/renesas/r8a774a1-beacon-rzg2m-kit.dts b/dts/src/arm64/renesas/r8a774a1-beacon-rzg2m-kit.dts index 3cf2e07694..24da6ee6ec 100644 --- a/dts/src/arm64/renesas/r8a774a1-beacon-rzg2m-kit.dts +++ b/dts/src/arm64/renesas/r8a774a1-beacon-rzg2m-kit.dts @@ -14,6 +14,14 @@ compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &iic_pmic; serial0 = &scif2; serial1 = &hscif0; serial2 = &hscif1; @@ -50,24 +58,3 @@ clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1", "dclkin.2"; }; - -/* Reference versaclock instead of audio_clk_a */ -&rcar_sound { - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&versaclock6_bb 4>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; -}; diff --git a/dts/src/arm64/renesas/r8a774a1.dtsi b/dts/src/arm64/renesas/r8a774a1.dtsi index 12846125a4..95b0a1f6de 100644 --- a/dts/src/arm64/renesas/r8a774a1.dtsi +++ b/dts/src/arm64/renesas/r8a774a1.dtsi @@ -10,24 +10,11 @@ #include <dt-bindings/clock/r8a774a1-cpg-mssr.h> #include <dt-bindings/power/r8a774a1-sysc.h> -#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 - / { compatible = "renesas,r8a774a1"; #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &iic_pmic; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. @@ -283,6 +270,7 @@ compatible = "renesas,r8a774a1-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1178,6 +1166,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774A1_CLK_CANFD>, <&can_clk>; @@ -1687,7 +1676,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1722,7 +1711,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -2332,7 +2321,6 @@ reg-names = "regs", "dirmap", "wbuf"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; @@ -2369,8 +2357,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -2381,6 +2369,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2396,8 +2386,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; @@ -2408,6 +2398,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2737,8 +2729,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; @@ -2775,8 +2765,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a774b1-beacon-rzg2n-kit.dts b/dts/src/arm64/renesas/r8a774b1-beacon-rzg2n-kit.dts index 89d708346b..8b9df6afff 100644 --- a/dts/src/arm64/renesas/r8a774b1-beacon-rzg2n-kit.dts +++ b/dts/src/arm64/renesas/r8a774b1-beacon-rzg2n-kit.dts @@ -14,6 +14,14 @@ compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &iic_pmic; serial0 = &scif2; serial1 = &hscif0; serial2 = &hscif1; @@ -46,24 +54,3 @@ clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; - -/* Reference versaclock instead of audio_clk_a */ -&rcar_sound { - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&versaclock6_bb 4>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774B1_CLK_S0D4>; -}; diff --git a/dts/src/arm64/renesas/r8a774b1.dtsi b/dts/src/arm64/renesas/r8a774b1.dtsi index a4b406a346..786660fcde 100644 --- a/dts/src/arm64/renesas/r8a774b1.dtsi +++ b/dts/src/arm64/renesas/r8a774b1.dtsi @@ -10,8 +10,6 @@ #include <dt-bindings/clock/r8a774b1-cpg-mssr.h> #include <dt-bindings/power/r8a774b1-sysc.h> -#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4 - / { compatible = "renesas,r8a774b1"; #address-cells = <2>; @@ -156,6 +154,7 @@ compatible = "renesas,r8a774b1-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1051,6 +1050,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774B1_CLK_CANFD>, <&can_clk>; @@ -1560,7 +1560,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1595,7 +1595,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774B1_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -2189,7 +2189,6 @@ reg-names = "regs", "dirmap", "wbuf"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; @@ -2237,8 +2236,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -2249,6 +2248,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2264,8 +2265,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; @@ -2276,6 +2277,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2582,8 +2585,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; @@ -2620,8 +2621,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a774c0-cat874.dts b/dts/src/arm64/renesas/r8a774c0-cat874.dts index 4e72e4f2ba..5a6ea08ffd 100644 --- a/dts/src/arm64/renesas/r8a774c0-cat874.dts +++ b/dts/src/arm64/renesas/r8a774c0-cat874.dts @@ -172,7 +172,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&tda19988_in>; }; }; diff --git a/dts/src/arm64/renesas/r8a774c0.dtsi b/dts/src/arm64/renesas/r8a774c0.dtsi index e123c8d1ba..eed94ffed7 100644 --- a/dts/src/arm64/renesas/r8a774c0.dtsi +++ b/dts/src/arm64/renesas/r8a774c0.dtsi @@ -49,17 +49,14 @@ opp-shared; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; opp-suspend; }; @@ -145,6 +142,7 @@ compatible = "renesas,r8a774c0-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1008,6 +1006,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774C0_CLK_CANFD>, <&can_clk>; @@ -1279,7 +1278,7 @@ vin4csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin4>; + remote-endpoint = <&csi40vin4>; }; }; }; @@ -1307,7 +1306,7 @@ vin5csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin5>; + remote-endpoint = <&csi40vin5>; }; }; }; @@ -1315,7 +1314,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1351,7 +1350,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774C0_CLK_ZA2>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -1669,7 +1668,6 @@ reg-names = "regs", "dirmap", "wbuf"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; @@ -1706,8 +1704,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -1718,6 +1716,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -1870,8 +1870,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { @@ -1913,8 +1911,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -1940,8 +1936,6 @@ port@1 { reg = <1>; - lvds1_out: endpoint { - }; }; }; }; @@ -1956,7 +1950,7 @@ cpu-thermal { polling-delay-passive = <250>; polling-delay = <0>; - thermal-sensors = <&thermal 0>; + thermal-sensors = <&thermal>; sustainable-power = <717>; cooling-maps { diff --git a/dts/src/arm64/renesas/r8a774e1-beacon-rzg2h-kit.dts b/dts/src/arm64/renesas/r8a774e1-beacon-rzg2h-kit.dts index 3e9ced3b2d..146f78cb6f 100644 --- a/dts/src/arm64/renesas/r8a774e1-beacon-rzg2h-kit.dts +++ b/dts/src/arm64/renesas/r8a774e1-beacon-rzg2h-kit.dts @@ -14,6 +14,14 @@ compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &iic_pmic; serial0 = &scif2; serial1 = &hscif0; serial2 = &hscif1; @@ -51,24 +59,3 @@ clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; - -/* Reference versaclock instead of audio_clk_a */ -&rcar_sound { - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&versaclock6_bb 4>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774E1_CLK_S0D4>; -}; diff --git a/dts/src/arm64/renesas/r8a774e1.dtsi b/dts/src/arm64/renesas/r8a774e1.dtsi index 989c1c00dc..175e5d296d 100644 --- a/dts/src/arm64/renesas/r8a774e1.dtsi +++ b/dts/src/arm64/renesas/r8a774e1.dtsi @@ -10,8 +10,6 @@ #include <dt-bindings/clock/r8a774e1-cpg-mssr.h> #include <dt-bindings/power/r8a774e1-sysc.h> -#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 - / { compatible = "renesas,r8a774e1"; #address-cells = <2>; @@ -769,7 +767,7 @@ status = "disabled"; }; - i2c_dvfs: i2c@e60b0000 { + iic_pmic: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a774e1", @@ -1280,6 +1278,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774E1_CLK_CANFD>, <&can_clk>; @@ -1773,7 +1772,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1808,7 +1807,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774E1_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -2422,7 +2421,6 @@ reg-names = "regs", "dirmap", "wbuf"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; @@ -2471,8 +2469,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -2483,6 +2481,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2498,8 +2498,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; @@ -2510,6 +2510,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2857,8 +2859,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; @@ -2895,8 +2895,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a77950-salvator-x.dts b/dts/src/arm64/renesas/r8a77950-salvator-x.dts deleted file mode 100644 index c6ca61a8ed..0000000000 --- a/dts/src/arm64/renesas/r8a77950-salvator-x.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77950"; - compatible = "renesas,salvator-x", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&x22_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; diff --git a/dts/src/arm64/renesas/r8a77950-ulcb-kf.dts b/dts/src/arm64/renesas/r8a77950-ulcb-kf.dts deleted file mode 100644 index 85f008ef63..0000000000 --- a/dts/src/arm64/renesas/r8a77950-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB Kingfisher board with R-Car H3 ES1.x - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include "r8a77950-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas H3ULCB Kingfisher board based on r8a77950"; - compatible = "shimafuji,kingfisher", "renesas,h3ulcb", - "renesas,r8a7795"; -}; diff --git a/dts/src/arm64/renesas/r8a77950-ulcb.dts b/dts/src/arm64/renesas/r8a77950-ulcb.dts deleted file mode 100644 index 5340579931..0000000000 --- a/dts/src/arm64/renesas/r8a77950-ulcb.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES1.x - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas H3ULCB board based on r8a77950"; - compatible = "renesas,h3ulcb", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; diff --git a/dts/src/arm64/renesas/r8a77950.dtsi b/dts/src/arm64/renesas/r8a77950.dtsi deleted file mode 100644 index 57eb88177e..0000000000 --- a/dts/src/arm64/renesas/r8a77950.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H3 (R8A77950) SoC - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#include "r8a77951.dtsi" - -#undef SOC_HAS_USB2_CH3 - -&audma0 { - iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>, - <&ipmmu_mp1 2>, <&ipmmu_mp1 3>, - <&ipmmu_mp1 4>, <&ipmmu_mp1 5>, - <&ipmmu_mp1 6>, <&ipmmu_mp1 7>, - <&ipmmu_mp1 8>, <&ipmmu_mp1 9>, - <&ipmmu_mp1 10>, <&ipmmu_mp1 11>, - <&ipmmu_mp1 12>, <&ipmmu_mp1 13>, - <&ipmmu_mp1 14>, <&ipmmu_mp1 15>; -}; - -&audma1 { - iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>, - <&ipmmu_mp1 18>, <&ipmmu_mp1 19>, - <&ipmmu_mp1 20>, <&ipmmu_mp1 21>, - <&ipmmu_mp1 22>, <&ipmmu_mp1 23>, - <&ipmmu_mp1 24>, <&ipmmu_mp1 25>, - <&ipmmu_mp1 26>, <&ipmmu_mp1 27>, - <&ipmmu_mp1 28>, <&ipmmu_mp1 29>, - <&ipmmu_mp1 30>, <&ipmmu_mp1 31>; -}; - -&cluster0_opp { - /delete-node/ opp-1600000000; - /delete-node/ opp-1700000000; -}; - -&du { - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>; -}; - -&fcpvb1 { - iommus = <&ipmmu_vp0 7>; -}; - -&fcpf1 { - iommus = <&ipmmu_vp0 1>; -}; - -&fcpvi1 { - iommus = <&ipmmu_vp0 9>; -}; - -&fcpvd2 { - iommus = <&ipmmu_vi0 10>; -}; - -&gpio1 { - gpio-ranges = <&pfc 0 32 28>; -}; - -&ipmmu_vi0 { - renesas,ipmmu-main = <&ipmmu_mm 11>; -}; - -&ipmmu_vp0 { - renesas,ipmmu-main = <&ipmmu_mm 12>; -}; - -&ipmmu_vc0 { - renesas,ipmmu-main = <&ipmmu_mm 9>; -}; - -&ipmmu_vc1 { - renesas,ipmmu-main = <&ipmmu_mm 10>; -}; - -&ipmmu_rt { - renesas,ipmmu-main = <&ipmmu_mm 7>; -}; - -&soc { - /delete-node/ dma-controller@e6460000; - /delete-node/ dma-controller@e6470000; - - ipmmu_mp1: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec680000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_sy: iommu@e7730000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7730000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - /delete-node/ iommu@fd950000; - /delete-node/ iommu@fd960000; - /delete-node/ iommu@fd970000; - /delete-node/ iommu@febe0000; - /delete-node/ iommu@fe980000; - - xhci1: usb@ee040000 { - compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; - reg = <0 0xee040000 0 0xc00>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 327>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 327>; - status = "disabled"; - }; - - /delete-node/ usb@e659c000; - /delete-node/ usb@ee0e0000; - /delete-node/ usb@ee0e0100; - - /delete-node/ usb-phy@ee0e0200; - - fdp1@fe948000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe948000 0 0x2400>; - interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 117>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 117>; - renesas,fcp = <&fcpf2>; - }; - - fcpf2: fcp@fe952000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe952000 0 0x200>; - clocks = <&cpg CPG_MOD 613>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 613>; - iommus = <&ipmmu_vp0 2>; - }; - - fcpvd3: fcp@fea3f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea3f000 0 0x200>; - clocks = <&cpg CPG_MOD 600>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 600>; - iommus = <&ipmmu_vi0 11>; - }; - - fcpvi2: fcp@fe9cf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9cf000 0 0x200>; - clocks = <&cpg CPG_MOD 609>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 609>; - iommus = <&ipmmu_vp0 10>; - }; - - vspd3: vsp@fea38000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea38000 0 0x5000>; - interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 620>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 620>; - - renesas,fcp = <&fcpvd3>; - }; - - vspi2: vsp@fe9c0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9c0000 0 0x8000>; - interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 629>; - - renesas,fcp = <&fcpvi2>; - }; - - csi21: csi2@fea90000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea90000 0 0x10000>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 713>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi21vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi21>; - }; - csi21vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi21>; - }; - csi21vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi21>; - }; - csi21vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi21>; - }; - csi21vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi21>; - }; - csi21vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi21>; - }; - csi21vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi21>; - }; - csi21vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi21>; - }; - }; - }; - }; -}; - -&vin0 { - ports { - port@1 { - vin0csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin0>; - }; - }; - }; -}; - -&vin1 { - ports { - port@1 { - vin1csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin1>; - }; - }; - }; -}; - -&vin2 { - ports { - port@1 { - vin2csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin2>; - }; - }; - }; -}; - -&vin3 { - ports { - port@1 { - vin3csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin3>; - }; - }; - }; -}; - -&vin4 { - ports { - port@1 { - vin4csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin4>; - }; - }; - }; -}; - -&vin5 { - ports { - port@1 { - vin5csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin5>; - }; - }; - }; -}; - -&vin6 { - ports { - port@1 { - vin6csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin6>; - }; - }; - }; -}; - -&vin7 { - ports { - port@1 { - vin7csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin7>; - }; - }; - }; -}; diff --git a/dts/src/arm64/renesas/r8a77951.dtsi b/dts/src/arm64/renesas/r8a77951.dtsi index 4e87e8776a..a4260d9291 100644 --- a/dts/src/arm64/renesas/r8a77951.dtsi +++ b/dts/src/arm64/renesas/r8a77951.dtsi @@ -9,8 +9,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7795-sysc.h> -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - #define SOC_HAS_HDMI1 #define SOC_HAS_SATA #define SOC_HAS_USB2_CH2 @@ -21,17 +19,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. @@ -86,7 +73,6 @@ opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; @@ -369,6 +355,7 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1367,6 +1354,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A7795_CLK_CANFD>, <&can_clk>; @@ -2007,7 +1995,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -2042,7 +2030,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7795_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -2731,6 +2719,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a7795-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a7795", "renesas,rcar-gen3-sata"; @@ -2772,8 +2776,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -2784,6 +2788,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2799,8 +2805,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; @@ -2811,6 +2817,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -3334,8 +3342,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; @@ -3378,8 +3384,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a77960.dtsi b/dts/src/arm64/renesas/r8a77960.dtsi index 6f79da8cc8..a631ead171 100644 --- a/dts/src/arm64/renesas/r8a77960.dtsi +++ b/dts/src/arm64/renesas/r8a77960.dtsi @@ -9,24 +9,11 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7796-sysc.h> -#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 - / { compatible = "renesas,r8a7796"; #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. @@ -81,13 +68,11 @@ opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; @@ -334,6 +319,7 @@ compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1239,6 +1225,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A7796_CLK_CANFD>, <&can_clk>; @@ -1879,7 +1866,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1914,7 +1901,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7796_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -2531,6 +2518,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a7796-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -2560,8 +2563,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -2572,6 +2575,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2587,8 +2592,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; @@ -2599,6 +2604,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2937,8 +2944,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; @@ -2975,8 +2980,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a77961.dtsi b/dts/src/arm64/renesas/r8a77961.dtsi index 68cbbb322a..7254912a24 100644 --- a/dts/src/arm64/renesas/r8a77961.dtsi +++ b/dts/src/arm64/renesas/r8a77961.dtsi @@ -9,8 +9,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a77961-sysc.h> -#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 - / { compatible = "renesas,r8a77961"; #address-cells = <2>; @@ -70,13 +68,11 @@ opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; @@ -323,6 +319,7 @@ compatible = "renesas,r8a77961-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1222,6 +1219,32 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77961-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77961_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; @@ -1723,7 +1746,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1758,7 +1781,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A77961_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -2375,6 +2398,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77961-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -2404,8 +2443,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -2416,6 +2455,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2431,8 +2472,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; @@ -2443,6 +2484,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2722,8 +2765,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; @@ -2760,8 +2801,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a77965.dtsi b/dts/src/arm64/renesas/r8a77965.dtsi index 9f858af8b7..e57b902706 100644 --- a/dts/src/arm64/renesas/r8a77965.dtsi +++ b/dts/src/arm64/renesas/r8a77965.dtsi @@ -12,8 +12,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a77965-sysc.h> -#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4 - #define SOC_HAS_SATA / { @@ -21,17 +19,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. @@ -86,13 +73,11 @@ opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; @@ -205,6 +190,7 @@ compatible = "renesas,r8a77965-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1102,6 +1088,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77965_CLK_CANFD>, <&can_clk>; @@ -1742,7 +1729,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1777,7 +1764,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A77965_CLK_S0D4>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -2378,6 +2365,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77965-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a77965", "renesas,rcar-gen3-sata"; @@ -2418,8 +2421,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -2430,6 +2433,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2445,8 +2450,8 @@ <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; @@ -2457,6 +2462,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2749,8 +2756,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; @@ -2787,8 +2792,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a77970-eagle.dts b/dts/src/arm64/renesas/r8a77970-eagle.dts index 49d1a929ae..0608dce92e 100644 --- a/dts/src/arm64/renesas/r8a77970-eagle.dts +++ b/dts/src/arm64/renesas/r8a77970-eagle.dts @@ -15,6 +15,11 @@ compatible = "renesas,eagle", "renesas,r8a77970"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; serial0 = &scif0; ethernet0 = &avb; }; @@ -24,6 +29,15 @@ stdout-path = "serial0:115200n8"; }; + d1p8: regulator-fixed { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + d3p3: regulator-fixed { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; @@ -161,6 +175,12 @@ interrupt-parent = <&gpio1>; interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + avdd-supply = <&d1p8>; + dvdd-supply = <&d1p8>; + pvdd-supply = <&d1p8>; + dvdd-3v-supply = <&d3p3>; + bgvdd-supply = <&d1p8>; + adi,input-depth = <8>; adi,input-colorspace = "rgb"; adi,input-clock = "1x"; @@ -282,6 +302,9 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + avb_pins: avb0 { groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; function = "avb0"; @@ -311,6 +334,11 @@ groups = "scif0_data"; function = "scif0"; }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; }; &rpc { @@ -386,3 +414,7 @@ status = "okay"; }; + +&scif_clk { + clock-frequency = <14745600>; +}; diff --git a/dts/src/arm64/renesas/r8a77970-v3msk.dts b/dts/src/arm64/renesas/r8a77970-v3msk.dts index 39f3e6cbba..e36999e91a 100644 --- a/dts/src/arm64/renesas/r8a77970-v3msk.dts +++ b/dts/src/arm64/renesas/r8a77970-v3msk.dts @@ -15,6 +15,11 @@ compatible = "renesas,v3msk", "renesas,r8a77970"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; serial0 = &scif0; }; @@ -140,7 +145,7 @@ status = "okay"; clock-frequency = <400000>; - hdmi@39{ + hdmi@39 { compatible = "adi,adv7511w"; #sound-dai-cells = <0>; reg = <0x39>; diff --git a/dts/src/arm64/renesas/r8a77970.dtsi b/dts/src/arm64/renesas/r8a77970.dtsi index 517892cf62..ed6e2e47c6 100644 --- a/dts/src/arm64/renesas/r8a77970.dtsi +++ b/dts/src/arm64/renesas/r8a77970.dtsi @@ -16,14 +16,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { compatible = "fixed-clock"; @@ -108,6 +100,7 @@ compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -556,6 +549,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77970_CLK_CANFD>, <&can_clk>; @@ -1051,7 +1045,6 @@ reg-names = "regs", "dirmap", "wbuf"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; @@ -1156,8 +1149,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { @@ -1190,8 +1181,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a77980-condor.dts b/dts/src/arm64/renesas/r8a77980-condor.dts index 43ed033eb5..68d1f1d53b 100644 --- a/dts/src/arm64/renesas/r8a77980-condor.dts +++ b/dts/src/arm64/renesas/r8a77980-condor.dts @@ -8,541 +8,17 @@ /dts-v1/; #include "r8a77980.dtsi" -#include <dt-bindings/gpio/gpio.h> +#include "condor-common.dtsi" / { model = "Renesas Condor board based on r8a77980"; compatible = "renesas,condor", "renesas,r8a77980"; - - aliases { - serial0 = &scif0; - ethernet0 = &gether; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - d1_8v: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "D1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - d3_3v: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&d3_3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0 0x48000000 0 0x78000000>; - }; - - vddq_vin01: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VDDQ_VIN01"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - x1_clk: x1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; - -&csi40 { - status = "okay"; - - ports { - port@0 { - csi40_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&max9286_out0>; - }; - }; - }; -}; - -&csi41 { - status = "okay"; - - ports { - port@0 { - csi41_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&max9286_out1>; - }; - }; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&x1_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gether { - pinctrl-0 = <&gether_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii-id"; - phy-handle = <&phy0>; - renesas,no-ether-link; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - }; }; &i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander0: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - io_expander1: gpio@21 { - compatible = "onnn,pca9654"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&d1_8v>; - dvdd-supply = <&d1_8v>; - pvdd-supply = <&d1_8v>; - bgvdd-supply = <&d1_8v>; - dvdd-3v-supply = <&d3_3v>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - gmsl0: gmsl-deserializer@48 { - compatible = "maxim,max9286"; - reg = <0x48>; - - maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; - enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - }; - - port@2 { - reg = <2>; - }; - - port@3 { - reg = <3>; - }; - - port@4 { - reg = <4>; - max9286_out0: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi40_in>; - }; - }; - }; - - i2c-mux { - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - status = "disabled"; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - status = "disabled"; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - status = "disabled"; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - status = "disabled"; - }; - }; + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; }; - - gmsl1: gmsl-deserializer@4a { - compatible = "maxim,max9286"; - reg = <0x4a>; - - maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; - enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - }; - - port@2 { - reg = <2>; - }; - - port@3 { - reg = <3>; - }; - - port@4 { - reg = <4>; - max9286_out1: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi41_in>; - }; - }; - }; - - i2c-mux { - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - status = "disabled"; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - status = "disabled"; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - status = "disabled"; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - status = "disabled"; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&vddq_vin01>; - mmc-hs200-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pfc { - canfd0_pins: canfd0 { - groups = "canfd0_data_a"; - function = "canfd0"; - }; - - gether_pins: gether { - groups = "gether_mdio_a", "gether_rgmii", - "gether_txcrefclk", "gether_txcrefclk_mega"; - function = "gether"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootparam@0 { - reg = <0x00000000 0x040000>; - read-only; - }; - cr7@40000 { - reg = <0x00040000 0x080000>; - read-only; - }; - cert_header_sa3@c0000 { - reg = <0x000c0000 0x080000>; - read-only; - }; - bl2@140000 { - reg = <0x00140000 0x040000>; - read-only; - }; - cert_header_sa6@180000 { - reg = <0x00180000 0x040000>; - read-only; - }; - bl31@1c0000 { - reg = <0x001c0000 0x460000>; - read-only; - }; - uboot@640000 { - reg = <0x00640000 0x0c0000>; - read-only; - }; - uboot-env@700000 { - reg = <0x00700000 0x040000>; - read-only; - }; - dtb@740000 { - reg = <0x00740000 0x080000>; - }; - kernel@7c0000 { - reg = <0x007c0000 0x1400000>; - }; - user@1bc0000 { - reg = <0x01bc0000 0x2440000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; }; diff --git a/dts/src/arm64/renesas/r8a77980-v3hsk.dts b/dts/src/arm64/renesas/r8a77980-v3hsk.dts index 1d09d88676..77d22df25f 100644 --- a/dts/src/arm64/renesas/r8a77980-v3hsk.dts +++ b/dts/src/arm64/renesas/r8a77980-v3hsk.dts @@ -15,6 +15,12 @@ compatible = "renesas,v3hsk", "renesas,r8a77980"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; serial0 = &scif0; ethernet0 = &gether; }; @@ -116,6 +122,7 @@ phy0: ethernet-phy@0 { compatible = "ethernet-phy-id0022.1622", "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio4>; interrupts = <23 IRQ_TYPE_LEVEL_LOW>; diff --git a/dts/src/arm64/renesas/r8a77980.dtsi b/dts/src/arm64/renesas/r8a77980.dtsi index 347c068ff2..5ed2daaca1 100644 --- a/dts/src/arm64/renesas/r8a77980.dtsi +++ b/dts/src/arm64/renesas/r8a77980.dtsi @@ -16,15 +16,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { compatible = "fixed-clock"; @@ -138,6 +129,7 @@ compatible = "renesas,r8a77980-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -608,6 +600,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77980_CLK_CANFD>, <&can_clk>; @@ -1357,7 +1350,6 @@ reg-names = "regs", "dirmap", "wbuf"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; @@ -1394,7 +1386,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; @@ -1407,6 +1400,8 @@ resets = <&cpg 319>; phys = <&pcie_phy>; phy-names = "pcie"; + iommu-map = <0 &ipmmu_vi0 5 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -1533,8 +1528,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { @@ -1568,8 +1561,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a77980a-condor-i.dts b/dts/src/arm64/renesas/r8a77980a-condor-i.dts new file mode 100644 index 0000000000..53fc217093 --- /dev/null +++ b/dts/src/arm64/renesas/r8a77980a-condor-i.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Condor-I board on r8a77980A (ES2.0) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77980a.dtsi" +#include "condor-common.dtsi" + +/ { + model = "Renesas Condor-I board based on r8a77980A (ES2.0)"; + compatible = "renesas,condor-i", "renesas,r8a77980a", "renesas,r8a77980"; +}; + +&mmc0 { + mmc-hs400-1_8v; +}; diff --git a/dts/src/arm64/renesas/r8a77980a.dtsi b/dts/src/arm64/renesas/r8a77980a.dtsi new file mode 100644 index 0000000000..83f5e21111 --- /dev/null +++ b/dts/src/arm64/renesas/r8a77980a.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree Source for the R-Car V3H2 (R8A77980A) SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#include "r8a77980.dtsi" + +/ { + compatible = "renesas,r8a77980a", "renesas,r8a77980"; +}; diff --git a/dts/src/arm64/renesas/r8a77990-ebisu.dts b/dts/src/arm64/renesas/r8a77990-ebisu.dts index 9da0fd08f8..d5ac34a966 100644 --- a/dts/src/arm64/renesas/r8a77990-ebisu.dts +++ b/dts/src/arm64/renesas/r8a77990-ebisu.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the Ebisu board with R-Car E3 + * Device Tree Source for the Ebisu/Ebisu-4D board with R-Car E3 * * Copyright (C) 2018 Renesas Electronics Corp. */ diff --git a/dts/src/arm64/renesas/r8a77990.dtsi b/dts/src/arm64/renesas/r8a77990.dtsi index 7e0f1aab21..8c2b283423 100644 --- a/dts/src/arm64/renesas/r8a77990.dtsi +++ b/dts/src/arm64/renesas/r8a77990.dtsi @@ -14,17 +14,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. @@ -60,17 +49,14 @@ opp-shared; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; opp-suspend; }; @@ -90,7 +76,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <277>; - clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -102,7 +88,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; - clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -171,6 +157,7 @@ compatible = "renesas,r8a77990-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -1051,6 +1038,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77990_CLK_CANFD>, <&can_clk>; @@ -1322,7 +1310,7 @@ vin4csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin4>; + remote-endpoint = <&csi40vin4>; }; }; }; @@ -1350,7 +1338,7 @@ vin5csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin5>; + remote-endpoint = <&csi40vin5>; }; }; }; @@ -1478,7 +1466,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1513,7 +1501,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A77990_CLK_ZA2>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", @@ -1837,6 +1825,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77990-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1866,8 +1870,8 @@ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; @@ -1878,6 +1882,8 @@ clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2031,8 +2037,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { @@ -2074,8 +2078,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -2101,8 +2103,6 @@ port@1 { reg = <1>; - lvds1_out: endpoint { - }; }; }; }; @@ -2117,7 +2117,7 @@ cpu-thermal { polling-delay-passive = <250>; polling-delay = <0>; - thermal-sensors = <&thermal 0>; + thermal-sensors = <&thermal>; sustainable-power = <717>; cooling-maps { diff --git a/dts/src/arm64/renesas/r8a77995.dtsi b/dts/src/arm64/renesas/r8a77995.dtsi index cac1f9467f..8cf6473c63 100644 --- a/dts/src/arm64/renesas/r8a77995.dtsi +++ b/dts/src/arm64/renesas/r8a77995.dtsi @@ -94,6 +94,7 @@ compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 402>; @@ -556,6 +557,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77995_CLK_CANFD>, <&can_clk>; @@ -1035,7 +1037,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; @@ -1061,7 +1063,7 @@ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, - <&cpg CPG_CORE R8A77995_CLK_ZA2>; + <&cpg CPG_MOD 922>; clock-names = "ssi-all", "ssi.4", "ssi.3", "src.6", "src.5", @@ -1237,6 +1239,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77995-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1350,8 +1368,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { @@ -1393,8 +1409,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -1420,8 +1434,6 @@ port@1 { reg = <1>; - lvds1_out: endpoint { - }; }; }; }; diff --git a/dts/src/arm64/renesas/r8a779a0-falcon-cpu.dtsi b/dts/src/arm64/renesas/r8a779a0-falcon-cpu.dtsi index 6af3f4f4f2..99b73e21c8 100644 --- a/dts/src/arm64/renesas/r8a779a0-falcon-cpu.dtsi +++ b/dts/src/arm64/renesas/r8a779a0-falcon-cpu.dtsi @@ -16,6 +16,13 @@ compatible = "renesas,falcon-cpu", "renesas,r8a779a0"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; serial0 = &scif0; }; @@ -192,14 +199,17 @@ clock-frequency = <400000>; bridge@2c { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + compatible = "ti,sn65dsi86"; reg = <0x2c>; clocks = <&sn65dsi86_refclk>; clock-names = "refclk"; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; vccio-supply = <®_1p8v>; vpll-supply = <®_1p8v>; @@ -271,6 +281,11 @@ function = "i2c6"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + keys_pins: keys { pins = "GP_6_18", "GP_6_19", "GP_6_20"; bias-pull-up; diff --git a/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi b/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi index e06b8eda85..dbc8dcab10 100644 --- a/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi +++ b/dts/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2021 Glider bv */ +#include <dt-bindings/media/video-interfaces.h> + &csi40 { status = "okay"; @@ -105,6 +107,7 @@ port@4 { reg = <4>; max96712_out0: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; clock-lanes = <0>; data-lanes = <1 2 3 4>; remote-endpoint = <&csi40_in>; @@ -125,6 +128,7 @@ port@4 { reg = <4>; max96712_out1: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; clock-lanes = <0>; data-lanes = <1 2 3 4>; lane-polarities = <0 0 0 0 1>; @@ -146,6 +150,7 @@ port@4 { reg = <4>; max96712_out2: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; clock-lanes = <0>; data-lanes = <1 2 3 4>; lane-polarities = <0 0 0 0 1>; diff --git a/dts/src/arm64/renesas/r8a779a0-falcon.dts b/dts/src/arm64/renesas/r8a779a0-falcon.dts index e46dc9aa0a..63db822e5f 100644 --- a/dts/src/arm64/renesas/r8a779a0-falcon.dts +++ b/dts/src/arm64/renesas/r8a779a0-falcon.dts @@ -37,6 +37,24 @@ }; }; +&can_clk { + clock-frequency = <40000000>; +}; + +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + &i2c0 { eeprom@51 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -65,4 +83,19 @@ }; }; + + can_clk_pins: can-clk { + groups = "can_clk"; + function = "can_clk"; + }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; }; diff --git a/dts/src/arm64/renesas/r8a779a0.dtsi b/dts/src/arm64/renesas/r8a779a0.dtsi index c4be288b19..4e67a03564 100644 --- a/dts/src/arm64/renesas/r8a779a0.dtsi +++ b/dts/src/arm64/renesas/r8a779a0.dtsi @@ -14,14 +14,11 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; cpus { @@ -34,6 +31,7 @@ device_type = "cpu"; power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76_0>; + clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>; }; L3_CA76_0: cache-controller-0 { @@ -79,8 +77,9 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a779a0-wdt", - "renesas,rcar-gen3-wdt"; + "renesas,rcar-gen4-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 907>; @@ -97,7 +96,8 @@ }; gpio0: gpio@e6058180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6058180 0 0x54>; interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 916>; @@ -111,7 +111,8 @@ }; gpio1: gpio@e6050180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6050180 0 0x54>; interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 915>; @@ -125,7 +126,8 @@ }; gpio2: gpio@e6050980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6050980 0 0x54>; interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 915>; @@ -139,7 +141,8 @@ }; gpio3: gpio@e6058980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6058980 0 0x54>; interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 916>; @@ -153,7 +156,8 @@ }; gpio4: gpio@e6060180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6060180 0 0x54>; interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; @@ -167,7 +171,8 @@ }; gpio5: gpio@e6060980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6060980 0 0x54>; interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; @@ -181,7 +186,8 @@ }; gpio6: gpio@e6068180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6068180 0 0x54>; interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 918>; @@ -195,7 +201,8 @@ }; gpio7: gpio@e6068980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6068980 0 0x54>; interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 918>; @@ -209,7 +216,8 @@ }; gpio8: gpio@e6069180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6069180 0 0x54>; interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 918>; @@ -223,7 +231,8 @@ }; gpio9: gpio@e6069980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6069980 0 0x54>; interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 918>; @@ -238,7 +247,7 @@ cmt0: timer@e60f0000 { compatible = "renesas,r8a779a0-cmt0", - "renesas,rcar-gen3-cmt0"; + "renesas,rcar-gen4-cmt0"; reg = <0 0xe60f0000 0 0x1004>; interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>; @@ -251,7 +260,7 @@ cmt1: timer@e6130000 { compatible = "renesas,r8a779a0-cmt1", - "renesas,rcar-gen3-cmt1"; + "renesas,rcar-gen4-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, @@ -270,7 +279,7 @@ cmt2: timer@e6140000 { compatible = "renesas,r8a779a0-cmt1", - "renesas,rcar-gen3-cmt1"; + "renesas,rcar-gen4-cmt1"; reg = <0 0xe6140000 0 0x1004>; interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, @@ -289,7 +298,7 @@ cmt3: timer@e6148000 { compatible = "renesas,r8a779a0-cmt1", - "renesas,rcar-gen3-cmt1"; + "renesas,rcar-gen4-cmt1"; reg = <0 0xe6148000 0 0x1004>; interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, @@ -422,7 +431,7 @@ i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe6500000 0 0x40>; interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 518>; @@ -438,7 +447,7 @@ i2c1: i2c@e6508000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 519>; @@ -454,7 +463,7 @@ i2c2: i2c@e6510000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe6510000 0 0x40>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 520>; @@ -470,7 +479,7 @@ i2c3: i2c@e66d0000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66d0000 0 0x40>; interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 521>; @@ -486,7 +495,7 @@ i2c4: i2c@e66d8000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66d8000 0 0x40>; interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 522>; @@ -502,7 +511,7 @@ i2c5: i2c@e66e0000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66e0000 0 0x40>; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 523>; @@ -518,7 +527,7 @@ i2c6: i2c@e66e8000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66e8000 0 0x40>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 524>; @@ -534,7 +543,7 @@ hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6540000 0 0x60>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 514>, @@ -550,7 +559,7 @@ hscif1: serial@e6550000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6550000 0 0x60>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 515>, @@ -566,7 +575,7 @@ hscif2: serial@e6560000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6560000 0 0x60>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 516>, @@ -582,7 +591,7 @@ hscif3: serial@e66a0000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe66a0000 0 0x60>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 517>, @@ -596,9 +605,59 @@ status = "disabled"; }; + canfd: can@e6660000 { + compatible = "renesas,r8a779a0-canfd", + "renesas,rcar-gen4-canfd"; + reg = <0 0xe6660000 0 0x8000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; + clocks = <&cpg CPG_MOD 328>, + <&cpg CPG_CORE R8A779A0_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>; + assigned-clock-rates = <80000000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + + channel2 { + status = "disabled"; + }; + + channel3 { + status = "disabled"; + }; + + channel4 { + status = "disabled"; + }; + + channel5 { + status = "disabled"; + }; + + channel6 { + status = "disabled"; + }; + + channel7 { + status = "disabled"; + }; + }; + avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6800000 0 0x800>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, @@ -646,7 +705,7 @@ avb1: ethernet@e6810000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6810000 0 0x800>; interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, @@ -694,7 +753,7 @@ avb2: ethernet@e6820000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6820000 0 0x1000>; interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, @@ -742,7 +801,7 @@ avb3: ethernet@e6830000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6830000 0 0x1000>; interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, @@ -790,7 +849,7 @@ avb4: ethernet@e6840000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6840000 0 0x1000>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, @@ -838,7 +897,7 @@ avb5: ethernet@e6850000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6850000 0 0x1000>; interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, @@ -884,9 +943,59 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>, @@ -902,7 +1011,7 @@ scif1: serial@e6e68000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, @@ -918,7 +1027,7 @@ scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 704>, @@ -934,7 +1043,7 @@ scif4: serial@e6c40000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 705>, @@ -961,7 +1070,7 @@ msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6e90000 0 0x0064>; interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 618>; @@ -976,7 +1085,7 @@ msiof1: spi@e6ea0000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6ea0000 0 0x0064>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 619>; @@ -991,7 +1100,7 @@ msiof2: spi@e6c00000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6c00000 0 0x0064>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 620>; @@ -1006,7 +1115,7 @@ msiof3: spi@e6c10000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6c10000 0 0x0064>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; @@ -1021,7 +1130,7 @@ msiof4: spi@e6c20000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6c20000 0 0x0064>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; @@ -1036,7 +1145,7 @@ msiof5: spi@e6c28000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6c28000 0 0x0064>; interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; @@ -1946,7 +2055,8 @@ }; dmac1: dma-controller@e7350000 { - compatible = "renesas,dmac-r8a779a0"; + compatible = "renesas,dmac-r8a779a0", + "renesas,rcar-gen4-dmac"; reg = <0 0xe7350000 0 0x1000>, <0 0xe7300000 0 0x10000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, @@ -1980,7 +2090,8 @@ }; dmac2: dma-controller@e7351000 { - compatible = "renesas,dmac-r8a779a0"; + compatible = "renesas,dmac-r8a779a0", + "renesas,rcar-gen4-dmac"; reg = <0 0xe7351000 0 0x1000>, <0 0xe7310000 0 0x10000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, @@ -2005,7 +2116,7 @@ mmc0: mmc@ee140000 { compatible = "renesas,sdhi-r8a779a0", - "renesas,rcar-gen3-sdhi"; + "renesas,rcar-gen4-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779A0_CLK_SD0H>; @@ -2026,7 +2137,6 @@ reg-names = "regs", "dirmap", "wbuf"; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 629>; - clock-names = "rpc"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 629>; #address-cells = <1>; @@ -2035,95 +2145,107 @@ }; ipmmu_rt0: iommu@ee480000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee480000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_rt1: iommu@ee4c0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee4c0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 19>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_ds0: iommu@eed00000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_ds1: iommu@eed40000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_ir: iommu@eed80000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed80000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_A3IR>; #iommu-cells = <1>; }; ipmmu_vc0: iommu@eedc0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeedc0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_vi0: iommu@eee80000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee80000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_vi1: iommu@eeec0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeeec0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_3dg: iommu@eee00000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_vip0: iommu@eef00000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeef00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_vip1: iommu@eef40000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeef40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 11>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; ipmmu_mm: iommu@eefc0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeefc0000 0 0x20000>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -2138,8 +2260,7 @@ interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; fcpvd0: fcp@fea10000 { @@ -2786,9 +2907,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/dts/src/arm64/renesas/r8a779f0-spider-cpu.dtsi b/dts/src/arm64/renesas/r8a779f0-spider-cpu.dtsi index 6e07c54148..477f3114d2 100644 --- a/dts/src/arm64/renesas/r8a779f0-spider-cpu.dtsi +++ b/dts/src/arm64/renesas/r8a779f0-spider-cpu.dtsi @@ -1,16 +1,47 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Spider CPU board * * Copyright (C) 2021 Renesas Electronics Corp. */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + #include "r8a779f0.dtsi" / { model = "Renesas Spider CPU board"; compatible = "renesas,spider-cpu", "renesas,r8a779f0"; + aliases { + serial0 = &hscif0; + serial1 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:1843200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-7 { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <7>; + }; + + led-8 { + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <8>; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -21,6 +52,36 @@ device_type = "memory"; reg = <0x4 0x80000000 0x0 0x80000000>; }; + + rc21012_pci: clk-rc21012-pci { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + + rc21012_ufs: clk-rc21012-ufs { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &extal_clk { @@ -31,13 +92,111 @@ clock-frequency = <32768>; }; +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gpio_exp_20: gpio@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + rc21012-gpio2-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-high; + }; + }; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +/* + * This board also has a microSD slot which we will not support upstream + * because we cannot directly switch voltages in software. + */ +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pcie0_clkref { + compatible = "gpio-gate-clock"; + clocks = <&rc21012_pci>; + enable-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + /delete-property/ clock-frequency; +}; + +&pciec0 { + reset-gpio = <&gpio_exp_20 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; - scif3_pins: scif3 { - groups = "scif3_data", "scif3_ctrl"; - function = "scif3"; + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; }; scif_clk_pins: scif_clk { @@ -51,8 +210,8 @@ status = "okay"; }; -&scif3 { - pinctrl-0 = <&scif3_pins>; +&scif0 { + pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; uart-has-rtscts; @@ -62,3 +221,14 @@ &scif_clk { clock-frequency = <24000000>; }; + +&ufs { + status = "okay"; +}; + +&ufs30_clk { + compatible = "gpio-gate-clock"; + clocks = <&rc21012_ufs>; + enable-gpios = <&gpio_exp_20 4 GPIO_ACTIVE_LOW>; + /delete-property/ clock-frequency; +}; diff --git a/dts/src/arm64/renesas/r8a779f0-spider-ethernet.dtsi b/dts/src/arm64/renesas/r8a779f0-spider-ethernet.dtsi new file mode 100644 index 0000000000..33c1015e9a --- /dev/null +++ b/dts/src/arm64/renesas/r8a779f0-spider-ethernet.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Spider Ethernet sub-board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +ð_serdes { + status = "okay"; +}; + +&i2c4 { + eeprom@52 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "ethernet-sub-board"; + reg = <0x52>; + pagesize = <8>; + }; +}; + +&pfc { + tsn0_pins: tsn0 { + groups = "tsn0_mdio_b", "tsn0_link_b"; + function = "tsn0"; + power-source = <1800>; + }; + + tsn1_pins: tsn1 { + groups = "tsn1_mdio_b", "tsn1_link_b"; + function = "tsn1"; + power-source = <1800>; + }; + + tsn2_pins: tsn2 { + groups = "tsn2_mdio_b", "tsn2_link_b"; + function = "tsn2"; + power-source = <1800>; + }; +}; + +&rswitch { + pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <&u101>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u101: ethernet-phy@1 { + reg = <1>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + port@1 { + reg = <1>; + phy-handle = <&u201>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u201: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + port@2 { + reg = <2>; + phy-handle = <&u301>; + phy-mode = "sgmii"; + phys = <ð_serdes 2>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u301: ethernet-phy@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/r8a779f0-spider.dts b/dts/src/arm64/renesas/r8a779f0-spider.dts index f286254b41..f139cc4feb 100644 --- a/dts/src/arm64/renesas/r8a779f0-spider.dts +++ b/dts/src/arm64/renesas/r8a779f0-spider.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Spider CPU and BreakOut boards * @@ -7,16 +7,18 @@ /dts-v1/; #include "r8a779f0-spider-cpu.dtsi" +#include "r8a779f0-spider-ethernet.dtsi" / { model = "Renesas Spider CPU and Breakout boards based on r8a779f0"; compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0"; +}; - aliases { - serial0 = &scif3; - }; - - chosen { - stdout-path = "serial0:115200n8"; +&i2c4 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; }; }; diff --git a/dts/src/arm64/renesas/r8a779f0.dtsi b/dts/src/arm64/renesas/r8a779f0.dtsi index f4e5498673..7fb4989cce 100644 --- a/dts/src/arm64/renesas/r8a779f0.dtsi +++ b/dts/src/arm64/renesas/r8a779f0.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC * @@ -14,15 +14,237 @@ #address-cells = <2>; #size-cells = <2>; + cluster01_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + opp-suspend; + }; + }; + + cluster23_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a55_0>; + }; + core1 { + cpu = <&a55_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a55_2>; + }; + core1 { + cpu = <&a55_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&a55_4>; + }; + core1 { + cpu = <&a55_5>; + }; + }; + + cluster3 { + core0 { + cpu = <&a55_6>; + }; + core1 { + cpu = <&a55_7>; + }; + }; + }; + a55_0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA55_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + operating-points-v2 = <&cluster01_opp>; + }; + + a55_1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA55_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + operating-points-v2 = <&cluster01_opp>; + }; + + a55_2: cpu@10000 { + compatible = "arm,cortex-a55"; + reg = <0x10000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; + next-level-cache = <&L3_CA55_1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + operating-points-v2 = <&cluster01_opp>; + }; + + a55_3: cpu@10100 { + compatible = "arm,cortex-a55"; + reg = <0x10100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; + next-level-cache = <&L3_CA55_1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + operating-points-v2 = <&cluster01_opp>; + }; + + a55_4: cpu@20000 { + compatible = "arm,cortex-a55"; + reg = <0x20000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; + next-level-cache = <&L3_CA55_2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + operating-points-v2 = <&cluster23_opp>; + }; + + a55_5: cpu@20100 { + compatible = "arm,cortex-a55"; + reg = <0x20100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; + next-level-cache = <&L3_CA55_2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + operating-points-v2 = <&cluster23_opp>; + }; + + a55_6: cpu@30000 { + compatible = "arm,cortex-a55"; + reg = <0x30000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; + next-level-cache = <&L3_CA55_3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + operating-points-v2 = <&cluster23_opp>; + }; + + a55_7: cpu@30100 { + compatible = "arm,cortex-a55"; + reg = <0x30100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; + next-level-cache = <&L3_CA55_3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + operating-points-v2 = <&cluster23_opp>; + }; + + L3_CA55_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_1: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D1>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_2: cache-controller-2 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E1D0>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_3: cache-controller-3 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E1D1>; + cache-unified; + cache-level = <3>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; }; }; @@ -40,11 +262,30 @@ clock-frequency = <0>; }; + pcie0_clkref: pcie0-clkref { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pcie1_clkref: pcie1-clkref { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + pmu_a55 { compatible = "arm,cortex-a55-pmu"; interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -63,6 +304,7 @@ compatible = "renesas,r8a779f0-wdt", "renesas,rcar-gen4-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 907>; @@ -75,6 +317,136 @@ <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; }; + gpio0: gpio@e6050180 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050180 0 0x54>; + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e6050980 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050980 0 0x54>; + interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 32 25>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e6051180 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6051180 0 0x54>; + interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 64 17>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e6051980 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6051980 0 0x54>; + interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 19>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + cmt0: timer@e60f0000 { + compatible = "renesas,r8a779f0-cmt0", + "renesas,rcar-gen4-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 910>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 910>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a779f0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 911>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 911>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a779f0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 912>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 912>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a779f0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 913>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 913>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; @@ -96,20 +468,642 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a779f0-thermal"; + /* The 4th sensor is in control domain and not for Linux */ + reg = <0 0xe6198000 0 0x200>, + <0 0xe61a0000 0 0x200>, + <0 0xe61a8000 0 0x200>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 919>; + #thermal-sensor-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + }; + + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + eth_serdes: phy@e6444000 { + compatible = "renesas,r8a779f0-ether-serdes"; + reg = <0 0xe6444000 0 0x2800>; + clocks = <&cpg CPG_MOD 1506>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1506>; + #phy-cells = <1>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + dmas = <&dmac0 0x91>, <&dmac0 0x90>, + <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + dmas = <&dmac0 0x93>, <&dmac0 0x92>, + <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + dmas = <&dmac0 0x95>, <&dmac0 0x94>, + <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>, + <&dmac1 0x97>, <&dmac1 0x96>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 522>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>, + <&dmac1 0x99>, <&dmac1 0x98>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, + <&dmac1 0x9b>, <&dmac1 0x9a>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x31>, <&dmac0 0x30>, + <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x33>, <&dmac0 0x32>, + <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x35>, <&dmac0 0x34>, + <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>, + <&dmac1 0x37>, <&dmac1 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + pciec0: pcie@e65d0000 { + compatible = "renesas,r8a779f0-pcie", + "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>, + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, + <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + snps,enable-cdm-check; + status = "disabled"; + }; + + pciec1: pcie@e65d8000 { + compatible = "renesas,r8a779f0-pcie", + "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>, + <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, + <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, + <0 0xee900000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; + interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; + snps,enable-cdm-check; + status = "disabled"; + }; + + pciec0_ep: pcie-ep@e65d0000 { + compatible = "renesas,r8a779f0-pcie-ep", + "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, + <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + max-functions = /bits/ 8 <2>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@e65d8000 { + compatible = "renesas,r8a779f0-pcie-ep", + "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>, + <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, + <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, + <0 0xee900000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + max-functions = /bits/ 8 <2>; + status = "disabled"; + }; + + ufs: ufs@e6860000 { + compatible = "renesas,r8a779f0-ufs"; + reg = <0 0xe6860000 0 0x100>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; + clock-names = "fck", "ref_clk"; + freq-table-hz = <200000000 200000000>, <38400000 38400000>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1514>; + status = "disabled"; + }; + + rswitch: ethernet@e6880000 { + compatible = "renesas,r8a779f0-ether-switch"; + reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>; + reg-names = "base", "secure_base"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mfwd_error", "race_error", + "coma_error", "gwca0_error", + "gwca1_error", "etha0_error", + "etha1_error", "etha2_error", + "gptp0_status", "gptp1_status", + "mfwd_status", "race_status", + "coma_status", "gwca0_status", + "gwca1_status", "etha0_status", + "etha1_status", "etha2_status", + "rmac0_status", "rmac1_status", + "rmac2_status", + "gwca0_rxtx0", "gwca0_rxtx1", + "gwca0_rxtx2", "gwca0_rxtx3", + "gwca0_rxtx4", "gwca0_rxtx5", + "gwca0_rxtx6", "gwca0_rxtx7", + "gwca1_rxtx0", "gwca1_rxtx1", + "gwca1_rxtx2", "gwca1_rxtx3", + "gwca1_rxtx4", "gwca1_rxtx5", + "gwca1_rxtx6", "gwca1_rxtx7", + "gwca0_rxts0", "gwca0_rxts1", + "gwca1_rxts0", "gwca1_rxts1", + "rmac0_mdio", "rmac1_mdio", + "rmac2_mdio", + "rmac0_phy", "rmac1_phy", + "rmac2_phy"; + clocks = <&cpg CPG_MOD 1505>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1505>; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phys = <ð_serdes 0>; + }; + port@1 { + reg = <1>; + phys = <ð_serdes 1>; + }; + port@2 { + reg = <2>; + phys = <ð_serdes 2>; + }; + }; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x51>, <&dmac0 0x50>, + <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x53>, <&dmac0 0x52>, + <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 704>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>, + <&dmac1 0x57>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 704>; status = "disabled"; }; + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>, + <&dmac1 0x59>, <&dmac1 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a779f0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 618>; + dmas = <&dmac0 0x41>, <&dmac0 0x40>, + <&dmac1 0x41>, <&dmac1 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 618>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a779f0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 619>; + dmas = <&dmac0 0x43>, <&dmac0 0x42>, + <&dmac1 0x43>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 619>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a779f0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 620>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>, + <&dmac1 0x45>, <&dmac1 0x44>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 620>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a779f0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>, + <&dmac1 0x47>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 621>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779f0", "renesas,rcar-gen4-dmac"; @@ -143,6 +1137,14 @@ resets = <&cpg 709>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7351000 { @@ -178,6 +1180,74 @@ resets = <&cpg 710>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, + <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, + <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, + <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, + <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, + <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, + <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, + <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; + }; + + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779f0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + iommus = <&ipmmu_ds0 32>; + status = "disabled"; + }; + + ipmmu_rt0: iommu@ee480000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee480000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt1: iommu@ee4c0000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee4c0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds0: iommu@eed00000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@eed40000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@eefc0000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeefc0000 0 0x20000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; gic: interrupt-controller@f1000000 { @@ -187,8 +1257,7 @@ interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; prr: chipid@fff00044 { @@ -197,11 +1266,62 @@ }; }; + thermal-zones { + sensor_thermal_rtcore: sensor1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_apcore0: sensor2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_apcore4: sensor3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + ufs30_clk: ufs30-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; }; }; diff --git a/dts/src/arm64/renesas/r8a779f4-s4sk.dts b/dts/src/arm64/renesas/r8a779f4-s4sk.dts new file mode 100644 index 0000000000..abfda5c6ca --- /dev/null +++ b/dts/src/arm64/renesas/r8a779f4-s4sk.dts @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree Source for the R-Car S4 Starter Kit board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "r8a779f4.dtsi" + +/ { + model = "R-Car S4 Starter Kit board"; + compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0"; + + aliases { + serial0 = &hscif0; + serial1 = &hscif1; + eth0 = &rswitch; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:921600n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + /* The last 512MB is reserved for CR. */ + reg = <0x0 0x48000000 0x0 0x58000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + vcc_sdhi: regulator-vcc-sdhi { + compatible = "regulator-fixed"; + regulator-name = "SDHI Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ð_serdes { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c5 { + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "st,24c16", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&mmc0 { + pinctrl-0 = <&sd_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi>; + cd-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data", "hscif1_ctrl"; + function = "hscif1"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + + i2c5_pins: i2c5 { + groups = "i2c5"; + function = "i2c5"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; + + sd_pins: sd { + groups = "mmc_data4", "mmc_ctrl"; + function = "mmc"; + power-source = <3300>; + }; + + tsn0_pins: tsn0 { + groups = "tsn0_mdio_b", "tsn0_link_b"; + function = "tsn0"; + drive-strength = <18>; + power-source = <3300>; + }; + + tsn1_pins: tsn1 { + groups = "tsn1_mdio_b", "tsn1_link_b"; + function = "tsn1"; + drive-strength = <18>; + power-source = <3300>; + }; +}; + +&rswitch { + pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <&ic99>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ic99: ethernet-phy@1 { + reg = <1>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + + port@1 { + reg = <1>; + phy-handle = <&ic102>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ic102: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + + port@2 { + status = "disabled"; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; + +&ufs { + status = "okay"; +}; + +&ufs30_clk { + clock-frequency = <38400000>; +}; diff --git a/dts/src/arm64/renesas/r8a779f4.dtsi b/dts/src/arm64/renesas/r8a779f4.dtsi new file mode 100644 index 0000000000..ebed41892d --- /dev/null +++ b/dts/src/arm64/renesas/r8a779f4.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree Source for the R-Car S4-8 (R8A779F4) SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include "r8a779f0.dtsi" + +/ { + compatible = "renesas,r8a779f4", "renesas,r8a779f0"; +}; diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso b/dts/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso new file mode 100644 index 0000000000..e6f53377ec --- /dev/null +++ b/dts/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the White Hawk board with ARD-AUDIO-DA7212 Board + * + * You can find and buy "ARD-AUDIO-DA7212" at Digi-Key + * + * https://www.digikey.jp/en/products/detail/ARD-AUDIO-DA7212/1564-1021-ND/5456357 + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + * + * [Connection] + * + * White Hawk ARD-AUDIO-DA7212 + * +----------------------------+ + * |CPU board | + * | | + * |CN40 (IO PIN HEADER) | + * | AUDIO_CLKIN_V pin1 |<--\ +---------------+ + * |(*) GP1_25/SL_SW2_V pin2 |<--/ |J2 | + * | AUDIO_CLKOUT_V pin5 |<----->| pin7 MCLK | + * | SSI_SCK_V pin9 |<----->| pin1 BCLK | + * | SSI_WS_V pin13 |<----->| pin3 WCLK | + * | SSI_SD_V pin15 |<----->| pin5 DATIN | (@) + * | | \-->| pin15 DATOUT | [CAPTURE] + * +----------------------------+ +---------------+ + * +----------------------------+ + * |Breakout board | + * | | +---------------+ + * |CN34 (I2C CN) | |J1 | + * | I2C0_SCL pin3 |<----->| pin20 SCL | + * | I2C0_SDA pin5 |<----->| pin18 SDA | + * | | +---------------+ + * | | +-----------------------+ + * |CN4 (Power) | |J7 | + * | 3v3 (v) pin9 |<----->| pin4 / pin8 3.3v | + * | GND (v) pin3 / pin4 |<----->| pin12 / pin14 GND | + * +----------------------------+ +-----------------------+ + * (*) GP1_25/SL_SW2_V is used as TPU + * (@) Connect to pin5 (DATIN = playback) or pin15 (DATOUT = capture) + * (v) These are just sample pins. You can find many 3v3 / GND pins on + * White Hawk board, not only CN4. You can use other pins for it. + * + * [How to enable] + * + * You need these configs + * + * CONFIG_PWM + * CONFIG_PWM_RENESAS_TPU + * CONFIG_COMMON_CLK_PWM + * CONFIG_SND_SOC_DA7213 + * + * [How to use] + * + * 44.1kHz groups sound is available by default. + * You need to update audio_clkin settings to switch to 48kHz groups sound. + * see + * [(C) clock] + * + * You can use capture if you change the settings + * see + * [CAPTURE] + * + * You need to setup Headphone + * + * > amixer set "Headphone" 40% + * > amixer set "Headphone" on + * > amixer set "Mixout Left DAC Left" on + * > amixer set "Mixout Right DAC Right" on + */ + +/dts-v1/; +/plugin/; +#include <dt-bindings/clock/r8a779g0-cpg-mssr.h> + +&{/} { + sound_card: sound { + compatible = "audio-graph-card"; + label = "rcar-sound"; + + dais = <&rsnd_port>; /* DA7212 Audio Codec */ + }; + + tpu_clk: tpu-clk { + compatible = "pwm-clock"; + #clock-cells = <0>; + + /* 44.1kHz groups [(C) clock] */ + clock-frequency = <11289600>; + pwms = <&tpu 0 88 0>; /* 1000000000 / 88 =~ 11289600 */ + + /* 48 kHz groups [(C) clock] */ +// clock-frequency = <12288000>; +// pwms = <&tpu 0 81 0>; /* 1000000000 / 81 =~ 12288000 */ + }; + +}; + +&pfc { + sound_pins: sound { + groups = "ssi_ctrl", "ssi_data"; + function = "ssi"; + }; + + sound_clk_pins: sound-clk { + groups = "audio_clkin", "audio_clkout"; + function = "audio_clk"; + }; + + tpu0_pins: tpu0 { + groups = "tpu_to0_a"; + function = "tpu"; + }; +}; + +&tpu { + pinctrl-0 = <&tpu0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + codec@1a { + compatible = "dlg,da7212"; + + #sound-dai-cells = <0>; + reg = <0x1a>; + + clocks = <&rcar_sound>; + clock-names = "mclk"; + + dlg,micbias1-lvl = <2500>; + dlg,micbias2-lvl = <2500>; + dlg,dmic-data-sel = "lrise_rfall"; + dlg,dmic-samplephase = "between_clkedge"; + dlg,dmic-clkrate = <3000000>; + + VDDA-supply = <®_1p8v>; + VDDMIC-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + + port { + da7212_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint>; + }; + }; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_clk_pins>, <&sound_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout */ + #clock-cells = <0>; + clock-frequency = <5644800>; /* 44.1kHz groups [(C) clock] */ +// clock-frequency = <6144000>; /* 48 kHz groups [(C) clock] */ + + status = "okay"; + + /* Update <clkin> to <tpu_clk> */ + clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&tpu_clk>; + + ports { + rsnd_port: port { + rsnd_endpoint: endpoint { + remote-endpoint = <&da7212_endpoint>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint>; + frame-master = <&rsnd_endpoint>; + + /* Mutually exclusive with 'capture' */ + playback = <&ssi0>; + /* [CAPTURE] */ + /* capture = <&ssi0>; */ + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi b/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi new file mode 100644 index 0000000000..913f70fe6c --- /dev/null +++ b/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the White Hawk CPU board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include "r8a779g0.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Renesas White Hawk CPU board"; + compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; + + aliases { + ethernet0 = &avb0; + serial0 = &hscif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:921600n8"; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_1>; + label = "SW47"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_2>; + label = "SW48"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + label = "SW49"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + led-2 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led-3 { + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; + + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; +}; + +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; +}; + +&dsi0 { + status = "okay"; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander_a: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; + hscif0_pins: hscif0 { + groups = "hscif0_data"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + keys_pins: keys { + pins = "GP_5_0", "GP_5_1", "GP_5_2"; + bias-pull-up; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0x1200000>; + read-only; + }; + user@1200000 { + reg = <0x1200000 0x2e00000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk-csi-dsi.dtsi b/dts/src/arm64/renesas/r8a779g0-white-hawk-csi-dsi.dtsi new file mode 100644 index 0000000000..f8537f7ea4 --- /dev/null +++ b/dts/src/arm64/renesas/r8a779g0-white-hawk-csi-dsi.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board + * + * Copyright (C) 2022 Glider bv + */ + +#include <dt-bindings/media/video-interfaces.h> + +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3>; + remote-endpoint = <&max96712_out0>; + }; + }; + }; +}; + +&csi41 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi41_in: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3>; + remote-endpoint = <&max96712_out1>; + }; + }; + }; +}; + +&i2c0 { + pca9654_a: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9654_b: gpio@22 { + compatible = "onnn,pca9654"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@52 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "csi-dsi-sub-board-id"; + reg = <0x52>; + pagesize = <8>; + }; +}; + +&i2c1 { + gmsl0: gmsl-deserializer@49 { + compatible = "maxim,max96712"; + reg = <0x49>; + enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out0: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + + gmsl1: gmsl-deserializer@4b { + compatible = "maxim,max96712"; + reg = <0x4b>; + enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out1: endpoint { + bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>; + clock-lanes = <0>; + data-lanes = <1 2 3>; + remote-endpoint = <&csi41_in>; + }; + }; + }; + }; +}; + +&isp0 { + status = "okay"; +}; + +&isp1 { + status = "okay"; +}; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; + +&vin08 { + status = "okay"; +}; + +&vin09 { + status = "okay"; +}; + +&vin10 { + status = "okay"; +}; + +&vin11 { + status = "okay"; +}; + +&vin12 { + status = "okay"; +}; + +&vin13 { + status = "okay"; +}; + +&vin14 { + status = "okay"; +}; + +&vin15 { + status = "okay"; +}; diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk-ethernet.dtsi b/dts/src/arm64/renesas/r8a779g0-white-hawk-ethernet.dtsi new file mode 100644 index 0000000000..4f411f95c6 --- /dev/null +++ b/dts/src/arm64/renesas/r8a779g0-white-hawk-ethernet.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) + * sub-board + * + * Copyright (C) 2022 Glider bv + */ + +&i2c0 { + eeprom@53 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "ethernet-sub-board-id"; + reg = <0x53>; + pagesize = <8>; + }; +}; diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk.dts b/dts/src/arm64/renesas/r8a779g0-white-hawk.dts new file mode 100644 index 0000000000..eff1ef6e2c --- /dev/null +++ b/dts/src/arm64/renesas/r8a779g0-white-hawk.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the White Hawk CPU and BreakOut boards + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779g0-white-hawk-cpu.dtsi" +#include "r8a779g0-white-hawk-csi-dsi.dtsi" +#include "r8a779g0-white-hawk-ethernet.dtsi" + +/ { + model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; + compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0"; + + can_transceiver0: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + max-bitrate = <5000000>; + }; +}; + +&can_clk { + clock-frequency = <40000000>; +}; + +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; + + channel0 { + status = "okay"; + phys = <&can_transceiver0>; + }; + + channel1 { + status = "okay"; + }; +}; + +&i2c0 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; +}; + +&pfc { + can_clk_pins: can-clk { + groups = "can_clk"; + function = "can_clk"; + }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; +}; diff --git a/dts/src/arm64/renesas/r8a779g0.dtsi b/dts/src/arm64/renesas/r8a779g0.dtsi new file mode 100644 index 0000000000..d3d25e077c --- /dev/null +++ b/dts/src/arm64/renesas/r8a779g0.dtsi @@ -0,0 +1,2349 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H (R8A779G0) SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/r8a779g0-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a779g0-sysc.h> + +/ { + compatible = "renesas,r8a779g0"; + #address-cells = <2>; + #size-cells = <2>; + + /* External Audio clock - to be overridden by boards that provide it */ + audio_clkin: audio_clkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + opp-suspend; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <880000>; + clock-latency-ns = <500000>; + turbo-mode; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a76_0>; + }; + core1 { + cpu = <&a76_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a76_2>; + }; + core1 { + cpu = <&a76_3>; + }; + }; + }; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_1: cpu@100 { + compatible = "arm,cortex-a76"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA76_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_2: cpu@10000 { + compatible = "arm,cortex-a76"; + reg = <0x10000>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D1C0>; + next-level-cache = <&L3_CA76_1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_3: cpu@10100 { + compatible = "arm,cortex-a76"; + reg = <0x10100>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D1C1>; + next-level-cache = <&L3_CA76_1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; + + L3_CA76_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779G0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; + }; + + L3_CA76_1: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A779G0_PD_A2E0D1>; + cache-unified; + cache-level = <3>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779g0-wdt", + "renesas,rcar-gen4-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a779g0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, + <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, + <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, + <0 0xe6068000 0 0x16c>; + }; + + gpio0: gpio@e6050180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050180 0 0x54>; + interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 19>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e6050980 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050980 0 0x54>; + interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 32 29>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e6058180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058180 0 0x54>; + interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 64 20>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e6058980 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058980 0 0x54>; + interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 30>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@e6060180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060180 0 0x54>; + interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 128 25>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@e6060980 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060980 0 0x54>; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 160 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@e6061180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061180 0 0x54>; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 192 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@e6061980 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061980 0 0x54>; + interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 224 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio@e6068180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6068180 0 0x54>; + interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 256 14>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + cmt0: timer@e60f0000 { + compatible = "renesas,r8a779g0-cmt0", + "renesas,rcar-gen4-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 910>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 910>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a779g0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 911>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 911>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a779g0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 912>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 912>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a779g0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 913>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 913>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779g0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779g0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779g0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a779g0-thermal"; + reg = <0 0xe6198000 0 0x200>, + <0 0xe61a0000 0 0x200>, + <0 0xe61a8000 0 0x200>, + <0 0xe61b0000 0 0x200>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 919>; + #thermal-sensor-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 611>; + }; + + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>; + dmas = <&dmac0 0x91>, <&dmac0 0x90>, + <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>; + dmas = <&dmac0 0x93>, <&dmac0 0x92>, + <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>; + dmas = <&dmac0 0x95>, <&dmac0 0x94>, + <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 521>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>, + <&dmac1 0x97>, <&dmac1 0x96>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + dma-names = "tx", "rx", "tx", "rx"; + dmas = <&dmac0 0x99>, <&dmac0 0x98>, + <&dmac1 0x99>, <&dmac1 0x98>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 522>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 523>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, + <&dmac1 0x9b>, <&dmac1 0x9a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779g0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x31>, <&dmac0 0x30>, + <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a779g0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x33>, <&dmac0 0x32>, + <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a779g0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x35>, <&dmac0 0x34>, + <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a779g0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>, + <&dmac1 0x37>, <&dmac1 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + canfd: can@e6660000 { + compatible = "renesas,r8a779g0-canfd", + "renesas,rcar-gen4-canfd"; + reg = <0 0xe6660000 0 0x8500>; + interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch_int", "g_int"; + clocks = <&cpg CPG_MOD 328>, + <&cpg CPG_CORE R8A779G0_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>; + assigned-clock-rates = <80000000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + + channel2 { + status = "disabled"; + }; + + channel3 { + status = "disabled"; + }; + + channel4 { + status = "disabled"; + }; + + channel5 { + status = "disabled"; + }; + + channel6 { + status = "disabled"; + }; + + channel7 { + status = "disabled"; + }; + }; + + avb0: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a779g0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6800000 0 0x800>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15", "ch16", "ch17", + "ch18", "ch19", "ch20", "ch21", + "ch22", "ch23", "ch24"; + clocks = <&cpg CPG_MOD 211>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 211>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb1: ethernet@e6810000 { + compatible = "renesas,etheravb-r8a779g0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6810000 0 0x800>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15", "ch16", "ch17", + "ch18", "ch19", "ch20", "ch21", + "ch22", "ch23", "ch24"; + clocks = <&cpg CPG_MOD 212>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 212>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb2: ethernet@e6820000 { + compatible = "renesas,etheravb-r8a779g0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6820000 0 0x1000>; + interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15", "ch16", "ch17", + "ch18", "ch19", "ch20", "ch21", + "ch22", "ch23", "ch24"; + clocks = <&cpg CPG_MOD 213>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 213>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm7: pwm@e6e37000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e37000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm8: pwm@e6e38000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e38000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm9: pwm@e6e39000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e39000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779g0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x51>, <&dmac0 0x50>, + <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779g0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x53>, <&dmac0 0x52>, + <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779g0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>, + <&dmac1 0x57>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779g0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>, + <&dmac1 0x59>, <&dmac1 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + tpu: pwm@e6e80000 { + compatible = "renesas,tpu-r8a779g0", "renesas,tpu"; + reg = <0 0xe6e80000 0 0x148>; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 718>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 718>; + #pwm-cells = <3>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 618>; + dmas = <&dmac0 0x41>, <&dmac0 0x40>, + <&dmac1 0x41>, <&dmac1 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 618>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 619>; + dmas = <&dmac0 0x43>, <&dmac0 0x42>, + <&dmac1 0x43>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 619>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 620>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>, + <&dmac1 0x45>, <&dmac1 0x44>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 620>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>, + <&dmac1 0x47>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 621>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof4: spi@e6c20000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c20000 0 0x0064>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + dmas = <&dmac0 0x49>, <&dmac0 0x48>, + <&dmac1 0x49>, <&dmac1 0x48>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 622>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof5: spi@e6c28000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c28000 0 0x0064>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + dmas = <&dmac0 0x4b>, <&dmac0 0x4a>, + <&dmac1 0x4b>, <&dmac1 0x4a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 623>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin00: video@e6ef0000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 730>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 730>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin00isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin00>; + }; + }; + }; + }; + + vin01: video@e6ef1000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 731>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 731>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin01isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin01>; + }; + }; + }; + }; + + vin02: video@e6ef2000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 800>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 800>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin02isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin02>; + }; + }; + }; + }; + + vin03: video@e6ef3000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 801>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 801>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin03isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin03>; + }; + }; + }; + }; + + vin04: video@e6ef4000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 802>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin04isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin04>; + }; + }; + }; + }; + + vin05: video@e6ef5000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 803>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 803>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin05isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin05>; + }; + }; + }; + }; + + vin06: video@e6ef6000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin06isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin06>; + }; + }; + }; + }; + + vin07: video@e6ef7000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin07isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin07>; + }; + }; + }; + }; + + vin08: video@e6ef8000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef8000 0 0x1000>; + interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <8>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin08isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin08>; + }; + }; + }; + }; + + vin09: video@e6ef9000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef9000 0 0x1000>; + interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <9>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin09isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin09>; + }; + }; + }; + }; + + vin10: video@e6efa000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efa000 0 0x1000>; + interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <10>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin10isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin10>; + }; + }; + }; + }; + + vin11: video@e6efb000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efb000 0 0x1000>; + interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <11>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin11isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin11>; + }; + }; + }; + }; + + vin12: video@e6efc000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efc000 0 0x1000>; + interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <12>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin12isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin12>; + }; + }; + }; + }; + + vin13: video@e6efd000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efd000 0 0x1000>; + interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <13>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin13isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin13>; + }; + }; + }; + }; + + vin14: video@e6efe000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efe000 0 0x1000>; + interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 812>; + renesas,id = <14>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin14isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin14>; + }; + }; + }; + }; + + vin15: video@e6eff000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6eff000 0 0x1000>; + interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 813>; + renesas,id = <15>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin15isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin15>; + }; + }; + }; + }; + + dmac0: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779g0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; + }; + + dmac1: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779g0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, + <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, + <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, + <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, + <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, + <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, + <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, + <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; + }; + + rcar_sound: sound@ec5a0000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * audio_clkout0/1/2/3 : #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4"; + reg = <0 0xec5a0000 0 0x020>, + <0 0xec540000 0 0x1000>, + <0 0xec541000 0 0x050>, + <0 0xec400000 0 0x40000>; + reg-names = "adg", "ssiu", "ssi", "sdmc"; + + clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>; + clock-names = "ssiu.0", "ssi.0", "clkin"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 2926>, <&cpg 2927>; + reset-names = "ssiu.0", "ssi.0"; + status = "disabled"; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&dmac0 0x6e>, <&dmac0 0x6f>; + dma-names = "tx", "rx"; + }; + ssiu01: ssiu-1 { + dmas = <&dmac0 0x6c>, <&dmac0 0x6d>; + dma-names = "tx", "rx"; + }; + ssiu02: ssiu-2 { + dmas = <&dmac0 0x6a>, <&dmac0 0x6b>; + dma-names = "tx", "rx"; + }; + ssiu03: ssiu-3 { + dmas = <&dmac0 0x68>, <&dmac0 0x69>; + dma-names = "tx", "rx"; + }; + ssiu04: ssiu-4 { + dmas = <&dmac0 0x66>, <&dmac0 0x67>; + dma-names = "tx", "rx"; + }; + ssiu05: ssiu-5 { + dmas = <&dmac0 0x64>, <&dmac0 0x65>; + dma-names = "tx", "rx"; + }; + ssiu06: ssiu-6 { + dmas = <&dmac0 0x62>, <&dmac0 0x63>; + dma-names = "tx", "rx"; + }; + ssiu07: ssiu-7 { + dmas = <&dmac0 0x60>, <&dmac0 0x61>; + dma-names = "tx", "rx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; + + ipmmu_rt0: iommu@ee480000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee480000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt1: iommu@ee4c0000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee4c0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds0: iommu@eed00000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@eed40000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: iommu@eed80000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_vc: iommu@eedc0000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeedc0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_3dg: iommu@eee00000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeee00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@eee80000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeee80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: iommu@eeec0000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeeec0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vip0: iommu@eef00000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeef00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vip1: iommu@eef40000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeef40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@eefc0000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeefc0000 0 0x20000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779g0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 706>, + <&cpg CPG_CORE R8A779G0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + iommus = <&ipmmu_ds0 32>; + status = "disabled"; + }; + + rpc: spi@ee200000 { + compatible = "renesas,r8a779g0-rpc-if", + "renesas,rcar-gen4-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + csi40: csi2@fe500000 { + compatible = "renesas,r8a779g0-csi2"; + reg = <0 0xfe500000 0 0x40000>; + interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 331>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi40isp0: endpoint { + remote-endpoint = <&isp0csi40>; + }; + }; + }; + }; + + csi41: csi2@fe540000 { + compatible = "renesas,r8a779g0-csi2"; + reg = <0 0xfe540000 0 0x40000>; + interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 400>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 400>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi41isp1: endpoint { + remote-endpoint = <&isp1csi41>; + }; + }; + }; + }; + + fcpvd0: fcp@fea10000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea10000 0 0x200>; + clocks = <&cpg CPG_MOD 508>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 508>; + }; + + fcpvd1: fcp@fea11000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea11000 0 0x200>; + clocks = <&cpg CPG_MOD 509>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 509>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x7000>; + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 830>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 830>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x7000>; + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 831>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 831>; + + renesas,fcp = <&fcpvd1>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a779g0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + isp0: isp@fed00000 { + compatible = "renesas,r8a779g0-isp"; + reg = <0 0xfed00000 0 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cpg CPG_MOD 612>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 612>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp0csi40: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi40isp0>; + }; + }; + + port@1 { + reg = <1>; + isp0vin00: endpoint { + remote-endpoint = <&vin00isp0>; + }; + }; + + port@2 { + reg = <2>; + isp0vin01: endpoint { + remote-endpoint = <&vin01isp0>; + }; + }; + + port@3 { + reg = <3>; + isp0vin02: endpoint { + remote-endpoint = <&vin02isp0>; + }; + }; + + port@4 { + reg = <4>; + isp0vin03: endpoint { + remote-endpoint = <&vin03isp0>; + }; + }; + + port@5 { + reg = <5>; + isp0vin04: endpoint { + remote-endpoint = <&vin04isp0>; + }; + }; + + port@6 { + reg = <6>; + isp0vin05: endpoint { + remote-endpoint = <&vin05isp0>; + }; + }; + + port@7 { + reg = <7>; + isp0vin06: endpoint { + remote-endpoint = <&vin06isp0>; + }; + }; + + port@8 { + reg = <8>; + isp0vin07: endpoint { + remote-endpoint = <&vin07isp0>; + }; + }; + }; + }; + + isp1: isp@fed20000 { + compatible = "renesas,r8a779g0-isp"; + reg = <0 0xfed20000 0 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cpg CPG_MOD 613>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 613>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp1csi41: endpoint@1 { + reg = <1>; + remote-endpoint = <&csi41isp1>; + }; + }; + + port@1 { + reg = <1>; + isp1vin08: endpoint { + remote-endpoint = <&vin08isp1>; + }; + }; + + port@2 { + reg = <2>; + isp1vin09: endpoint { + remote-endpoint = <&vin09isp1>; + }; + }; + + port@3 { + reg = <3>; + isp1vin10: endpoint { + remote-endpoint = <&vin10isp1>; + }; + }; + + port@4 { + reg = <4>; + isp1vin11: endpoint { + remote-endpoint = <&vin11isp1>; + }; + }; + + port@5 { + reg = <5>; + isp1vin12: endpoint { + remote-endpoint = <&vin12isp1>; + }; + }; + + port@6 { + reg = <6>; + isp1vin13: endpoint { + remote-endpoint = <&vin13isp1>; + }; + }; + + port@7 { + reg = <7>; + isp1vin14: endpoint { + remote-endpoint = <&vin14isp1>; + }; + }; + + port@8 { + reg = <8>; + isp1vin15: endpoint { + remote-endpoint = <&vin15isp1>; + }; + }; + }; + }; + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 415>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 416>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + thermal-zones { + sensor_thermal_cr52: sensor1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_cnn: sensor2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_ca76: sensor3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_ddr1: sensor4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 3>; + + trips { + sensor4_crit: sensor4-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/dts/src/arm64/renesas/r8a779m0.dtsi b/dts/src/arm64/renesas/r8a779m0.dtsi index 6fb1979cc0..38978360e7 100644 --- a/dts/src/arm64/renesas/r8a779m0.dtsi +++ b/dts/src/arm64/renesas/r8a779m0.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car H3e (R8A779M0) SoC * diff --git a/dts/src/arm64/renesas/r8a779m1-salvator-xs.dts b/dts/src/arm64/renesas/r8a779m1-salvator-xs.dts index 084b75b046..74b0ac04ff 100644 --- a/dts/src/arm64/renesas/r8a779m1-salvator-xs.dts +++ b/dts/src/arm64/renesas/r8a779m1-salvator-xs.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Salvator-X 2nd version board with R-Car H3e-2G * diff --git a/dts/src/arm64/renesas/r8a779m1-ulcb-kf.dts b/dts/src/arm64/renesas/r8a779m1-ulcb-kf.dts index 0baebc5c58..d2089e1d71 100644 --- a/dts/src/arm64/renesas/r8a779m1-ulcb-kf.dts +++ b/dts/src/arm64/renesas/r8a779m1-ulcb-kf.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the H3ULCB Kingfisher board with R-Car H3e-2G * diff --git a/dts/src/arm64/renesas/r8a779m1-ulcb.dts b/dts/src/arm64/renesas/r8a779m1-ulcb.dts index e294b6bda2..705ea047ef 100644 --- a/dts/src/arm64/renesas/r8a779m1-ulcb.dts +++ b/dts/src/arm64/renesas/r8a779m1-ulcb.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) with R-Car H3e-2G * diff --git a/dts/src/arm64/renesas/r8a779m1.dtsi b/dts/src/arm64/renesas/r8a779m1.dtsi index b6e855f52a..be0219defe 100644 --- a/dts/src/arm64/renesas/r8a779m1.dtsi +++ b/dts/src/arm64/renesas/r8a779m1.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car H3e-2G (R8A779M1) SoC * @@ -12,6 +12,9 @@ }; &cluster0_opp { + opp-1700000000 { + /delete-property/ turbo-mode; + }; opp-2000000000 { opp-hz = /bits/ 64 <2000000000>; opp-microvolt = <960000>; diff --git a/dts/src/arm64/renesas/r8a779m2.dtsi b/dts/src/arm64/renesas/r8a779m2.dtsi index 324627340b..bced12764c 100644 --- a/dts/src/arm64/renesas/r8a779m2.dtsi +++ b/dts/src/arm64/renesas/r8a779m2.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car M3e (R8A779M2) SoC * diff --git a/dts/src/arm64/renesas/r8a779m3-salvator-xs.dts b/dts/src/arm64/renesas/r8a779m3-salvator-xs.dts index 4ab26fd723..e53a6e88cc 100644 --- a/dts/src/arm64/renesas/r8a779m3-salvator-xs.dts +++ b/dts/src/arm64/renesas/r8a779m3-salvator-xs.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Salvator-X 2nd version board with R-Car M3e-2G * diff --git a/dts/src/arm64/renesas/r8a779m3-ulcb-kf.dts b/dts/src/arm64/renesas/r8a779m3-ulcb-kf.dts index 6bacee1d2e..587e8764bc 100644 --- a/dts/src/arm64/renesas/r8a779m3-ulcb-kf.dts +++ b/dts/src/arm64/renesas/r8a779m3-ulcb-kf.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the M3ULCB Kingfisher board with R-Car M3e-2G * diff --git a/dts/src/arm64/renesas/r8a779m3-ulcb.dts b/dts/src/arm64/renesas/r8a779m3-ulcb.dts index 8f215a0b77..413f000b46 100644 --- a/dts/src/arm64/renesas/r8a779m3-ulcb.dts +++ b/dts/src/arm64/renesas/r8a779m3-ulcb.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) with R-Car M3e-2G * diff --git a/dts/src/arm64/renesas/r8a779m3.dtsi b/dts/src/arm64/renesas/r8a779m3.dtsi index 6cff38a6d2..ffde141137 100644 --- a/dts/src/arm64/renesas/r8a779m3.dtsi +++ b/dts/src/arm64/renesas/r8a779m3.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car M3e-2G (R8A779M3) SoC * @@ -12,6 +12,9 @@ }; &cluster0_opp { + opp-1800000000 { + /delete-property/ turbo-mode; + }; opp-2000000000 { opp-hz = /bits/ 64 <2000000000>; opp-microvolt = <960000>; diff --git a/dts/src/arm64/renesas/r8a779m4.dtsi b/dts/src/arm64/renesas/r8a779m4.dtsi index d7fbb6c055..ae84860569 100644 --- a/dts/src/arm64/renesas/r8a779m4.dtsi +++ b/dts/src/arm64/renesas/r8a779m4.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car M3Ne (R8A779M4) SoC * diff --git a/dts/src/arm64/renesas/r8a779m5-salvator-xs.dts b/dts/src/arm64/renesas/r8a779m5-salvator-xs.dts index c0341a88d6..6efc23171a 100644 --- a/dts/src/arm64/renesas/r8a779m5-salvator-xs.dts +++ b/dts/src/arm64/renesas/r8a779m5-salvator-xs.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Salvator-X 2nd version board with R-Car M3Ne-2G * diff --git a/dts/src/arm64/renesas/r8a779m5.dtsi b/dts/src/arm64/renesas/r8a779m5.dtsi index 8c9c0557fe..aded03ad31 100644 --- a/dts/src/arm64/renesas/r8a779m5.dtsi +++ b/dts/src/arm64/renesas/r8a779m5.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car M3Ne-2G (R8A779M5) SoC * @@ -12,6 +12,9 @@ }; &cluster0_opp { + opp-1800000000 { + /delete-property/ turbo-mode; + }; opp-2000000000 { opp-hz = /bits/ 64 <2000000000>; opp-microvolt = <960000>; diff --git a/dts/src/arm64/renesas/r8a779m6.dtsi b/dts/src/arm64/renesas/r8a779m6.dtsi index afe3cabfb8..94d6a6cf50 100644 --- a/dts/src/arm64/renesas/r8a779m6.dtsi +++ b/dts/src/arm64/renesas/r8a779m6.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car E3e (R8A779M6) SoC * diff --git a/dts/src/arm64/renesas/r8a779m7.dtsi b/dts/src/arm64/renesas/r8a779m7.dtsi index 4958babc52..0580fa6140 100644 --- a/dts/src/arm64/renesas/r8a779m7.dtsi +++ b/dts/src/arm64/renesas/r8a779m7.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car D3e (R8A779M7) SoC * diff --git a/dts/src/arm64/renesas/r8a779m8.dtsi b/dts/src/arm64/renesas/r8a779m8.dtsi index 752440b0c4..dfccc080fb 100644 --- a/dts/src/arm64/renesas/r8a779m8.dtsi +++ b/dts/src/arm64/renesas/r8a779m8.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car H3Ne (R8A779M8) SoC * @@ -10,3 +10,8 @@ / { compatible = "renesas,r8a779m8", "renesas,r8a7795"; }; + +&cluster0_opp { + /delete-node/ opp-1600000000; + /delete-node/ opp-1700000000; +}; diff --git a/dts/src/arm64/renesas/r8a779mb.dtsi b/dts/src/arm64/renesas/r8a779mb.dtsi new file mode 100644 index 0000000000..181b737c91 --- /dev/null +++ b/dts/src/arm64/renesas/r8a779mb.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree Source for the R-Car H3Ne-1.7G (R8A779MB) SoC + * + * Copyright (C) 2022 Glider bv + */ + +#include "r8a77951.dtsi" + +/ { + compatible = "renesas,r8a779mb", "renesas,r8a7795"; +}; diff --git a/dts/src/arm64/renesas/r9a07g043-smarc-pmod.dtso b/dts/src/arm64/renesas/r9a07g043-smarc-pmod.dtso new file mode 100644 index 0000000000..4edd103c77 --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g043-smarc-pmod.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/{G2UL, Five} SMARC EVK PMOD parts + * + * Copyright (C) 2023 Renesas Electronics Corp. + * + * + * [Connection] + * + * SMARC EVK + * +----------------------------+ + * |CN7 (PMOD1 PIN HEADER) | + * | SCI0_TXD pin7 | + * | SCI0_RXD pin8 | + * | Gnd pin11 | + * | Vcc pin12 | + * +----------------------------+ + * + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +&pinctrl { + can0-stb-hog { + status = "disabled"; + }; + + can1-stb-hog { + status = "disabled"; + }; + + sci0_pins: sci0-pins { + pinmux = <RZG2L_PORT_PINMUX(2, 2, 5)>, /* TxD */ + <RZG2L_PORT_PINMUX(2, 3, 5)>; /* RxD */ + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/dts/src/arm64/renesas/r9a07g043.dtsi b/dts/src/arm64/renesas/r9a07g043.dtsi new file mode 100644 index 0000000000..8721f4c9fa --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g043.dtsi @@ -0,0 +1,911 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five and RZ/G2UL SoCs + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/r9a07g043-cpg.h> + +/ { + compatible = "renesas,r9a07g043"; + #address-cells = <2>; + #size-cells = <2>; + + audio_clk1: audio1-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + audio_clk2: audio2-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mtu3: timer@10001200 { + compatible = "renesas,r9a07g043-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x10001200 0 0xb00>; + interrupts = <SOC_PERIPHERAL_IRQ(170) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(171) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(172) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(173) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(174) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(175) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(176) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(177) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(178) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(179) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(180) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(181) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(182) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(183) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(184) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(185) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(186) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(187) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(188) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(189) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(190) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(191) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(192) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(193) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(194) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(195) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(196) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(197) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(198) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(199) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(200) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(201) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(202) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(203) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(204) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(205) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(206) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(207) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(208) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(209) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(210) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(211) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(213) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tciv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tciv1", "tciu1", + "tgia2", "tgib2", "tciv2", "tciu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tciv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tciv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tciv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tciv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tciv8", "tciu8"; + clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>; + #pwm-cells = <2>; + status = "disabled"; + }; + + ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x10049c00 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2655>, <&dmac 0x2656>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2659>, <&dmac 0x265a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; + dmas = <&dmac 0x265f>; + dma-names = "rt"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2661>, <&dmac 0x2662>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; + resets = <&cpg R9A07G043_RSPI0_RST>; + dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@1004b000 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b000 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; + resets = <&cpg R9A07G043_RSPI1_RST>; + dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; + resets = <&cpg R9A07G043_RSPI2_RST>; + dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + sci0: serial@1004d000 { + compatible = "renesas,r9a07g043-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g043-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCI1_RST>; + status = "disabled"; + }; + + canfd: can@10050000 { + compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; + reg = <0 0x10050000 0 0x8000>; + interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G043_CANFD_RSTP_N>, + <&cpg R9A07G043_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + }; + + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; + reg = <0 0x10058000 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; + reg = <0 0x10058400 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c3: i2c@10058c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; + reg = <0 0x10058c00 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + adc: adc@10059000 { + compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; + reg = <0 0x10059000 0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G043_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A07G043_ADC_PRESETN>, + <&cpg R9A07G043_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + }; + + tsu: thermal@10059400 { + compatible = "renesas,r9a07g043-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>; + resets = <&cpg R9A07G043_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; + }; + + sbc: spi@10060000 { + compatible = "renesas,r9a07g043-rpc-if", + "renesas,rzg2l-rpc-if"; + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>, + <&cpg CPG_MOD R9A07G043_SPI_CLK>; + resets = <&cpg R9A07G043_SPI_RST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g043-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g043-sysc"; + reg = <0 0x11020000 0 0x10000>; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g043-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 152>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_GPIO_RSTN>, + <&cpg R9A07G043_GPIO_PORT_RESETN>, + <&cpg R9A07G043_GPIO_SPARE_RESETN>; + }; + + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g043-dmac", + "renesas,rz-dmac"; + reg = <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, + <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; + clock-names = "main", "register"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_DMAC_ARESETN>, + <&cpg R9A07G043_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; + #dma-cells = <1>; + dma-channels = <16>; + }; + + sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g043", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c00000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G043_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g043", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c10000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G043_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + phyrst: usbphy-ctrl@11c40000 { + compatible = "renesas,r9a07g043-usbphy-ctrl", + "renesas,rzg2l-usbphy-ctrl"; + reg = <0 0x11c40000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; + resets = <&cpg R9A07G043_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; + }; + + ohci0: usb@11c50000 { + compatible = "generic-ohci"; + reg = <0 0x11c50000 0 0x100>; + interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G043_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@11c70000 { + compatible = "generic-ohci"; + reg = <0 0x11c70000 0 0x100>; + interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G043_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@11c50100 { + compatible = "generic-ehci"; + reg = <0 0x11c50100 0 0x100>; + interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G043_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@11c70100 { + compatible = "generic-ehci"; + reg = <0 0x11c70100 0 0x100>; + interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G043_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@11c50200 { + compatible = "renesas,usb2-phy-r9a07g043", + "renesas,rzg2l-usb2-phy"; + reg = <0 0x11c50200 0 0x700>; + interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; + resets = <&phyrst 0>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@11c70200 { + compatible = "renesas,usb2-phy-r9a07g043", + "renesas,rzg2l-usb2-phy"; + reg = <0 0x11c70200 0 0x700>; + interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; + resets = <&phyrst 1>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + hsusb: usb@11c60000 { + compatible = "renesas,usbhs-r9a07g043", + "renesas,rza2-usbhs"; + reg = <0 0x11c60000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g043-wdt", + "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G043_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G043_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm0: timer@12801000 { + compatible = "renesas,r9a07g043-ostm", + "renesas,ostm"; + reg = <0x0 0x12801000 0x0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; + resets = <&cpg R9A07G043_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@12801400 { + compatible = "renesas,r9a07g043-ostm", + "renesas,ostm"; + reg = <0x0 0x12801400 0x0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; + resets = <&cpg R9A07G043_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@12801800 { + compatible = "renesas,r9a07g043-ostm", + "renesas,ostm"; + reg = <0x0 0x12801800 0x0 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; + resets = <&cpg R9A07G043_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/r9a07g043u.dtsi b/dts/src/arm64/renesas/r9a07g043u.dtsi new file mode 100644 index 0000000000..2ab231572d --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g043u.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include "r9a07g043.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + operating-points-v2 = <&cluster0_opp>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + cache-level = <3>; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pinctrl { + interrupt-parent = <&irqc>; +}; + +&soc { + interrupt-parent = <&gic>; + + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g043u-irqc", + "renesas,rzg2l-irqc"; + reg = <0 0x110a0000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err"; + clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, + <&cpg CPG_MOD R9A07G043_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_IA55_RESETN>; + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&sysc { + interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; +}; diff --git a/dts/src/arm64/renesas/r9a07g043u11-smarc.dts b/dts/src/arm64/renesas/r9a07g043u11-smarc.dts new file mode 100644 index 0000000000..8e0107df2d --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g043u11-smarc.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; + +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) + * Please change below macros according to SW1 setting on the SoM + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + +/* + * To enable MTU3a PWM on PMOD0, + * - Set DIP-Switch SW1-3 to On position. + * - Set PMOD_MTU3 macro to 1. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && !SW_ET0_EN_N) +#error "Cannot set as both PMOD_MTU3 and !SW_ET0_EN_N are mutually exclusive" +#endif + +#include "r9a07g043u.dtsi" +#include "rzg2ul-smarc-som.dtsi" +#include "rzg2ul-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043u11"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; +}; diff --git a/dts/src/arm64/renesas/r9a07g044.dtsi b/dts/src/arm64/renesas/r9a07g044.dtsi index 19287cccb1..66f68fc2b2 100644 --- a/dts/src/arm64/renesas/r9a07g044.dtsi +++ b/dts/src/arm64/renesas/r9a07g044.dtsi @@ -13,14 +13,14 @@ #address-cells = <2>; #size-cells = <2>; - audio_clk1: audio_clk1 { + audio_clk1: audio1-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ clock-frequency = <0>; }; - audio_clk2: audio_clk2 { + audio_clk2: audio2-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ @@ -28,14 +28,14 @@ }; /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { + can_clk: can-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ - extal_clk: extal { + extal_clk: extal-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ @@ -109,6 +109,7 @@ compatible = "cache"; cache-unified; cache-size = <0x40000>; + cache-level = <3>; }; }; @@ -156,6 +157,11 @@ }; }; + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -168,15 +174,84 @@ #size-cells = <2>; ranges; + mtu3: timer@10001200 { + compatible = "renesas,r9a07g044-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x10001200 0 0xb00>; + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tciv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tciv1", "tciu1", + "tgia2", "tgib2", "tciv2", "tciu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tciv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tciv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tciv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tciv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tciv8", "tciu8"; + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; + #pwm-cells = <2>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { compatible = "renesas,r9a07g044-ssi", "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -195,9 +270,8 @@ reg = <0 0x1004a000 0 0x400>; interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -215,10 +289,8 @@ "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + interrupt-names = "int_req", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -237,9 +309,8 @@ reg = <0 0x1004a800 0 0x400>; interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -261,6 +332,8 @@ interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; resets = <&cpg R9A07G044_RSPI0_RST>; + dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; @@ -277,6 +350,8 @@ interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; resets = <&cpg R9A07G044_RSPI1_RST>; + dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; @@ -293,6 +368,8 @@ interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; resets = <&cpg R9A07G044_RSPI2_RST>; + dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; @@ -394,8 +471,8 @@ compatible = "renesas,r9a07g044-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; @@ -409,8 +486,8 @@ compatible = "renesas,r9a07g044-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; @@ -611,6 +688,138 @@ status = "disabled"; }; + cru: video@10830000 { + compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; + reg = <0 0x10830000 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, + <&cpg CPG_MOD R9A07G044_CRU_PCLK>, + <&cpg CPG_MOD R9A07G044_CRU_ACLK>; + clock-names = "video", "apb", "axi"; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + resets = <&cpg R9A07G044_CRU_PRESETN>, + <&cpg R9A07G044_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + cruparallel: endpoint@0 { + reg = <0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi2cru>; + }; + }; + }; + }; + + csi2: csi2@10830400 { + compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2"; + reg = <0 0x10830400 0 0xfc00>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>, + <&cpg CPG_MOD R9A07G044_CRU_VCLK>, + <&cpg CPG_MOD R9A07G044_CRU_PCLK>; + clock-names = "system", "video", "apb"; + resets = <&cpg R9A07G044_CRU_PRESETN>, + <&cpg R9A07G044_CRU_CMN_RSTB>; + reset-names = "presetn", "cmn-rstb"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2cru: endpoint@0 { + reg = <0>; + remote-endpoint = <&crucsi2>; + }; + }; + }; + }; + + dsi: dsi@10850000 { + compatible = "renesas,r9a07g044-mipi-dsi", + "renesas,rzg2l-mipi-dsi"; + reg = <0 0x10850000 0 0x20000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + }; + + vspd: vsp@10870000 { + compatible = "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + + fcpvd: fcp@10880000 { + compatible = "renesas,r9a07g044-fcpvd", + "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -638,6 +847,9 @@ reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-parent = <&irqc>; + interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; power-domains = <&cpg>; @@ -646,6 +858,61 @@ <&cpg R9A07G044_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g044-irqc", + "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x110a0000 0 0x10000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_IA55_RESETN>; + }; + dmac: dma-controller@11820000 { compatible = "renesas,r9a07g044-dmac", "renesas,rz-dmac"; @@ -675,9 +942,11 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; + clock-names = "main", "register"; power-domains = <&cpg>; resets = <&cpg R9A07G044_DMAC_ARESETN>, <&cpg R9A07G044_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; #dma-cells = <1>; dma-channels = <16>; }; @@ -713,7 +982,7 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; - sdhi0: mmc@11c00000 { + sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g044", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; @@ -929,21 +1198,6 @@ status = "disabled"; }; - wdt2: watchdog@12800400 { - compatible = "renesas,r9a07g044-wdt", - "renesas,rzg2l-wdt"; - reg = <0 0x12800400 0 0x400>; - clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>, - <&cpg CPG_MOD R9A07G044_WDT2_CLK>; - clock-names = "pclk", "oscclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "wdt", "perrout"; - resets = <&cpg R9A07G044_WDT2_PRESETN>; - power-domains = <&cpg>; - status = "disabled"; - }; - ostm0: timer@12801000 { compatible = "renesas,r9a07g044-ostm", "renesas,ostm"; @@ -1011,9 +1265,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/dts/src/arm64/renesas/r9a07g044c1.dtsi b/dts/src/arm64/renesas/r9a07g044c1.dtsi index 1d57df7069..56a979e82c 100644 --- a/dts/src/arm64/renesas/r9a07g044c1.dtsi +++ b/dts/src/arm64/renesas/r9a07g044c1.dtsi @@ -15,13 +15,6 @@ /delete-node/ cpu-map; /delete-node/ cpu@100; }; - - timer { - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; &soc { diff --git a/dts/src/arm64/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso b/dts/src/arm64/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso new file mode 100644 index 0000000000..f983bdd3ea --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/G2LC SMARC EVK with + * OV5645 camera connected to CSI and CRU enabled. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +#define OV5645_PARENT_I2C i2c0 +#include "rz-smarc-cru-csi-ov5645.dtsi" + +&ov5645 { + enable-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_HIGH>; + reset-gpios = <&pinctrl RZG2L_GPIO(5, 2) GPIO_ACTIVE_LOW>; +}; diff --git a/dts/src/arm64/renesas/r9a07g044c2-smarc.dts b/dts/src/arm64/renesas/r9a07g044c2-smarc.dts index 5a5cea82a5..0b90367b6d 100644 --- a/dts/src/arm64/renesas/r9a07g044c2-smarc.dts +++ b/dts/src/arm64/renesas/r9a07g044c2-smarc.dts @@ -6,86 +6,52 @@ */ /dts-v1/; -#include "r9a07g044c2.dtsi" -#include "rzg2lc-smarc.dtsi" - -/ { - model = "Renesas SMARC EVK based on r9a07g044c2"; - compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; -}; - -&ehci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ehci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&hsusb { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&i2c0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; -&i2c1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; +/* + * DIP-Switch SW1 setting on SoM + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) + * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) + * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) + * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) + * Please change below macros according to SW1 setting + */ -&i2c3 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; +#define SW_SD0_DEV_SEL 1 -&ohci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; +#define SW_SCIF_CAN 0 +#if (SW_SCIF_CAN) +/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ +#define SW_RSPI_CAN 0 +#else +/* Please set SW_RSPI_CAN. Default value is 1 */ +#define SW_RSPI_CAN 1 +#endif -&ohci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; +#if (SW_SCIF_CAN && SW_RSPI_CAN) +#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" +#endif -&phyrst { - status = "disabled"; -}; +/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 -&spi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; +/* + * To enable MTU3a PWM on PMOD0, + * - Set DIP-Switch SW1-4 to Off position. + * - Set SW_RSPI_CAN macro to 0. + * - Set PMOD_MTU3 macro to 1. + */ +#define PMOD_MTU3 0 -&ssi0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; +#if (PMOD_MTU3 && SW_RSPI_CAN) +#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive" +#endif -&usb2_phy0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; +#include "r9a07g044c2.dtsi" +#include "rzg2lc-smarc-som.dtsi" +#include "rzg2lc-smarc.dtsi" -&usb2_phy1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; +/ { + model = "Renesas SMARC EVK based on r9a07g044c2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; diff --git a/dts/src/arm64/renesas/r9a07g044l1.dtsi b/dts/src/arm64/renesas/r9a07g044l1.dtsi index 9d89d45903..9cf27ca9f1 100644 --- a/dts/src/arm64/renesas/r9a07g044l1.dtsi +++ b/dts/src/arm64/renesas/r9a07g044l1.dtsi @@ -15,11 +15,4 @@ /delete-node/ cpu-map; /delete-node/ cpu@100; }; - - timer { - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; diff --git a/dts/src/arm64/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso b/dts/src/arm64/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso new file mode 100644 index 0000000000..736c1e688c --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/{G2L, V2L} SMARC EVK with OV5645 camera + * connected to CSI and CRU enabled. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +#define OV5645_PARENT_I2C i2c0 +#include "rz-smarc-cru-csi-ov5645.dtsi" + +&ov5645 { + enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>; + reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>; +}; diff --git a/dts/src/arm64/renesas/r9a07g044l2-smarc.dts b/dts/src/arm64/renesas/r9a07g044l2-smarc.dts index bc2af6c92c..568d49cfe4 100644 --- a/dts/src/arm64/renesas/r9a07g044l2-smarc.dts +++ b/dts/src/arm64/renesas/r9a07g044l2-smarc.dts @@ -6,6 +6,27 @@ */ /dts-v1/; + +/* Enable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/* + * To enable MTU3a PWM on PMOD0, + * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and + * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && PMOD1_SER0) +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive " +#endif + +#define MTU3_COUNTER_Z_PHASE_SIGNAL 0 + +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" +#endif + #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/dts/src/arm64/renesas/r9a07g054.dtsi b/dts/src/arm64/renesas/r9a07g054.dtsi index 5d39e765c2..1f1d481dc7 100644 --- a/dts/src/arm64/renesas/r9a07g054.dtsi +++ b/dts/src/arm64/renesas/r9a07g054.dtsi @@ -13,14 +13,14 @@ #address-cells = <2>; #size-cells = <2>; - audio_clk1: audio_clk1 { + audio_clk1: audio1-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ clock-frequency = <0>; }; - audio_clk2: audio_clk2 { + audio_clk2: audio2-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ @@ -28,20 +28,47 @@ }; /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { + can_clk: can-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ - extal_clk: extal { + extal_clk: extal-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +92,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -74,13 +102,64 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { compatible = "cache"; cache-unified; cache-size = <0x40000>; + cache-level = <3>; + }; + }; + + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1100000>; + }; + + opp-62500000 { + opp-hz = /bits/ 64 <62500000>; + opp-microvolt = <1100000>; }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <1100000>; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; psci { @@ -95,17 +174,207 @@ #size-cells = <2>; ranges; + mtu3: timer@10001200 { + compatible = "renesas,r9a07g054-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x10001200 0 0xb00>; + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tciv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tciv1", "tciu1", + "tgia2", "tgib2", "tciv2", "tciu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tciv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tciv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tciv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tciv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tciv8", "tciu8"; + clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>; + #pwm-cells = <2>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2655>, <&dmac 0x2656>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; #sound-dai-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2659>, <&dmac 0x265a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI2_RST_M2_REG>; + dmas = <&dmac 0x265f>; + dma-names = "rt"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2661>, <&dmac 0x2662>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>; + resets = <&cpg R9A07G054_RSPI0_RST>; + dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; spi1: spi@1004b000 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; reg = <0 0x1004b000 0 0x400>; + interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>; + resets = <&cpg R9A07G054_RSPI1_RST>; + dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>; + resets = <&cpg R9A07G054_RSPI2_RST>; + dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; scif0: serial@1004b800 { @@ -207,8 +476,8 @@ compatible = "renesas,r9a07g054-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; @@ -222,8 +491,8 @@ compatible = "renesas,r9a07g054-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; @@ -234,43 +503,327 @@ }; canfd: can@10050000 { + compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - /* place holder */ + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G054_CANFD_RSTP_N>, + <&cpg R9A07G054_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; }; i2c0: i2c@10058000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c1: i2c@10058400 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c3: i2c@10058c00 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; adc: adc@10059000 { + compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G054_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A07G054_ADC_PRESETN>, + <&cpg R9A07G054_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; + }; + + tsu: thermal@10059400 { + compatible = "renesas,r9a07g054-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>; + resets = <&cpg R9A07G054_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; }; sbc: spi@10060000 { + compatible = "renesas,r9a07g054-rpc-if", + "renesas,rzg2l-rpc-if"; reg = <0 0x10060000 0 0x10000>, <0 0x20000000 0 0x10000000>, <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>, + <&cpg CPG_MOD R9A07G054_SPI_CLK>; + resets = <&cpg R9A07G054_SPI_RST>; + power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + cru: video@10830000 { + compatible = "renesas,r9a07g054-cru", "renesas,rzg2l-cru"; + reg = <0 0x10830000 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>, + <&cpg CPG_MOD R9A07G054_CRU_PCLK>, + <&cpg CPG_MOD R9A07G054_CRU_ACLK>; + clock-names = "video", "apb", "axi"; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + resets = <&cpg R9A07G054_CRU_PRESETN>, + <&cpg R9A07G054_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + cruparallel: endpoint@0 { + reg = <0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi2cru>; + }; + }; + }; + }; + + csi2: csi2@10830400 { + compatible = "renesas,r9a07g054-csi2", "renesas,rzg2l-csi2"; + reg = <0 0x10830400 0 0xfc00>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>, + <&cpg CPG_MOD R9A07G054_CRU_VCLK>, + <&cpg CPG_MOD R9A07G054_CRU_PCLK>; + clock-names = "system", "video", "apb"; + resets = <&cpg R9A07G054_CRU_PRESETN>, + <&cpg R9A07G054_CRU_CMN_RSTB>; + reset-names = "presetn", "cmn-rstb"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2cru: endpoint@0 { + reg = <0>; + remote-endpoint = <&crucsi2>; + }; + }; + }; + }; + + dsi: dsi@10850000 { + compatible = "renesas,r9a07g054-mipi-dsi", + "renesas,rzg2l-mipi-dsi"; + reg = <0 0x10850000 0 0x20000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G054_MIPI_DSI_ARESET_N>, + <&cpg R9A07G054_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + }; + + vspd: vsp@10870000 { + compatible = "renesas,r9a07g054-vsp2", + "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + + fcpvd: fcp@10880000 { + compatible = "renesas,r9a07g054-fcpvd", + "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; }; cpg: clock-controller@11010000 { @@ -301,6 +854,9 @@ reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-parent = <&irqc>; + interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; power-domains = <&cpg>; @@ -309,6 +865,61 @@ <&cpg R9A07G054_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g054-irqc", + "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x110a0000 0 0x10000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>, + <&cpg CPG_MOD R9A07G054_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_IA55_RESETN>; + }; + dmac: dma-controller@11820000 { compatible = "renesas,r9a07g054-dmac", "renesas,rz-dmac"; @@ -338,16 +949,34 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; + clock-names = "main", "register"; power-domains = <&cpg>; resets = <&cpg R9A07G054_DMAC_ARESETN>, <&cpg R9A07G054_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; #dma-cells = <1>; dma-channels = <16>; }; gpu: gpu@11840000 { + compatible = "renesas,r9a07g054-mali", + "arm,mali-bifrost"; reg = <0x0 0x11840000 0x0 0x10000>; - /* place holder */ + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_GPU_RESETN>, + <&cpg R9A07G054_GPU_AXI_RESETN>, + <&cpg R9A07G054_GPU_ACE_RESETN>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; }; gic: interrupt-controller@11900000 { @@ -360,14 +989,36 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; - sdhi0: mmc@11c00000 { + sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - /* place holder */ + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - /* place holder */ + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; eth0: ethernet@11c20000 { @@ -411,81 +1062,219 @@ }; phyrst: usbphy-ctrl@11c40000 { + compatible = "renesas,r9a07g054-usbphy-ctrl", + "renesas,rzg2l-usbphy-ctrl"; reg = <0 0x11c40000 0 0x10000>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>; + resets = <&cpg R9A07G054_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; }; ohci0: usb@11c50000 { + compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - /* place holder */ + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ohci1: usb@11c70000 { + compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - /* place holder */ + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ehci0: usb@11c50100 { + compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - /* place holder */ + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; }; ehci1: usb@11c70100 { + compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - /* place holder */ + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy0: usb-phy@11c50200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - /* place holder */ + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy1: usb-phy@11c70200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - /* place holder */ + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; hsusb: usb@11c60000 { + compatible = "renesas,usbhs-r9a07g054", + "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - /* place holder */ + interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800800 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt1: watchdog@12800c00 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800C00 0 0x400>; - /* place holder */ - }; - - wdt2: watchdog@12800400 { - reg = <0 0x12800400 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT1_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT1_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; ostm0: timer@12801000 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>; + resets = <&cpg R9A07G054_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm1: timer@12801400 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>; + resets = <&cpg R9A07G054_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm2: timer@12801800 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>; + resets = <&cpg R9A07G054_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; }; }; timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/dts/src/arm64/renesas/r9a07g054l1.dtsi b/dts/src/arm64/renesas/r9a07g054l1.dtsi index c448cc6634..d85a6ac0f0 100644 --- a/dts/src/arm64/renesas/r9a07g054l1.dtsi +++ b/dts/src/arm64/renesas/r9a07g054l1.dtsi @@ -15,11 +15,4 @@ /delete-node/ cpu-map; /delete-node/ cpu@100; }; - - timer { - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; diff --git a/dts/src/arm64/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso b/dts/src/arm64/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso new file mode 100644 index 0000000000..736c1e688c --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/{G2L, V2L} SMARC EVK with OV5645 camera + * connected to CSI and CRU enabled. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +#define OV5645_PARENT_I2C i2c0 +#include "rz-smarc-cru-csi-ov5645.dtsi" + +&ov5645 { + enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>; + reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>; +}; diff --git a/dts/src/arm64/renesas/r9a07g054l2-smarc.dts b/dts/src/arm64/renesas/r9a07g054l2-smarc.dts index fc334b4c2a..b3e6016880 100644 --- a/dts/src/arm64/renesas/r9a07g054l2-smarc.dts +++ b/dts/src/arm64/renesas/r9a07g054l2-smarc.dts @@ -1,11 +1,31 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC EVK board + * Device Tree Source for the RZ/V2L SMARC EVK board * * Copyright (C) 2021 Renesas Electronics Corp. */ /dts-v1/; + +/* Enable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/* + * To enable MTU3a PWM on PMOD0, + * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and + * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && PMOD1_SER0) +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive " +#endif + +#define MTU3_COUNTER_Z_PHASE_SIGNAL 0 +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" +#endif + #include "r9a07g054l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" @@ -16,11 +36,3 @@ model = "Renesas SMARC EVK based on r9a07g054l2"; compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054"; }; - -&pinctrl { - /delete-node/ can0-stb-hog; - /delete-node/ can1-stb-hog; - /delete-node/ gpio-sd0-pwr-en-hog; - /delete-node/ sd0-dev-sel-hog; - /delete-node/ sd1-pwr-en-hog; -}; diff --git a/dts/src/arm64/renesas/r9a08g045.dtsi b/dts/src/arm64/renesas/r9a08g045.dtsi new file mode 100644 index 0000000000..5facfad961 --- /dev/null +++ b/dts/src/arm64/renesas/r9a08g045.dtsi @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a08g045-cpg.h> + +/ { + compatible = "renesas,r9a08g045"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x40000>; + }; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a08g045-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a08g045-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a08g045-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&irqc>; + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_GPIO_RSTN>, + <&cpg R9A08G045_GPIO_PORT_RESETN>, + <&cpg R9A08G045_GPIO_SPARE_RESETN>; + }; + + irqc: interrupt-controller@11050000 { + compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x11050000 0 0x10000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err"; + clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, + <&cpg CPG_MOD R9A08G045_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_IA55_RESETN>; + }; + + sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c00000 0 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c10000 0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi2: mmc@11c20000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c20000 0 0x10000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI2_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + eth0: ethernet@11c30000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c40000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c40000 0 0x10000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@12400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x12400000 0 0x40000>, + <0x0 0x12440000 0 0x60000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/dts/src/arm64/renesas/r9a08g045s33-smarc.dts b/dts/src/arm64/renesas/r9a08g045s33-smarc.dts new file mode 100644 index 0000000000..6b57e0e02d --- /dev/null +++ b/dts/src/arm64/renesas/r9a08g045s33-smarc.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SMARC EVK board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a08g045s33.dtsi" +#include "rzg3s-smarc-som.dtsi" +#include "rzg3s-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK version 2 based on r9a08g045s33"; + compatible = "renesas,smarc2-evk", "renesas,rzg3s-smarcm", + "renesas,r9a08g045s33", "renesas,r9a08g045"; +}; diff --git a/dts/src/arm64/renesas/r9a08g045s33.dtsi b/dts/src/arm64/renesas/r9a08g045s33.dtsi new file mode 100644 index 0000000000..3351f26c7a --- /dev/null +++ b/dts/src/arm64/renesas/r9a08g045s33.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S R9A08G045S33 SoC specific part + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a08g045.dtsi" + +/ { + compatible = "renesas,r9a08g045s33", "renesas,r9a08g045"; +}; diff --git a/dts/src/arm64/renesas/r9a09g011-v2mevk2.dts b/dts/src/arm64/renesas/r9a09g011-v2mevk2.dts new file mode 100644 index 0000000000..39fe3f9499 --- /dev/null +++ b/dts/src/arm64/renesas/r9a09g011-v2mevk2.dts @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g011.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzv2m-pinctrl.h> + +/ { + model = "RZ/V2M Evaluation Kit 2.0"; + compatible = "renesas,rzv2mevk2", "renesas,r9a09g011"; + + aliases { + serial0 = &uart0; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + + memory@58000000 { + device_type = "memory"; + /* + * first 1.25GiB is reserved for ISP Firmware, + * next 128MiB is reserved for secure area. + */ + reg = <0x0 0x58000000 0x0 0x28000000>; + }; + + memory@180000000 { + device_type = "memory"; + reg = <0x1 0x80000000 0x0 0x80000000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&pwc 0 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 0>, <1800000 1>; + }; +}; + +&avb { + renesas,no-ether-link; + phy-handle = <&phy0>; + phy-mode = "gmii"; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&emmc { + pinctrl-0 = <&emmc_pins>; + pinctrl-1 = <&emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_1v8>; + bus-width = <8>; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + fixed-emmc-driver-type = <1>; + max-frequency = <200000000>; + status = "okay"; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + hd3ss3220@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&pinctrl { + emmc_pins: emmc { + data { + pinmux = <RZV2M_PORT_PINMUX(0, 0, 2)>, /* MMDAT0 */ + <RZV2M_PORT_PINMUX(0, 1, 2)>, /* MMDAT1 */ + <RZV2M_PORT_PINMUX(0, 2, 2)>, /* MMDAT2 */ + <RZV2M_PORT_PINMUX(0, 3, 2)>, /* MMDAT3 */ + <RZV2M_PORT_PINMUX(0, 4, 2)>, /* MMDAT4 */ + <RZV2M_PORT_PINMUX(0, 5, 2)>, /* MMDAT5 */ + <RZV2M_PORT_PINMUX(0, 6, 2)>, /* MMDAT6 */ + <RZV2M_PORT_PINMUX(0, 7, 2)>; /* MMDAT7 */ + power-source = <1800>; + }; + + ctrl { + pinmux = <RZV2M_PORT_PINMUX(0, 10, 2)>, /* MMCMD */ + <RZV2M_PORT_PINMUX(0, 11, 2)>; /* MMCLK */ + power-source = <1800>; + }; + }; + + i2c0_pins: i2c0 { + pinmux = <RZV2M_PORT_PINMUX(5, 0, 2)>, /* SDA */ + <RZV2M_PORT_PINMUX(5, 1, 2)>; /* SCL */ + }; + + i2c2_pins: i2c2 { + pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */ + <RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */ + }; + + sdhi0_pins: sd0 { + data { + pinmux = <RZV2M_PORT_PINMUX(8, 2, 1)>, /* SD0DAT0 */ + <RZV2M_PORT_PINMUX(8, 3, 1)>, /* SD0DAT1 */ + <RZV2M_PORT_PINMUX(8, 4, 1)>, /* SD0DAT2 */ + <RZV2M_PORT_PINMUX(8, 5, 1)>; /* SD0DAT3 */ + power-source = <3300>; + }; + + ctrl { + pinmux = <RZV2M_PORT_PINMUX(8, 0, 1)>, /* SD0CMD */ + <RZV2M_PORT_PINMUX(8, 1, 1)>; /* SD0CLK */ + power-source = <3300>; + }; + + cd { + pinmux = <RZV2M_PORT_PINMUX(8, 7, 1)>; /* SD0CD */ + power-source = <3300>; + }; + }; + + sdhi0_pins_uhs: sd0-uhs { + data { + pinmux = <RZV2M_PORT_PINMUX(8, 2, 1)>, /* SD0DAT0 */ + <RZV2M_PORT_PINMUX(8, 3, 1)>, /* SD0DAT1 */ + <RZV2M_PORT_PINMUX(8, 4, 1)>, /* SD0DAT2 */ + <RZV2M_PORT_PINMUX(8, 5, 1)>; /* SD0DAT3 */ + power-source = <1800>; + }; + + ctrl { + pinmux = <RZV2M_PORT_PINMUX(8, 0, 1)>, /* SD0CMD */ + <RZV2M_PORT_PINMUX(8, 1, 1)>; /* SD0CLK */ + power-source = <1800>; + }; + + cd { + pinmux = <RZV2M_PORT_PINMUX(8, 7, 1)>; /* SD0CD */ + power-source = <1800>; + }; + }; + + uart0_pins: uart0 { + pinmux = <RZV2M_PORT_PINMUX(3, 0, 2)>, /* UATX0 */ + <RZV2M_PORT_PINMUX(3, 1, 2)>, /* UARX0 */ + <RZV2M_PORT_PINMUX(3, 2, 2)>, /* UACTS0N */ + <RZV2M_PORT_PINMUX(3, 3, 2)>; /* UARTS0N */ + }; +}; + +&pwc { + renesas,rzv2m-pwc-power; + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3v3>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&usb3drd { + status = "okay"; +}; + +&usb3host { + status = "okay"; +}; + +&usb3peri { + companion = <&usb3host>; + status = "okay"; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&wdt0 { + status = "okay"; +}; diff --git a/dts/src/arm64/renesas/r9a09g011.dtsi b/dts/src/arm64/renesas/r9a09g011.dtsi new file mode 100644 index 0000000000..50ed66d42a --- /dev/null +++ b/dts/src/arm64/renesas/r9a09g011.dtsi @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a09g011-cpg.h> + +/ { + compatible = "renesas,r9a09g011"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L2_CA53>; + clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; + }; + + L2_CA53: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@82010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x82010000 0 0x1000>, + <0x0 0x82020000 0 0x20000>, + <0x0 0x82040000 0 0x20000>, + <0x0 0x82060000 0 0x20000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; + clock-names = "clk"; + }; + + sdhi0: mmc@85000000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85000000 0 0x2000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>, + <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>, + <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>, + <&cpg CPG_MOD R9A09G011_SDI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_SDI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@85010000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85010000 0 0x2000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>, + <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>, + <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>, + <&cpg CPG_MOD R9A09G011_SDI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_SDI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + emmc: mmc@85020000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85020000 0 0x2000>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>, + <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>, + <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>, + <&cpg CPG_MOD R9A09G011_EMM_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_EMM_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb3drd: usb3drd@85070400 { + compatible = "renesas,r9a09g011-usb3drd", + "renesas,rzv2m-usb3drd"; + reg = <0x0 0x85070400 0x0 0x100>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "drd", "bc", "gpi"; + clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>, + <&cpg CPG_MOD R9A09G011_USB_PCLK>; + clock-names = "axi", "reg"; + resets = <&cpg R9A09G011_USB_DRD_RESET>; + power-domains = <&cpg>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + usb3host: usb@85060000 { + compatible = "renesas,r9a09g011-xhci", + "renesas,rzv2m-xhci"; + reg = <0 0x85060000 0 0x2000>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>, + <&cpg CPG_MOD R9A09G011_USB_PCLK>; + clock-names = "axi", "reg"; + resets = <&cpg R9A09G011_USB_ARESETN_H>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb3peri: usb3peri@85070000 { + compatible = "renesas,r9a09g011-usb3-peri", + "renesas,rzv2m-usb3-peri"; + reg = <0x0 0x85070000 0x0 0x400>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>, + <&cpg CPG_MOD R9A09G011_USB_PCLK>; + clock-names = "axi", "reg"; + resets = <&cpg R9A09G011_USB_ARESETN_P>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + + avb: ethernet@a3300000 { + compatible = "renesas,etheravb-r9a09g011", "renesas,etheravb-rzv2m"; + reg = <0 0xa3300000 0 0x800>; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */ + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */ + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */ + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */ + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */ + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */ + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */ + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */ + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */ + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */ + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */ + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "dia", "dib", + "err_a", "err_b", "mgmt_a", "mgmt_b", + "line3"; + clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>; + clock-names = "axi", "chi", "gptp"; + resets = <&cpg R9A09G011_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + cpg: clock-controller@a3500000 { + compatible = "renesas,r9a09g011-cpg"; + reg = <0 0xa3500000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + pwc: pwc@a3700000 { + compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc"; + reg = <0 0xa3700000 0 0x800>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + sys: system-controller@a3f03000 { + compatible = "renesas,r9a09g011-sys"; + reg = <0 0xa3f03000 0 0x400>; + }; + + csi0: spi@a4020000 { + compatible = "renesas,rzv2m-csi"; + reg = <0 0xa4020000 0 0x80>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>, + <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>; + clock-names = "csiclk", "pclk"; + resets = <&cpg R9A09G011_CSI_GPG_PRESETN>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + csi4: spi@a4020200 { + compatible = "renesas,rzv2m-csi"; + reg = <0 0xa4020200 0 0x80>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>, + <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>; + clock-names = "csiclk", "pclk"; + resets = <&cpg R9A09G011_CSI_GPH_PRESETN>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@a4030000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; + reg = <0 0xa4030000 0 0x80>; + interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tia", "tis"; + clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>; + resets = <&cpg R9A09G011_IIC_GPA_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@a4030100 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; + reg = <0 0xa4030100 0 0x80>; + interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tia", "tis"; + clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>; + resets = <&cpg R9A09G011_IIC_GPB_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + uart0: serial@a4040000 { + compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; + reg = <0 0xa4040000 0 0x80>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>, + <&cpg CPG_MOD R9A09G011_URT_PCLK>; + clock-names = "sclk", "pclk"; + status = "disabled"; + }; + + wdt0: watchdog@a4050000 { + compatible = "renesas,r9a09g011-wdt", + "renesas,rzv2m-wdt"; + reg = <0 0xa4050000 0 0x80>; + clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>, + <&cpg CPG_MOD R9A09G011_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + resets = <&cpg R9A09G011_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + pinctrl: pinctrl@b6250000 { + compatible = "renesas,r9a09g011-pinctrl"; + reg = <0 0xb6250000 0 0x800>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 352>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A09G011_PFC_PRESETN>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/dts/src/arm64/renesas/rz-smarc-common.dtsi b/dts/src/arm64/renesas/rz-smarc-common.dtsi index 588117aafa..b7a3e6caa3 100644 --- a/dts/src/arm64/renesas/rz-smarc-common.dtsi +++ b/dts/src/arm64/renesas/rz-smarc-common.dtsi @@ -26,19 +26,12 @@ serial0 = &scif0; i2c0 = &i2c0; i2c1 = &i2c1; - i2c3 = &i2c3; }; chosen { stdout-path = "serial0:115200n8"; }; - audio_mclock: audio_mclock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - snd_rzg2l: sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -53,11 +46,10 @@ "Mic Bias", "Microphone Jack"; cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi0>; }; codec_dai: simple-audio-card,codec { - clocks = <&audio_mclock>; + clocks = <&versa3 2>; sound-dai = <&wm8978>; }; }; @@ -75,17 +67,22 @@ regulator-name = "SDHI1 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; + + x1: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; -&audio_clk1{ +&audio_clk1 { clock-frequency = <11289600>; }; -&audio_clk2{ +&audio_clk2 { clock-frequency = <12288000>; }; @@ -131,20 +128,6 @@ status = "okay"; }; -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - status = "okay"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - &ohci0 { dr_mode = "otg"; status = "okay"; @@ -184,13 +167,6 @@ status = "okay"; }; -&ssi0 { - pinctrl-0 = <&ssi0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; diff --git a/dts/src/arm64/renesas/rz-smarc-cru-csi-ov5645.dtsi b/dts/src/arm64/renesas/rz-smarc-cru-csi-ov5645.dtsi new file mode 100644 index 0000000000..c5bb63c63b --- /dev/null +++ b/dts/src/arm64/renesas/rz-smarc-cru-csi-ov5645.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common Device Tree for the RZ/G2L SMARC EVK (and alike EVKs) with + * OV5645 camera connected to CSI and CRU enabled. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +&{/} { + ov5645_vdddo_1v8: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ov5645_vdda_2v8: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ov5645_vddd_1v5: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + ov5645_fixed_clk: osc25250-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&cru { + status = "okay"; +}; + +&csi2 { + status = "okay"; + + ports { + port@0 { + csi2_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5645_ep>; + }; + }; + }; +}; + +&OV5645_PARENT_I2C { + #address-cells = <1>; + #size-cells = <0>; + + ov5645: camera@3c { + compatible = "ovti,ov5645"; + reg = <0x3c>; + clocks = <&ov5645_fixed_clk>; + clock-frequency = <24000000>; + vdddo-supply = <&ov5645_vdddo_1v8>; + vdda-supply = <&ov5645_vdda_2v8>; + vddd-supply = <&ov5645_vddd_1v5>; + + port { + ov5645_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2_in>; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/rzg2l-smarc-pinfunction.dtsi b/dts/src/arm64/renesas/rzg2l-smarc-pinfunction.dtsi index 9085d8c76c..18c526c7a4 100644 --- a/dts/src/arm64/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/dts/src/arm64/renesas/rzg2l-smarc-pinfunction.dtsi @@ -53,6 +53,26 @@ <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */ }; + mtu3_pins: mtu3 { + mtu3-ext-clk-input-pin { + pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */ + <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */ + }; + + mtu3-pwm { + pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */ + <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */ + <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */ + <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */ + }; + +#if MTU3_COUNTER_Z_PHASE_SIGNAL + mtu3-zphase-clk { + pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */ + }; +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ + }; + scif0_pins: scif0 { pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ diff --git a/dts/src/arm64/renesas/rzg2l-smarc-som.dtsi b/dts/src/arm64/renesas/rzg2l-smarc-som.dtsi index aeacd22e9e..4409c47239 100644 --- a/dts/src/arm64/renesas/rzg2l-smarc-som.dtsi +++ b/dts/src/arm64/renesas/rzg2l-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */ @@ -34,7 +35,7 @@ reg = <0x0 0x48000000 0x0 0x78000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -43,7 +44,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -72,6 +73,13 @@ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; regulator-always-on; }; + + /* 32.768kHz crystal */ + x2: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; &adc { @@ -94,10 +102,12 @@ compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -120,10 +130,12 @@ compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -143,6 +155,17 @@ mali-supply = <®_1p1v>; }; +&i2c3 { + raa215300: pmic@12 { + compatible = "renesas,raa215300"; + reg = <0x12>, <0x6f>; + reg-names = "main", "rtc"; + + clocks = <&x2>; + clock-names = "xin"; + }; +}; + &ostm1 { status = "okay"; }; @@ -171,7 +194,8 @@ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ }; eth1_pins: eth1 { @@ -189,7 +213,8 @@ <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ - <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ }; gpio-sd0-pwr-en-hog { @@ -287,6 +312,7 @@ m25p,fast-read; spi-max-frequency = <50000000>; spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; partitions { compatible = "fixed-partitions"; @@ -344,8 +370,3 @@ status = "okay"; timeout-sec = <60>; }; - -&wdt2 { - status = "okay"; - timeout-sec = <60>; -}; diff --git a/dts/src/arm64/renesas/rzg2l-smarc.dtsi b/dts/src/arm64/renesas/rzg2l-smarc.dtsi index 33ddfd18bd..37807f1bda 100644 --- a/dts/src/arm64/renesas/rzg2l-smarc.dtsi +++ b/dts/src/arm64/renesas/rzg2l-smarc.dtsi @@ -8,15 +8,150 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> -/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ -#define PMOD1_SER0 1 - / { aliases { serial1 = &scif2; + i2c3 = &i2c3; + }; + + osc1: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; +}; + +&cpu_dai { + sound-dai = <&ssi0>; +}; + +&dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&i2c1 { + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + + interrupt-parent = <&pinctrl>; + interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>; + clocks = <&osc1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +#if MTU3_COUNTER_Z_PHASE_SIGNAL +/* SDHI cd pin is muxed with counter Z phase signal */ +&sdhi1 { + status = "disabled"; +}; +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ + +&spi1 { + status = "disabled"; +}; +#endif /* PMOD_MTU3 */ + /* * To enable SCIF2 (SER0) on PMOD1 (CN7) * SW1 should be at position 2->3 so that SER0_CTS# line is activated @@ -33,3 +168,14 @@ status = "okay"; }; #endif + +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; +}; diff --git a/dts/src/arm64/renesas/rzg2lc-smarc-pinfunction.dtsi b/dts/src/arm64/renesas/rzg2lc-smarc-pinfunction.dtsi index 37ff209158..92c64d5834 100644 --- a/dts/src/arm64/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/dts/src/arm64/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -12,11 +12,6 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; - scif0_pins: scif0 { - pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ - <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ - }; - #if SW_SCIF_CAN /* SW8 should be at position 2->1 */ can1_pins: can1 { @@ -25,13 +20,6 @@ }; #endif - scif1_pins: scif1 { - pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */ - <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */ - <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */ - <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */ - }; - #if SW_RSPI_CAN /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ can1-stb-hog { @@ -47,6 +35,42 @@ }; #endif + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */ + <RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */ + }; + + mtu3_pins: mtu3 { + mtu3-pwm { + pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */ + <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */ + <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */ + <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */ + }; + }; + + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ + }; + + scif1_pins: scif1 { + pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */ + <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */ + <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>; @@ -90,5 +114,30 @@ pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; }; + + spi1_pins: spi1 { + pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */ + <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */ + <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */ + <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */ + }; + + ssi0_pins: ssi0 { + pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */ + <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */ + <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */ + <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */ + }; + + usb0_pins: usb0 { + pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */ + <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */ + <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */ + <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */ + }; }; diff --git a/dts/src/arm64/renesas/rzg2lc-smarc-som.dtsi b/dts/src/arm64/renesas/rzg2lc-smarc-som.dtsi index 88a7938017..5e4209d6fb 100644 --- a/dts/src/arm64/renesas/rzg2lc-smarc-som.dtsi +++ b/dts/src/arm64/renesas/rzg2lc-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> / { @@ -23,7 +24,7 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -32,7 +33,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -41,6 +42,15 @@ regulator-always-on; }; + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; @@ -52,6 +62,13 @@ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; regulator-always-on; }; + + /* 32.768kHz crystal */ + x2: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; ð0 { @@ -65,10 +82,12 @@ compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -84,6 +103,29 @@ clock-frequency = <24000000>; }; +&gpu { + mali-supply = <®_1p1v>; +}; + +&i2c2 { + raa215300: pmic@12 { + compatible = "renesas,raa215300"; + reg = <0x12>, <0x6f>; + reg-names = "main", "rtc"; + + clocks = <&x2>; + clock-names = "xin"; + }; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + &pinctrl { eth0_pins: eth0 { pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ @@ -100,7 +142,8 @@ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */ }; gpio-sd0-pwr-en-hog { @@ -110,6 +153,18 @@ line-name = "gpio_sd0_pwr_en"; }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; + power-source = <1800>; + }; + }; + /* * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] * The below switch logic can be used to select the device between @@ -175,6 +230,35 @@ }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu512a", "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x2000000>; + read-only; + }; + user@2000000 { + reg = <0x2000000 0x2000000>; + }; + }; + }; +}; + #if (!SW_SD0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_pins>; @@ -215,8 +299,3 @@ status = "okay"; timeout-sec = <60>; }; - -&wdt2 { - status = "okay"; - timeout-sec = <60>; -}; diff --git a/dts/src/arm64/renesas/rzg2lc-smarc.dtsi b/dts/src/arm64/renesas/rzg2lc-smarc.dtsi index df7631fe5f..859bc8745e 100644 --- a/dts/src/arm64/renesas/rzg2lc-smarc.dtsi +++ b/dts/src/arm64/renesas/rzg2lc-smarc.dtsi @@ -8,41 +8,30 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> -/* - * DIP-Switch SW1 setting on SoM - * 1 : High; 0: Low - * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) - * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) - * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) - * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) - * Please change below macros according to SW1 setting - */ - -#define SW_SD0_DEV_SEL 1 - -#define SW_SCIF_CAN 0 -#if (SW_SCIF_CAN) -/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ -#define SW_RSPI_CAN 0 -#else -/* Please set SW_RSPI_CAN. Default value is 1 */ -#define SW_RSPI_CAN 1 -#endif - -#if (SW_SCIF_CAN & SW_RSPI_CAN) -#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" -#endif - -#include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" -/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ -#define PMOD1_SER0 1 - / { aliases { serial1 = &scif1; + i2c2 = &i2c2; + }; + + osc1: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; }; }; @@ -59,6 +48,119 @@ }; #endif +&cpu_dai { + sound-dai = <&ssi0>; +}; + +&dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&i2c1 { + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + + interrupt-parent = <&pinctrl>; + interrupts = <RZG2L_GPIO(43, 1) IRQ_TYPE_EDGE_FALLING>; + clocks = <&osc1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; +}; + +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&spi1 { + status = "disabled"; +}; +#endif + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated @@ -75,3 +177,22 @@ status = "okay"; }; #endif + +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +#if (SW_RSPI_CAN) +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; +}; diff --git a/dts/src/arm64/renesas/rzg2ul-smarc-pinfunction.dtsi b/dts/src/arm64/renesas/rzg2ul-smarc-pinfunction.dtsi new file mode 100644 index 0000000000..355694fe4a --- /dev/null +++ b/dts/src/arm64/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SMARC pincontrol parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +&pinctrl { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + can0_pins: can0 { + pinmux = <RZG2L_PORT_PINMUX(1, 1, 3)>, /* TX */ + <RZG2L_PORT_PINMUX(1, 2, 3)>; /* RX */ + }; + +#if (SW_ET0_EN_N) + can0-stb-hog { + gpio-hog; + gpios = <RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "can0_stb"; + }; +#endif + + can1_pins: can1 { + pinmux = <RZG2L_PORT_PINMUX(2, 0, 3)>, /* TX */ + <RZG2L_PORT_PINMUX(2, 1, 3)>; /* RX */ + }; + +#if (SW_ET0_EN_N) + can1-stb-hog { + gpio-hog; + gpios = <RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "can1_stb"; + }; +#endif + + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + mtu3_pins: mtu3 { + mtu2-pwm { + pinmux = <RZG2L_PORT_PINMUX(4, 0, 4)>; /* MTIOC2A */ + }; + }; + + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */ + <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */ + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */ + }; + }; + + sound_clk_pins: sound_clk { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; + + spi1_pins: spi1 { + pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */ + <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */ + <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */ + <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */ + }; + + ssi1_pins: ssi1 { + pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* BCK */ + <RZG2L_PORT_PINMUX(3, 1, 2)>, /* RCK */ + <RZG2L_PORT_PINMUX(3, 2, 2)>, /* TXD */ + <RZG2L_PORT_PINMUX(3, 3, 2)>; /* RXD */ + }; + + usb0_pins: usb0 { + pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>, /* VBUS */ + <RZG2L_PORT_PINMUX(5, 2, 1)>, /* OVC */ + <RZG2L_PORT_PINMUX(5, 3, 1)>; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = <RZG2L_PORT_PINMUX(5, 4, 5)>, /* OVC */ + <RZG2L_PORT_PINMUX(6, 0, 1)>; /* VBUS */ + }; +}; diff --git a/dts/src/arm64/renesas/rzg2ul-smarc-som.dtsi b/dts/src/arm64/renesas/rzg2ul-smarc-som.dtsi new file mode 100644 index 0000000000..97cdad2a12 --- /dev/null +++ b/dts/src/arm64/renesas/rzg2ul-smarc-som.dtsi @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SMARC SOM common parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/ { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + +#if !(SW_SW0_DEV_SEL) + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1>, <1800000 0>; + regulator-boot-on; + gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; +#endif +}; + +#if (SW_SW0_DEV_SEL) +&adc { + pinctrl-0 = <&adc_pins>; + pinctrl-names = "default"; + status = "okay"; +}; +#endif + +#if (!SW_ET0_EN_N) +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; +#endif + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&pinctrl { + adc_pins: adc { + pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */ + }; + + eth0_pins: eth0 { + pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */ + <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */ + <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */ + <RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */ + <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */ + <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */ + <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */ + <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */ + <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */ + <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */ + <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */ + <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */ + <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */ + <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */ + <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */ + }; + + eth1_pins: eth1 { + pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */ + <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */ + <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */ + <RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */ + <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */ + <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */ + <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */ + <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */ + <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */ + <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */ + <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */ + <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */ + <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */ + <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */ + <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */ + }; + + sdhi0_emmc_pins: sd0emmc { + sd0_emmc_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_emmc_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_emmc_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + sd0_mux { + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + sd0_ctrl_uhs { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_mux_uhs { + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ + }; + }; +}; + +#if (SW_SW0_DEV_SEL) +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; +#else +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif + +&wdt0 { + status = "okay"; + timeout-sec = <60>; +}; diff --git a/dts/src/arm64/renesas/rzg2ul-smarc.dtsi b/dts/src/arm64/renesas/rzg2ul-smarc.dtsi new file mode 100644 index 0000000000..de590996e1 --- /dev/null +++ b/dts/src/arm64/renesas/rzg2ul-smarc.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include "rzg2ul-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" + +#if (!SW_ET0_EN_N) +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + +&cpu_dai { + sound-dai = <&ssi1>; +}; + +&i2c0 { + clock-frequency = <400000>; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; +}; + +&i2c1 { + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&spi1 { + status = "disabled"; +}; +#endif + +#if (SW_ET0_EN_N) +&ssi1 { + pinctrl-0 = <&ssi1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#else +&snd_rzg2l { + status = "disabled"; +}; + +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ssi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>; +}; diff --git a/dts/src/arm64/renesas/rzg3s-smarc-som.dtsi b/dts/src/arm64/renesas/rzg3s-smarc-som.dtsi new file mode 100644 index 0000000000..f062d4ad78 --- /dev/null +++ b/dts/src/arm64/renesas/rzg3s-smarc-som.dtsi @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/* + * On-board switches' states: + * @SW_OFF: switch's state is OFF + * @SW_ON: switch's state is ON + */ +#define SW_OFF 0 +#define SW_ON 1 + +/* + * SW_CONFIG[x] switches' states: + * @SW_CONFIG2: + * SW_OFF - SD0 is connected to eMMC + * SW_ON - SD0 is connected to uSD0 card + * @SW_CONFIG3: + * SW_OFF - SD2 is connected to SoC + * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + */ +#define SW_CONFIG2 SW_ON +#define SW_CONFIG3 SW_ON + +/ { + compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; + + aliases { + mmc0 = &sdhi0; +#if SW_CONFIG3 == SW_OFF + mmc2 = &sdhi2; +#else + eth0 = ð0; + eth1 = ð1; +#endif + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* First 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + vcc_sdhi0: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + +#if SW_CONFIG2 == SW_ON + vccq_sdhi0: regulator1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +#else + reg_1p8v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; +#endif + + vcc_sdhi2: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +#if SW_CONFIG3 == SW_ON +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + reg = <7>; + interrupt-parent = <&pinctrl>; + interrupts = <RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>; + rxc-skew-psec = <0>; + txc-skew-psec = <0>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + reg = <7>; + interrupt-parent = <&pinctrl>; + interrupts = <RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>; + rxc-skew-psec = <0>; + txc-skew-psec = <0>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; +#endif + +&extal_clk { + clock-frequency = <24000000>; +}; + +#if SW_CONFIG2 == SW_ON +/* SD0 slot */ +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <125000000>; + status = "okay"; +}; +#else +/* eMMC */ +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + max-frequency = <125000000>; + status = "okay"; +}; +#endif + +#if SW_CONFIG3 == SW_OFF +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_sdhi2>; + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; +#endif + +&pinctrl { + eth0-phy-irq-hog { + gpio-hog; + gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>; + input; + line-name = "eth0-phy-irq"; + }; + + eth0_pins: eth0 { + txc { + pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */ + power-source = <1800>; + output-enable; + input-enable; + drive-strength-microamp = <5200>; + }; + + tx_ctl { + pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + mux { + pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */ + <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */ + <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */ + <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */ + <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */ + <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */ + <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */ + <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */ + <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */ + <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */ + <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */ + <RZG2L_PORT_PINMUX(4, 5, 1)>; /* ET0_LINKSTA */ + power-source = <1800>; + }; + }; + + eth1-phy-irq-hog { + gpio-hog; + gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>; + input; + line-name = "eth1-phy-irq"; + }; + + eth1_pins: eth1 { + txc { + pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */ + power-source = <1800>; + output-enable; + input-enable; + drive-strength-microamp = <5200>; + }; + + tx_ctl { + pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>; /* ET1_TX_CTL */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + mux { + pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */ + <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */ + <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */ + <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */ + <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */ + <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */ + <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */ + <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */ + <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */ + <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */ + <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */ + <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */ + <RZG2L_PORT_PINMUX(10, 4, 1)>; /* ET1_LINKSTA */ + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + cd { + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ + }; + }; + + sdhi0_uhs_pins: sd0-uhs { + data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + cd { + pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ + }; + }; + + sdhi0_emmc_pins: sd0-emmc { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7", + "SD0_CLK", "SD0_CMD", "SD0_RST#"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + data { + pins = "P11_2", "P11_3", "P12_0", "P12_1"; + input-enable; + }; + + ctrl { + pins = "P11_1"; + input-enable; + }; + + mux { + pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */ + <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */ + <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */ + <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */ + <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */ + <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */ + <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */ + }; + }; +}; diff --git a/dts/src/arm64/renesas/rzg3s-smarc.dtsi b/dts/src/arm64/renesas/rzg3s-smarc.dtsi new file mode 100644 index 0000000000..2145201372 --- /dev/null +++ b/dts/src/arm64/renesas/rzg3s-smarc.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ SMARC Carrier-II Board. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +/ { + aliases { + serial0 = &scif0; + mmc1 = &sdhi1; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +}; + +&pinctrl { + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */ + <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */ + }; + + sdhi1_pins: sd1 { + data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + cd { + pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1-uhs { + data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + cd { + pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */ + }; + }; +}; + +&scif0 { + pinctrl-names = "default"; + pinctrl-0 = <&scif0_pins>; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <125000000>; + status = "okay"; +}; diff --git a/dts/src/arm64/renesas/salvator-common.dtsi b/dts/src/arm64/renesas/salvator-common.dtsi index 6092dc4531..1eb4883b32 100644 --- a/dts/src/arm64/renesas/salvator-common.dtsi +++ b/dts/src/arm64/renesas/salvator-common.dtsi @@ -33,6 +33,14 @@ / { aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c_dvfs; serial0 = &scif2; serial1 = &hscif1; ethernet0 = &avb; @@ -170,7 +178,7 @@ }; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -179,7 +187,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -188,7 +196,7 @@ regulator-always-on; }; - reg_12v: regulator2 { + reg_12v: regulator-12v { compatible = "regulator-fixed"; regulator-name = "fixed-12V"; regulator-min-microvolt = <12000000>; @@ -386,7 +394,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&adv7123_in>; }; }; @@ -791,9 +799,6 @@ pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; pinctrl-names = "default"; - /* Single DAI */ - #sound-dai-cells = <0>; - /* audio_clkout0/1/2/3 */ #clock-cells = <1>; clock-frequency = <12288000 11289600>; @@ -817,7 +822,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + <&cpg CPG_MOD 922>; ports { #address-cells = <1>; @@ -832,7 +837,7 @@ frame-master = <&rsnd_endpoint0>; playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; + capture = <&ssi1>, <&src1>, <&dvc1>; }; }; @@ -866,6 +871,55 @@ }; }; +&rpc { + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; diff --git a/dts/src/arm64/renesas/salvator-panel-aa104xd12.dtso b/dts/src/arm64/renesas/salvator-panel-aa104xd12.dtso new file mode 100644 index 0000000000..c83a30adc6 --- /dev/null +++ b/dts/src/arm64/renesas/salvator-panel-aa104xd12.dtso @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree overlay for the AA104XD12 panel connected to LVDS0 on a + * Salvator-X or Salvator-XS board + * + * Copyright 2021 Ideas on Board Oy + */ + +/dts-v1/; +/plugin/; + +&{/} { +#include "panel-aa104xd12.dtsi" +}; + +&{/panel} { + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-audio-graph-card-mix+split.dtsi b/dts/src/arm64/renesas/ulcb-audio-graph-card-mix+split.dtsi new file mode 100644 index 0000000000..be6d7a0357 --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-audio-graph-card-mix+split.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Audio Graph Card (MIX) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <-----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ + +/ { + sound_card: sound { + compatible = "audio-graph-scu-card"; + label = "snd-ulcb-mix"; + + routing = "ak4613 Playback", "DAI0 Playback", + "ak4613 Playback", "DAI1 Playback", + "DAI0 Capture", "ak4613 Capture"; + + dais = <&snd_ulcb1 /* (A) CPU0 */ + &snd_ulcb2 /* (B) CPU1 */ + >; + }; +}; + +&ak4613 { + port { + #address-cells = <1>; + #size-cells = <0>; + + /* + * (X) ak4613 + */ + prefix = "ak4613"; + convert-rate = <48000>; + + /* (A) CPU0 <-> (X) ak4613 */ + ak4613_ep1: endpoint@0 { + reg = <0>; + remote-endpoint = <&rsnd_for_ak4613_1>; + }; + /* (B) CPU1 -> (X) ak4613 */ + ak4613_ep2: endpoint@1 { + reg = <1>; + remote-endpoint = <&rsnd_for_ak4613_2>; + }; + }; +}; + +&rcar_sound { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* + * (A) CPU0 + */ + snd_ulcb1: port@0 { + reg = <0>; + rsnd_for_ak4613_1: endpoint { + remote-endpoint = <&ak4613_ep1>; + bitclock-master; + frame-master; + playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; + capture = <&ssi1 &src0 &dvc1>; + }; + }; + /* + * (B) CPU1 + */ + snd_ulcb2: port@1 { + reg = <1>; + rsnd_for_ak4613_2: endpoint { + remote-endpoint = <&ak4613_ep2>; + bitclock-master; + frame-master; + playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-audio-graph-card.dtsi b/dts/src/arm64/renesas/ulcb-audio-graph-card.dtsi new file mode 100644 index 0000000000..3f1df6ee17 --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-audio-graph-card.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Audio Graph Card + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <-----> ak4613 + * (B) CPU1 -----> HDMI + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ + +/ { + sound_card: sound { + compatible = "audio-graph-card"; + label = "snd-ulcb"; + + dais = <&snd_ulcb1 /* (A) CPU0 <-> ak4613 */ + &snd_ulcb2 /* (B) CPU1 -> HDMI */ + >; + }; +}; + +&ak4613 { + #sound-dai-cells = <0>; + + port { + /* + * (A) CPU0 <-> ak4613 + */ + ak4613_endpoint: endpoint { + remote-endpoint = <&rsnd_for_ak4613>; + }; + }; +}; + +&hdmi0 { + ports { + port@2 { + /* + * (B) CPU1 -> HDMI + */ + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_for_hdmi>; + }; + }; + }; +}; + +&rcar_sound { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + snd_ulcb1: port@0 { + /* + * (A) CPU0 <-> ak4613 + */ + reg = <0>; + rsnd_for_ak4613: endpoint { + remote-endpoint = <&ak4613_endpoint>; + bitclock-master; + frame-master; + playback = <&ssi0>, <&src0>, <&dvc0>; + capture = <&ssi1>, <&src1>, <&dvc1>; + }; + }; + snd_ulcb2: port@1 { + /* + * (B) CPU1 -> HDMI + */ + reg = <1>; + rsnd_for_hdmi: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + bitclock-master; + frame-master; + playback = <&ssi2>; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-audio-graph-card2-mix+split.dtsi b/dts/src/arm64/renesas/ulcb-audio-graph-card2-mix+split.dtsi new file mode 100644 index 0000000000..8966e6a7d2 --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-audio-graph-card2-mix+split.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Audio Graph Card2 (MIX + TDM Split) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ +/ { + sound_card: sound { + compatible = "audio-graph-card2"; + label = "snd-ulcb-mix"; + + routing = "ak4613 Playback", "DAI0 Playback", + "ak4613 Playback", "DAI1 Playback", + "DAI0 Capture", "ak4613 Capture"; + + links = <&fe_a /* (A) CPU0 */ + &fe_b /* (B) CPU1 */ + &be_x /* (X) ak4613 */ + >; + + dpcm { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * FE + * (A) CPU0 (MIX-0) + * (B) CPU1 (MIX-1) + */ + fe_a: port@0 { reg = <0>; fe_a_ep: endpoint { remote-endpoint = <&rsnd_a_ep>; }; }; + fe_b: port@1 { reg = <1>; fe_b_ep: endpoint { remote-endpoint = <&rsnd_b_ep>; }; }; + }; + + ports@1 { + reg = <1>; + /* + * BE + * (X) ak4613 + */ + be_x: port { be_x_ep: endpoint { remote-endpoint = <&ak4613_x_ep>; }; }; + }; + }; + }; +}; + +&ak4613 { + port { + /* + * (X) ak4613 + */ + prefix = "ak4613"; + convert-rate = <48000>; + + ak4613_x_ep: endpoint { + remote-endpoint = <&be_x_ep>; + }; + }; +}; + +&rcar_sound { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* + * (A) CPU0 + */ + port@0 { + reg = <0>; + rsnd_a_ep: endpoint { + remote-endpoint = <&fe_a_ep>; + bitclock-master; + frame-master; + playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; + capture = <&ssi1 &src0 &dvc1>; + }; + }; + /* + * (B) CPU1 + */ + port@1 { + reg = <1>; + rsnd_b_ep: endpoint { + remote-endpoint = <&fe_b_ep>; + bitclock-master; + frame-master; + playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-audio-graph-card2.dtsi b/dts/src/arm64/renesas/ulcb-audio-graph-card2.dtsi new file mode 100644 index 0000000000..19fa6e1029 --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-audio-graph-card2.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Audio Graph Card2 + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ +#include "ulcb-audio-graph-card.dtsi" + +&sound_card { + compatible = "audio-graph-card2"; + + /delete-property/ dais; + links = <&snd_ulcb1 /* (A) CPU0 <-> ak4613 */ + &snd_ulcb2 /* (B) CPU1 -> HDMI */ + >; +}; diff --git a/dts/src/arm64/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi b/dts/src/arm64/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi new file mode 100644 index 0000000000..8ae6af1af0 --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Audio Graph Card (MIX + TDM Split) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * (C) CPU2 (2ch) ----> (8ch) (Y) PCM3168A-p (TDM-0 : 0,1ch) + * (D) CPU3 (2ch) --/ (TDM-1 : 2,3ch) + * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) + * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) + * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * + * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) + * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) + * (C) aplay -D plughw:1,0 xxx.wav (TDM-0) + * (D) aplay -D plughw:1,1 xxx.wav (TDM-1) + * (E) aplay -D plughw:1,2 xxx.wav (TDM-2) + * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) + * + * (A) arecord -D plughw:0,0 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav + */ +/ { + sound_card_kf: expand-sound { + compatible = "audio-graph-scu-card"; + label = "snd-kf-split"; + + routing = "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback"; + + dais = <&snd_kf1 /* (C) CPU2 */ + &snd_kf2 /* (D) CPU3 */ + &snd_kf3 /* (E) CPU4 */ + &snd_kf4 /* (F) CPU5 */ + &snd_kf5 /* (G) GPU6 */ + >; + }; +}; + +&pcm3168a { + ports { + #address-cells = <1>; + #size-cells = <0>; + mclk-fs = <512>; + + /* + * (Y) PCM3168A-p + */ + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + prefix = "pcm3168a"; + convert-channels = <8>; /* to 8ch TDM */ + + /* (C) CPU2 -> (Y) PCM3168A-p */ + pcm3168a_endpoint_p1: endpoint@0 { + reg = <0>; + remote-endpoint = <&rsnd_for_pcm3168a_play1>; + clocks = <&clksndsel>; + }; + /* (D) CPU3 -> (Y) PCM3168A-p */ + pcm3168a_endpoint_p2: endpoint@1 { + reg = <1>; + remote-endpoint = <&rsnd_for_pcm3168a_play2>; + clocks = <&clksndsel>; + }; + /* (E) CPU4 -> (Y) PCM3168A-p */ + pcm3168a_endpoint_p3: endpoint@2 { + reg = <2>; + remote-endpoint = <&rsnd_for_pcm3168a_play3>; + clocks = <&clksndsel>; + }; + /* (F) CPU5 -> (Y) PCM3168A-p */ + pcm3168a_endpoint_p4: endpoint@3 { + reg = <3>; + remote-endpoint = <&rsnd_for_pcm3168a_play4>; + clocks = <&clksndsel>; + }; + }; + /* + * (Z) PCM3168A-c + */ + port@1 { + reg = <1>; + /* (G) CPU6 <- PCM3168A-c */ + pcm3168a_endpoint_c: endpoint { + remote-endpoint = <&rsnd_for_pcm3168a_capture>; + clocks = <&clksndsel>; + }; + }; + }; +}; + +&rcar_sound { + ports@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + /* + * (C) CPU2 + */ + snd_kf1: port@2 { + reg = <2>; + rsnd_for_pcm3168a_play1: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p1>; + bitclock-master; + frame-master; + playback = <&ssiu30 &ssi3>; + }; + }; + /* + * (D) CPU3 + */ + snd_kf2: port@3 { + reg = <3>; + rsnd_for_pcm3168a_play2: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p2>; + bitclock-master; + frame-master; + playback = <&ssiu31 &ssi3>; + }; + }; + /* + * (E) CPU4 + */ + snd_kf3: port@4 { + reg = <4>; + rsnd_for_pcm3168a_play3: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p3>; + bitclock-master; + frame-master; + playback = <&ssiu32 &ssi3>; + }; + }; + /* + * (F) CPU5 + */ + snd_kf4: port@5 { + reg = <5>; + rsnd_for_pcm3168a_play4: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p4>; + bitclock-master; + frame-master; + playback = <&ssiu33 &ssi3>; + }; + }; + /* + * (G) CPU6 + */ + snd_kf5: port@6 { + reg = <6>; + rsnd_for_pcm3168a_capture: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c>; + bitclock-master; + frame-master; + dai-tdm-slot-num = <6>; + capture = <&ssi4>; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-kf-audio-graph-card.dtsi b/dts/src/arm64/renesas/ulcb-kf-audio-graph-card.dtsi new file mode 100644 index 0000000000..5fbd4ca83e --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-kf-audio-graph-card.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Audio Graph Card + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * (C) CPU2 ----> PCM3168A-p (8ch) + * (D) CPU3 <---- PCM3168A-c (6ch) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * (C) aplay -D plughw:1,0 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + * (D) arecord -D plughw:1,1 xxx.wav + */ +/ { + sound_card_kf: expand-sound { + compatible = "audio-graph-card"; + label = "snd-kf"; + + dais = <&snd_kf1 /* (C) CPU2 -> PCM3168A-p */ + &snd_kf2 /* (D) CPU3 <- PCM3168A-c */ + >; + }; +}; + +&pcm3168a { + ports { + #address-cells = <1>; + #size-cells = <0>; + mclk-fs = <512>; + /* + * (C) CPU2 -> PCM3168A-p + */ + port@0 { + reg = <0>; + pcm3168a_endpoint_p: endpoint { + remote-endpoint = <&rsnd_for_pcm3168a_play>; + clocks = <&clksndsel>; + }; + }; + /* + * (D) CPU3 <- PCM3168A-c + */ + port@1 { + reg = <1>; + pcm3168a_endpoint_c: endpoint { + remote-endpoint = <&rsnd_for_pcm3168a_capture>; + clocks = <&clksndsel>; + }; + }; + }; +}; + +&rcar_sound { + ports@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + /* + * (C) CPU2 -> PCM3168A-p + */ + snd_kf1: port@2 { + reg = <2>; + rsnd_for_pcm3168a_play: endpoint { + remote-endpoint = <&pcm3168a_endpoint_p>; + bitclock-master; + frame-master; + dai-tdm-slot-num = <8>; + playback = <&ssi3>; + }; + }; + /* + * (D) CPU3 <- PCM3168A-c + */ + snd_kf2: port@3 { + reg = <3>; + rsnd_for_pcm3168a_capture: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c>; + bitclock-master; + frame-master; + dai-tdm-slot-num = <6>; + capture = <&ssi4>; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi b/dts/src/arm64/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi new file mode 100644 index 0000000000..4cf632bc46 --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Audio Graph Card2 (MIX + TDM Split) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * (C) CPU3 (2ch) ----> (8ch) (Y) PCM3168A-p (TDM-0 : 0,1ch) + * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) + * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) + * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) + * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * + * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) + * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) + * (C) aplay -D plughw:1,0 xxx.wav (TDM-0) + * (D) aplay -D plughw:1,1 xxx.wav (TDM-1) + * (E) aplay -D plughw:1,2 xxx.wav (TDM-2) + * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) + * + * (A) arecord -D plughw:0,0 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav + */ +/ { + sound_card_kf: expand-sound { + compatible = "audio-graph-card2"; + label = "snd-kf-split"; + + routing = "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback", + "DAI6 Capture", "pcm3168a Capture"; + + links = <&fe_c /* (C) CPU2 */ + &fe_d /* (D) CPU3 */ + &fe_e /* (E) CPU4 */ + &fe_f /* (F) CPU5 */ + &rsnd_g /* (G) CPU6 */ + &be_y /* (Y) PCM3168A-p */ + >; + + dpcm { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* + * FE + * + * (C) CPU2 + * (D) CPU3 + * (E) CPU4 + * (F) CPU5 + */ + fe_c: port@2 { reg = <2>; fe_c_ep: endpoint { remote-endpoint = <&rsnd_c_ep>; }; }; + fe_d: port@3 { reg = <3>; fe_d_ep: endpoint { remote-endpoint = <&rsnd_d_ep>; }; }; + fe_e: port@4 { reg = <4>; fe_e_ep: endpoint { remote-endpoint = <&rsnd_e_ep>; }; }; + fe_f: port@5 { reg = <5>; fe_f_ep: endpoint { remote-endpoint = <&rsnd_f_ep>; }; }; + }; + + ports@1 { + reg = <1>; + /* + * BE + * + * (Y) PCM3168A-p + */ + be_y: port { be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + }; + }; + }; +}; + +&pcm3168a { + ports { + #address-cells = <1>; + #size-cells = <0>; + + mclk-fs = <512>; + prefix = "pcm3168a"; + + /* + * (Y) PCM3168A-p + */ + port@0 { + reg = <0>; + convert-channels = <8>; /* to 8ch TDM */ + pcm3168a_y_ep: endpoint { + remote-endpoint = <&be_y_ep>; + clocks = <&clksndsel>; + }; + }; + /* + * (Z) PCM3168A-c + */ + port@1 { + reg = <1>; + pcm3168a_z_ep: endpoint { + remote-endpoint = <&rsnd_g_ep>; + clocks = <&clksndsel>; + }; + }; + }; +}; + +&rcar_sound { + ports@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + /* + * (C) CPU2 + */ + port@2 { + reg = <2>; + rsnd_c_ep: endpoint { + remote-endpoint = <&fe_c_ep>; + bitclock-master; + frame-master; + playback = <&ssiu30 &ssi3>; + }; + }; + /* + * (D) CPU3 + */ + port@3 { + reg = <3>; + rsnd_d_ep: endpoint { + remote-endpoint = <&fe_d_ep>; + bitclock-master; + frame-master; + playback = <&ssiu31 &ssi3>; + }; + }; + /* + * (E) CPU4 + */ + port@4 { + reg = <4>; + rsnd_e_ep: endpoint { + remote-endpoint = <&fe_e_ep>; + bitclock-master; + frame-master; + playback = <&ssiu32 &ssi3>; + }; + }; + /* + * (F) CPU5 + */ + port@5 { + reg = <5>; + rsnd_f_ep: endpoint { + remote-endpoint = <&fe_f_ep>; + bitclock-master; + frame-master; + playback = <&ssiu33 &ssi3>; + }; + }; + /* + * (G) CPU6 + */ + rsnd_g: port@6 { + reg = <6>; + rsnd_g_ep: endpoint { + remote-endpoint = <&pcm3168a_z_ep>; + bitclock-master; + frame-master; + capture = <&ssi4>; + }; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-kf-audio-graph-card2.dtsi b/dts/src/arm64/renesas/ulcb-kf-audio-graph-card2.dtsi new file mode 100644 index 0000000000..4fc229418d --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-kf-audio-graph-card2.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Audio Graph Card2 + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * (C) CPU2 ----> PCM3168A-p (8ch) + * (D) CPU3 <---- PCM3168A-c (6ch) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * (C) aplay -D plughw:1,0 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + * (D) arecord -D plughw:1,1 xxx.wav + */ +#include "ulcb-kf-audio-graph-card.dtsi" + +&sound_card_kf { + compatible = "audio-graph-card2"; + + /delete-property/ dais; + links = <&snd_kf1 /* (C) CPU2 -> PCM3168A-p */ + &snd_kf2 /* (D) CPU3 <- PCM3168A-c */ + >; +}; diff --git a/dts/src/arm64/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi b/dts/src/arm64/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi new file mode 100644 index 0000000000..f01d91aaad --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Simple Audio Card (MIX + TDM Split) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * (C) CPU3 (2ch) ----> (8ch) (Y) PCM3168A-p (TDM-0 : 0,1ch) + * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) + * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) + * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) + * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * + * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) + * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) + * (C) aplay -D plughw:1,0 xxx.wav (TDM-0) + * (D) aplay -D plughw:1,1 xxx.wav (TDM-1) + * (E) aplay -D plughw:1,2 xxx.wav (TDM-2) + * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) + * + * (A) arecord -D plughw:0,0 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav + */ + +/ { + sound_card_kf: expand-sound { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "simple-scu-audio-card"; + label = "snd-kf-split"; + + simple-audio-card,routing = "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback", + "pcm3168a Playback", "DAI5 Playback"; + + simple-audio-card,dai-link@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + convert-channels = <8>; /* to 8ch TDM */ + + /* + * (C) CPU2 + */ + cpu@0 { + reg = <0>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 2>; + }; + /* + * (D) CPU3 + */ + cpu@1 { + reg = <1>; + sound-dai = <&rcar_sound 3>; + }; + /* + * (E) CPU4 + */ + cpu@2 { + reg = <2>; + sound-dai = <&rcar_sound 4>; + }; + /* + * (F) CPU5 + */ + cpu@3 { + reg = <3>; + sound-dai = <&rcar_sound 5>; + }; + /* + * (Y) PCM3168A-p + */ + codec { + prefix = "pcm3168a"; + mclk-fs = <512>; + sound-dai = <&pcm3168a 0>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + /* + * (G) CPU6 + */ + cpu { + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 6>; + }; + /* + * (Z) PCM3168A-c + */ + codec { + prefix = "pcm3168a"; + mclk-fs = <512>; + sound-dai = <&pcm3168a 1>; + }; + }; + }; +}; + +&pcm3168a { + /* + * (Y) PCM3168A-p + * (Z) PCM3168A-c + */ + #sound-dai-cells = <1>; +}; + +&rcar_sound { + rcar_sound,dai@1 { + reg = <1>; + + /* dai0-1 are defined in ulcb.dtsi */ + + /* + * (C) CPU2 + */ + dai2 { + playback = <&ssiu30 &ssi3>; + }; + /* + * (D) CPU3 + */ + dai3 { + playback = <&ssiu31 &ssi3>; + }; + /* + * (E) CPU4 + */ + dai4 { + playback = <&ssiu32 &ssi3>; + }; + /* + * (F) CPU5 + */ + dai5 { + playback = <&ssiu33 &ssi3>; + }; + /* + * (G) CPU6 + */ + dai6 { + capture = <&ssi4>; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-kf-simple-audio-card.dtsi b/dts/src/arm64/renesas/ulcb-kf-simple-audio-card.dtsi new file mode 100644 index 0000000000..28d29ecfb3 --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-kf-simple-audio-card.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Kingfisher + Simple Audio Card + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * (C) CPU2 ----> PCM3168A-p + * (D) CPU3 <---- PCM3168A-c + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * (C) aplay -D plughw:1,0 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + * (D) arecord -D plughw:1,1 xxx.wav + */ + +/ { + sound_card_kf: expand-sound { + compatible = "simple-audio-card"; + label = "snd-kf"; + + #address-cells = <1>; + #size-cells = <0>; + + /* + * (C) CPU2 -> PCM3168A-p + */ + simple-audio-card,dai-link@0 { + reg = <0>; + cpu { + bitclock-master; + frame-master; + dai-tdm-slot-num = <8>; + sound-dai = <&rcar_sound 2>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&pcm3168a 0>; + }; + }; + /* + * (D) CPU3 <- PCM3168A-c + */ + simple-audio-card,dai-link@1 { + reg = <1>; + cpu { + bitclock-master; + frame-master; + dai-tdm-slot-num = <6>; + sound-dai = <&rcar_sound 3>; + }; + codec { + mclk-fs = <512>; + sound-dai = <&pcm3168a 1>; + }; + }; + }; +}; + +&pcm3168a { + /* + * (C) CPU2 -> PCM3168A-p + * (D) CPU3 <- PCM3168A-c + */ + #sound-dai-cells = <1>; +}; + +&rcar_sound { + rcar_sound,dai@1 { + reg = <1>; + + /* + * (C) CPU2 -> PCM3168A-p + */ + dai2 { + playback = <&ssi3>; + }; + /* + * (D) CPU3 <- PCM3168A-c + */ + dai3 { + capture = <&ssi4>; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-kf.dtsi b/dts/src/arm64/renesas/ulcb-kf.dtsi index ae532cd217..50de17e4fb 100644 --- a/dts/src/arm64/renesas/ulcb-kf.dtsi +++ b/dts/src/arm64/renesas/ulcb-kf.dtsi @@ -6,16 +6,11 @@ * Copyright (C) 2017 Cogent Embedded, Inc. */ -/* - * SSI-PCM3168A - * aplay -D plughw:0,2 xxx.wav - * arecord -D plughw:0,3 xxx.wav - */ - / { aliases { serial1 = &hscif0; serial2 = &scif1; + serial3 = &hscif1; mmc2 = &sdhi3; }; @@ -97,8 +92,14 @@ status = "okay"; }; -&du_out_rgb { - remote-endpoint = <&adv7513_in>; +&du { + ports { + port@0 { + du_out_rgb: endpoint { + remote-endpoint = <&adv7513_in>; + }; + }; + }; }; &ehci0 { @@ -114,13 +115,21 @@ status = "okay"; }; +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + status = "okay"; +}; + &hsusb { dr_mode = "otg"; status = "okay"; }; &i2c2 { - i2cswitch2: i2c-switch@71 { + i2cmux2: i2c-mux@71 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -200,32 +209,12 @@ clocks = <&clksndsel>; clock-names = "scki"; - VDD1-supply = <&snd_3p3v>; - VDD2-supply = <&snd_3p3v>; - VCCAD1-supply = <&snd_vcc5v>; - VCCAD2-supply = <&snd_vcc5v>; - VCCDA1-supply = <&snd_vcc5v>; - VCCDA2-supply = <&snd_vcc5v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - mclk-fs = <512>; - port@0 { - reg = <0>; - pcm3168a_endpoint_p: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_play>; - clocks = <&clksndsel>; - }; - }; - port@1 { - reg = <1>; - pcm3168a_endpoint_c: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_capture>; - clocks = <&clksndsel>; - }; - }; - }; + VDD1-supply = <&snd_3p3v>; + VDD2-supply = <&snd_3p3v>; + VCCAD1-supply = <&snd_vcc5v>; + VCCAD2-supply = <&snd_vcc5v>; + VCCDA1-supply = <&snd_vcc5v>; + VCCDA2-supply = <&snd_vcc5v>; }; gyroscope@6b { @@ -245,6 +234,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; + #interrupt-cells = <2>; interrupt-parent = <&gpio6>; interrupts = <8 IRQ_TYPE_EDGE_FALLING>; @@ -305,13 +295,14 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; + #interrupt-cells = <2>; interrupt-parent = <&gpio6>; interrupts = <4 IRQ_TYPE_EDGE_FALLING>; }; }; &i2c4 { - i2cswitch4: i2c-switch@71 { + i2cmux4: i2c-mux@71 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -325,6 +316,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; + #interrupt-cells = <2>; interrupt-parent = <&gpio7>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; }; @@ -335,6 +327,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; + #interrupt-cells = <2>; interrupt-parent = <&gpio5>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; }; @@ -386,8 +379,13 @@ function = "hscif0"; }; + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + scif1_pins: scif1 { - groups = "scif1_data_b", "scif1_ctrl"; + groups = "scif1_data_b"; function = "scif1"; }; @@ -412,36 +410,11 @@ pinctrl-0 = <&sound_pins &sound_clk_pins &sound_pcm_pins>; - - ports { - /* rsnd_port0/1 are defined in ulcb.dtsi */ - rsnd_port2: port@2 { - reg = <2>; - rsnd_for_pcm3168a_play: endpoint { - remote-endpoint = <&pcm3168a_endpoint_p>; - bitclock-master; - frame-master; - dai-tdm-slot-num = <8>; - playback = <&ssi3>; - }; - }; - rsnd_port3: port@3 { - reg = <3>; - rsnd_for_pcm3168a_capture: endpoint { - remote-endpoint = <&pcm3168a_endpoint_c>; - bitclock-master; - frame-master; - dai-tdm-slot-num = <6>; - capture = <&ssi4>; - }; - }; - }; }; &scif1 { pinctrl-0 = <&scif1_pins>; pinctrl-names = "default"; - uart-has-rtscts; status = "okay"; }; @@ -470,14 +443,6 @@ }; }; -&sound_card { - links = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2 /* pcm3168a playback */ - &rsnd_port3 /* pcm3168a capture */ - >; -}; - &ssi4 { shared-pin; }; @@ -492,3 +457,17 @@ &xhci0 { status = "okay"; }; + +/* + * For sound-test. + * + * We can switch Audio Card for testing + * see also ulcb.dtsi + * + * #include "ulcb-kf-simple-audio-card.dtsi" + * #include "ulcb-kf-simple-audio-card-mix+split.dtsi" + * #include "ulcb-kf-audio-graph-card.dtsi" + * #include "ulcb-kf-audio-graph-card-mix+split.dtsi" + * #include "ulcb-kf-audio-graph-card2-mix+split.dtsi" + */ +#include "ulcb-kf-audio-graph-card2.dtsi" diff --git a/dts/src/arm64/renesas/ulcb-simple-audio-card-mix+split.dtsi b/dts/src/arm64/renesas/ulcb-simple-audio-card-mix+split.dtsi new file mode 100644 index 0000000000..9b955510e3 --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-simple-audio-card-mix+split.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Simple Audio Card (MIXer) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * Note: + * The HDMI output is ignored due to the limited number of subdevices + * + * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0) + * (B) CPU1 (2ch) --/ (MIX-1) + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ + +/ { + sound_card: sound { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "simple-scu-audio-card"; + label = "snd-ulcb-mix"; + + simple-audio-card,prefix = "ak4613"; + simple-audio-card,routing = "ak4613 Playback", "DAI0 Playback", + "ak4613 Playback", "DAI1 Playback", + "DAI0 Capture", "ak4613 Capture"; + + simple-audio-card,dai-link@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + convert-rate = <48000>; + + /* + * (A) CPU0 + */ + cpu@0 { + reg = <0>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 0>; + }; + /* + * (B) CPU1 + */ + cpu@1 { + reg = <1>; + sound-dai = <&rcar_sound 1>; + }; + /* + * (X) ak4613 + */ + codec { + prefix = "ak4613"; + sound-dai = <&ak4613>; + }; + }; + }; +}; + +&ak4613 { + /* + * (X) ak4613 + */ + #sound-dai-cells = <0>; +}; + +&rcar_sound { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + rcar_sound,dai@0 { + reg = <0>; + + /* + * (A) CPU0 + */ + dai0 { + playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>; + capture = <&ssi1 &src0 &dvc1>; + }; + /* + * (B) CPU1 + */ + dai1 { + playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb-simple-audio-card.dtsi b/dts/src/arm64/renesas/ulcb-simple-audio-card.dtsi new file mode 100644 index 0000000000..ba0e188e7b --- /dev/null +++ b/dts/src/arm64/renesas/ulcb-simple-audio-card.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for ULCB + Simple Audio Card + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/* + * (A) CPU0 <----> ak4613 + * (B) CPU1 ----> HDMI + * + * (A) aplay -D plughw:0,0 xxx.wav + * (B) aplay -D plughw:0,1 xxx.wav + * + * (A) arecord -D plughw:0,0 xxx.wav + */ + +/ { + sound_card: sound { + compatible = "simple-audio-card"; + label = "snd-ulcb"; + + #address-cells = <1>; + #size-cells = <0>; + + /* + * (A) CPU0 <-> ak4613 + */ + simple-audio-card,dai-link@0 { + reg = <0>; + cpu { + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 0>; + }; + codec { + sound-dai = <&ak4613>; + }; + }; + /* + * (B) CPU1 -> HDMI + */ + simple-audio-card,dai-link@1 { + reg = <1>; + cpu { + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 1>; + }; + codec { + sound-dai = <&hdmi0>; + }; + }; + }; +}; + +&ak4613 { + /* + * (A) CPU0 <-> ak4613 + */ + #sound-dai-cells = <0>; +}; + +&hdmi0 { + /* + * (B) CPU1 -> HDMI + */ + #sound-dai-cells = <0>; +}; + +&rcar_sound { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + rcar_sound,dai@0 { + reg = <0>; + + /* + * (A) CPU0 <-> ak4613 + */ + dai0 { + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; + /* + * (B) CPU1 -> HDMI + */ + dai1 { + playback = <&ssi2>; + }; + }; +}; diff --git a/dts/src/arm64/renesas/ulcb.dtsi b/dts/src/arm64/renesas/ulcb.dtsi index b4bdb2d7e4..a2f66f9160 100644 --- a/dts/src/arm64/renesas/ulcb.dtsi +++ b/dts/src/arm64/renesas/ulcb.dtsi @@ -6,14 +6,6 @@ * Copyright (C) 2016 Cogent Embedded, Inc. */ -/* - * SSI-AK4613 - * aplay -D plughw:0,0 xxx.wav - * arecord -D plughw:0,0 xxx.wav - * SSI-HDMI - * aplay -D plughw:0,1 xxx.wav - */ - #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -21,6 +13,14 @@ model = "Renesas R-Car Gen3 ULCB board"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c_dvfs; serial0 = &scif2; ethernet0 = &avb; mmc0 = &sdhi2; @@ -76,7 +76,7 @@ }; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -85,7 +85,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -94,15 +94,6 @@ regulator-always-on; }; - sound_card: sound { - compatible = "audio-graph-card2"; - label = "rcar-sound"; - - links = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - >; - }; - vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; @@ -193,9 +184,6 @@ }; port@2 { reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_for_hdmi>; - }; }; }; }; @@ -210,7 +198,6 @@ ak4613: codec@10 { compatible = "asahi-kasei,ak4613"; - #sound-dai-cells = <0>; reg = <0x10>; clocks = <&rcar_sound 3>; @@ -222,12 +209,6 @@ asahi-kasei,out4-single-end; asahi-kasei,out5-single-end; asahi-kasei,out6-single-end; - - port { - ak4613_endpoint: endpoint { - remote-endpoint = <&rsnd_for_ak4613>; - }; - }; }; cs2000: clk-multiplier@4f { @@ -286,6 +267,12 @@ }; }; }; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; }; &ohci1 { @@ -373,9 +360,6 @@ pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; pinctrl-names = "default"; - /* Single DAI */ - #sound-dai-cells = <0>; - /* audio_clkout0/1/2/3 */ #clock-cells = <1>; clock-frequency = <12288000 11289600>; @@ -399,28 +383,53 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; + <&cpg CPG_MOD 922>; +}; - ports { - #address-cells = <1>; - #size-cells = <0>; - rsnd_port0: port@0 { - reg = <0>; - rsnd_for_ak4613: endpoint { - remote-endpoint = <&ak4613_endpoint>; - bitclock-master; - frame-master; - playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; +&rpc { + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; }; - }; - rsnd_port1: port@1 { - reg = <1>; - rsnd_for_hdmi: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - bitclock-master; - frame-master; - playback = <&ssi2>; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; }; }; }; @@ -484,3 +493,17 @@ status = "okay"; }; + + +/* + * For sound-test. + * + * We can switch Audio Card for testing + * + * #include "ulcb-simple-audio-card.dtsi" + * #include "ulcb-simple-audio-card-mix+split.dtsi" + * #include "ulcb-audio-graph-card.dtsi" + * #include "ulcb-audio-graph-card-mix+split.dtsi" + * #include "ulcb-audio-graph-card2-mix+split.dtsi" + */ +#include "ulcb-audio-graph-card2.dtsi" |