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Diffstat (limited to 'dts/src/arm64/rockchip/rk3399-nanopi4.dtsi')
-rw-r--r--dts/src/arm64/rockchip/rk3399-nanopi4.dtsi27
1 files changed, 25 insertions, 2 deletions
diff --git a/dts/src/arm64/rockchip/rk3399-nanopi4.dtsi b/dts/src/arm64/rockchip/rk3399-nanopi4.dtsi
index d325e11..dd16c80 100644
--- a/dts/src/arm64/rockchip/rk3399-nanopi4.dtsi
+++ b/dts/src/arm64/rockchip/rk3399-nanopi4.dtsi
@@ -148,15 +148,28 @@
assigned-clocks = <&cru SCLK_RMII_SRC>;
clock_in_out = "input";
pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+ phy-handle = <&rtl8211e>;
phy-mode = "rgmii";
phy-supply = <&vcc3v3_s3>;
snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
+ snps,reset-delays-us = <0 10000 30000>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtl8211e: phy@1 {
+ reg = <1>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
};
&gpu {
@@ -481,6 +494,16 @@
};
};
+ phy {
+ phy_intb: phy-intb {
+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_rstb: phy-rstb {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;