summaryrefslogtreecommitdiffstats
path: root/dts/src/arm64/ti/k3-am65-main.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'dts/src/arm64/ti/k3-am65-main.dtsi')
-rw-r--r--dts/src/arm64/ti/k3-am65-main.dtsi126
1 files changed, 126 insertions, 0 deletions
diff --git a/dts/src/arm64/ti/k3-am65-main.dtsi b/dts/src/arm64/ti/k3-am65-main.dtsi
index 11887c72f2..61815228e2 100644
--- a/dts/src/arm64/ti/k3-am65-main.dtsi
+++ b/dts/src/arm64/ti/k3-am65-main.dtsi
@@ -287,6 +287,17 @@
mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
<0x4090 0x3>; /* SERDES1 lane select */
};
+
+ dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {
+ compatible = "syscon";
+ reg = <0x0000041E0 0x14>;
+ };
+
+ ehrpwm_tbclk: syscon@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
};
dwc3_0: dwc3@4000000 {
@@ -570,6 +581,28 @@
<0x5>; /* RX_CHAN */
ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
};
+
+ cpts@310d0000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x0 0x310d0000 0x0 0x400>;
+ reg-names = "cpts";
+ clocks = <&main_cpts_mux>;
+ clock-names = "cpts";
+ interrupts-extended = <&intr_main_navss 163 0>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
+
+ main_cpts_mux: refclk-mux {
+ #clock-cells = <0>;
+ clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
+ <&k3_clks 118 6>, <&k3_clks 118 3>,
+ <&k3_clks 118 8>, <&k3_clks 118 14>,
+ <&k3_clks 120 3>, <&k3_clks 121 3>;
+ assigned-clocks = <&main_cpts_mux>;
+ assigned-clock-parents = <&k3_clks 118 5>;
+ };
+ };
};
main_gpio0: main_gpio0@600000 {
@@ -746,4 +779,97 @@
};
};
};
+
+ dss: dss@04a00000 {
+ compatible = "ti,am65x-dss";
+ reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
+ <0x0 0x04a06000 0x0 0x1000>, /* vid */
+ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
+ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
+ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
+ <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
+ reg-names = "common", "vidl1", "vid",
+ "ovr1", "ovr2", "vp1", "vp2";
+
+ ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
+
+ power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
+
+ clocks = <&k3_clks 67 1>,
+ <&k3_clks 216 1>,
+ <&k3_clks 67 2>;
+ clock-names = "fck", "vp1", "vp2";
+
+ /*
+ * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
+ * DIV1. See "Figure 12-3365. DSS Integration"
+ * in AM65x TRM for details.
+ */
+ assigned-clocks = <&k3_clks 67 2>;
+ assigned-clock-parents = <&k3_clks 67 5>;
+
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ dss_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ ehrpwm0: pwm@3000000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3000000 0x0 0x100>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm1: pwm@3010000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3010000 0x0 0x100>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm2: pwm@3020000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3020000 0x0 0x100>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm3: pwm@3030000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3030000 0x0 0x100>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm4: pwm@3040000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3040000 0x0 0x100>;
+ power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ ehrpwm5: pwm@3050000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3050000 0x0 0x100>;
+ power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
+ clock-names = "tbclk", "fck";
+ };
};