diff options
Diffstat (limited to 'dts/src/arm64/xilinx/zynqmp-zc1254-revA.dts')
| -rw-r--r-- | dts/src/arm64/xilinx/zynqmp-zc1254-revA.dts | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/dts/src/arm64/xilinx/zynqmp-zc1254-revA.dts b/dts/src/arm64/xilinx/zynqmp-zc1254-revA.dts index 3d0aaa02f1..3dec57cf18 100644 --- a/dts/src/arm64/xilinx/zynqmp-zc1254-revA.dts +++ b/dts/src/arm64/xilinx/zynqmp-zc1254-revA.dts @@ -2,10 +2,10 @@ /* * dts file for Xilinx ZynqMP ZC1254 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> - * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + * Michal Simek <michal.simek@amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> */ /dts-v1/; @@ -20,6 +20,7 @@ aliases { serial0 = &uart0; serial1 = &dcc; + spi0 = &qspi; }; chosen { @@ -37,6 +38,19 @@ status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &uart0 { status = "okay"; }; |