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Diffstat (limited to 'dts/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts')
-rw-r--r--dts/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts6
1 files changed, 3 insertions, 3 deletions
diff --git a/dts/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts b/dts/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts
index 7a49deeae6..4ea6ef5a7f 100644
--- a/dts/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts
+++ b/dts/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
*
- * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ * (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm017-dc3 RevA";
@@ -73,7 +73,7 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
- phy0: phy@0 { /* VSC8211 */
+ phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
};
};