diff options
Diffstat (limited to 'dts/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts')
| -rw-r--r-- | dts/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts | 56 |
1 files changed, 43 insertions, 13 deletions
diff --git a/dts/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts b/dts/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts index 2366cd9f09..6ec1d98139 100644 --- a/dts/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/dts/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -2,9 +2,9 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ /dts-v1/; @@ -26,6 +26,7 @@ rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; + spi0 = &qspi; }; chosen { @@ -115,17 +116,21 @@ status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; - ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ - reg = <0>; - }; - ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ - reg = <7>; - }; - ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ - reg = <3>; - }; - ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ - reg = <8>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ + reg = <0>; + }; + ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ + reg = <7>; + }; + ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ + reg = <3>; + }; + ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ + reg = <8>; + }; }; }; @@ -151,6 +156,10 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -161,6 +170,19 @@ status = "okay"; }; +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; /* also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + &rtc { status = "okay"; }; @@ -176,3 +198,11 @@ &watchdog0 { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; +}; |