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Diffstat (limited to 'dts/src/arm64/xilinx/zynqmp.dtsi')
-rw-r--r--dts/src/arm64/xilinx/zynqmp.dtsi74
1 files changed, 71 insertions, 3 deletions
diff --git a/dts/src/arm64/xilinx/zynqmp.dtsi b/dts/src/arm64/xilinx/zynqmp.dtsi
index 3c731e7390..26d926eb14 100644
--- a/dts/src/arm64/xilinx/zynqmp.dtsi
+++ b/dts/src/arm64/xilinx/zynqmp.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP
*
- * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ * (C) Copyright 2014 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
@@ -12,6 +12,8 @@
* the License, or (at your option) any later version.
*/
+#include <dt-bindings/power/xlnx-zynqmp-power.h>
+
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
@@ -118,8 +120,31 @@
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
+ #power-domain-cells = <1>;
method = "smc";
+ zynqmp_power: zynqmp-power {
+ compatible = "xlnx,zynqmp-power";
+ interrupt-parent = <&gic>;
+ interrupts = <0 35 4>;
+ };
+
+ zynqmp_clk: clock-controller {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clk";
+ clocks = <&pss_ref_clk>,
+ <&video_clk>,
+ <&pss_alt_ref_clk>,
+ <&aux_ref_clk>,
+ <&gt_crx_ref_clk>;
+ clock-names = "pss_ref_clk",
+ "video_clk",
+ "pss_alt_ref_clk",
+ "aux_ref_clk",
+ "gt_crx_ref_clk";
+ };
+
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
@@ -187,6 +212,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ power-domains = <&zynqmp_firmware PD_CAN_0>;
};
can1: can@ff070000 {
@@ -198,6 +224,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ power-domains = <&zynqmp_firmware PD_CAN_1>;
};
cci: cci@fd6e0000 {
@@ -228,6 +255,7 @@
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan2: dma@fd510000 {
@@ -238,6 +266,7 @@
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan3: dma@fd520000 {
@@ -248,6 +277,7 @@
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan4: dma@fd530000 {
@@ -258,6 +288,7 @@
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan5: dma@fd540000 {
@@ -268,6 +299,7 @@
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan6: dma@fd550000 {
@@ -278,6 +310,7 @@
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan7: dma@fd560000 {
@@ -288,6 +321,7 @@
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan8: dma@fd570000 {
@@ -298,6 +332,7 @@
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
/* LPDDMA default allows only secured access. inorder to enable
@@ -312,6 +347,7 @@
interrupts = <0 77 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan2: dma@ffa90000 {
@@ -322,6 +358,7 @@
interrupts = <0 78 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan3: dma@ffaa0000 {
@@ -332,6 +369,7 @@
interrupts = <0 79 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan4: dma@ffab0000 {
@@ -342,6 +380,7 @@
interrupts = <0 80 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan5: dma@ffac0000 {
@@ -352,6 +391,7 @@
interrupts = <0 81 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan6: dma@ffad0000 {
@@ -362,6 +402,7 @@
interrupts = <0 82 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan7: dma@ffae0000 {
@@ -372,6 +413,7 @@
interrupts = <0 83 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan8: dma@ffaf0000 {
@@ -382,6 +424,7 @@
interrupts = <0 84 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
mc: memory-controller@fd070000 {
@@ -400,6 +443,7 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_ETH_0>;
};
gem1: ethernet@ff0c0000 {
@@ -411,6 +455,7 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_ETH_1>;
};
gem2: ethernet@ff0d0000 {
@@ -422,6 +467,7 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_ETH_2>;
};
gem3: ethernet@ff0e0000 {
@@ -433,6 +479,7 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_ETH_3>;
};
gpio: gpio@ff0a0000 {
@@ -445,6 +492,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
+ power-domains = <&zynqmp_firmware PD_GPIO>;
};
i2c0: i2c@ff020000 {
@@ -455,6 +503,7 @@
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_I2C_0>;
};
i2c1: i2c@ff030000 {
@@ -465,6 +514,7 @@
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_I2C_1>;
};
pcie: pcie@fd0e0000 {
@@ -496,6 +546,7 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+ power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
@@ -519,24 +570,31 @@
reg = <0x0 0xfd0c0000 0x0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
+ power-domains = <&zynqmp_firmware PD_SATA>;
};
sdhci0: mmc@ff160000 {
- compatible = "arasan,sdhci-8.9a";
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
+ #clock-cells = <1>;
+ clock-output-names = "clk_out_sd0", "clk_in_sd0";
+ power-domains = <&zynqmp_firmware PD_SD_0>;
};
sdhci1: mmc@ff170000 {
- compatible = "arasan,sdhci-8.9a";
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 49 4>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
+ #clock-cells = <1>;
+ clock-output-names = "clk_out_sd1", "clk_in_sd1";
+ power-domains = <&zynqmp_firmware PD_SD_1>;
};
smmu: smmu@fd800000 {
@@ -561,6 +619,7 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_SPI_0>;
};
spi1: spi@ff050000 {
@@ -572,6 +631,7 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_SPI_1>;
};
ttc0: timer@ff110000 {
@@ -581,6 +641,7 @@
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
reg = <0x0 0xff110000 0x0 0x1000>;
timer-width = <32>;
+ power-domains = <&zynqmp_firmware PD_TTC_0>;
};
ttc1: timer@ff120000 {
@@ -590,6 +651,7 @@
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
reg = <0x0 0xff120000 0x0 0x1000>;
timer-width = <32>;
+ power-domains = <&zynqmp_firmware PD_TTC_1>;
};
ttc2: timer@ff130000 {
@@ -599,6 +661,7 @@
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
reg = <0x0 0xff130000 0x0 0x1000>;
timer-width = <32>;
+ power-domains = <&zynqmp_firmware PD_TTC_2>;
};
ttc3: timer@ff140000 {
@@ -608,6 +671,7 @@
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
reg = <0x0 0xff140000 0x0 0x1000>;
timer-width = <32>;
+ power-domains = <&zynqmp_firmware PD_TTC_3>;
};
uart0: serial@ff000000 {
@@ -617,6 +681,7 @@
interrupts = <0 21 4>;
reg = <0x0 0xff000000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
+ power-domains = <&zynqmp_firmware PD_UART_0>;
};
uart1: serial@ff010000 {
@@ -626,6 +691,7 @@
interrupts = <0 22 4>;
reg = <0x0 0xff010000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
+ power-domains = <&zynqmp_firmware PD_UART_1>;
};
usb0: usb@fe200000 {
@@ -635,6 +701,7 @@
interrupts = <0 65 4>;
reg = <0x0 0xfe200000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
+ power-domains = <&zynqmp_firmware PD_USB_0>;
};
usb1: usb@fe300000 {
@@ -644,6 +711,7 @@
interrupts = <0 70 4>;
reg = <0x0 0xfe300000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
+ power-domains = <&zynqmp_firmware PD_USB_1>;
};
watchdog0: watchdog@fd4d0000 {
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-25 04:27:04 +0000