diff options
Diffstat (limited to 'dts/src/arm')
248 files changed, 5852 insertions, 1776 deletions
diff --git a/dts/src/arm/am335x-baltos-ir2110.dts b/dts/src/arm/am335x-baltos-ir2110.dts index daf4cb3980..75992eec83 100644 --- a/dts/src/arm/am335x-baltos-ir2110.dts +++ b/dts/src/arm/am335x-baltos-ir2110.dts @@ -81,3 +81,147 @@ pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "NC", + "NC", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "RMII1_TXD1", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "RMII1_TXD0", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "NC", + "NC", + "NC", + "SD_CD", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "RMII1_RXD1", + "RMII1_RXD0", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "RMII1_CRS_DV", + "RMII1_RXER", + "RMII1_TXEN", + "NC", + "NC", + "NC", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "ModeA0", + "ModeA1", + "ModeA2", + "ModeA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/dts/src/arm/am335x-baltos-ir3220.dts b/dts/src/arm/am335x-baltos-ir3220.dts index 2123bd5894..087e084506 100644 --- a/dts/src/arm/am335x-baltos-ir3220.dts +++ b/dts/src/arm/am335x-baltos-ir3220.dts @@ -91,6 +91,10 @@ interrupts = <20 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "ModeA0", "ModeA1", "ModeA2", "ModeA3", + "ModeB0", "ModeB1", "ModeB2", "ModeB3"; }; }; @@ -123,3 +127,147 @@ pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "UART2_RX", + "UART2_TX", + "I2C1_SDA", + "I2C1_SCL", + "WLAN_BTN", + "W_DISABLE", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "TCA6416_INT", + "RMII1_TXD1", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "RMII1_TXD0", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "UART2_DTR", + "UART2_DSR", + "UART2_DCD", + "UART2_RI", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SD_CD", + "SD_WP", + "RMII1_RXD1", + "RMII1_RXD0", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "RMII1_CRS_DV", + "RMII1_RXER", + "RMII1_TXEN", + "3G_PWR_EN", + "UART2_CTSN", + "UART2_RTSN", + "WLAN_IRQ", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "USB1_DRVVBUS", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/dts/src/arm/am335x-baltos-ir5221.dts b/dts/src/arm/am335x-baltos-ir5221.dts index 2f3872dbf4..faeb39aab6 100644 --- a/dts/src/arm/am335x-baltos-ir5221.dts +++ b/dts/src/arm/am335x-baltos-ir5221.dts @@ -99,6 +99,10 @@ interrupts = <20 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "ModeA0", "ModeA1", "ModeA2", "ModeA3", + "ModeB0", "ModeB1", "ModeB2", "ModeB3"; }; }; @@ -147,3 +151,147 @@ pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "UART2_RX", + "UART2_TX", + "I2C1_SDA", + "I2C1_SCL", + "WLAN_BTN", + "W_DISABLE", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "TCA6416_INT", + "RMII1_TXD1", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "RMII1_TXD0", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "DCAN1_TX", + "DCAN1_RX", + "CONSOLE_RX", + "CONSOLE_TX", + "UART2_DTR", + "UART2_DSR", + "UART2_DCD", + "UART2_RI", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SD_CD", + "SD_WP", + "RMII1_RXD1", + "RMII1_RXD0", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "RMII1_CRS_DV", + "RMII1_RXER", + "RMII1_TXEN", + "3G_PWR_EN", + "UART2_CTSN", + "UART2_RTSN", + "WLAN_IRQ", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "USB1_DRVVBUS", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/dts/src/arm/am335x-baltos.dtsi b/dts/src/arm/am335x-baltos.dtsi index d3eafee79a..6161c8929a 100644 --- a/dts/src/arm/am335x-baltos.dtsi +++ b/dts/src/arm/am335x-baltos.dtsi @@ -197,7 +197,7 @@ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; - ti,nand-xfer-type = "polled"; + ti,nand-xfer-type = "prefetch-dma"; gpmc,device-nand = "true"; gpmc,device-width = <1>; diff --git a/dts/src/arm/am335x-netcan-plus-1xx.dts b/dts/src/arm/am335x-netcan-plus-1xx.dts index 57e756b0f1..2e049489ac 100644 --- a/dts/src/arm/am335x-netcan-plus-1xx.dts +++ b/dts/src/arm/am335x-netcan-plus-1xx.dts @@ -85,3 +85,147 @@ status = "okay"; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "NC", + "NC", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "can_data", + "can_error", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "NC", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "NC", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "DCAN1_TX", + "DCAN1_RX", + "CONSOLE_RX", + "CONSOLE_TX", + "NC", + "NC", + "NC", + "NC", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "ModeA0", + "ModeA1", + "ModeA2", + "ModeA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/dts/src/arm/am335x-netcom-plus-2xx.dts b/dts/src/arm/am335x-netcom-plus-2xx.dts index c6cc1c6218..6ed886c330 100644 --- a/dts/src/arm/am335x-netcom-plus-2xx.dts +++ b/dts/src/arm/am335x-netcom-plus-2xx.dts @@ -93,3 +93,147 @@ ti,dual-emac-pvid = <2>; phy-handle = <&phy1>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "UART2_RX", + "UART2_TX", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "UART1_CTSN", + "UART1_RTSN", + "UART1_RX", + "UART1_TX", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "NC", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "NC", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "UART2_DTR", + "UART2_DSR", + "UART2_DCD", + "UART2_RI", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "UART1_DTR", + "UART1_DSR", + "UART1_DCD", + "UART1_RI", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "NC", + "NC", + "NC", + "NC", + "UART2_CTSN", + "UART2_RTSN", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "ModeA0", + "ModeA1", + "ModeA2", + "ModeA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/dts/src/arm/am335x-netcom-plus-8xx.dts b/dts/src/arm/am335x-netcom-plus-8xx.dts index 96dffd3ffd..ad3adc7679 100644 --- a/dts/src/arm/am335x-netcom-plus-8xx.dts +++ b/dts/src/arm/am335x-netcom-plus-8xx.dts @@ -71,6 +71,10 @@ interrupts = <20 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&tca6416_pins>; + gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3", + "GP_IN4", "GP_IN5", "GP_IN6", "GP_IN7", + "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3", + "GP_OUT4", "GP_OUT5", "GP_OUT6", "GP_OUT7"; }; }; @@ -86,6 +90,10 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + gpio-line-names = "CH1_M0", "CH1_M1", "CH1_M2", "CH1_M3", + "CH2_M0", "CH2_M1", "CH2_M2", "CH2_M3", + "CH3_M0", "CH3_M1", "CH3_M2", "CH3_M3", + "CH4_M0", "CH4_M1", "CH4_M2", "CH4_M3"; }; tca6416c: gpio@21 { @@ -93,6 +101,10 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; + gpio-line-names = "CH5_M0", "CH5_M1", "CH5_M2", "CH5_M3", + "CH6_M0", "CH6_M1", "CH6_M2", "CH6_M3", + "CH7_M0", "CH7_M1", "CH7_M2", "CH7_M3", + "CH8_M0", "CH8_M1", "CH8_M2", "CH8_M3"; }; }; @@ -113,3 +125,147 @@ ti,dual-emac-pvid = <2>; phy-handle = <&phy1>; }; + +&gpio0 { + gpio-line-names = + "MDIO", + "MDC", + "NC", + "NC", + "I2C1_SDA", + "I2C1_SCL", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "I2C2_SDA", + "I2C2_SCL", + "NC", + "NC", + "onrisc:blue:wlan", + "onrisc:green:app", + "USB0_DRVVBUS", + "ETH2_INT", + "NC", + "NC", + "MMC1_DAT0", + "MMC1_DAT1", + "NC", + "NC", + "MMC1_DAT2", + "MMC1_DAT3", + "NC", + "NC", + "GPMC_WAIT0", + "GPMC_WP_N"; +}; + +&gpio1 { + gpio-line-names = + "GPMC_AD0", + "GPMC_AD1", + "GPMC_AD2", + "GPMC_AD3", + "GPMC_AD4", + "GPMC_AD5", + "GPMC_AD6", + "GPMC_AD7", + "NC", + "NC", + "CONSOLE_RX", + "CONSOLE_TX", + "SW2_0_alt", + "SW2_1_alt", + "SW2_2_alt", + "SW2_3_alt", + "RGMII2_TCTL", + "RGMII2_RCTL", + "RGMII2_TD3", + "RGMII2_TD2", + "RGMII2_TD1", + "RGMII2_TD0", + "RGMII2_TCLK", + "RGMII2_RCLK", + "RGMII2_RD3", + "RGMII2_RD2", + "RGMII2_RD1", + "RGMII2_RD0", + "PMIC_INT1", + "GPMC_CSN0_Flash", + "MMC1_CLK", + "MMC1_CMD"; +}; + +&gpio2 { + gpio-line-names = + "GPMC_CSN3_BUS", + "GPMC_CLK", + "GPMC_ADVN_ALE", + "GPMC_OEN_RE_N", + "GPMC_WE_N", + "GPMC_BEN0_CLE", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "SW2_0", + "SW2_1", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "MMC0_DAT3", + "MMC0_DAT2", + "MMC0_DAT1", + "MMC0_DAT0", + "MMC0_CLK", + "MMC0_CMD"; +}; + +&gpio3 { + gpio-line-names = + "onrisc:red:power", + "NC", + "NC", + "NC", + "3G_PWR_EN", + "NC", + "NC", + "WLAN_IRQ", + "WLAN_EN", + "SW2_2", + "SW2_3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; +}; diff --git a/dts/src/arm/armada-370.dtsi b/dts/src/arm/armada-370.dtsi index 46e6d3ed8f..9dc928859a 100644 --- a/dts/src/arm/armada-370.dtsi +++ b/dts/src/arm/armada-370.dtsi @@ -60,16 +60,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie2: pcie@2,0 { @@ -78,16 +88,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 9>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/dts/src/arm/armada-375.dtsi b/dts/src/arm/armada-375.dtsi index 7f2f24a29e..929deaf312 100644 --- a/dts/src/arm/armada-375.dtsi +++ b/dts/src/arm/armada-375.dtsi @@ -568,16 +568,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie1: pcie@2,0 { @@ -586,16 +596,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/dts/src/arm/armada-380.dtsi b/dts/src/arm/armada-380.dtsi index cff1269f3f..ce1dddb226 100644 --- a/dts/src/arm/armada-380.dtsi +++ b/dts/src/arm/armada-380.dtsi @@ -64,16 +64,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -83,16 +93,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -102,16 +122,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/dts/src/arm/armada-385-turris-omnia.dts b/dts/src/arm/armada-385-turris-omnia.dts index d1e0db6e57..72ac807cae 100644 --- a/dts/src/arm/armada-385-turris-omnia.dts +++ b/dts/src/arm/armada-385-turris-omnia.dts @@ -105,6 +105,33 @@ */ status = "disabled"; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&audio_controller 1>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; +}; + +&audio_controller { + /* Pin header U16, GPIO51 in SPDIFO mode */ + pinctrl-0 = <&spdif_pins>; + pinctrl-names = "default"; + spdif-mode; + status = "okay"; }; &bm { @@ -166,6 +193,7 @@ buffer-manager = <&bm>; bm,pool-long = <2>; bm,pool-short = <3>; + label = "wan"; }; &i2c0 { @@ -476,7 +504,7 @@ marvell,function = "spi0"; }; - spi0cs1_pins: spi0cs1-pins { + spi0cs2_pins: spi0cs2-pins { marvell,pins = "mpp26"; marvell,function = "spi0"; }; @@ -511,7 +539,7 @@ }; }; - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ }; &uart0 { diff --git a/dts/src/arm/armada-388-db.dts b/dts/src/arm/armada-388-db.dts index 5130eccc32..2bcec5419b 100644 --- a/dts/src/arm/armada-388-db.dts +++ b/dts/src/arm/armada-388-db.dts @@ -36,6 +36,11 @@ i2c@11000 { status = "okay"; clock-frequency = <100000>; + audio_codec: audio-codec@4a { + #sound-dai-cells = <0>; + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + }; }; i2c@11100 { @@ -99,6 +104,12 @@ no-1-8-v; }; + audio-controller@e8000 { + pinctrl-0 = <&i2s_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + usb3@f0000 { status = "okay"; }; @@ -128,6 +139,64 @@ }; }; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Armada 385 DB Audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Headphone", "Out Jack", + "Line", "In Jack"; + simple-audio-card,routing = + "Out Jack", "HPL", + "Out Jack", "HPR", + "AIN1L", "In Jack", + "AIN1R", "In Jack"; + status = "disabled"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 0>; + }; + + codec { + sound-dai = <&audio_codec>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_out>; + }; + }; + + simple-audio-card,dai-link@2 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_in>; + }; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + + spdif_in: spdif-in { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; + }; }; &spi0 { diff --git a/dts/src/arm/armada-38x.dtsi b/dts/src/arm/armada-38x.dtsi index df3c8d1d8f..446861b6b1 100644 --- a/dts/src/arm/armada-38x.dtsi +++ b/dts/src/arm/armada-38x.dtsi @@ -289,6 +289,18 @@ marvell,pins = "mpp44"; marvell,function = "sata3"; }; + + i2s_pins: i2s-pins { + marvell,pins = "mpp48", "mpp49", + "mpp50", "mpp51", + "mpp52", "mpp53"; + marvell,function = "audio"; + }; + + spdif_pins: spdif-pins { + marvell,pins = "mpp51"; + marvell,function = "audio"; + }; }; gpio0: gpio@18100 { @@ -298,6 +310,7 @@ reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; #gpio-cells = <2>; #pwm-cells = <2>; interrupt-controller; @@ -316,6 +329,7 @@ reg-names = "gpio", "pwm"; ngpios = <28>; gpio-controller; + gpio-ranges = <&pinctrl 0 32 28>; #gpio-cells = <2>; #pwm-cells = <2>; interrupt-controller; @@ -618,6 +632,18 @@ status = "disabled"; }; + audio_controller: audio-controller@e8000 { + #sound-dai-cells = <1>; + compatible = "marvell,armada-380-audio"; + reg = <0xe8000 0x4000>, <0x18410 0xc>, + <0x18204 0x4>; + reg-names = "i2s_regs", "pll_regs", "soc_ctrl"; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 0>; + clock-names = "internal"; + status = "disabled"; + }; + usb3_0: usb3@f0000 { compatible = "marvell,armada-380-xhci"; reg = <0xf0000 0x4000>,<0xf4000 0x4000>; diff --git a/dts/src/arm/armada-39x.dtsi b/dts/src/arm/armada-39x.dtsi index e0b7c20998..923b035a3a 100644 --- a/dts/src/arm/armada-39x.dtsi +++ b/dts/src/arm/armada-39x.dtsi @@ -438,16 +438,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -457,16 +467,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -476,16 +496,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* @@ -498,16 +528,26 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/dts/src/arm/armada-xp-98dx3236.dtsi b/dts/src/arm/armada-xp-98dx3236.dtsi index 38a052a031..b21ffb819b 100644 --- a/dts/src/arm/armada-xp-98dx3236.dtsi +++ b/dts/src/arm/armada-xp-98dx3236.dtsi @@ -76,16 +76,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/dts/src/arm/armada-xp-lenovo-ix4-300d.dts b/dts/src/arm/armada-xp-lenovo-ix4-300d.dts index 87dcb502f7..0dad95ea26 100644 --- a/dts/src/arm/armada-xp-lenovo-ix4-300d.dts +++ b/dts/src/arm/armada-xp-lenovo-ix4-300d.dts @@ -164,7 +164,7 @@ }; }; - spi3 { + spi-3 { compatible = "spi-gpio"; status = "okay"; gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>; diff --git a/dts/src/arm/armada-xp-mv78230.dtsi b/dts/src/arm/armada-xp-mv78230.dtsi index 8558bf6bb5..bf9360f41e 100644 --- a/dts/src/arm/armada-xp-mv78230.dtsi +++ b/dts/src/arm/armada-xp-mv78230.dtsi @@ -83,16 +83,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie2: pcie@2,0 { @@ -101,16 +111,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 59>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie3: pcie@3,0 { @@ -119,16 +139,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 60>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; clocks = <&gateclk 7>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie4: pcie@4,0 { @@ -137,16 +167,26 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 61>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; clocks = <&gateclk 8>; status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie5: pcie@5,0 { @@ -155,16 +195,26 @@ reg = <0x2800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 9>; status = "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/dts/src/arm/armada-xp-mv78260.dtsi b/dts/src/arm/armada-xp-mv78260.dtsi index 2d85fe8ac3..0714af52e6 100644 --- a/dts/src/arm/armada-xp-mv78260.dtsi +++ b/dts/src/arm/armada-xp-mv78260.dtsi @@ -98,16 +98,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie2: pcie@2,0 { @@ -116,16 +126,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 59>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie3: pcie@3,0 { @@ -134,16 +154,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 60>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; clocks = <&gateclk 7>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie4: pcie@4,0 { @@ -152,16 +182,26 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 61>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; clocks = <&gateclk 8>; status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie5: pcie@5,0 { @@ -170,16 +210,26 @@ reg = <0x2800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 9>; status = "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie6: pcie@6,0 { @@ -188,16 +238,26 @@ reg = <0x3000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 63>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie6_intc 0>, + <0 0 0 2 &pcie6_intc 1>, + <0 0 0 3 &pcie6_intc 2>, + <0 0 0 4 &pcie6_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <1>; clocks = <&gateclk 10>; status = "disabled"; + + pcie6_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie7: pcie@7,0 { @@ -206,16 +266,26 @@ reg = <0x3800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 64>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie7_intc 0>, + <0 0 0 2 &pcie7_intc 1>, + <0 0 0 3 &pcie7_intc 2>, + <0 0 0 4 &pcie7_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <2>; clocks = <&gateclk 11>; status = "disabled"; + + pcie7_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie8: pcie@8,0 { @@ -224,16 +294,26 @@ reg = <0x4000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 65>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie8_intc 0>, + <0 0 0 2 &pcie8_intc 1>, + <0 0 0 3 &pcie8_intc 2>, + <0 0 0 4 &pcie8_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <3>; clocks = <&gateclk 12>; status = "disabled"; + + pcie8_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie9: pcie@9,0 { @@ -242,16 +322,26 @@ reg = <0x4800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 99>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie9_intc 0>, + <0 0 0 2 &pcie9_intc 1>, + <0 0 0 3 &pcie9_intc 2>, + <0 0 0 4 &pcie9_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 26>; status = "disabled"; + + pcie9_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/dts/src/arm/armada-xp-mv78460.dtsi b/dts/src/arm/armada-xp-mv78460.dtsi index 230a3fd36b..16185edf9a 100644 --- a/dts/src/arm/armada-xp-mv78460.dtsi +++ b/dts/src/arm/armada-xp-mv78460.dtsi @@ -119,16 +119,26 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 58>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie2: pcie@2,0 { @@ -137,16 +147,26 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 59>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 59>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <1>; clocks = <&gateclk 6>; status = "disabled"; + + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie3: pcie@3,0 { @@ -155,16 +175,26 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 60>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 60>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <2>; clocks = <&gateclk 7>; status = "disabled"; + + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie4: pcie@4,0 { @@ -173,16 +203,26 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 61>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 61>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <3>; clocks = <&gateclk 8>; status = "disabled"; + + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie5: pcie@5,0 { @@ -191,16 +231,26 @@ reg = <0x2800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 0x81000000 0 0 0x81000000 0x5 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 62>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie5_intc 0>, + <0 0 0 2 &pcie5_intc 1>, + <0 0 0 3 &pcie5_intc 2>, + <0 0 0 4 &pcie5_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 9>; status = "disabled"; + + pcie5_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie6: pcie@6,0 { @@ -209,16 +259,26 @@ reg = <0x3000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 63>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 0x81000000 0 0 0x81000000 0x6 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 63>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie6_intc 0>, + <0 0 0 2 &pcie6_intc 1>, + <0 0 0 3 &pcie6_intc 2>, + <0 0 0 4 &pcie6_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <1>; clocks = <&gateclk 10>; status = "disabled"; + + pcie6_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie7: pcie@7,0 { @@ -227,16 +287,26 @@ reg = <0x3800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 64>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 0x81000000 0 0 0x81000000 0x7 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 64>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie7_intc 0>, + <0 0 0 2 &pcie7_intc 1>, + <0 0 0 3 &pcie7_intc 2>, + <0 0 0 4 &pcie7_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <2>; clocks = <&gateclk 11>; status = "disabled"; + + pcie7_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie8: pcie@8,0 { @@ -245,16 +315,26 @@ reg = <0x4000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 65>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 0x81000000 0 0 0x81000000 0x8 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 65>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie8_intc 0>, + <0 0 0 2 &pcie8_intc 1>, + <0 0 0 3 &pcie8_intc 2>, + <0 0 0 4 &pcie8_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <3>; clocks = <&gateclk 12>; status = "disabled"; + + pcie8_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie9: pcie@9,0 { @@ -263,16 +343,26 @@ reg = <0x4800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 99>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 0x81000000 0 0 0x81000000 0x9 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 99>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie9_intc 0>, + <0 0 0 2 &pcie9_intc 1>, + <0 0 0 3 &pcie9_intc 2>, + <0 0 0 4 &pcie9_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 26>; status = "disabled"; + + pcie9_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie10: pcie@a,0 { @@ -281,16 +371,26 @@ reg = <0x5000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&mpic 103>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 0x81000000 0 0 0x81000000 0xa 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &mpic 103>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie10_intc 0>, + <0 0 0 2 &pcie10_intc 1>, + <0 0 0 3 &pcie10_intc 2>, + <0 0 0 4 &pcie10_intc 3>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 27>; status = "disabled"; + + pcie10_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/dts/src/arm/aspeed-ast2600-evb-a1.dts b/dts/src/arm/aspeed-ast2600-evb-a1.dts index d0a5c2ff0f..f34a2b1ec2 100644 --- a/dts/src/arm/aspeed-ast2600-evb-a1.dts +++ b/dts/src/arm/aspeed-ast2600-evb-a1.dts @@ -5,7 +5,7 @@ / { model = "AST2600 A1 EVB"; - compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600"; + compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600-evb", "aspeed,ast2600"; /delete-node/regulator-vcc-sdhci0; /delete-node/regulator-vcc-sdhci1; diff --git a/dts/src/arm/aspeed-ast2600-evb.dts b/dts/src/arm/aspeed-ast2600-evb.dts index c698e65382..de83c0eb1d 100644 --- a/dts/src/arm/aspeed-ast2600-evb.dts +++ b/dts/src/arm/aspeed-ast2600-evb.dts @@ -8,7 +8,7 @@ / { model = "AST2600 EVB"; - compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600"; + compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; aliases { serial4 = &uart5; @@ -182,6 +182,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #include "openbmc-flash-layout-64.dtsi" }; @@ -196,6 +197,7 @@ status = "okay"; m25p,fast-read; label = "pnor"; + spi-rx-bus-width = <4>; spi-max-frequency = <100000000>; }; }; @@ -207,11 +209,6 @@ &i2c0 { status = "okay"; - - temp@2e { - compatible = "adi,adt7490"; - reg = <0x2e>; - }; }; &i2c1 { @@ -240,10 +237,26 @@ &i2c7 { status = "okay"; + + temp@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; }; &i2c8 { status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; }; &i2c9 { diff --git a/dts/src/arm/aspeed-bmc-amd-daytonax.dts b/dts/src/arm/aspeed-bmc-amd-daytonax.dts new file mode 100644 index 0000000000..64bb9bf92d --- /dev/null +++ b/dts/src/arm/aspeed-bmc-amd-daytonax.dts @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "AMD DaytonaX BMC"; + compatible = "amd,daytonax-bmc", "aspeed,ast2500"; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + aliases { + serial0 = &uart1; + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200"; + }; + + leds { + compatible = "gpio-leds"; + + led-fault { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + led-identify { + gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>, + <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>, + <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + #include "openbmc-flash-layout.dtsi" + }; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&uart1 { + //Host Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + //BMC Console + status = "okay"; +}; + +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x3f8>; + aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","led-fault","led-identify","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "id-button","","","","","","","", + /*D0-D7*/ "","","ASSERT_BMC_READY","","","","","", + /*E0-E7*/ "reset-button","reset-control","power-button","power-control","", + "power-good","power-ok","", + /*F0-F7*/ "","","","","","","BATTERY_DETECT","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "FM_BMC_READ_SPD_TEMP","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>, <0x81>; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@10 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@11 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@12 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@13 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; + + fan@14 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e>; + }; + + fan@15 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0f>; + }; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vhub { + status = "okay"; +}; diff --git a/dts/src/arm/aspeed-bmc-ampere-mtjade.dts b/dts/src/arm/aspeed-bmc-ampere-mtjade.dts index 82a6f14a45..d127cbcc79 100644 --- a/dts/src/arm/aspeed-bmc-ampere-mtjade.dts +++ b/dts/src/arm/aspeed-bmc-ampere-mtjade.dts @@ -97,101 +97,6 @@ }; }; - gpio-keys { - compatible = "gpio-keys"; - - event-shutdown-ack { - label = "SHUTDOWN_ACK"; - gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(G, 2)>; - }; - - event-reboot-ack { - label = "REBOOT_ACK"; - gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(J, 3)>; - }; - - event-s0-overtemp { - label = "S0_OVERTEMP"; - gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(G, 3)>; - }; - - event-s0-hightemp { - label = "S0_HIGHTEMP"; - gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(J, 0)>; - }; - - event-s0-cpu-fault { - label = "S0_CPU_FAULT"; - gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; - linux,code = <ASPEED_GPIO(J, 1)>; - }; - - event-s0-scp-auth-fail { - label = "S0_SCP_AUTH_FAIL"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(J, 2)>; - }; - - event-s1-scp-auth-fail { - label = "S1_SCP_AUTH_FAIL"; - gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(Z, 5)>; - }; - - event-s1-overtemp { - label = "S1_OVERTEMP"; - gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(Z, 6)>; - }; - - event-s1-hightemp { - label = "S1_HIGHTEMP"; - gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(AB, 0)>; - }; - - event-s1-cpu-fault { - label = "S1_CPU_FAULT"; - gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; - linux,code = <ASPEED_GPIO(Z, 1)>; - }; - - event-id { - label = "ID_BUTTON"; - gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(Q, 5)>; - }; - - event-psu1-vin-good { - label = "PSU1_VIN_GOOD"; - gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(H, 4)>; - }; - - event-psu2-vin-good { - label = "PSU2_VIN_GOOD"; - gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(H, 5)>; - }; - - event-psu1-present { - label = "PSU1_PRESENT"; - gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(I, 0)>; - }; - - event-psu2-present { - label = "PSU2_PRESENT"; - gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(I, 1)>; - }; - - }; - gpioA0mux: mux-controller { compatible = "gpio-mux"; #mux-control-cells = <0>; diff --git a/dts/src/arm/aspeed-bmc-ampere-mtmitchell.dts b/dts/src/arm/aspeed-bmc-ampere-mtmitchell.dts new file mode 100644 index 0000000000..606cd4be24 --- /dev/null +++ b/dts/src/arm/aspeed-bmc-ampere-mtmitchell.dts @@ -0,0 +1,546 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2022, Ampere Computing LLC + +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "Ampere Mt.Mitchell BMC"; + compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600"; + + chosen { + stdout-path = &uart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: video { + size = <0x04000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; + }; + + voltage_mon_reg: voltage-mon-regulator { + compatible = "regulator-fixed"; + regulator-name = "ltc2497_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + gpioI5mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&gpio0 ASPEED_GPIO(I, 5) GPIO_ACTIVE_HIGH>; + }; + + adc0mux: adc0mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 0>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc1mux: adc1mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 1>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc2mux: adc2mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 2>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc3mux: adc3mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 3>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc4mux: adc4mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 4>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc5mux: adc5mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 5>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc6mux: adc6mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 6>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc7mux: adc7mux { + compatible = "io-channel-mux"; + io-channels = <&adc0 7>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc8mux: adc8mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 0>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc9mux: adc9mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 1>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc10mux: adc10mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 2>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc11mux: adc11mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 3>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc12mux: adc12mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 4>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc13mux: adc13mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 5>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc14mux: adc14mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 6>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + adc15mux: adc15mux { + compatible = "io-channel-mux"; + io-channels = <&adc1 7>; + #io-channel-cells = <1>; + io-channel-names = "parent"; + mux-controls = <&gpioI5mux>; + channels = "s0", "s1"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0mux 0>, <&adc0mux 1>, + <&adc1mux 0>, <&adc1mux 1>, + <&adc2mux 0>, <&adc2mux 1>, + <&adc3mux 0>, <&adc3mux 1>, + <&adc4mux 0>, <&adc4mux 1>, + <&adc5mux 0>, <&adc5mux 1>, + <&adc6mux 0>, <&adc6mux 1>, + <&adc7mux 0>, <&adc7mux 1>, + <&adc8mux 0>, <&adc8mux 1>, + <&adc9mux 0>, <&adc9mux 1>, + <&adc10mux 0>, <&adc10mux 1>, + <&adc11mux 0>, <&adc11mux 1>, + <&adc12mux 0>, <&adc12mux 1>, + <&adc13mux 0>, <&adc13mux 1>, + <&adc14mux 0>, <&adc14mux 1>, + <&adc15mux 0>, <&adc15mux 1>, + <&adc_i2c 0>, <&adc_i2c 1>, + <&adc_i2c 2>, <&adc_i2c 3>, + <&adc_i2c 4>, <&adc_i2c 5>, + <&adc_i2c 6>, <&adc_i2c 7>, + <&adc_i2c 8>, <&adc_i2c 9>, + <&adc_i2c 10>, <&adc_i2c 11>, + <&adc_i2c 12>, <&adc_i2c 13>, + <&adc_i2c 14>, <&adc_i2c 15>; + }; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac0 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default>; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <20000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + temperature-sensor@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + psu@59 { + compatible = "pmbus"; + reg = <0x59>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + adc_i2c: adc@16 { + compatible = "lltc,ltc2497"; + reg = <0x16>; + vref-supply = <&voltage_mon_reg>; + #io-channel-cells = <1>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-mux@70 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c4_bus70_chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + outlet_temp1: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + psu1_inlet_temp2: temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + i2c4_bus70_chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + pcie_zone_temp1: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + psu0_inlet_temp2: temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + i2c4_bus70_chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + pcie_zone_temp2: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + outlet_temp2: temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + i2c4_bus70_chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + mb_inlet_temp1: temperature-sensor@7c { + compatible = "microchip,emc1413"; + reg = <0x7c>; + }; + mb_inlet_temp2: temperature-sensor@4c { + compatible = "microchip,emc1413"; + reg = <0x4c>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + }; +}; + +&i2c6 { + status = "okay"; + rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + bmc_ast2600_cpu: temperature-sensor@35 { + compatible = "ti,tmp175"; + reg = <0x35>; + }; +}; + +&adc0 { + ref_voltage = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + ref_voltage = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n", + /*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","", + /*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","","", + "irq-n","","vrd-sel","spd-sel", + /*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n", + "","bmc-ncsi-txen","","", + /*E0-E7*/ "","","clk50m-bmc-ncsi","","","","","", + /*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control", + "cpu-bios-recover","s0-heartbeat","hs-csout-prochot", + "s0-vr-hot-n","s1-vr-hot-n", + /*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","", + /*H0-H7*/ "","","wd-disable-n","power-chassis-good","","","","", + /*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","s0-ddr-save","soc-spi-nor-access","presence-cpu0", + "s0-rtc-lock","","","", + /*N0-N7*/ "hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb", + "jtag-dbgr-prsnt-n","s1-heartbeat","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "ps0-ac-loss-n","ps1-ac-loss-n","","", + "led-fault","cpld-user-mode","jtag-srst-n","led-bmc-hb", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","identify-button","led-identify", + "s1-ddr-save","spi-nor-access","sys-pgood","presence-cpu1", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", + "host0-reboot-ack-n","host0-ready","host0-shd-req-n", + "host0-shd-ack-n","s0-overtemp-n", + /*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","", + "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel", + /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok", + "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n", + "s1-overtemp-n","s1-spi-auth-fail-n", + /*Y0-Y7*/ "","","","","","","","host0-special-boot", + /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","","","s0-soc-pgood","", + /*18C0-18C7*/ "uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1", + "uart3-mode0","uart3-mode1","uart4-mode0","uart4-mode1", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","",""; +}; diff --git a/dts/src/arm/aspeed-bmc-facebook-bletchley.dts b/dts/src/arm/aspeed-bmc-facebook-bletchley.dts index 41d2b1535d..1fc3e7cbf0 100644 --- a/dts/src/arm/aspeed-bmc-facebook-bletchley.dts +++ b/dts/src/arm/aspeed-bmc-facebook-bletchley.dts @@ -7,6 +7,7 @@ #include <dt-bindings/usb/pd.h> #include <dt-bindings/leds/leds-pca955x.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/i2c/i2c.h> / { model = "Facebook Bletchley BMC"; @@ -792,11 +793,6 @@ reg = <0x4f>; }; - hdc1080@40 { - compatible = "ti,hdc1080"; - reg = <0x40>; - }; - front_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; @@ -857,6 +853,13 @@ multi-master; aspeed,hw-timeout-ms = <1000>; status = "okay"; + + //USB Debug Connector + ipmb13@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &gpio0 { diff --git a/dts/src/arm/aspeed-bmc-facebook-elbert.dts b/dts/src/arm/aspeed-bmc-facebook-elbert.dts index 27b43fe099..8e1a1d1b28 100644 --- a/dts/src/arm/aspeed-bmc-facebook-elbert.dts +++ b/dts/src/arm/aspeed-bmc-facebook-elbert.dts @@ -183,3 +183,21 @@ &i2c11 { status = "okay"; }; + +/* + * BMC's "mac3" controller is connected to BCM53134P's IMP_RGMII port + * directly (fixed link, no PHY in between). + * Note: BMC's "mdio0" controller is connected to BCM53134P's MDIO + * interface, and the MDIO channel will be enabled in dts later, when + * BCM53134 is added to "bcm53xx" DSA driver. + */ +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/dts/src/arm/aspeed-bmc-facebook-yosemitev2.dts b/dts/src/arm/aspeed-bmc-facebook-yosemitev2.dts index 8864e9c312..6bf2ff85a4 100644 --- a/dts/src/arm/aspeed-bmc-facebook-yosemitev2.dts +++ b/dts/src/arm/aspeed-bmc-facebook-yosemitev2.dts @@ -207,11 +207,16 @@ &i2c12 { status = "okay"; - //MEZZ_FRU - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - pagesize = <32>; +}; + +&i2c13 { + status = "okay"; + // Debug Card + multi-master; + ipmb13@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; }; }; diff --git a/dts/src/arm/aspeed-g5.dtsi b/dts/src/arm/aspeed-g5.dtsi index c89092c390..04f98d1dbb 100644 --- a/dts/src/arm/aspeed-g5.dtsi +++ b/dts/src/arm/aspeed-g5.dtsi @@ -262,6 +262,14 @@ quality = <100>; }; + hace: crypto@1e6e3000 { + compatible = "aspeed,ast2500-hace"; + reg = <0x1e6e3000 0x100>; + interrupts = <4>; + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; + resets = <&syscon ASPEED_RESET_HACE>; + }; + gfx: display@1e6e6000 { compatible = "aspeed,ast2500-gfx", "syscon"; reg = <0x1e6e6000 0x1000>; diff --git a/dts/src/arm/aspeed-g6.dtsi b/dts/src/arm/aspeed-g6.dtsi index 6660564855..ebbcfe445d 100644 --- a/dts/src/arm/aspeed-g6.dtsi +++ b/dts/src/arm/aspeed-g6.dtsi @@ -323,6 +323,14 @@ #size-cells = <1>; ranges; + hace: crypto@1e6d0000 { + compatible = "aspeed,ast2600-hace"; + reg = <0x1e6d0000 0x200>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; + resets = <&syscon ASPEED_RESET_HACE>; + }; + syscon: syscon@1e6e2000 { compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1000>; @@ -756,6 +764,62 @@ status = "disabled"; }; + uart6: serial@1e790000 { + compatible = "ns16550a"; + reg = <0x1e790000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6_default>; + + status = "disabled"; + }; + + uart7: serial@1e790100 { + compatible = "ns16550a"; + reg = <0x1e790100 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7_default>; + + status = "disabled"; + }; + + uart8: serial@1e790200 { + compatible = "ns16550a"; + reg = <0x1e790200 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8_default>; + + status = "disabled"; + }; + + uart9: serial@1e790300 { + compatible = "ns16550a"; + reg = <0x1e790300 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart9_default>; + + status = "disabled"; + }; + i2c: bus@1e78a000 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/dts/src/arm/at91-sam9x60ek.dts b/dts/src/arm/at91-sam9x60ek.dts index 81c38e101f..4ba52ba11d 100644 --- a/dts/src/arm/at91-sam9x60ek.dts +++ b/dts/src/arm/at91-sam9x60ek.dts @@ -34,48 +34,6 @@ }; }; - regulators: regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_1v8: fixed-regulator-vdd_1v8@0 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - status = "okay"; - }; - - vdd_1v15: fixed-regulator-vdd_1v15@1 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - status = "okay"; - }; - - vdd1_3v3: fixed-regulator-vdd1_3v3@2 { - compatible = "regulator-fixed"; - regulator-name = "VDD1_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - - vdd2_3v3: regulator-fixed-vdd2_3v3@3 { - compatible = "regulator-fixed"; - regulator-name = "VDD2_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -111,6 +69,42 @@ linux,default-trigger = "heartbeat"; }; }; + + vdd_1v8: fixed-regulator-vdd_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + status = "okay"; + }; + + vdd_1v15: fixed-regulator-vdd_1v15 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + status = "okay"; + }; + + vdd1_3v3: fixed-regulator-vdd1_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD1_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + status = "okay"; + }; + + vdd2_3v3: regulator-fixed-vdd2_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + status = "okay"; + }; }; &adc { @@ -264,8 +258,9 @@ status = "okay"; uart1: serial@200 { - compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | diff --git a/dts/src/arm/at91-sama5d3_eds.dts b/dts/src/arm/at91-sama5d3_eds.dts new file mode 100644 index 0000000000..c287b03d76 --- /dev/null +++ b/dts/src/arm/at91-sama5d3_eds.dts @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet + * Development System board. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Jerry Ray <jerry.ray@microchip.com> + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "SAMA5D3 Ethernet Development System"; + compatible = "microchip,sama5d3-eds", "atmel,sama5d36", + "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + button-3 { + label = "PB_USER"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + memory@20000000 { + reg = <0x20000000 0x10000000>; + }; + + vcc_3v3_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_2v5_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "VCC_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v8_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v2_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_mmc0_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "mmc0-card-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; +}; + +&can0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&pinctrl_i2c2_pu>; + status = "okay"; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0-pu { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_i2c2_pu: i2c2-pu { + atmel,pins = + <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_key_gpio: key-gpio-0 { + atmel,pins = + <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + pinctrl_mmc0_cd: mmc0-cd { + atmel,pins = + <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + /* Reserved for reset signal to the RGMII connector. */ + pinctrl_rgmii_rstn: rgmii-rstn { + atmel,pins = + <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + /* Reserved for an interrupt line from the RMII and RGMII connectors. */ + pinctrl_spi_irqn: spi-irqn { + atmel,pins = + <AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_spi0_cs: spi0-cs-default { + atmel,pins = + <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + + pinctrl_spi1_cs: spi1-cs-default { + atmel,pins = <AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOC 28 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + + pinctrl_usba_vbus: usba-vbus { + atmel,pins = + <AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_usb_default: usb-default { + atmel,pins = + <AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + + /* Reserved for VBUS fault interrupt. */ + pinctrl_vbusfault_irqn: vbusfault-irqn { + atmel,pins = + <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + + pinctrl_vcc_mmc0_reg_gpio: vcc-mmc0-reg-gpio-default { + atmel,pins = <AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&spi0 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi0_cs>; + cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; + cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioC 28 0>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usb0 { /* USB Device port with VBUS detection. */ + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { /* 3-port Host. First port is unused. */ + atmel,vbus-gpio = <0 + &pioE 3 GPIO_ACTIVE_HIGH + &pioE 4 GPIO_ACTIVE_HIGH + >; + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/dts/src/arm/at91rm9200.dtsi b/dts/src/arm/at91rm9200.dtsi index d1181ead18..7a113325ab 100644 --- a/dts/src/arm/at91rm9200.dtsi +++ b/dts/src/arm/at91rm9200.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -596,6 +597,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -607,6 +609,7 @@ usart0: serial@fffc0000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -620,6 +623,7 @@ usart1: serial@fffc4000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -633,6 +637,7 @@ usart2: serial@fffc8000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffc8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -646,6 +651,7 @@ usart3: serial@fffcc000 { compatible = "atmel,at91rm9200-usart"; reg = <0xfffcc000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; diff --git a/dts/src/arm/at91sam9260.dtsi b/dts/src/arm/at91sam9260.dtsi index 9d9820db94..789fe356db 100644 --- a/dts/src/arm/at91sam9260.dtsi +++ b/dts/src/arm/at91sam9260.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -532,6 +533,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -543,6 +545,7 @@ usart0: serial@fffb0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -556,6 +559,7 @@ usart1: serial@fffb4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -569,6 +573,7 @@ usart2: serial@fffb8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -582,6 +587,7 @@ usart3: serial@fffd0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -595,6 +601,7 @@ uart0: serial@fffd4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -608,6 +615,7 @@ uart1: serial@fffd8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffd8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; diff --git a/dts/src/arm/at91sam9261.dtsi b/dts/src/arm/at91sam9261.dtsi index 259aca5653..ee0bd1aceb 100644 --- a/dts/src/arm/at91sam9261.dtsi +++ b/dts/src/arm/at91sam9261.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -179,6 +180,7 @@ usart0: serial@fffb0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -192,6 +194,7 @@ usart1: serial@fffb4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -205,6 +208,7 @@ usart2: serial@fffb8000{ compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -301,6 +305,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; diff --git a/dts/src/arm/at91sam9263.dtsi b/dts/src/arm/at91sam9263.dtsi index c080df8c23..3ce9ea9873 100644 --- a/dts/src/arm/at91sam9263.dtsi +++ b/dts/src/arm/at91sam9263.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -540,6 +541,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -551,6 +553,7 @@ usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -564,6 +567,7 @@ usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -577,6 +581,7 @@ usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; diff --git a/dts/src/arm/at91sam9g45.dtsi b/dts/src/arm/at91sam9g45.dtsi index 09794561c7..95f5d76234 100644 --- a/dts/src/arm/at91sam9g45.dtsi +++ b/dts/src/arm/at91sam9g45.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -675,6 +676,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; reg = <0xffffee00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; @@ -687,6 +689,7 @@ usart0: serial@fff8c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff8c000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -700,6 +703,7 @@ usart1: serial@fff90000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff90000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -713,6 +717,7 @@ usart2: serial@fff94000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff94000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -726,6 +731,7 @@ usart3: serial@fff98000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfff98000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; diff --git a/dts/src/arm/at91sam9n12.dtsi b/dts/src/arm/at91sam9n12.dtsi index 556f35ce49..83114d26f1 100644 --- a/dts/src/arm/at91sam9n12.dtsi +++ b/dts/src/arm/at91sam9n12.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -593,6 +594,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -618,6 +620,7 @@ usart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x4000>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; @@ -629,6 +632,7 @@ usart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x4000>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; @@ -640,6 +644,7 @@ usart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x4000>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; @@ -651,6 +656,7 @@ usart3: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x4000>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; diff --git a/dts/src/arm/at91sam9rl.dtsi b/dts/src/arm/at91sam9rl.dtsi index 12c6348118..364a2ff0a7 100644 --- a/dts/src/arm/at91sam9rl.dtsi +++ b/dts/src/arm/at91sam9rl.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -175,6 +176,7 @@ usart0: serial@fffb0000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb0000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -188,6 +190,7 @@ usart1: serial@fffb4000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb4000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -201,6 +204,7 @@ usart2: serial@fffb8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -214,6 +218,7 @@ usart3: serial@fffbc000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffbc000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; atmel,use-dma-rx; atmel,use-dma-tx; @@ -322,6 +327,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; diff --git a/dts/src/arm/at91sam9x5.dtsi b/dts/src/arm/at91sam9x5.dtsi index ea3b11336c..0c26c92576 100644 --- a/dts/src/arm/at91sam9x5.dtsi +++ b/dts/src/arm/at91sam9x5.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -674,6 +675,7 @@ dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; @@ -688,6 +690,7 @@ usart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; @@ -702,6 +705,7 @@ usart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; @@ -716,6 +720,7 @@ usart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; @@ -775,6 +780,7 @@ uart0: serial@f8040000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8040000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -786,6 +792,7 @@ uart1: serial@f8044000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8044000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/dts/src/arm/at91sam9x5_usart3.dtsi b/dts/src/arm/at91sam9x5_usart3.dtsi index 098d3fef5c..a47c765e1b 100644 --- a/dts/src/arm/at91sam9x5_usart3.dtsi +++ b/dts/src/arm/at91sam9x5_usart3.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/mfd/at91-usart.h> / { aliases { @@ -44,6 +45,7 @@ usart3: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; diff --git a/dts/src/arm/dove.dtsi b/dts/src/arm/dove.dtsi index 89e0bdaf3a..00a36fba2f 100644 --- a/dts/src/arm/dove.dtsi +++ b/dts/src/arm/dove.dtsi @@ -122,8 +122,18 @@ bus-range = <0x00 0xff>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 16>; + interrupt-names = "intx", "error"; + interrupts = <16>, <15>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie1: pcie@2 { @@ -141,8 +151,18 @@ bus-range = <0x00 0xff>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 18>; + interrupt-names = "intx", "error"; + interrupts = <18>, <17>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/dts/src/arm/exynos4412-midas.dtsi b/dts/src/arm/exynos4412-midas.dtsi index b967397a46..8e1c19a8ad 100644 --- a/dts/src/arm/exynos4412-midas.dtsi +++ b/dts/src/arm/exynos4412-midas.dtsi @@ -586,7 +586,7 @@ clocks = <&camera 1>; clock-names = "extclk"; samsung,camclk-out = <1>; - gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>; + gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; port { is_s5k6a3_ep: endpoint { diff --git a/dts/src/arm/exynos4412-origen.dts b/dts/src/arm/exynos4412-origen.dts index 6db09dba07..a3905e27b9 100644 --- a/dts/src/arm/exynos4412-origen.dts +++ b/dts/src/arm/exynos4412-origen.dts @@ -95,7 +95,7 @@ }; &ehci { - samsung,vbus-gpio = <&gpx3 5 1>; + samsung,vbus-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>; status = "okay"; phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; phy-names = "hsic0", "hsic1"; diff --git a/dts/src/arm/gemini-ns2502.dts b/dts/src/arm/gemini-ns2502.dts index 704abd212d..e6eeb35e88 100644 --- a/dts/src/arm/gemini-ns2502.dts +++ b/dts/src/arm/gemini-ns2502.dts @@ -39,10 +39,6 @@ phy0: ethernet-phy@1 { reg = <1>; device_type = "ethernet-phy"; - /* We lack the knowledge of necessary GPIO to achieve - * Gigabit - */ - max-speed = <100>; }; }; }; @@ -50,7 +46,7 @@ ðernet { status = "okay"; ethernet-port@0 { - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; }; }; @@ -65,30 +61,9 @@ pinctrl-1 = <&pflash_disabled_pins>; partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00020000>; - }; - partition@20000 { - label = "kernel"; - reg = <0x00020000 0x00700000>; - }; - partition@720000 { - label = "VCTL"; - reg = <0x00720000 0x00020000>; - }; - partition@740000 { - label = "CurConf"; - reg = <0x00740000 0x000a0000>; - }; - partition@7e0000 { - label = "FIS"; - reg = <0x007e0000 0x00010000>; - }; + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; }; }; diff --git a/dts/src/arm/gemini-ssi1328.dts b/dts/src/arm/gemini-ssi1328.dts index 2b3e7db84f..42e85f07cf 100644 --- a/dts/src/arm/gemini-ssi1328.dts +++ b/dts/src/arm/gemini-ssi1328.dts @@ -40,10 +40,6 @@ phy0: ethernet-phy@1 { reg = <1>; device_type = "ethernet-phy"; - /* We lack the knowledge of necessary GPIO to achieve - * Gigabit - */ - max-speed = <100>; }; /* WAN ICPlus IP101A */ phy1: ethernet-phy@2 { diff --git a/dts/src/arm/imx23-xfi3.dts b/dts/src/arm/imx23-xfi3.dts index a6213c590f..b1d8210f3e 100644 --- a/dts/src/arm/imx23-xfi3.dts +++ b/dts/src/arm/imx23-xfi3.dts @@ -158,19 +158,19 @@ default-brightness-level = <6>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - voldown { + key-voldown { label = "volume-down"; linux,code = <114>; gpios = <&gpio2 7 0>; debounce-interval = <20>; }; - volup { + key-volup { label = "volume-up"; linux,code = <115>; gpios = <&gpio2 8 0>; diff --git a/dts/src/arm/imx25-eukrea-mbimxsd25-baseboard.dts b/dts/src/arm/imx25-eukrea-mbimxsd25-baseboard.dts index 3f38c2e60a..c7207ea437 100644 --- a/dts/src/arm/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/dts/src/arm/imx25-eukrea-mbimxsd25-baseboard.dts @@ -13,12 +13,12 @@ model = "Eukrea MBIMXSD25"; compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiokeys>; - bp1 { + button { label = "BP1"; gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; diff --git a/dts/src/arm/imx25.dtsi b/dts/src/arm/imx25.dtsi index bc4de0c055..5f90d72b84 100644 --- a/dts/src/arm/imx25.dtsi +++ b/dts/src/arm/imx25.dtsi @@ -515,7 +515,7 @@ #interrupt-cells = <2>; }; - sdma: sdma@53fd4000 { + sdma: dma-controller@53fd4000 { compatible = "fsl,imx25-sdma"; reg = <0x53fd4000 0x4000>; clocks = <&clks 112>, <&clks 68>; diff --git a/dts/src/arm/imx28-cfa10049.dts b/dts/src/arm/imx28-cfa10049.dts index a92b05ef39..9ef0d567ea 100644 --- a/dts/src/arm/imx28-cfa10049.dts +++ b/dts/src/arm/imx28-cfa10049.dts @@ -327,7 +327,7 @@ }; }; - spi2 { + spi-2 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10049>; @@ -351,7 +351,7 @@ }; }; - spi3 { + spi-3 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&spi3_pins_cfa10049>; @@ -388,12 +388,12 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&rotary_btn_pins_cfa10049>; - rotary_button { + rotary-button { label = "rotary_button"; gpios = <&gpio3 26 1>; debounce-interval = <10>; diff --git a/dts/src/arm/imx28-cfa10055.dts b/dts/src/arm/imx28-cfa10055.dts index d05c370dfc..fac5bbda7a 100644 --- a/dts/src/arm/imx28-cfa10055.dts +++ b/dts/src/arm/imx28-cfa10055.dts @@ -129,7 +129,7 @@ }; }; - spi2 { + spi-2 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10055>; diff --git a/dts/src/arm/imx28-cfa10056.dts b/dts/src/arm/imx28-cfa10056.dts index c1060bd5f1..c5f3337e8b 100644 --- a/dts/src/arm/imx28-cfa10056.dts +++ b/dts/src/arm/imx28-cfa10056.dts @@ -88,7 +88,7 @@ }; }; - spi2 { + spi-2 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10056>; diff --git a/dts/src/arm/imx28-duckbill-2-enocean.dts b/dts/src/arm/imx28-duckbill-2-enocean.dts index bacb846f99..73f521c46c 100644 --- a/dts/src/arm/imx28-duckbill-2-enocean.dts +++ b/dts/src/arm/imx28-duckbill-2-enocean.dts @@ -204,7 +204,7 @@ pinctrl-names = "default"; pinctrl-0 = <&enocean_button>; - enocean { + key-enocean { label = "EnOcean"; linux,code = <KEY_NEW>; gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; diff --git a/dts/src/arm/imx28-eukrea-mbmx28lc.dtsi b/dts/src/arm/imx28-eukrea-mbmx28lc.dtsi index 3280fddaaf..b285a946e2 100644 --- a/dts/src/arm/imx28-eukrea-mbmx28lc.dtsi +++ b/dts/src/arm/imx28-eukrea-mbmx28lc.dtsi @@ -19,12 +19,12 @@ default-brightness-level = <10>; }; - button-sw3 { + gpio-keys-0 { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_button_sw3_pins_mbmx28lc>; - sw3 { + switch-sw3 { label = "SW3"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; @@ -32,12 +32,12 @@ }; }; - button-sw4 { + gpio-keys-1 { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_button_sw4_pins_mbmx28lc>; - sw4 { + switch-sw4 { label = "SW4"; gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; diff --git a/dts/src/arm/imx28-tx28.dts b/dts/src/arm/imx28-tx28.dts index 6d7b044fec..096f246032 100644 --- a/dts/src/arm/imx28-tx28.dts +++ b/dts/src/arm/imx28-tx28.dts @@ -221,7 +221,7 @@ linux,no-autorepeat; }; - spi_gpio: spi-gpio { + spi_gpio: spi { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/imx31.dtsi b/dts/src/arm/imx31.dtsi index 5c4938b0d5..95c05f17a6 100644 --- a/dts/src/arm/imx31.dtsi +++ b/dts/src/arm/imx31.dtsi @@ -297,7 +297,7 @@ #interrupt-cells = <2>; }; - sdma: sdma@53fd4000 { + sdma: dma-controller@53fd4000 { compatible = "fsl,imx31-sdma"; reg = <0x53fd4000 0x4000>; interrupts = <34>; diff --git a/dts/src/arm/imx35-eukrea-mbimxsd35-baseboard.dts b/dts/src/arm/imx35-eukrea-mbimxsd35-baseboard.dts index b1c11170ac..7f4f812b08 100644 --- a/dts/src/arm/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/dts/src/arm/imx35-eukrea-mbimxsd35-baseboard.dts @@ -13,12 +13,12 @@ model = "Eukrea CPUIMX35"; compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bp1>; - bp1 { + button { label = "BP1"; gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; diff --git a/dts/src/arm/imx35.dtsi b/dts/src/arm/imx35.dtsi index 8e41c8b7bd..d650f54c3f 100644 --- a/dts/src/arm/imx35.dtsi +++ b/dts/src/arm/imx35.dtsi @@ -284,7 +284,7 @@ #interrupt-cells = <2>; }; - sdma: sdma@53fd4000 { + sdma: dma-controller@53fd4000 { compatible = "fsl,imx35-sdma"; reg = <0x53fd4000 0x4000>; clocks = <&clks 9>, <&clks 65>; diff --git a/dts/src/arm/imx50-kobo-aura.dts b/dts/src/arm/imx50-kobo-aura.dts index 82ce8c43be..51bf6117fb 100644 --- a/dts/src/arm/imx50-kobo-aura.dts +++ b/dts/src/arm/imx50-kobo-aura.dts @@ -38,20 +38,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiokeys>; - power { + key-power { label = "Power Button"; gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; }; - hallsensor { + event-hallsensor { label = "Hallsensor"; gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESERVED>; linux,input-type = <EV_SW>; }; - frontlight { + event-frontlight { label = "Frontlight"; gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_DISPLAYTOGGLE>; diff --git a/dts/src/arm/imx50.dtsi b/dts/src/arm/imx50.dtsi index c0c7575fbe..3d9a9f37f6 100644 --- a/dts/src/arm/imx50.dtsi +++ b/dts/src/arm/imx50.dtsi @@ -421,7 +421,7 @@ status = "disabled"; }; - sdma: sdma@63fb0000 { + sdma: dma-controller@63fb0000 { compatible = "fsl,imx50-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; diff --git a/dts/src/arm/imx51-apf51dev.dts b/dts/src/arm/imx51-apf51dev.dts index c66f274ba4..b61d55ca14 100644 --- a/dts/src/arm/imx51-apf51dev.dts +++ b/dts/src/arm/imx51-apf51dev.dts @@ -63,7 +63,7 @@ leds { compatible = "gpio-leds"; - user { + led-user { label = "Heartbeat"; gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/dts/src/arm/imx51-babbage.dts b/dts/src/arm/imx51-babbage.dts index 552196d8a6..a1f9c6a722 100644 --- a/dts/src/arm/imx51-babbage.dts +++ b/dts/src/arm/imx51-babbage.dts @@ -154,7 +154,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; linux,code = <KEY_POWER>; diff --git a/dts/src/arm/imx51-zii-rdu1.dts b/dts/src/arm/imx51-zii-rdu1.dts index ec8ca3ac2c..3140f038aa 100644 --- a/dts/src/arm/imx51-zii-rdu1.dts +++ b/dts/src/arm/imx51-zii-rdu1.dts @@ -137,7 +137,7 @@ }; }; - spi_gpio: spi-gpio { + spi_gpio: spi { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/imx51.dtsi b/dts/src/arm/imx51.dtsi index 592d9c23a4..853707574d 100644 --- a/dts/src/arm/imx51.dtsi +++ b/dts/src/arm/imx51.dtsi @@ -504,7 +504,7 @@ status = "disabled"; }; - sdma: sdma@83fb0000 { + sdma: dma-controller@83fb0000 { compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; diff --git a/dts/src/arm/imx53-ard.dts b/dts/src/arm/imx53-ard.dts index 6208fbb2e7..23a7492e29 100644 --- a/dts/src/arm/imx53-ard.dts +++ b/dts/src/arm/imx53-ard.dts @@ -61,34 +61,34 @@ gpio-keys { compatible = "gpio-keys"; - home { + key-home { label = "Home"; gpios = <&gpio5 10 0>; linux,code = <KEY_HOME>; wakeup-source; }; - back { + key-back { label = "Back"; gpios = <&gpio5 11 0>; linux,code = <KEY_BACK>; wakeup-source; }; - program { + key-program { label = "Program"; gpios = <&gpio5 12 0>; linux,code = <KEY_PROGRAM >; wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio5 13 0>; linux,code = <KEY_VOLUMEUP>; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio4 0 0>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/dts/src/arm/imx53-qsb-common.dtsi b/dts/src/arm/imx53-qsb-common.dtsi index fe4244044a..50fef8dd36 100644 --- a/dts/src/arm/imx53-qsb-common.dtsi +++ b/dts/src/arm/imx53-qsb-common.dtsi @@ -45,20 +45,20 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power Button"; gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -71,7 +71,7 @@ pinctrl-names = "default"; pinctrl-0 = <&led_pin_gpio7_7>; - user { + led-user { label = "Heartbeat"; gpios = <&gpio7 7 0>; linux,default-trigger = "heartbeat"; diff --git a/dts/src/arm/imx53-smd.dts b/dts/src/arm/imx53-smd.dts index 9be44e8071..f8d17967a6 100644 --- a/dts/src/arm/imx53-smd.dts +++ b/dts/src/arm/imx53-smd.dts @@ -19,13 +19,13 @@ gpio-keys { compatible = "gpio-keys"; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio2 14 0>; linux,code = <KEY_VOLUMEUP>; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio2 15 0>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/dts/src/arm/imx53-tx53.dtsi b/dts/src/arm/imx53-tx53.dtsi index 8712e98514..892dd1a4ba 100644 --- a/dts/src/arm/imx53-tx53.dtsi +++ b/dts/src/arm/imx53-tx53.dtsi @@ -81,7 +81,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_key>; - power { + key-power { label = "Power Button"; gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; linux,code = <116>; /* KEY_POWER */ diff --git a/dts/src/arm/imx53.dtsi b/dts/src/arm/imx53.dtsi index b7a6469d34..56b3c13f4e 100644 --- a/dts/src/arm/imx53.dtsi +++ b/dts/src/arm/imx53.dtsi @@ -710,7 +710,7 @@ status = "disabled"; }; - sdma: sdma@63fb0000 { + sdma: dma-controller@63fb0000 { compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; diff --git a/dts/src/arm/imx6-logicpd-baseboard.dtsi b/dts/src/arm/imx6-logicpd-baseboard.dtsi index d9de9b4f0c..d477a937b4 100644 --- a/dts/src/arm/imx6-logicpd-baseboard.dtsi +++ b/dts/src/arm/imx6-logicpd-baseboard.dtsi @@ -6,7 +6,7 @@ keyboard { compatible = "gpio-keys"; - btn0 { + button-0 { gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>; label = "btn0"; linux,code = <KEY_WAKEUP>; @@ -14,7 +14,7 @@ wakeup-source; }; - btn1 { + button-1 { gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>; label = "btn1"; linux,code = <KEY_WAKEUP>; @@ -22,7 +22,7 @@ wakeup-source; }; - btn2 { + button-2 { gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>; label = "btn2"; linux,code = <KEY_WAKEUP>; @@ -30,7 +30,7 @@ wakeup-source; }; - btn3 { + button-3 { gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>; label = "btn3"; linux,code = <KEY_WAKEUP>; diff --git a/dts/src/arm/imx6dl-b1x5pv2.dtsi b/dts/src/arm/imx6dl-b1x5pv2.dtsi index ec5b664531..337db29b00 100644 --- a/dts/src/arm/imx6dl-b1x5pv2.dtsi +++ b/dts/src/arm/imx6dl-b1x5pv2.dtsi @@ -188,7 +188,7 @@ rotary-encoder-key { compatible = "gpio-keys"; - rotary-encoder-press { + rotary-encoder-event { label = "rotary-encoder press"; gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>; linux,code = <KEY_ENTER>; diff --git a/dts/src/arm/imx6dl-prtmvt.dts b/dts/src/arm/imx6dl-prtmvt.dts index a35a1c66e7..1f8cddd83c 100644 --- a/dts/src/arm/imx6dl-prtmvt.dts +++ b/dts/src/arm/imx6dl-prtmvt.dts @@ -51,98 +51,98 @@ pinctrl-0 = <&pinctrl_gpiokeys>; autorepeat; - power { + key-power { label = "Power Button"; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - f1 { + key-f1 { label = "GPIO Key F1"; linux,code = <KEY_F1>; gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; }; - f2 { + key-f2 { label = "GPIO Key F2"; linux,code = <KEY_F2>; gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; }; - f3 { + key-f3 { label = "GPIO Key F3"; linux,code = <KEY_F3>; gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; }; - f4 { + key-f4 { label = "GPIO Key F4"; linux,code = <KEY_F4>; gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; }; - f5 { + key-f5 { label = "GPIO Key F5"; linux,code = <KEY_F5>; gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; }; - cycle { + key-cycle { label = "GPIO Key CYCLE"; linux,code = <KEY_CYCLEWINDOWS>; gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; }; - esc { + key-esc { label = "GPIO Key ESC"; linux,code = <KEY_ESC>; gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; }; - up { + key-up { label = "GPIO Key UP"; linux,code = <KEY_UP>; gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; }; - down { + key-down { label = "GPIO Key DOWN"; linux,code = <KEY_DOWN>; gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; }; - ok { + key-ok { label = "GPIO Key OK"; linux,code = <KEY_OK>; gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; }; - f6 { + key-f6 { label = "GPIO Key F6"; linux,code = <KEY_F6>; gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; }; - f7 { + key-f7 { label = "GPIO Key F7"; linux,code = <KEY_F7>; gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; }; - f8 { + key-f8 { label = "GPIO Key F8"; linux,code = <KEY_F8>; gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; }; - f9 { + key-f9 { label = "GPIO Key F9"; linux,code = <KEY_F9>; gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; }; - f10 { + key-f10 { label = "GPIO Key F10"; linux,code = <KEY_F10>; gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; diff --git a/dts/src/arm/imx6dl-prtvt7.dts b/dts/src/arm/imx6dl-prtvt7.dts index 0a0b7acddf..a1eb538517 100644 --- a/dts/src/arm/imx6dl-prtvt7.dts +++ b/dts/src/arm/imx6dl-prtvt7.dts @@ -62,91 +62,91 @@ compatible = "gpio-keys"; autorepeat; - esc { + key-esc { label = "GPIO Key ESC"; linux,code = <KEY_ESC>; gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; }; - up { + key-up { label = "GPIO Key UP"; linux,code = <KEY_UP>; gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; }; - down { + key-down { label = "GPIO Key DOWN"; linux,code = <KEY_DOWN>; gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; }; - enter { + key-enter { label = "GPIO Key Enter"; linux,code = <KEY_ENTER>; gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; }; - cycle { + key-cycle { label = "GPIO Key CYCLE"; linux,code = <KEY_CYCLEWINDOWS>; gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; }; - f1 { + key-f1 { label = "GPIO Key F1"; linux,code = <KEY_F1>; gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; }; - f2 { + key-f2 { label = "GPIO Key F2"; linux,code = <KEY_F2>; gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; }; - f3 { + key-f3 { label = "GPIO Key F3"; linux,code = <KEY_F3>; gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; }; - f4 { + key-f4 { label = "GPIO Key F4"; linux,code = <KEY_F4>; gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; }; - f5 { + key-f5 { label = "GPIO Key F5"; linux,code = <KEY_F5>; gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; }; - f6 { + key-f6 { label = "GPIO Key F6"; linux,code = <KEY_F6>; gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; }; - f7 { + key-f7 { label = "GPIO Key F7"; linux,code = <KEY_F7>; gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; }; - f8 { + key-f8 { label = "GPIO Key F8"; linux,code = <KEY_F8>; gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; }; - f9 { + key-f9 { label = "GPIO Key F9"; linux,code = <KEY_F9>; gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; }; - f10 { + key-f10 { label = "GPIO Key F10"; linux,code = <KEY_F10>; gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; diff --git a/dts/src/arm/imx6dl-riotboard.dts b/dts/src/arm/imx6dl-riotboard.dts index e7d9bfbfd0..e7be05f205 100644 --- a/dts/src/arm/imx6dl-riotboard.dts +++ b/dts/src/arm/imx6dl-riotboard.dts @@ -90,6 +90,7 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-handle = <&rgmii_phy>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/dts/src/arm/imx6dl-victgo.dts b/dts/src/arm/imx6dl-victgo.dts index 779b52858a..72df1dba83 100644 --- a/dts/src/arm/imx6dl-victgo.dts +++ b/dts/src/arm/imx6dl-victgo.dts @@ -18,14 +18,14 @@ pinctrl-0 = <&pinctrl_gpiokeys>; autorepeat; - power { + key-power { label = "Power Button"; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - enter { + key-enter { label = "Rotary Key"; gpios = <&gpio2 05 GPIO_ACTIVE_LOW>; linux,code = <KEY_ENTER>; diff --git a/dts/src/arm/imx6dl-yapp4-common.dtsi b/dts/src/arm/imx6dl-yapp4-common.dtsi index 674af39c88..52162e8c72 100644 --- a/dts/src/arm/imx6dl-yapp4-common.dtsi +++ b/dts/src/arm/imx6dl-yapp4-common.dtsi @@ -55,6 +55,7 @@ panel: panel { compatible = "dataimage,scf0700c48ggu18"; power-supply = <&sw2_reg>; + backlight = <&backlight>; status = "disabled"; port { diff --git a/dts/src/arm/imx6dl.dtsi b/dts/src/arm/imx6dl.dtsi index 8e0ed209ed..dc919e09a5 100644 --- a/dts/src/arm/imx6dl.dtsi +++ b/dts/src/arm/imx6dl.dtsi @@ -84,6 +84,9 @@ ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; diff --git a/dts/src/arm/imx6q-arm2.dts b/dts/src/arm/imx6q-arm2.dts index 0b40f52268..75586299d9 100644 --- a/dts/src/arm/imx6q-arm2.dts +++ b/dts/src/arm/imx6q-arm2.dts @@ -178,6 +178,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/dts/src/arm/imx6q-evi.dts b/dts/src/arm/imx6q-evi.dts index c63f371ede..78d941fef5 100644 --- a/dts/src/arm/imx6q-evi.dts +++ b/dts/src/arm/imx6q-evi.dts @@ -146,6 +146,7 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/dts/src/arm/imx6q-mccmon6.dts b/dts/src/arm/imx6q-mccmon6.dts index 55692c7394..f08b370102 100644 --- a/dts/src/arm/imx6q-mccmon6.dts +++ b/dts/src/arm/imx6q-mccmon6.dts @@ -100,8 +100,10 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; diff --git a/dts/src/arm/imx6q-novena.dts b/dts/src/arm/imx6q-novena.dts index 225cf6b7a7..ee8c0bd3ec 100644 --- a/dts/src/arm/imx6q-novena.dts +++ b/dts/src/arm/imx6q-novena.dts @@ -86,7 +86,7 @@ linux,code = <KEY_POWER>; }; - lid { + lid-event { label = "Lid"; gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; linux,input-type = <5>; /* EV_SW */ @@ -99,7 +99,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds_novena>; - heartbeat { + led-heartbeat { label = "novena:white:panel"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; diff --git a/dts/src/arm/imx6q-pistachio.dts b/dts/src/arm/imx6q-pistachio.dts index 7a33e54cc0..bad8d831e6 100644 --- a/dts/src/arm/imx6q-pistachio.dts +++ b/dts/src/arm/imx6q-pistachio.dts @@ -100,7 +100,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; wakeup-source; diff --git a/dts/src/arm/imx6q-sabrelite.dts b/dts/src/arm/imx6q-sabrelite.dts index dc51262e7b..7c6a2f234c 100644 --- a/dts/src/arm/imx6q-sabrelite.dts +++ b/dts/src/arm/imx6q-sabrelite.dts @@ -1,43 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/dts/src/arm/imx6q-utilite-pro.dts b/dts/src/arm/imx6q-utilite-pro.dts index d16ff2083d..ad59b23ef2 100644 --- a/dts/src/arm/imx6q-utilite-pro.dts +++ b/dts/src/arm/imx6q-utilite-pro.dts @@ -89,7 +89,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/dts/src/arm/imx6q-var-dt6customboard.dts b/dts/src/arm/imx6q-var-dt6customboard.dts index 6355035134..2290c12376 100644 --- a/dts/src/arm/imx6q-var-dt6customboard.dts +++ b/dts/src/arm/imx6q-var-dt6customboard.dts @@ -28,7 +28,7 @@ compatible = "gpio-keys"; autorepeat; - back { + key-back { gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; label = "Key Back"; @@ -37,7 +37,7 @@ wakeup-source; }; - home { + key-home { gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; label = "Key Home"; @@ -46,7 +46,7 @@ wakeup-source; }; - menu { + key-menu { gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; label = "Key Menu"; diff --git a/dts/src/arm/imx6q-yapp4-crux.dts b/dts/src/arm/imx6q-yapp4-crux.dts index 15f4824a51..bddf3822eb 100644 --- a/dts/src/arm/imx6q-yapp4-crux.dts +++ b/dts/src/arm/imx6q-yapp4-crux.dts @@ -33,6 +33,10 @@ status = "okay"; }; +®_pu { + regulator-always-on; +}; + ®_usb_h1_vbus { status = "okay"; }; diff --git a/dts/src/arm/imx6q.dtsi b/dts/src/arm/imx6q.dtsi index 3b77eae40e..df86049a69 100644 --- a/dts/src/arm/imx6q.dtsi +++ b/dts/src/arm/imx6q.dtsi @@ -163,6 +163,9 @@ ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x40000>; + ranges = <0 0x00900000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; diff --git a/dts/src/arm/imx6qdl-dhcom-pdk2.dtsi b/dts/src/arm/imx6qdl-dhcom-pdk2.dtsi index fe72650295..6248b126b5 100644 --- a/dts/src/arm/imx6qdl-dhcom-pdk2.dtsi +++ b/dts/src/arm/imx6qdl-dhcom-pdk2.dtsi @@ -332,37 +332,4 @@ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ >; }; - - pinctrl_ipu1_lcdif: ipu1-lcdif-grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 - >; - }; }; diff --git a/dts/src/arm/imx6qdl-dhcom-som.dtsi b/dts/src/arm/imx6qdl-dhcom-som.dtsi index 5befbe13d1..eaa87b3331 100644 --- a/dts/src/arm/imx6qdl-dhcom-som.dtsi +++ b/dts/src/arm/imx6qdl-dhcom-som.dtsi @@ -667,6 +667,39 @@ >; }; + pinctrl_ipu1_lcdif: ipu1-lcdif-grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 + >; + }; + pinctrl_pcie: pcie-grp { fsl,pins = < MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */ diff --git a/dts/src/arm/imx6qdl-gw52xx.dtsi b/dts/src/arm/imx6qdl-gw52xx.dtsi index b1df2beb28..728810b9d6 100644 --- a/dts/src/arm/imx6qdl-gw52xx.dtsi +++ b/dts/src/arm/imx6qdl-gw52xx.dtsi @@ -137,6 +137,16 @@ regulator-always-on; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; @@ -170,6 +180,7 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; status = "okay"; }; @@ -612,7 +623,6 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ >; }; @@ -702,6 +712,12 @@ >; }; + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 diff --git a/dts/src/arm/imx6qdl-gw53xx.dtsi b/dts/src/arm/imx6qdl-gw53xx.dtsi index a0710d5627..6c0c109046 100644 --- a/dts/src/arm/imx6qdl-gw53xx.dtsi +++ b/dts/src/arm/imx6qdl-gw53xx.dtsi @@ -129,6 +129,16 @@ regulator-always-on; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_h1_vbus"; @@ -170,6 +180,7 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; status = "okay"; }; @@ -600,7 +611,6 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ >; }; @@ -691,6 +701,12 @@ >; }; + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 diff --git a/dts/src/arm/imx6qdl-gw54xx.dtsi b/dts/src/arm/imx6qdl-gw54xx.dtsi index cda48bf2f1..a9b04f9f1c 100644 --- a/dts/src/arm/imx6qdl-gw54xx.dtsi +++ b/dts/src/arm/imx6qdl-gw54xx.dtsi @@ -137,6 +137,16 @@ regulator-always-on; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usb_h1_vbus: regulator@2 { compatible = "regulator-fixed"; reg = <2>; @@ -200,6 +210,7 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; status = "okay"; }; @@ -687,7 +698,6 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ >; }; @@ -786,6 +796,12 @@ >; }; + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 diff --git a/dts/src/arm/imx6qdl-gw5910.dtsi b/dts/src/arm/imx6qdl-gw5910.dtsi index 68e5ab2e27..6bb4855d13 100644 --- a/dts/src/arm/imx6qdl-gw5910.dtsi +++ b/dts/src/arm/imx6qdl-gw5910.dtsi @@ -29,7 +29,7 @@ user-pb { label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; diff --git a/dts/src/arm/imx6qdl-gw5913.dtsi b/dts/src/arm/imx6qdl-gw5913.dtsi index 8e23cec714..696427b487 100644 --- a/dts/src/arm/imx6qdl-gw5913.dtsi +++ b/dts/src/arm/imx6qdl-gw5913.dtsi @@ -26,7 +26,7 @@ user-pb { label = "user_pb"; - gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; diff --git a/dts/src/arm/imx6qdl-kontron-samx6i.dtsi b/dts/src/arm/imx6qdl-kontron-samx6i.dtsi index 6b791d515e..85aeebc948 100644 --- a/dts/src/arm/imx6qdl-kontron-samx6i.dtsi +++ b/dts/src/arm/imx6qdl-kontron-samx6i.dtsi @@ -260,7 +260,23 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-handle = <ðphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; }; &i2c_intern { @@ -387,7 +403,7 @@ /* HDMI_CTRL */ &i2c2 { - clock-frequency = <375000>; + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; }; diff --git a/dts/src/arm/imx6qdl-mba6.dtsi b/dts/src/arm/imx6qdl-mba6.dtsi index f4dca20669..78555a6188 100644 --- a/dts/src/arm/imx6qdl-mba6.dtsi +++ b/dts/src/arm/imx6qdl-mba6.dtsi @@ -244,7 +244,6 @@ status = "okay"; }; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; diff --git a/dts/src/arm/imx6qdl-nit6xlite.dtsi b/dts/src/arm/imx6qdl-nit6xlite.dtsi index 0ad4cb4f1e..a53a5d0766 100644 --- a/dts/src/arm/imx6qdl-nit6xlite.dtsi +++ b/dts/src/arm/imx6qdl-nit6xlite.dtsi @@ -192,6 +192,7 @@ phy-mode = "rgmii"; phy-handle = <ðphy>; phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi index beaa2dcd43..57c21a01f1 100644 --- a/dts/src/arm/imx6qdl-nitrogen6_max.dtsi +++ b/dts/src/arm/imx6qdl-nitrogen6_max.dtsi @@ -334,6 +334,7 @@ phy-mode = "rgmii"; phy-handle = <ðphy>; phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi index ee7e2371f9..000e9dc97b 100644 --- a/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi +++ b/dts/src/arm/imx6qdl-nitrogen6_som2.dtsi @@ -263,6 +263,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/dts/src/arm/imx6qdl-nitrogen6x.dtsi b/dts/src/arm/imx6qdl-nitrogen6x.dtsi index 904d5d051d..731759bdd7 100644 --- a/dts/src/arm/imx6qdl-nitrogen6x.dtsi +++ b/dts/src/arm/imx6qdl-nitrogen6x.dtsi @@ -267,6 +267,7 @@ phy-mode = "rgmii"; phy-handle = <ðphy>; phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/dts/src/arm/imx6qdl-phytec-mira-peb-av-02.dtsi b/dts/src/arm/imx6qdl-phytec-mira-peb-av-02.dtsi index 393475cb0f..0020dbb172 100644 --- a/dts/src/arm/imx6qdl-phytec-mira-peb-av-02.dtsi +++ b/dts/src/arm/imx6qdl-phytec-mira-peb-av-02.dtsi @@ -64,7 +64,7 @@ interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_NONE>; status = "disabled"; - }; + }; }; &ipu1_di0_disp0 { diff --git a/dts/src/arm/imx6qdl-sabreauto.dtsi b/dts/src/arm/imx6qdl-sabreauto.dtsi index 1368a47620..3dbb460ef1 100644 --- a/dts/src/arm/imx6qdl-sabreauto.dtsi +++ b/dts/src/arm/imx6qdl-sabreauto.dtsi @@ -295,6 +295,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/dts/src/arm/imx6qdl-sabrelite.dtsi b/dts/src/arm/imx6qdl-sabrelite.dtsi index 901b9a761b..22f8e2783c 100644 --- a/dts/src/arm/imx6qdl-sabrelite.dtsi +++ b/dts/src/arm/imx6qdl-sabrelite.dtsi @@ -1,43 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/clock/imx6qdl-clock.h> diff --git a/dts/src/arm/imx6qdl-skov-cpu-revc.dtsi b/dts/src/arm/imx6qdl-skov-cpu-revc.dtsi index 8254bce1b8..b81799d707 100644 --- a/dts/src/arm/imx6qdl-skov-cpu-revc.dtsi +++ b/dts/src/arm/imx6qdl-skov-cpu-revc.dtsi @@ -2,35 +2,60 @@ // // Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de> +/ { + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <65000>; + touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; +}; + &ecspi4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; status = "okay"; - touchscreen@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - compatible = "ti,tsc2046"; + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; reg = <0>; + pinctrl-0 = <&pinctrl_touch>; + pinctrl-names ="default"; spi-max-frequency = <1000000>; interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>; - vcc-supply = <®_3v3>; - pendown-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = /bits/ 16 <850>; - ti,y-plate-ohms = /bits/ 16 <295>; - ti,pressure-min = /bits/ 16 <2>; - ti,pressure-max = /bits/ 16 <1500>; - ti,vref-mv = /bits/ 16 <3300>; - ti,settle-delay-usec = /bits/ 16 <15>; - ti,vref-delay-usecs = /bits/ 16 <0>; - ti,penirq-recheck-delay-usecs = /bits/ 16 <100>; - ti,debounce-max = /bits/ 16 <100>; - ti,debounce-tol = /bits/ 16 <(~0)>; - ti,debounce-rep = /bits/ 16 <4>; - touchscreen-swapped-x-y; - touchscreen-inverted-y; - wakeup-source; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; }; }; diff --git a/dts/src/arm/imx6qdl-tqma6a.dtsi b/dts/src/arm/imx6qdl-tqma6a.dtsi index 7dc3f0005b..aff46f3040 100644 --- a/dts/src/arm/imx6qdl-tqma6a.dtsi +++ b/dts/src/arm/imx6qdl-tqma6a.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> &fec { + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; @@ -35,6 +36,7 @@ compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; + vcc-supply = <®_3p3v>; }; }; diff --git a/dts/src/arm/imx6qdl-tqma6b.dtsi b/dts/src/arm/imx6qdl-tqma6b.dtsi index dd09257664..a3f6543c3a 100644 --- a/dts/src/arm/imx6qdl-tqma6b.dtsi +++ b/dts/src/arm/imx6qdl-tqma6b.dtsi @@ -29,5 +29,6 @@ compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; + vcc-supply = <®_3p3v>; }; }; diff --git a/dts/src/arm/imx6qdl-ts7970.dtsi b/dts/src/arm/imx6qdl-ts7970.dtsi index d6ba4b2a60..c096d25a6f 100644 --- a/dts/src/arm/imx6qdl-ts7970.dtsi +++ b/dts/src/arm/imx6qdl-ts7970.dtsi @@ -192,6 +192,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; + /delete-property/ interrupts; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; diff --git a/dts/src/arm/imx6qdl-vicut1.dtsi b/dts/src/arm/imx6qdl-vicut1.dtsi index c5a98b0110..c4e6cf0527 100644 --- a/dts/src/arm/imx6qdl-vicut1.dtsi +++ b/dts/src/arm/imx6qdl-vicut1.dtsi @@ -37,6 +37,16 @@ power-supply = <®_3v3>; }; + /* only for backwards compatibility with old HW */ + backlight_isb: backlight-isb { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = <0 8 48 255>; + num-interpolated-steps = <5>; + default-brightness-level = <0>; + power-supply = <®_3v3>; + }; + connector { compatible = "composite-video-connector"; label = "Composite0"; @@ -370,6 +380,12 @@ status = "okay"; }; +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; @@ -601,6 +617,12 @@ >; }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0 + >; + }; + pinctrl_pwm3: pwm3grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 diff --git a/dts/src/arm/imx6qdl.dtsi b/dts/src/arm/imx6qdl.dtsi index 4f7fefc14d..ff1e0173b3 100644 --- a/dts/src/arm/imx6qdl.dtsi +++ b/dts/src/arm/imx6qdl.dtsi @@ -929,7 +929,7 @@ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; }; - sdma: sdma@20ec000 { + sdma: dma-controller@20ec000 { compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm/imx6qp-yapp4-crux-plus.dts b/dts/src/arm/imx6qp-yapp4-crux-plus.dts index cea165f216..afaf4a6759 100644 --- a/dts/src/arm/imx6qp-yapp4-crux-plus.dts +++ b/dts/src/arm/imx6qp-yapp4-crux-plus.dts @@ -33,6 +33,10 @@ status = "okay"; }; +®_pu { + regulator-always-on; +}; + ®_usb_h1_vbus { status = "okay"; }; diff --git a/dts/src/arm/imx6qp.dtsi b/dts/src/arm/imx6qp.dtsi index 0503655138..fc164991d2 100644 --- a/dts/src/arm/imx6qp.dtsi +++ b/dts/src/arm/imx6qp.dtsi @@ -9,12 +9,18 @@ ocram2: sram@940000 { compatible = "mmio-sram"; reg = <0x00940000 0x20000>; + ranges = <0 0x00940000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; ocram3: sram@960000 { compatible = "mmio-sram"; reg = <0x00960000 0x20000>; + ranges = <0 0x00960000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi index 06a515121d..28111efb19 100644 --- a/dts/src/arm/imx6sl.dtsi +++ b/dts/src/arm/imx6sl.dtsi @@ -61,10 +61,10 @@ <792000 1175000>, <396000 975000>; fsl,soc-operating-points = - /* ARM kHz SOC-PU uV */ - <996000 1225000>, - <792000 1175000>, - <396000 1175000>; + /* ARM kHz SOC-PU uV */ + <996000 1225000>, + <792000 1175000>, + <396000 1175000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, @@ -115,6 +115,9 @@ ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6SL_CLK_OCRAM>; }; @@ -222,7 +225,7 @@ uart5: serial@2018000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02018000 0x4000>; interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -235,7 +238,7 @@ uart1: serial@2020000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -248,7 +251,7 @@ uart2: serial@2024000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02024000 0x4000>; interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -309,7 +312,7 @@ uart3: serial@2034000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02034000 0x4000>; interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -322,7 +325,7 @@ uart4: serial@2038000 { compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02038000 0x4000>; interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_UART>, @@ -711,7 +714,7 @@ #power-domain-cells = <0>; power-supply = <®_pu>; clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; + <&clks IMX6SL_CLK_GPU2D_PODF>; }; pd_disp: power-domain@2 { @@ -747,7 +750,7 @@ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; }; - sdma: sdma@20ec000 { + sdma: dma-controller@20ec000 { compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm/imx6sll.dtsi b/dts/src/arm/imx6sll.dtsi index d4a000c3dd..2873369a57 100644 --- a/dts/src/arm/imx6sll.dtsi +++ b/dts/src/arm/imx6sll.dtsi @@ -115,6 +115,9 @@ ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; }; intc: interrupt-controller@a01000 { diff --git a/dts/src/arm/imx6sx-udoo-neo.dtsi b/dts/src/arm/imx6sx-udoo-neo.dtsi index 35861bbea9..c84ea1fac5 100644 --- a/dts/src/arm/imx6sx-udoo-neo.dtsi +++ b/dts/src/arm/imx6sx-udoo-neo.dtsi @@ -226,7 +226,7 @@ &iomuxc { pinctrl_bt_reg: btreggrp { fsl,pins = - <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>; + <MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x15059>; }; pinctrl_enet1: enet1grp { @@ -306,7 +306,6 @@ >; }; - pinctrl_uart1: uart1grp { fsl,pins = <MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1>, @@ -347,24 +346,23 @@ pinctrl_otg1_reg: otg1grp { fsl,pins = - <MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>; + <MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0>; }; - pinctrl_otg2_reg: otg2grp { fsl,pins = - <MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>; + <MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x10b0>; }; pinctrl_usb_otg1: usbotg1grp { fsl,pins = - <MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>, - <MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>; + <MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059>, + <MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x10b0>; }; pinctrl_usb_otg2: usbot2ggrp { fsl,pins = - <MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>; + <MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x10b0>; }; pinctrl_usdhc2: usdhc2grp { diff --git a/dts/src/arm/imx6sx.dtsi b/dts/src/arm/imx6sx.dtsi index 4d075e2bf7..abc3572d69 100644 --- a/dts/src/arm/imx6sx.dtsi +++ b/dts/src/arm/imx6sx.dtsi @@ -164,12 +164,18 @@ ocram_s: sram@8f8000 { compatible = "mmio-sram"; reg = <0x008f8000 0x4000>; + ranges = <0 0x008f8000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6SX_CLK_OCRAM_S>; }; ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; @@ -842,7 +848,7 @@ reg = <0x020e4000 0x4000>; }; - sdma: sdma@20ec000 { + sdma: dma-controller@20ec000 { compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm/imx6ul-14x14-evk.dtsi b/dts/src/arm/imx6ul-14x14-evk.dtsi index 1a18c41ce3..c83e64a62d 100644 --- a/dts/src/arm/imx6ul-14x14-evk.dtsi +++ b/dts/src/arm/imx6ul-14x14-evk.dtsi @@ -82,7 +82,7 @@ "AMIC", "MICB"; }; - spi4 { + spi-4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; diff --git a/dts/src/arm/imx6ul-kontron-n6310-s-43.dts b/dts/src/arm/imx6ul-kontron-bl-43.dts index 5bfad4655b..0c643706a1 100644 --- a/dts/src/arm/imx6ul-kontron-n6310-s-43.dts +++ b/dts/src/arm/imx6ul-kontron-bl-43.dts @@ -5,12 +5,12 @@ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> */ -#include "imx6ul-kontron-n6310-s.dts" +#include "imx6ul-kontron-bl.dts" / { - model = "Kontron N6310 S 43"; - compatible = "kontron,imx6ul-n6310-s-43", "kontron,imx6ul-n6310-s", - "kontron,imx6ul-n6310-som", "fsl,imx6ul"; + model = "Kontron BL i.MX6UL 43 (N631X S 43)"; + compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul", + "kontron,sl-imx6ul", "fsl,imx6ul"; backlight { compatible = "pwm-backlight"; diff --git a/dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi b/dts/src/arm/imx6ul-kontron-bl-common.dtsi index 43868311f4..43868311f4 100644 --- a/dts/src/arm/imx6ul-kontron-n6x1x-s.dtsi +++ b/dts/src/arm/imx6ul-kontron-bl-common.dtsi diff --git a/dts/src/arm/imx6ul-kontron-n6310-s.dts b/dts/src/arm/imx6ul-kontron-bl.dts index 5a3e06d621..dadf6d3d5f 100644 --- a/dts/src/arm/imx6ul-kontron-n6310-s.dts +++ b/dts/src/arm/imx6ul-kontron-bl.dts @@ -7,11 +7,10 @@ /dts-v1/; -#include "imx6ul-kontron-n6310-som.dtsi" -#include "imx6ul-kontron-n6x1x-s.dtsi" +#include "imx6ul-kontron-sl.dtsi" +#include "imx6ul-kontron-bl-common.dtsi" / { - model = "Kontron N6310 S"; - compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som", - "fsl,imx6ul"; + model = "Kontron BL i.MX6UL (N631X S)"; + compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul"; }; diff --git a/dts/src/arm/imx6ul-kontron-n6310-som.dtsi b/dts/src/arm/imx6ul-kontron-n6310-som.dtsi deleted file mode 100644 index acd936540d..0000000000 --- a/dts/src/arm/imx6ul-kontron-n6310-som.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-n6x1x-som-common.dtsi" - -/ { - model = "Kontron N6310 SOM"; - compatible = "kontron,imx6ul-n6310-som", "fsl,imx6ul"; - - memory@80000000 { - reg = <0x80000000 0x10000000>; - device_type = "memory"; - }; -}; - -&qspi { - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <108000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - - partition@8000000 { - label = "ubi2"; - reg = <0x08000000 0x08000000>; - }; - }; -}; diff --git a/dts/src/arm/imx6ul-kontron-n6311-s.dts b/dts/src/arm/imx6ul-kontron-n6311-s.dts deleted file mode 100644 index 239a1af3ae..0000000000 --- a/dts/src/arm/imx6ul-kontron-n6311-s.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ul-kontron-n6311-som.dtsi" -#include "imx6ul-kontron-n6x1x-s.dtsi" - -/ { - model = "Kontron N6311 S"; - compatible = "kontron,imx6ul-n6311-s", "kontron,imx6ul-n6311-som", - "fsl,imx6ul"; -}; diff --git a/dts/src/arm/imx6ul-kontron-n6311-som.dtsi b/dts/src/arm/imx6ul-kontron-n6311-som.dtsi deleted file mode 100644 index 29ed38dce5..0000000000 --- a/dts/src/arm/imx6ul-kontron-n6311-som.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-n6x1x-som-common.dtsi" - -/ { - model = "Kontron N6311 SOM"; - compatible = "kontron,imx6ul-n6311-som", "fsl,imx6ul"; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - device_type = "memory"; - }; -}; - -&qspi { - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - - partition@8000000 { - label = "ubi2"; - reg = <0x08000000 0x18000000>; - }; - }; -}; diff --git a/dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi b/dts/src/arm/imx6ul-kontron-sl-common.dtsi index 09a83dbdf6..dcf88f6103 100644 --- a/dts/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi +++ b/dts/src/arm/imx6ul-kontron-sl-common.dtsi @@ -11,6 +11,11 @@ chosen { stdout-path = &uart4; }; + + memory@80000000 { + reg = <0x80000000 0x10000000>; + device_type = "memory"; + }; }; &ecspi2 { @@ -55,6 +60,16 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + }; }; &wdog1 { diff --git a/dts/src/arm/imx6ul-kontron-sl.dtsi b/dts/src/arm/imx6ul-kontron-sl.dtsi new file mode 100644 index 0000000000..0580d043e5 --- /dev/null +++ b/dts/src/arm/imx6ul-kontron-sl.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> + */ + +#include "imx6ul.dtsi" +#include "imx6ul-kontron-sl-common.dtsi" + +/ { + model = "Kontron SL i.MX6UL (N631X SOM)"; + compatible = "kontron,sl-imx6ul", "fsl,imx6ul"; +}; diff --git a/dts/src/arm/imx6ul-tx6ul.dtsi b/dts/src/arm/imx6ul-tx6ul.dtsi index c485d058e0..15ee0275fe 100644 --- a/dts/src/arm/imx6ul-tx6ul.dtsi +++ b/dts/src/arm/imx6ul-tx6ul.dtsi @@ -212,7 +212,7 @@ enable-active-high; }; - spi_gpio: spi-gpio { + spi_gpio: spi { #address-cells = <1>; #size-cells = <0>; compatible = "spi-gpio"; diff --git a/dts/src/arm/imx6ul.dtsi b/dts/src/arm/imx6ul.dtsi index c95efd1d8c..2b59963957 100644 --- a/dts/src/arm/imx6ul.dtsi +++ b/dts/src/arm/imx6ul.dtsi @@ -744,7 +744,7 @@ status = "disabled"; }; - sdma: sdma@20ec000 { + sdma: dma-controller@20ec000 { compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; diff --git a/dts/src/arm/imx6ull-kontron-bl.dts b/dts/src/arm/imx6ull-kontron-bl.dts new file mode 100644 index 0000000000..fa016465cd --- /dev/null +++ b/dts/src/arm/imx6ull-kontron-bl.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6ull-kontron-sl.dtsi" +#include "imx6ul-kontron-bl-common.dtsi" + +/ { + model = "Kontron BL i.MX6ULL (N641X S)"; + compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull"; +}; diff --git a/dts/src/arm/imx6ull-kontron-n6411-s.dts b/dts/src/arm/imx6ull-kontron-n6411-s.dts deleted file mode 100644 index 57588a5e1e..0000000000 --- a/dts/src/arm/imx6ull-kontron-n6411-s.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2019 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ull-kontron-n6411-som.dtsi" -#include "imx6ul-kontron-n6x1x-s.dtsi" - -/ { - model = "Kontron N6411 S"; - compatible = "kontron,imx6ull-n6411-s", "kontron,imx6ull-n6411-som", - "fsl,imx6ull"; -}; diff --git a/dts/src/arm/imx6ull-kontron-n6411-som.dtsi b/dts/src/arm/imx6ull-kontron-n6411-som.dtsi deleted file mode 100644 index d000606c07..0000000000 --- a/dts/src/arm/imx6ull-kontron-n6411-som.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ull.dtsi" -#include "imx6ul-kontron-n6x1x-som-common.dtsi" - -/ { - model = "Kontron N6411 SOM"; - compatible = "kontron,imx6ull-n6311-som", "fsl,imx6ull"; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - device_type = "memory"; - }; -}; - -&qspi { - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - - partition@0 { - label = "ubi1"; - reg = <0x00000000 0x08000000>; - }; - - partition@8000000 { - label = "ubi2"; - reg = <0x08000000 0x18000000>; - }; - }; -}; diff --git a/dts/src/arm/imx6ull-kontron-sl.dtsi b/dts/src/arm/imx6ull-kontron-sl.dtsi new file mode 100644 index 0000000000..93f10eb349 --- /dev/null +++ b/dts/src/arm/imx6ull-kontron-sl.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ull.dtsi" +#include "imx6ul-kontron-sl-common.dtsi" + +/ { + model = "Kontron SL i.MX6ULL (N641X SOM)"; + compatible = "kontron,sl-imx6ull", "fsl,imx6ull"; +}; diff --git a/dts/src/arm/imx7d-pico.dtsi b/dts/src/arm/imx7d-pico.dtsi index e519897fae..e0bff39e8d 100644 --- a/dts/src/arm/imx7d-pico.dtsi +++ b/dts/src/arm/imx7d-pico.dtsi @@ -41,7 +41,7 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; enable-active-high; - }; + }; reg_wlreg_on: regulator-wlreg_on { compatible = "regulator-fixed"; @@ -432,7 +432,7 @@ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */ + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */ >; }; @@ -493,19 +493,19 @@ pinctrl_pwm1: pwm1 { fsl,pins = < - MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f >; }; pinctrl_pwm2: pwm2 { fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f >; }; pinctrl_pwm3: pwm3 { fsl,pins = < - MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f + MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f >; }; diff --git a/dts/src/arm/imx7d-sdb.dts b/dts/src/arm/imx7d-sdb.dts index 78f4224a9b..f483bc0afe 100644 --- a/dts/src/arm/imx7d-sdb.dts +++ b/dts/src/arm/imx7d-sdb.dts @@ -24,14 +24,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -39,7 +39,7 @@ }; }; - spi4 { + spi-4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; @@ -206,12 +206,7 @@ interrupt-parent = <&gpio2>; interrupts = <29 0>; pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <0>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <0>; - ti,pressure-max = /bits/ 16 <0>; - ti,x-plate-ohms = /bits/ 16 <400>; + touchscreen-max-pressure = <255>; wakeup-source; }; }; diff --git a/dts/src/arm/imx7d-zii-rmu2.dts b/dts/src/arm/imx7d-zii-rmu2.dts index 1065941807..1c9f25848b 100644 --- a/dts/src/arm/imx7d-zii-rmu2.dts +++ b/dts/src/arm/imx7d-zii-rmu2.dts @@ -24,7 +24,7 @@ pinctrl-0 = <&pinctrl_leds_debug>; pinctrl-names = "default"; - debug { + led-debug { label = "zii:green:debug1"; gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/dts/src/arm/imx7d-zii-rpu2.dts b/dts/src/arm/imx7d-zii-rpu2.dts index 893bd30aa2..9d29490ab4 100644 --- a/dts/src/arm/imx7d-zii-rpu2.dts +++ b/dts/src/arm/imx7d-zii-rpu2.dts @@ -36,7 +36,7 @@ pinctrl-0 = <&pinctrl_leds_debug>; pinctrl-names = "default"; - debug { + led-debug { label = "zii:green:debug1"; gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/dts/src/arm/imx7s.dtsi b/dts/src/arm/imx7s.dtsi index 29148285f9..0fc9e6b8b0 100644 --- a/dts/src/arm/imx7s.dtsi +++ b/dts/src/arm/imx7s.dtsi @@ -1224,7 +1224,7 @@ status = "disabled"; }; - sdma: sdma@30bd0000 { + sdma: dma-controller@30bd0000 { compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm/imx7ulp.dtsi b/dts/src/arm/imx7ulp.dtsi index bcec98b964..7f7d2d5122 100644 --- a/dts/src/arm/imx7ulp.dtsi +++ b/dts/src/arm/imx7ulp.dtsi @@ -328,8 +328,9 @@ compatible = "fsl,imx7ulp-lpi2c"; reg = <0x40a40000 0x10000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - clock-names = "ipg"; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; @@ -340,8 +341,9 @@ compatible = "fsl,imx7ulp-lpi2c"; reg = <0x40a50000 0x10000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - clock-names = "ipg"; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "per", "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; diff --git a/dts/src/arm/kirkwood-6192.dtsi b/dts/src/arm/kirkwood-6192.dtsi index 396bcba08a..705c0d7eff 100644 --- a/dts/src/arm/kirkwood-6192.dtsi +++ b/dts/src/arm/kirkwood-6192.dtsi @@ -26,12 +26,22 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gate_clk 2>; status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/dts/src/arm/kirkwood-6281.dtsi b/dts/src/arm/kirkwood-6281.dtsi index faa05849a4..8e311165fd 100644 --- a/dts/src/arm/kirkwood-6281.dtsi +++ b/dts/src/arm/kirkwood-6281.dtsi @@ -26,12 +26,22 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gate_clk 2>; status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/dts/src/arm/kirkwood-6282.dtsi b/dts/src/arm/kirkwood-6282.dtsi index e84c54b77d..e33723160c 100644 --- a/dts/src/arm/kirkwood-6282.dtsi +++ b/dts/src/arm/kirkwood-6282.dtsi @@ -30,12 +30,22 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gate_clk 2>; status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; pcie1: pcie@2,0 { @@ -48,12 +58,22 @@ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 10>; + interrupt-names = "intx", "error"; + interrupts = <10>, <45>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gate_clk 18>; status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/dts/src/arm/kirkwood-98dx4122.dtsi b/dts/src/arm/kirkwood-98dx4122.dtsi index 299c147298..c3469a2fc5 100644 --- a/dts/src/arm/kirkwood-98dx4122.dtsi +++ b/dts/src/arm/kirkwood-98dx4122.dtsi @@ -26,12 +26,22 @@ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gate_clk 2>; status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/dts/src/arm/kirkwood-lsxl.dtsi b/dts/src/arm/kirkwood-lsxl.dtsi index 7b151acb99..88b70ba1c8 100644 --- a/dts/src/arm/kirkwood-lsxl.dtsi +++ b/dts/src/arm/kirkwood-lsxl.dtsi @@ -10,6 +10,11 @@ ocp@f1000000 { pinctrl: pin-controller@10000 { + /* Non-default UART pins */ + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp4", "mpp5"; + }; + pmx_power_hdd: pmx-power-hdd { marvell,pins = "mpp10"; marvell,function = "gpo"; @@ -213,22 +218,11 @@ &mdio { status = "okay"; - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - ethphy1: ethernet-phy@8 { reg = <8>; }; }; -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - ð1 { status = "okay"; ethernet1-port@0 { diff --git a/dts/src/arm/lan966x-pcb8290.dts b/dts/src/arm/lan966x-pcb8290.dts new file mode 100644 index 0000000000..77187f59f0 --- /dev/null +++ b/dts/src/arm/lan966x-pcb8290.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Horatiu Vultur <horatiu.vultur@microchip.com> + */ +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB LAN9668"; + compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966"; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +&aes { + status = "disabled"; /* Reserved by secure OS */ +}; + +&gpio { + miim_a_pins: mdio-pins { + /* MDC, MDIO */ + pins = "GPIO_28", "GPIO_29"; + function = "miim_a"; + }; + + pps_out_pins: pps-out-pins { + /* 1pps output */ + pins = "GPIO_38"; + function = "ptpsync_3"; + }; + + ptp_ext_pins: ptp-ext-pins { + /* 1pps input */ + pins = "GPIO_35"; + function = "ptpsync_0"; + }; + + udc_pins: ucd-pins { + /* VBUS_DET B */ + pins = "GPIO_8"; + function = "usb_slave_b"; + }; +}; + +&mdio0 { + pinctrl-0 = <&miim_a_pins>; + pinctrl-names = "default"; + status = "okay"; + + ext_phy0: ethernet-phy@7 { + reg = <7>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy1: ethernet-phy@8 { + reg = <8>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy2: ethernet-phy@9 { + reg = <9>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy3: ethernet-phy@10 { + reg = <10>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy4: ethernet-phy@15 { + reg = <15>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy5: ethernet-phy@16 { + reg = <16>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy6: ethernet-phy@17 { + reg = <17>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; + + ext_phy7: ethernet-phy@18 { + reg = <18>; + coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; + }; +}; + +&port0 { + reg = <2>; + phy-handle = <&ext_phy2>; + phy-mode = "qsgmii"; + phys = <&serdes 0 SERDES6G(1)>; + status = "okay"; +}; + +&port1 { + reg = <3>; + phy-handle = <&ext_phy3>; + phy-mode = "qsgmii"; + phys = <&serdes 1 SERDES6G(1)>; + status = "okay"; +}; + +&port2 { + reg = <0>; + phy-handle = <&ext_phy0>; + phy-mode = "qsgmii"; + phys = <&serdes 2 SERDES6G(1)>; + status = "okay"; +}; + +&port3 { + reg = <1>; + phy-handle = <&ext_phy1>; + phy-mode = "qsgmii"; + phys = <&serdes 3 SERDES6G(1)>; + status = "okay"; +}; + +&port4 { + reg = <6>; + phy-handle = <&ext_phy6>; + phy-mode = "qsgmii"; + phys = <&serdes 4 SERDES6G(2)>; + status = "okay"; +}; + +&port5 { + reg = <7>; + phy-handle = <&ext_phy7>; + phy-mode = "qsgmii"; + phys = <&serdes 5 SERDES6G(2)>; + status = "okay"; +}; + +&port6 { + reg = <4>; + phy-handle = <&ext_phy4>; + phy-mode = "qsgmii"; + phys = <&serdes 6 SERDES6G(2)>; + status = "okay"; +}; + +&port7 { + reg = <5>; + phy-handle = <&ext_phy5>; + phy-mode = "qsgmii"; + phys = <&serdes 7 SERDES6G(2)>; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&switch { + pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&udc { + pinctrl-0 = <&udc_pins>; + pinctrl-names = "default"; + atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/dts/src/arm/lan966x-pcb8291.dts b/dts/src/arm/lan966x-pcb8291.dts index 24d9055c4a..f4f054cdf2 100644 --- a/dts/src/arm/lan966x-pcb8291.dts +++ b/dts/src/arm/lan966x-pcb8291.dts @@ -23,6 +23,38 @@ gpios = <&gpio 56 GPIO_ACTIVE_LOW>; priority = <200>; }; + + leds { + compatible = "gpio-leds"; + + led-s0-blue { + label = "s0:blue"; + gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s0-green { + label = "s0:green"; + gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-blue { + label = "s1:blue"; + gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-green { + label = "s1:green"; + gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&aes { + status = "disabled"; /* Reserved by secure OS */ }; &gpio { diff --git a/dts/src/arm/lan966x-pcb8309.dts b/dts/src/arm/lan966x-pcb8309.dts index 05ce27ed56..c436cd20d4 100644 --- a/dts/src/arm/lan966x-pcb8309.dts +++ b/dts/src/arm/lan966x-pcb8309.dts @@ -42,6 +42,34 @@ }; }; + leds { + compatible = "gpio-leds"; + + led-s0-green { + label = "s0:green"; + gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s0-red { + label = "s0:red"; + gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-green { + label = "s1:green"; + gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-s1-red { + label = "s1:red"; + gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + mux: mux-controller { compatible = "gpio-mux"; #mux-control-cells = <0>; @@ -69,6 +97,10 @@ }; }; +&aes { + status = "disabled"; /* Reserved by secure OS */ +}; + &flx3 { atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; status = "okay"; diff --git a/dts/src/arm/ls1021a.dtsi b/dts/src/arm/ls1021a.dtsi index fa761620f0..7c5510e344 100644 --- a/dts/src/arm/ls1021a.dtsi +++ b/dts/src/arm/ls1021a.dtsi @@ -647,7 +647,7 @@ status = "disabled"; }; - edma0: edma@2c00000 { + edma0: dma-controller@2c00000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; reg = <0x0 0x2c00000 0x0 0x10000>, diff --git a/dts/src/arm/qcom-apq8026-asus-sparrow.dts b/dts/src/arm/qcom-apq8026-asus-sparrow.dts index ace8cea279..215613c652 100644 --- a/dts/src/arm/qcom-apq8026-asus-sparrow.dts +++ b/dts/src/arm/qcom-apq8026-asus-sparrow.dts @@ -8,6 +8,8 @@ #include "qcom-msm8226.dtsi" #include "qcom-pm8226.dtsi" +/delete-node/ &adsp_region; + / { model = "ASUS ZenWatch 2"; compatible = "asus,sparrow", "qcom,apq8026"; @@ -57,6 +59,10 @@ }; }; +&adsp { + status = "okay"; +}; + &blsp1_uart1 { status = "okay"; diff --git a/dts/src/arm/qcom-apq8026-lg-lenok.dts b/dts/src/arm/qcom-apq8026-lg-lenok.dts index 2b7e52fda6..193569f0ca 100644 --- a/dts/src/arm/qcom-apq8026-lg-lenok.dts +++ b/dts/src/arm/qcom-apq8026-lg-lenok.dts @@ -8,6 +8,8 @@ #include "qcom-msm8226.dtsi" #include "qcom-pm8226.dtsi" +/delete-node/ &adsp_region; + / { model = "LG G Watch R"; compatible = "lg,lenok", "qcom,apq8026"; @@ -23,6 +25,13 @@ stdout-path = "serial0:115200n8"; }; + reserved-memory { + adsp_region: adsp@3300000 { + reg = <0x03300000 0x1400000>; + no-map; + }; + }; + vreg_wlan: wlan-regulator { compatible = "regulator-fixed"; @@ -38,6 +47,10 @@ }; }; +&adsp { + status = "okay"; +}; + &blsp1_i2c1 { status = "okay"; diff --git a/dts/src/arm/qcom-apq8060-dragonboard.dts b/dts/src/arm/qcom-apq8060-dragonboard.dts index 70a1dd629c..573e4dc66b 100644 --- a/dts/src/arm/qcom-apq8060-dragonboard.dts +++ b/dts/src/arm/qcom-apq8060-dragonboard.dts @@ -159,6 +159,19 @@ }; }; + dragon_gsbi3_i2c_pins: gsbi3_i2c { + mux { + pins = "gpio43", "gpio44"; + function = "gsbi3"; + }; + pinconf { + pins = "gpio43", "gpio44"; + drive-strength = <8>; + /* These have external pull-up 2.2kOhm to 1.8V */ + bias-disable; + }; + }; + dragon_gsbi8_i2c_pins: gsbi8_i2c { mux { pins = "gpio64", "gpio65"; @@ -240,6 +253,22 @@ bias-pull-up; }; }; + + dragon_tma340_gpios: tma340 { + reset { + /* RESET line, TS_ATTN, WAKE_CTP */ + pins = "gpio58"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + irq { + pins = "gpio61"; /* IRQ line */ + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; qcom,ssbi@500000 { @@ -444,6 +473,45 @@ }; }; + gsbi@16200000 { + qcom,mode = <GSBI_PROT_I2C>; + status = "okay"; + + gsbi3_i2c: i2c@16280000 { + pinctrl-names = "default"; + pinctrl-0 = <&dragon_gsbi3_i2c_pins>; + status = "okay"; + + touchscreen@24 { + compatible = "cypress,cy8ctma340"; + reg = <0x24>; + /* Certainly we can do at least 400 kHz */ + clock-frequency = <400000>; + /* IRQ on GPIO61 called /CTP_INT */ + interrupt-parent = <&tlmm>; + interrupts = <61 IRQ_TYPE_EDGE_FALLING>; + /* + * The I2C bus is using a PCA9306 level translator from L16A + * to L2B so these two voltages are needed and L16A is + * kind of the IO voltage, however L16Aisn't really fed to + * the TMA340, which relies entirely on L2B (PM8901 L2). + */ + vcpin-supply = <&pm8058_l16>; + vdd-supply = <&pm8901_l2>; + /* GPIO58, called WAKE_CTP */ + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + active-interval-ms = <0>; + touch-timeout-ms = <255>; + lowpower-interval-ms = <10>; + bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_tma340_gpios>; + }; + }; + }; + gsbi@19800000 { status = "okay"; qcom,mode = <GSBI_PROT_I2C>; @@ -634,7 +702,8 @@ bias-pull-down; }; l2 { - regulator-min-microvolt = <2850000>; + /* TMA340 requires strictly 3.3V */ + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; bias-pull-down; }; diff --git a/dts/src/arm/qcom-apq8064-cm-qs600.dts b/dts/src/arm/qcom-apq8064-cm-qs600.dts index e3bf57cd74..529629a0a9 100644 --- a/dts/src/arm/qcom-apq8064-cm-qs600.dts +++ b/dts/src/arm/qcom-apq8064-cm-qs600.dts @@ -215,7 +215,7 @@ vdda_refclk-supply = <&v3p3_fixed>; pinctrl-0 = <&pcie_pins>; pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; }; amba { diff --git a/dts/src/arm/qcom-apq8064-ifc6410.dts b/dts/src/arm/qcom-apq8064-ifc6410.dts index 0322cb88d4..a7f9021766 100644 --- a/dts/src/arm/qcom-apq8064-ifc6410.dts +++ b/dts/src/arm/qcom-apq8064-ifc6410.dts @@ -287,7 +287,7 @@ vdda_refclk-supply = <&ext_3p3v>; pinctrl-0 = <&pcie_pins>; pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; }; qcom,ssbi@500000 { diff --git a/dts/src/arm/qcom-apq8064.dtsi b/dts/src/arm/qcom-apq8064.dtsi index ada4c828bf..942aa22783 100644 --- a/dts/src/arm/qcom-apq8064.dtsi +++ b/dts/src/arm/qcom-apq8064.dtsi @@ -2,6 +2,7 @@ /dts-v1/; #include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/clock/qcom,lcc-msm8960.h> #include <dt-bindings/reset/qcom,gcc-msm8960.h> #include <dt-bindings/clock/qcom,mmcc-msm8960.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -815,6 +816,10 @@ #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; + clocks = <&cxo_board>, + <&pxo_board>, + <&lcc PLL4>; + clock-names = "cxo", "pxo", "pll4"; tsens: thermal-sensor { compatible = "qcom,msm8960-tsens"; @@ -834,6 +839,20 @@ reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; mmcc: clock-controller@4000000 { @@ -842,6 +861,22 @@ #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; }; l2cc: clock-controller@2011000 { @@ -1384,7 +1419,7 @@ }; pcie: pci@1b500000 { - compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; + compatible = "qcom,pcie-apq8064"; reg = <0x1b500000 0x1000>, <0x1b502000 0x80>, <0x1b600000 0x100>, diff --git a/dts/src/arm/qcom-apq8074-dragonboard.dts b/dts/src/arm/qcom-apq8074-dragonboard.dts index 3051a861ff..91716298ec 100644 --- a/dts/src/arm/qcom-apq8074-dragonboard.dts +++ b/dts/src/arm/qcom-apq8074-dragonboard.dts @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/gpio/gpio.h> #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" @@ -261,7 +262,7 @@ &sdhc_2 { status = "okay"; - cd-gpios = <&tlmm 62 0x1>; + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; vmmc-supply = <&pm8941_l21>; vqmmc-supply = <&pm8941_l13>; diff --git a/dts/src/arm/qcom-apq8084.dtsi b/dts/src/arm/qcom-apq8084.dtsi index 72f9255855..f2fb7c975a 100644 --- a/dts/src/arm/qcom-apq8084.dtsi +++ b/dts/src/arm/qcom-apq8084.dtsi @@ -239,6 +239,11 @@ reg = <0xf9011000 0x1000>; }; + sram@fc190000 { + compatible = "qcom,apq8084-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + qfprom: qfprom@fc4bc000 { compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x1000>; @@ -383,14 +388,9 @@ reg = <0xfc400000 0x4000>; }; - tcsr_mutex_regs: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; + tcsr_mutex: hwlock@fd484000 { + compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex"; + reg = <0xfd484000 0x1000>; #hwlock-cells = <1>; }; @@ -422,26 +422,26 @@ mmc@f9824900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; mmc@f98a4900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; diff --git a/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi b/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi index 03bb9e1768..0505270cf5 100644 --- a/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi +++ b/dts/src/arm/qcom-ipq4019-ap.dk01.1.dtsi @@ -14,6 +14,7 @@ * */ +#include <dt-bindings/gpio/gpio.h> #include "qcom-ipq4019.dtsi" / { @@ -72,7 +73,7 @@ pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; status = "okay"; - cs-gpios = <&tlmm 54 0>; + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; mx25l25635e@0 { #address-cells = <1>; diff --git a/dts/src/arm/qcom-ipq4019-ap.dk04.1.dtsi b/dts/src/arm/qcom-ipq4019-ap.dk04.1.dtsi index 44a9597d8b..a63b377863 100644 --- a/dts/src/arm/qcom-ipq4019-ap.dk04.1.dtsi +++ b/dts/src/arm/qcom-ipq4019-ap.dk04.1.dtsi @@ -87,7 +87,7 @@ pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; status = "okay"; - cs-gpios = <&tlmm 12 0>; + cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; flash@0 { #address-cells = <1>; @@ -100,7 +100,7 @@ pci@40000000 { status = "okay"; - perst-gpio = <&tlmm 38 0x1>; + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; qpic-nand@79b0000 { diff --git a/dts/src/arm/qcom-ipq4019-ap.dk07.1-c1.dts b/dts/src/arm/qcom-ipq4019-ap.dk07.1-c1.dts index c7a6e77da2..ea2987fcbf 100644 --- a/dts/src/arm/qcom-ipq4019-ap.dk07.1-c1.dts +++ b/dts/src/arm/qcom-ipq4019-ap.dk07.1-c1.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2018, The Linux Foundation. All rights reserved. +#include <dt-bindings/gpio/gpio.h> #include "qcom-ipq4019-ap.dk07.1.dtsi" / { @@ -10,7 +11,7 @@ soc { pci@40000000 { status = "okay"; - perst-gpio = <&tlmm 38 0x1>; + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; spi@78b6000 { @@ -50,7 +51,7 @@ pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; status = "okay"; - cs-gpios = <&tlmm 12 0>; + cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; flash@0 { #address-cells = <1>; diff --git a/dts/src/arm/qcom-ipq4019.dtsi b/dts/src/arm/qcom-ipq4019.dtsi index bb307b8f67..b23591110b 100644 --- a/dts/src/arm/qcom-ipq4019.dtsi +++ b/dts/src/arm/qcom-ipq4019.dtsi @@ -224,12 +224,13 @@ sdhci: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x11c>, <0x7824000 0x800>; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_DCD_XO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; @@ -412,7 +413,7 @@ }; pcie0: pci@40000000 { - compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; + compatible = "qcom,pcie-ipq4019"; reg = <0x40000000 0xf1d 0x40000f20 0xa8 0x80000 0x2000 diff --git a/dts/src/arm/qcom-ipq8062-smb208.dtsi b/dts/src/arm/qcom-ipq8062-smb208.dtsi new file mode 100644 index 0000000000..9d06255104 --- /dev/null +++ b/dts/src/arm/qcom-ipq8062-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "qcom-ipq8062.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/dts/src/arm/qcom-ipq8062.dtsi b/dts/src/arm/qcom-ipq8062.dtsi new file mode 100644 index 0000000000..5d3ebd3e2e --- /dev/null +++ b/dts/src/arm/qcom-ipq8062.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "qcom-ipq8064-v2.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8062"; + compatible = "qcom,ipq8062", "qcom,ipq8064"; +}; diff --git a/dts/src/arm/qcom-ipq8064-v2.0-smb208.dtsi b/dts/src/arm/qcom-ipq8064-v2.0-smb208.dtsi new file mode 100644 index 0000000000..0442580b22 --- /dev/null +++ b/dts/src/arm/qcom-ipq8064-v2.0-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064-v2.0.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/dts/src/arm/qcom-ipq8064-v2.0.dtsi b/dts/src/arm/qcom-ipq8064-v2.0.dtsi new file mode 100644 index 0000000000..2f117d576d --- /dev/null +++ b/dts/src/arm/qcom-ipq8064-v2.0.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064-v2.0"; + + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&gsbi4 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + /* + * The i2c device on gsbi4 should not be enabled. + * On ipq806x designs gsbi4 i2c is meant for exclusive + * RPM usage. Turning this on in kernel manifests as + * i2c failure for the RPM. + */ +}; + +&pcie0 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie1 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie2 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&sata { + ports-implemented = <0x1>; +}; + +&ss_phy_0 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; + +&ss_phy_1 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; diff --git a/dts/src/arm/qcom-ipq8064.dtsi b/dts/src/arm/qcom-ipq8064.dtsi index c8337c870b..90c08b5168 100644 --- a/dts/src/arm/qcom-ipq8064.dtsi +++ b/dts/src/arm/qcom-ipq8064.dtsi @@ -332,24 +332,64 @@ ranges; compatible = "simple-bus"; - lpass@28100000 { - compatible = "qcom,lpass-cpu"; - status = "disabled"; - clocks = <&lcc AHBIX_CLK>, - <&lcc MI2S_OSR_CLK>, - <&lcc MI2S_BIT_CLK>; - clock-names = "ahbix-clk", - "mi2s-osr-clk", - "mi2s-bit-clk"; - interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x28100000 0x10000>; - reg-names = "lpass-lpaif"; + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <7>; + snps,rd_osr_lmt = <7>; + snps,blen = <16 0 0 0 0 0 0>; + }; + + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-ipq8064"; + reg = <0x00108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ack", "err", "wakeup"; + + clocks = <&gcc RPM_MSG_RAM_H_CLK>; + clock-names = "ram"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + qfprom: qfprom@700000 { + compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + speedbin_efuse: speedbin@c0 { + reg = <0xc0 0x4>; + }; + tsens_calib: calib@400 { + reg = <0x400 0xb>; + }; + tsens_calib_backup: calib_backup@410 { + reg = <0x410 0xb>; + }; }; qcom_pinmux: pinmux@800000 { compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; + reg = <0x00800000 0x4000>; gpio-controller; gpio-ranges = <&qcom_pinmux 0 0 69>; @@ -471,6 +511,35 @@ }; }; + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064", "syscon"; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor@900000 { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; + + sfpb_mutex: hwlock@1200600 { + compatible = "qcom,sfpb-mutex"; + reg = <0x01200600 0x100>; + + #hwlock-cells = <1>; + }; + intc: interrupt-controller@2000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; @@ -500,46 +569,198 @@ cpu-offset = <0x80000>; }; + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x02011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + }; + acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; }; + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; }; - adm_dma: dma-controller@18300000 { - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; + nss_common: syscon@03000000 { + compatible = "syscon"; + reg = <0x03000000 0x0000FFFF>; + }; - resets = <&gcc ADM0_RESET>, - <&gcc ADM0_PBUS_RESET>, - <&gcc ADM0_C0_RESET>, - <&gcc ADM0_C1_RESET>, - <&gcc ADM0_C2_RESET>; - reset-names = "clk", "pbus", "c0", "c1", "c2"; - qcom,ee = <0>; + usb3_0: usb3@100f8800 { + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100f8800 0x8000>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_0_MASTER_RESET>; + reset-names = "master"; status = "disabled"; + + dwc3_0: dwc3@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + hs_phy_0: phy@100f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x100f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + ss_phy_0: phy@100f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x100f8830 0x30>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb3_1: usb3@110f8800 { + compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x110f8800 0x8000>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_1_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_1: dwc3@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hs_phy_1>, <&ss_phy_1>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + hs_phy_1: phy@110f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + ss_phy_1: phy@110f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x110f8830 0x30>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + sd-uhs-sdr104; + sd-uhs-ddr50; + vqmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc1: mmc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; }; gsbi1: gsbi@12440000 { @@ -654,56 +875,6 @@ }; }; - gsbi5: gsbi@1a200000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x1a200000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - syscon-tcsr = <&tcsr>; - - gsbi5_serial: serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x1000>, - <0x1a200000 0x1000>; - interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@1a280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - spi@1a280000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - gsbi6: gsbi@16500000 { compatible = "qcom,gsbi-v1.0.0"; reg = <0x16500000 0x100>; @@ -784,6 +955,82 @@ }; }; + adm_dma: dma-controller@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <0>; + + status = "disabled"; + }; + + gsbi5: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x1a200000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + + #size-cells = <1>; + ranges; + status = "disabled"; + + syscon-tcsr = <&tcsr>; + + gsbi5_serial: serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, + <0x1a200000 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + i2c@1a280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + spi@1a280000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; + rng@1a500000 { compatible = "qcom,prng"; reg = <0x1a500000 0x200>; @@ -791,17 +1038,6 @@ clock-names = "core"; }; - sata_phy: sata-phy@1b400000 { - compatible = "qcom,ipq806x-sata-phy"; - reg = <0x1b400000 0x200>; - - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - - #phy-cells = <0>; - status = "disabled"; - }; - nand: nand-controller@1ac00000 { compatible = "qcom,ipq806x-nand"; reg = <0x1ac00000 0x800>; @@ -824,113 +1060,17 @@ status = "disabled"; }; - sata: sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; - - interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", - "rxoob", "pmalive"; + sata_phy: sata-phy@1b400000 { + compatible = "qcom,ipq806x-sata-phy"; + reg = <0x1b400000 0x200>; - assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; - phys = <&sata_phy>; - phy-names = "sata-phy"; + #phy-cells = <0>; status = "disabled"; }; - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - qfprom: qfprom@700000 { - compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - speedbin_efuse: speedbin@c0 { - reg = <0xc0 0x4>; - }; - tsens_calib: calib@400 { - reg = <0x400 0xb>; - }; - tsens_calib_backup: calib_backup@410 { - reg = <0x410 0xb>; - }; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064", "syscon"; - clocks = <&pxo_board>, <&cxo_board>; - clock-names = "pxo", "cxo"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - tsens: thermal-sensor@900000 { - compatible = "qcom,ipq8064-tsens"; - - nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; - nvmem-cell-names = "calib", "calib_backup"; - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; - - #qcom,sensors = <11>; - #thermal-sensor-cells = <1>; - }; - }; - - rpm: rpm@108000 { - compatible = "qcom,rpm-ipq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ack", "err", "wakeup"; - - clocks = <&gcc RPM_MSG_RAM_H_CLK>; - clock-names = "ram"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&pxo_board>; - clock-names = "pxo"; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-ipq8064", "syscon"; - reg = <0x1a400000 0x100>; - }; - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-ipq8064"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - pcie0: pci@1b500000 { compatible = "qcom,pcie-ipq8064"; reg = <0x1b500000 0x1000 @@ -979,7 +1119,7 @@ pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; }; pcie1: pci@1b700000 { @@ -1030,7 +1170,7 @@ pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; }; pcie2: pci@1b900000 { @@ -1081,12 +1221,7 @@ pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; - }; - - nss_common: syscon@03000000 { - compatible = "syscon"; - reg = <0x03000000 0x0000FFFF>; + perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; }; qsgmii_csr: syscon@1bb00000 { @@ -1094,10 +1229,48 @@ reg = <0x1bb00000 0x000001FF>; }; - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <7>; - snps,rd_osr_lmt = <7>; - snps,blen = <16 0 0 0 0 0 0>; + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-ipq8064"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + lpass@28100000 { + compatible = "qcom,lpass-cpu"; + status = "disabled"; + clocks = <&lcc AHBIX_CLK>, + <&lcc MI2S_OSR_CLK>, + <&lcc MI2S_BIT_CLK>; + clock-names = "ahbix-clk", + "mi2s-osr-clk", + "mi2s-bit-clk"; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "lpass-irq-lpaif"; + reg = <0x28100000 0x10000>; + reg-names = "lpass-lpaif"; + }; + + sata: sata@29000000 { + compatible = "qcom,ipq806x-ahci", "generic-ahci"; + reg = <0x29000000 0x180>; + + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_face", "iface", "core", + "rxoob", "pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + status = "disabled"; }; gmac0: ethernet@37000000 { @@ -1195,179 +1368,5 @@ status = "disabled"; }; - - hs_phy_0: phy@100f8800 { - compatible = "qcom,ipq806x-usb-phy-hs"; - reg = <0x100f8800 0x30>; - clocks = <&gcc USB30_0_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - ss_phy_0: phy@100f8830 { - compatible = "qcom,ipq806x-usb-phy-ss"; - reg = <0x100f8830 0x30>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - usb3_0: usb3@100f8800 { - compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x100f8800 0x8000>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "core"; - - ranges; - - resets = <&gcc USB30_0_MASTER_RESET>; - reset-names = "master"; - - status = "disabled"; - - dwc3_0: dwc3@10000000 { - compatible = "snps,dwc3"; - reg = <0x10000000 0xcd00>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hs_phy_0>, <&ss_phy_0>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - snps,dis_u3_susphy_quirk; - }; - }; - - hs_phy_1: phy@110f8800 { - compatible = "qcom,ipq806x-usb-phy-hs"; - reg = <0x110f8800 0x30>; - clocks = <&gcc USB30_1_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - ss_phy_1: phy@110f8830 { - compatible = "qcom,ipq806x-usb-phy-ss"; - reg = <0x110f8830 0x30>; - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - status = "disabled"; - }; - - usb3_1: usb3@110f8800 { - compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x110f8800 0x8000>; - clocks = <&gcc USB30_1_MASTER_CLK>; - clock-names = "core"; - - ranges; - - resets = <&gcc USB30_1_MASTER_RESET>; - reset-names = "master"; - - status = "disabled"; - - dwc3_1: dwc3@11000000 { - compatible = "snps,dwc3"; - reg = <0x11000000 0xcd00>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hs_phy_1>, <&ss_phy_1>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - snps,dis_u3_susphy_quirk; - }; - }; - - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdcc1bam: dma-controller@12402000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc3bam: dma-controller@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - amba: amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-1_8v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - sd-uhs-sdr104; - sd-uhs-ddr50; - vqmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - }; - - sfpb_mutex: hwlock@1200600 { - compatible = "qcom,sfpb-mutex"; - reg = <0x01200600 0x100>; - - #hwlock-cells = <1>; - }; }; }; diff --git a/dts/src/arm/qcom-ipq8065-smb208.dtsi b/dts/src/arm/qcom-ipq8065-smb208.dtsi new file mode 100644 index 0000000000..803e6ff99e --- /dev/null +++ b/dts/src/arm/qcom-ipq8065-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8065.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/dts/src/arm/qcom-ipq8065.dtsi b/dts/src/arm/qcom-ipq8065.dtsi new file mode 100644 index 0000000000..ea49f6cc41 --- /dev/null +++ b/dts/src/arm/qcom-ipq8065.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064-v2.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8065"; + compatible = "qcom,ipq8065", "qcom,ipq8064"; +}; diff --git a/dts/src/arm/qcom-msm8226-samsung-s3ve3g.dts b/dts/src/arm/qcom-msm8226-samsung-s3ve3g.dts index d159188c8b..290e1df631 100644 --- a/dts/src/arm/qcom-msm8226-samsung-s3ve3g.dts +++ b/dts/src/arm/qcom-msm8226-samsung-s3ve3g.dts @@ -18,8 +18,6 @@ }; }; -&soc { - serial@f991f000 { - status = "ok"; - }; +&blsp1_uart3 { + status = "ok"; }; diff --git a/dts/src/arm/qcom-msm8226.dtsi b/dts/src/arm/qcom-msm8226.dtsi index 0b5effdb26..cf2d569294 100644 --- a/dts/src/arm/qcom-msm8226.dtsi +++ b/dts/src/arm/qcom-msm8226.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/reset/qcom,gcc-msm8974.h> / { @@ -44,13 +45,6 @@ }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; - - #hwlock-cells = <1>; - }; - reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -60,6 +54,11 @@ reg = <0x3000000 0x100000>; no-map; }; + + adsp_region: adsp@dc00000 { + reg = <0x0dc00000 0x1900000>; + no-map; + }; }; smd { @@ -115,6 +114,31 @@ hwlocks = <&tcsr_mutex 3>; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -137,14 +161,14 @@ sdhc_1: mmc@f9824900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc1_default_state>; status = "disabled"; @@ -153,14 +177,14 @@ sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc2_default_state>; status = "disabled"; @@ -169,14 +193,14 @@ sdhc_3: mmc@f9864900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc3_default_state>; status = "disabled"; @@ -508,9 +532,44 @@ reg = <0xfc428000 0x4000>; }; - tcsr_mutex_block: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; + tcsr_mutex: hwlock@fd484000 { + compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; + reg = <0xfd484000 0x1000>; + #hwlock-cells = <1>; + }; + + adsp: remoteproc@fe200000 { + compatible = "qcom,msm8226-adsp-pil"; + reg = <0xfe200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8226_VDDCX>; + power-domain-names = "cx"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + smd-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + + label = "lpass"; + }; }; }; diff --git a/dts/src/arm/qcom-msm8660-surf.dts b/dts/src/arm/qcom-msm8660-surf.dts index 414280d9bd..be18f1be29 100644 --- a/dts/src/arm/qcom-msm8660-surf.dts +++ b/dts/src/arm/qcom-msm8660-surf.dts @@ -15,38 +15,23 @@ stdout-path = "serial0:115200n8"; }; - soc { - gsbi@19c00000 { - status = "okay"; - qcom,mode = <GSBI_PROT_I2C_UART>; - serial@19c40000 { - status = "okay"; - }; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; +}; - amba { - /* eMMC */ - sdcc1: mmc@12400000 { - status = "okay"; - vmmc-supply = <&vsdcc_fixed>; - }; +&gsbi12 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "okay"; +}; - /* External micro SD card */ - sdcc3: mmc@12180000 { - status = "okay"; - vmmc-supply = <&vsdcc_fixed>; - }; - }; - }; +&gsbi12_serial { + status = "okay"; }; &pm8058 { @@ -76,3 +61,15 @@ keypad,num-columns = <5>; }; }; + +/* eMMC */ +&sdcc1 { + vmmc-supply = <&vsdcc_fixed>; + status = "okay"; +}; + +/* External micro SD card */ +&sdcc3 { + vmmc-supply = <&vsdcc_fixed>; + status = "okay"; +}; diff --git a/dts/src/arm/qcom-msm8660.dtsi b/dts/src/arm/qcom-msm8660.dtsi index 63a501c63c..ddce7d64ba 100644 --- a/dts/src/arm/qcom-msm8660.dtsi +++ b/dts/src/arm/qcom-msm8660.dtsi @@ -50,22 +50,25 @@ }; clocks { - cxo_board { + cxo_board: cxo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; + clock-output-names = "cxo_board"; }; - pxo_board: pxo_board { + pxo_board: pxo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "pxo_board"; }; - sleep_clk { + sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; + clock-output-names = "sleep_clk"; }; }; @@ -129,6 +132,59 @@ #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + }; + + gsbi1: gsbi@16000000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16000000 0x100>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi1_spi: spi@16080000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + status = "disabled"; + + gsbi3_i2c: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16280000 0x1000>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; gsbi6: gsbi@16500000 { diff --git a/dts/src/arm/qcom-msm8916-samsung-e5.dts b/dts/src/arm/qcom-msm8916-samsung-e5.dts new file mode 100644 index 0000000000..c8d34de8a7 --- /dev/null +++ b/dts/src/arm/qcom-msm8916-samsung-e5.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-e5.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/dts/src/arm/qcom-msm8916-samsung-e7.dts b/dts/src/arm/qcom-msm8916-samsung-e7.dts new file mode 100644 index 0000000000..85be286c86 --- /dev/null +++ b/dts/src/arm/qcom-msm8916-samsung-e7.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-e7.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/dts/src/arm/qcom-msm8916-samsung-grandmax.dts b/dts/src/arm/qcom-msm8916-samsung-grandmax.dts new file mode 100644 index 0000000000..d3abe05362 --- /dev/null +++ b/dts/src/arm/qcom-msm8916-samsung-grandmax.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "arm64/qcom/msm8916-samsung-grandmax.dts" +#include "qcom-msm8916-smp.dtsi" diff --git a/dts/src/arm/qcom-msm8960-cdp.dts b/dts/src/arm/qcom-msm8960-cdp.dts index d1fd0fe12f..9157e3c4f4 100644 --- a/dts/src/arm/qcom-msm8960-cdp.dts +++ b/dts/src/arm/qcom-msm8960-cdp.dts @@ -15,318 +15,6 @@ stdout-path = "serial0:115200n8"; }; - soc { - gsbi@16400000 { - status = "okay"; - qcom,mode = <GSBI_PROT_I2C_UART>; - serial@16440000 { - status = "okay"; - }; - }; - - amba { - /* eMMC */ - sdcc1: mmc@12400000 { - status = "okay"; - }; - - /* External micro SD card */ - sdcc3: mmc@12180000 { - status = "okay"; - }; - }; - - rpm@108000 { - regulators { - compatible = "qcom,rpm-pm8921-regulators"; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s4>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - vdd_ncp-supply = <&pm8921_l6>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l21_l23_l29-supply = <&pm8921_s8>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - - /* Buck SMPS */ - pm8921_s1: s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s2: s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - pm8921_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <4800000>; - bias-pull-down; - }; - - pm8921_s4: s4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; - }; - - pm8921_s7: s7 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - pm8921_s8: s8 { - regulator-always-on; - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - }; - - /* PMOS LDO */ - pm8921_l1: l1 { - regulator-always-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - bias-pull-down; - }; - - pm8921_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l3: l3 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - bias-pull-down; - }; - - pm8921_l4: l4 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l5: l5 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l6: l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l7: l7 { - regulator-always-on; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l8: l8 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l9: l9 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l10: l10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - }; - - pm8921_l11: l11 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - bias-pull-down; - }; - - pm8921_l12: l12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - bias-pull-down; - }; - - pm8921_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l16: l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - bias-pull-down; - }; - - pm8921_l17: l17 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - pm8921_l18: l18 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - bias-pull-down; - }; - - pm8921_l21: l21 { - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - pm8921_l22: l22 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - bias-pull-down; - }; - - pm8921_l23: l23 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - pm8921_l24: l24 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1150000>; - bias-pull-down; - }; - - pm8921_l25: l25 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - bias-pull-down; - }; - - /* Low Voltage Switch */ - pm8921_lvs1: lvs1 { - bias-pull-down; - }; - - pm8921_lvs2: lvs2 { - bias-pull-down; - }; - - pm8921_lvs3: lvs3 { - bias-pull-down; - }; - - pm8921_lvs4: lvs4 { - bias-pull-down; - }; - - pm8921_lvs5: lvs5 { - bias-pull-down; - }; - - pm8921_lvs6: lvs6 { - bias-pull-down; - }; - - pm8921_lvs7: lvs7 { - bias-pull-down; - }; - - pm8921_ncp: ncp { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - }; - }; - }; - - gsbi@16000000 { - status = "okay"; - qcom,mode = <GSBI_PROT_SPI>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_default>; - spi@16080000 { - status = "okay"; - ethernet@0 { - compatible = "micrel,ks8851"; - reg = <0>; - interrupt-parent = <&msmgpio>; - interrupts = <90 8>; - spi-max-frequency = <5400000>; - vdd-supply = <&ext_l2>; - vdd-io-supply = <&pm8921_lvs6>; - reset-gpios = <&msmgpio 89 0>; - }; - }; - }; - - pinctrl@800000 { - spi1_default: spi1_default { - mux { - pins = "gpio6", "gpio7", "gpio9"; - function = "gsbi1"; - }; - - mosi { - pins = "gpio6"; - drive-strength = <12>; - bias-disable; - }; - - miso { - pins = "gpio7"; - drive-strength = <12>; - bias-disable; - }; - - cs { - pins = "gpio8"; - drive-strength = <12>; - bias-disable; - output-low; - }; - - clk { - pins = "gpio9"; - drive-strength = <12>; - bias-disable; - }; - }; - }; - }; - regulators { compatible = "simple-bus"; @@ -340,6 +28,71 @@ }; }; +&gsbi1 { + qcom,mode = <GSBI_PROT_SPI>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_default>; + status = "okay"; +}; + +&gsbi1_spi { + status = "okay"; + + ethernet@0 { + compatible = "micrel,ks8851"; + reg = <0>; + interrupt-parent = <&msmgpio>; + interrupts = <90 8>; + spi-max-frequency = <5400000>; + vdd-supply = <&ext_l2>; + vdd-io-supply = <&pm8921_lvs6>; + reset-gpios = <&msmgpio 89 0>; + }; +}; + +&gsbi5 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "okay"; +}; + +&gsbi5_serial { + status = "okay"; +}; + +&msmgpio { + spi1_default: spi1_default { + mux { + pins = "gpio6", "gpio7", "gpio9"; + function = "gsbi1"; + }; + + mosi { + pins = "gpio6"; + drive-strength = <12>; + bias-disable; + }; + + miso { + pins = "gpio7"; + drive-strength = <12>; + bias-disable; + }; + + cs { + pins = "gpio8"; + drive-strength = <12>; + bias-disable; + output-low; + }; + + clk { + pins = "gpio9"; + drive-strength = <12>; + bias-disable; + }; + }; +}; + &pmicintc { keypad@148 { linux,keymap = < @@ -352,3 +105,249 @@ keypad,num-columns = <5>; }; }; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s4>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + vdd_ncp-supply = <&pm8921_l6>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l21_l23_l29-supply = <&pm8921_s8>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s8: s8 { + regulator-always-on; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8921_l1: l1 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l7: l7 { + regulator-always-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l8: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l10: l10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l11: l11 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8921_l12: l12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l16: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + bias-pull-down; + }; + + pm8921_l17: l17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l18: l18 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + bias-pull-down; + }; + + pm8921_l21: l21 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8921_l22: l22 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +/* eMMC */ +&sdcc1 { + status = "okay"; +}; + +/* External micro SD card */ +&sdcc3 { + status = "okay"; +}; diff --git a/dts/src/arm/qcom-msm8960.dtsi b/dts/src/arm/qcom-msm8960.dtsi index 19554f3b51..c5740da375 100644 --- a/dts/src/arm/qcom-msm8960.dtsi +++ b/dts/src/arm/qcom-msm8960.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/clock/qcom,lcc-msm8960.h> #include <dt-bindings/mfd/qcom-rpm.h> #include <dt-bindings/soc/qcom,gsbi.h> @@ -56,14 +57,14 @@ }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; clock-output-names = "cxo_board"; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -130,6 +131,10 @@ #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; + clocks = <&cxo_board>, + <&pxo_board>, + <&lcc PLL4>; + clock-names = "cxo", "pxo", "pll4"; }; lcc: clock-controller@28000000 { @@ -137,6 +142,20 @@ reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; clock-controller@4000000 { @@ -145,6 +164,22 @@ #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; }; l2cc: clock-controller@2011000 { @@ -152,7 +187,7 @@ reg = <0x2011000 0x1000>; }; - rpm@108000 { + rpm: rpm@108000 { compatible = "qcom,rpm-msm8960"; reg = <0x108000 0x1000>; qcom,ipc = <&l2cc 0x8 2>; @@ -307,7 +342,7 @@ reg = <0x1a400000 0x100>; }; - gsbi@16000000 { + gsbi1: gsbi@16000000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <1>; reg = <0x16000000 0x100>; @@ -317,7 +352,7 @@ #size-cells = <1>; ranges; - spi@16080000 { + gsbi1_spi: spi@16080000 { compatible = "qcom,spi-qup-v1.1.1"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts b/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts index ec5d340562..6daceaa878 100644 --- a/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -175,7 +175,7 @@ ak8963@f { compatible = "asahi-kasei,ak8963"; reg = <0x0f>; - gpios = <&tlmm 67 0>; + gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>; vid-supply = <&pm8941_lvs1>; vdd-supply = <&pm8941_l17>; }; diff --git a/dts/src/arm/qcom-msm8974.dtsi b/dts/src/arm/qcom-msm8974.dtsi index 8baca2a777..7a9be0acf3 100644 --- a/dts/src/arm/qcom-msm8974.dtsi +++ b/dts/src/arm/qcom-msm8974.dtsi @@ -439,14 +439,14 @@ sdhc_1: mmc@f9824900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <8>; non-removable; @@ -456,14 +456,14 @@ sdhc_3: mmc@f9864900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_APPS_CLK>, - <&gcc GCC_SDCC3_AHB_CLK>, + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <4>; #address-cells = <1>; @@ -475,14 +475,14 @@ sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <4>; #address-cells = <1>; @@ -762,6 +762,11 @@ }; }; + sram@fc190000 { + compatible = "qcom,msm8974-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + etf@fc307000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0xfc307000 0x1000>; diff --git a/dts/src/arm/qcom-msm8974pro.dtsi b/dts/src/arm/qcom-msm8974pro.dtsi index 1e882e16a2..58df6e75ab 100644 --- a/dts/src/arm/qcom-msm8974pro.dtsi +++ b/dts/src/arm/qcom-msm8974pro.dtsi @@ -10,10 +10,10 @@ }; &sdhc_1 { - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>, <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; - clock-names = "core", "iface", "xo", "cal", "sleep"; + clock-names = "iface", "core", "xo", "cal", "sleep"; }; diff --git a/dts/src/arm/qcom-pm8941.dtsi b/dts/src/arm/qcom-pm8941.dtsi index 59d0cde632..9cd49deb9f 100644 --- a/dts/src/arm/qcom-pm8941.dtsi +++ b/dts/src/arm/qcom-pm8941.dtsi @@ -93,7 +93,7 @@ #thermal-sensor-cells = <0>; }; - pm8941_vadc: vadc@3100 { + pm8941_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; @@ -144,7 +144,7 @@ #address-cells = <1>; #size-cells = <0>; - pm8941_lpg: lpg { + pm8941_lpg: pwm { compatible = "qcom,pm8941-lpg"; #address-cells = <1>; diff --git a/dts/src/arm/qcom-pma8084.dtsi b/dts/src/arm/qcom-pma8084.dtsi index 7b8a8d9695..e77602e9f9 100644 --- a/dts/src/arm/qcom-pma8084.dtsi +++ b/dts/src/arm/qcom-pma8084.dtsi @@ -56,7 +56,7 @@ io-channel-names = "thermal"; }; - pma8084_vadc: vadc@3100 { + pma8084_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; diff --git a/dts/src/arm/qcom-pmx55.dtsi b/dts/src/arm/qcom-pmx55.dtsi index 9de7578a4c..e1b869480b 100644 --- a/dts/src/arm/qcom-pmx55.dtsi +++ b/dts/src/arm/qcom-pmx55.dtsi @@ -16,7 +16,7 @@ #address-cells = <1>; #size-cells = <0>; - power-on@800 { + pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; diff --git a/dts/src/arm/qcom-sdx65.dtsi b/dts/src/arm/qcom-sdx65.dtsi index 8daefd5021..4cd405db55 100644 --- a/dts/src/arm/qcom-sdx65.dtsi +++ b/dts/src/arm/qcom-sdx65.dtsi @@ -334,7 +334,7 @@ sdhc_1: mmc@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; - reg-names = "hc_mem"; + reg-names = "hc"; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; diff --git a/dts/src/arm/r8a7742.dtsi b/dts/src/arm/r8a7742.dtsi index 420e0b3259..758a1bf02f 100644 --- a/dts/src/arm/r8a7742.dtsi +++ b/dts/src/arm/r8a7742.dtsi @@ -633,7 +633,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7742", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -645,11 +645,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/dts/src/arm/r8a7743.dtsi b/dts/src/arm/r8a7743.dtsi index c0c145a5fe..20f1d98a04 100644 --- a/dts/src/arm/r8a7743.dtsi +++ b/dts/src/arm/r8a7743.dtsi @@ -584,7 +584,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7743", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -596,11 +596,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/dts/src/arm/r8a7744.dtsi b/dts/src/arm/r8a7744.dtsi index 3f4fb53dd6..96b2d5a4e8 100644 --- a/dts/src/arm/r8a7744.dtsi +++ b/dts/src/arm/r8a7744.dtsi @@ -584,7 +584,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7744", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -596,11 +596,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/dts/src/arm/r8a7745.dtsi b/dts/src/arm/r8a7745.dtsi index fe8e98a66d..afc902e532 100644 --- a/dts/src/arm/r8a7745.dtsi +++ b/dts/src/arm/r8a7745.dtsi @@ -525,7 +525,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7745", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -537,11 +537,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/dts/src/arm/r8a77470.dtsi b/dts/src/arm/r8a77470.dtsi index c90f2a2702..a5cf663a01 100644 --- a/dts/src/arm/r8a77470.dtsi +++ b/dts/src/arm/r8a77470.dtsi @@ -357,7 +357,7 @@ status = "disabled"; }; - usbphy0: usb-phy@e6590100 { + usbphy0: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a77470", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -369,7 +369,7 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; @@ -393,7 +393,7 @@ status = "disabled"; }; - usbphy1: usb-phy@e6598100 { + usbphy1: usb-phy-controller@e6598100 { compatible = "renesas,usb-phy-r8a77470", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6598100 0 0x100>; @@ -405,7 +405,7 @@ resets = <&cpg 706>; status = "disabled"; - usb1: usb-channel@0 { + usb1: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; diff --git a/dts/src/arm/r8a7790.dtsi b/dts/src/arm/r8a7790.dtsi index a640488d51..db171e3c62 100644 --- a/dts/src/arm/r8a7790.dtsi +++ b/dts/src/arm/r8a7790.dtsi @@ -654,7 +654,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -666,11 +666,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/dts/src/arm/r8a7791.dtsi b/dts/src/arm/r8a7791.dtsi index 542ed0a718..d8f91d9f42 100644 --- a/dts/src/arm/r8a7791.dtsi +++ b/dts/src/arm/r8a7791.dtsi @@ -608,7 +608,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7791", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -620,11 +620,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/dts/src/arm/r8a7794.dtsi b/dts/src/arm/r8a7794.dtsi index b601ee6f75..7aa781ff3b 100644 --- a/dts/src/arm/r8a7794.dtsi +++ b/dts/src/arm/r8a7794.dtsi @@ -506,7 +506,7 @@ status = "disabled"; }; - usbphy: usb-phy@e6590100 { + usbphy: usb-phy-controller@e6590100 { compatible = "renesas,usb-phy-r8a7794", "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; @@ -518,11 +518,11 @@ resets = <&cpg 704>; status = "disabled"; - usb0: usb-channel@0 { + usb0: usb-phy@0 { reg = <0>; #phy-cells = <1>; }; - usb2: usb-channel@2 { + usb2: usb-phy@2 { reg = <2>; #phy-cells = <1>; }; diff --git a/dts/src/arm/r9a06g032-rzn1d400-db.dts b/dts/src/arm/r9a06g032-rzn1d400-db.dts index 4bf813335e..c18bbd7141 100644 --- a/dts/src/arm/r9a06g032-rzn1d400-db.dts +++ b/dts/src/arm/r9a06g032-rzn1d400-db.dts @@ -26,6 +26,22 @@ }; }; +&can0 { + pinctrl-0 = <&pins_can0>; + pinctrl-names = "default"; + + /* Assuming CN10/CN11 are wired for CAN1 */ + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&pins_can1>; + pinctrl-names = "default"; + + /* Please only enable can0 or can1, depending on CN10/CN11 */ + /* status = "okay"; */ +}; + ð_miic { status = "okay"; renesas,miic-switch-portin = <MIIC_GMAC2_PORT>; @@ -52,6 +68,18 @@ }; &pinctrl{ + pins_can0: pins_can0 { + pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>, /* CAN0_TXD */ + <RZN1_PINMUX(163, RZN1_FUNC_CAN)>; /* CAN0_RXD */ + drive-strength = <6>; + }; + + pins_can1: pins_can1 { + pinmux = <RZN1_PINMUX(109, RZN1_FUNC_CAN)>, /* CAN1_TXD */ + <RZN1_PINMUX(110, RZN1_FUNC_CAN)>; /* CAN1_RXD */ + drive-strength = <6>; + }; + pins_eth3: pins_eth3 { pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, diff --git a/dts/src/arm/r9a06g032.dtsi b/dts/src/arm/r9a06g032.dtsi index 5b97fa8547..563024c9a4 100644 --- a/dts/src/arm/r9a06g032.dtsi +++ b/dts/src/arm/r9a06g032.dtsi @@ -423,6 +423,26 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; + + can0: can@52104000 { + compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000"; + reg = <0x52104000 0x800>; + reg-io-width = <4>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_CAN0>; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + can1: can@52105000 { + compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; + reg = <0x52105000 0x800>; + reg-io-width = <4>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_CAN1>; + power-domains = <&sysctrl>; + status = "disabled"; + }; }; timer { diff --git a/dts/src/arm/rk3036-evb.dts b/dts/src/arm/rk3036-evb.dts index 2a7e6624ef..9fd4d9db9f 100644 --- a/dts/src/arm/rk3036-evb.dts +++ b/dts/src/arm/rk3036-evb.dts @@ -15,16 +15,20 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; phy = <&phy0>; - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ phy-reset-duration = <10>; /* millisecond */ - + phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>; status = "okay"; - phy0: ethernet-phy@0 { - reg = <0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/dts/src/arm/rk3036-kylin.dts b/dts/src/arm/rk3036-kylin.dts index e817eba8c6..67e1e04139 100644 --- a/dts/src/arm/rk3036-kylin.dts +++ b/dts/src/arm/rk3036-kylin.dts @@ -80,16 +80,20 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>; phy = <&phy0>; - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ phy-reset-duration = <10>; /* millisecond */ - + phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>; status = "okay"; - phy0: ethernet-phy@0 { - reg = <0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/dts/src/arm/rk3036.dtsi b/dts/src/arm/rk3036.dtsi index 9b0f049756..78686fc72c 100644 --- a/dts/src/arm/rk3036.dtsi +++ b/dts/src/arm/rk3036.dtsi @@ -225,11 +225,9 @@ }; emac: ethernet@10200000 { - compatible = "rockchip,rk3036-emac", "snps,arc-emac"; + compatible = "rockchip,rk3036-emac"; reg = <0x10200000 0x4000>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; rockchip,grf = <&grf>; clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; clock-names = "hclk", "macref", "macclk"; diff --git a/dts/src/arm/rk3066a-marsboard.dts b/dts/src/arm/rk3066a-marsboard.dts index a66d915aa0..8beecd6282 100644 --- a/dts/src/arm/rk3066a-marsboard.dts +++ b/dts/src/arm/rk3066a-marsboard.dts @@ -150,18 +150,21 @@ #include "tps65910.dtsi" &emac { - status = "okay"; - phy = <&phy0>; phy-supply = <&vcc_rmii>; - pinctrl-names = "default"; pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; + }; }; }; diff --git a/dts/src/arm/rk3066a-rayeager.dts b/dts/src/arm/rk3066a-rayeager.dts index dbbc517009..3eee42137b 100644 --- a/dts/src/arm/rk3066a-rayeager.dts +++ b/dts/src/arm/rk3066a-rayeager.dts @@ -142,15 +142,20 @@ }; &emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>; phy = <&phy0>; phy-supply = <&vcc_rmii>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>; status = "okay"; - phy0: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/dts/src/arm/rk3188-radxarock.dts b/dts/src/arm/rk3188-radxarock.dts index a9ed3cd2c2..e7cf188235 100644 --- a/dts/src/arm/rk3188-radxarock.dts +++ b/dts/src/arm/rk3188-radxarock.dts @@ -126,18 +126,21 @@ }; &emac { - status = "okay"; - + phy = <&phy0>; + phy-supply = <&vcc_rmii>; pinctrl-names = "default"; pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; + status = "okay"; - phy = <&phy0>; - phy-supply = <&vcc_rmii>; + mdio { + #address-cells = <1>; + #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; + }; }; }; diff --git a/dts/src/arm/rk3xxx.dtsi b/dts/src/arm/rk3xxx.dtsi index 616a828e0c..bf285091a9 100644 --- a/dts/src/arm/rk3xxx.dtsi +++ b/dts/src/arm/rk3xxx.dtsi @@ -186,8 +186,6 @@ compatible = "snps,arc-emac"; reg = <0x10204000 0x3c>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; rockchip,grf = <&grf>; diff --git a/dts/src/arm/s5pv210-aries.dtsi b/dts/src/arm/s5pv210-aries.dtsi index 5541df4df6..964c5fe517 100644 --- a/dts/src/arm/s5pv210-aries.dtsi +++ b/dts/src/arm/s5pv210-aries.dtsi @@ -738,7 +738,7 @@ samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; - magnetometer_i2c_pins: yas529-i2c-pins-pins { + magnetometer_i2c_pins: yas529-i2c-pins { samsung,pins = "gpj0-0", "gpj0-1"; samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; @@ -788,7 +788,7 @@ samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; - pmic_i2c_pins: pmic-i2c-pins-pins { + pmic_i2c_pins: pmic-i2c-pins { samsung,pins = "gpj4-0", "gpj4-3"; samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; diff --git a/dts/src/arm/s5pv210-galaxys.dts b/dts/src/arm/s5pv210-galaxys.dts index cdd3653d48..532d3f5bce 100644 --- a/dts/src/arm/s5pv210-galaxys.dts +++ b/dts/src/arm/s5pv210-galaxys.dts @@ -150,7 +150,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep_cfg>; - fm_i2c_pins: fm-i2c-pins-pins { + fm_i2c_pins: fm-i2c-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; diff --git a/dts/src/arm/sam9x60.dtsi b/dts/src/arm/sam9x60.dtsi index d3f60f6a45..8f5477e307 100644 --- a/dts/src/arm/sam9x60.dtsi +++ b/dts/src/arm/sam9x60.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> #include <dt-bindings/mfd/atmel-flexcom.h> / { @@ -583,6 +584,7 @@ dbgu: serial@fffff200 { compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | diff --git a/dts/src/arm/sama5d2.dtsi b/dts/src/arm/sama5d2.dtsi index 2c50a021aa..14c35c12a1 100644 --- a/dts/src/arm/sama5d2.dtsi +++ b/dts/src/arm/sama5d2.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/dma/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> #include <dt-bindings/iio/adc/at91-sama5d2_adc.h> / { @@ -441,6 +442,7 @@ uart0: serial@f801c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf801c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | @@ -457,6 +459,7 @@ uart1: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | @@ -473,6 +476,7 @@ uart2: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | @@ -530,6 +534,7 @@ uart5: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; clock-names = "usart"; @@ -600,6 +605,7 @@ uart6: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; clock-names = "usart"; @@ -769,6 +775,7 @@ uart3: serial@fc008000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc008000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | @@ -785,6 +792,7 @@ uart4: serial@fc00c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc00c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(43))>, @@ -810,6 +818,7 @@ uart7: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "usart"; @@ -880,6 +889,7 @@ uart8: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "usart"; @@ -951,6 +961,7 @@ uart9: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "usart"; diff --git a/dts/src/arm/sama5d3.dtsi b/dts/src/arm/sama5d3.dtsi index 2d0935ad22..bde8e92d60 100644 --- a/dts/src/arm/sama5d3.dtsi +++ b/dts/src/arm/sama5d3.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { #address-cells = <1>; @@ -194,6 +195,7 @@ usart0: serial@f001c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf001c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; @@ -208,6 +210,7 @@ usart1: serial@f0020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0020000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; @@ -222,6 +225,7 @@ uart0: serial@f0024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0024000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -356,6 +360,7 @@ usart2: serial@f8020000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; @@ -370,6 +375,7 @@ usart3: serial@f8024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; @@ -464,6 +470,7 @@ dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; diff --git a/dts/src/arm/sama5d3_uart.dtsi b/dts/src/arm/sama5d3_uart.dtsi index a3eaba995c..44d1173f2f 100644 --- a/dts/src/arm/sama5d3_uart.dtsi +++ b/dts/src/arm/sama5d3_uart.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/at91.h> +#include <dt-bindings/mfd/at91-usart.h> / { aliases { @@ -39,6 +40,7 @@ uart0: serial@f0024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0024000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; @@ -50,6 +52,7 @@ uart1: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/dts/src/arm/sama5d4.dtsi b/dts/src/arm/sama5d4.dtsi index 1e5c01898c..af62157ae2 100644 --- a/dts/src/arm/sama5d4.dtsi +++ b/dts/src/arm/sama5d4.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/at91.h> #include <dt-bindings/dma/at91.h> +#include <dt-bindings/mfd/at91-usart.h> #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> @@ -278,6 +279,7 @@ uart0: serial@f8004000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8004000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -437,6 +439,7 @@ usart0: serial@f802c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf802c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -455,6 +458,7 @@ usart1: serial@f8030000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8030000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -490,6 +494,7 @@ uart1: serial@fc004000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc004000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -508,6 +513,7 @@ usart2: serial@fc008000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc008000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -526,6 +532,7 @@ usart3: serial@fc00c000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc00c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -544,6 +551,7 @@ usart4: serial@fc010000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfc010000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; dmas = <&dma1 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) @@ -770,6 +778,7 @@ dbgu: serial@fc069000 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfc069000 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; diff --git a/dts/src/arm/sama7g5.dtsi b/dts/src/arm/sama7g5.dtsi index bb6d71e6df..7bd8ae8e8d 100644 --- a/dts/src/arm/sama7g5.dtsi +++ b/dts/src/arm/sama7g5.dtsi @@ -14,6 +14,7 @@ #include <dt-bindings/clock/at91.h> #include <dt-bindings/dma/at91.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/at91-usart.h> / { model = "Microchip SAMA7G5 family SoC"; @@ -603,6 +604,7 @@ uart0: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "usart"; @@ -651,6 +653,7 @@ uart3: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "usart"; @@ -694,6 +697,7 @@ uart4: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "usart"; @@ -719,6 +723,7 @@ uart7: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; clock-names = "usart"; @@ -866,9 +871,9 @@ #address-cells = <1>; #size-cells = <0>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, - <&dma0 AT91_XDMAC_DT_PERID(28)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, + <&dma0 AT91_XDMAC_DT_PERID(27)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; diff --git a/dts/src/arm/ste-href.dtsi b/dts/src/arm/ste-href.dtsi index fbaa0ce464..8f1bb78fc1 100644 --- a/dts/src/arm/ste-href.dtsi +++ b/dts/src/arm/ste-href.dtsi @@ -24,6 +24,14 @@ polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; diff --git a/dts/src/arm/ste-snowball.dts b/dts/src/arm/ste-snowball.dts index 1c9094f248..e2f0cdacba 100644 --- a/dts/src/arm/ste-snowball.dts +++ b/dts/src/arm/ste-snowball.dts @@ -28,6 +28,14 @@ polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; diff --git a/dts/src/arm/ste-ux500-samsung-codina-tmo.dts b/dts/src/arm/ste-ux500-samsung-codina-tmo.dts index d6940e0afa..27a3ab7e25 100644 --- a/dts/src/arm/ste-ux500-samsung-codina-tmo.dts +++ b/dts/src/arm/ste-ux500-samsung-codina-tmo.dts @@ -44,6 +44,14 @@ polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; diff --git a/dts/src/arm/ste-ux500-samsung-codina.dts b/dts/src/arm/ste-ux500-samsung-codina.dts index 5f41256d7f..b88f0c0787 100644 --- a/dts/src/arm/ste-ux500-samsung-codina.dts +++ b/dts/src/arm/ste-ux500-samsung-codina.dts @@ -57,6 +57,14 @@ polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; diff --git a/dts/src/arm/ste-ux500-samsung-gavini.dts b/dts/src/arm/ste-ux500-samsung-gavini.dts index 806da3fc33..7231bc7452 100644 --- a/dts/src/arm/ste-ux500-samsung-gavini.dts +++ b/dts/src/arm/ste-ux500-samsung-gavini.dts @@ -30,6 +30,14 @@ polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; diff --git a/dts/src/arm/ste-ux500-samsung-golden.dts b/dts/src/arm/ste-ux500-samsung-golden.dts index b0dce91aff..9604695edf 100644 --- a/dts/src/arm/ste-ux500-samsung-golden.dts +++ b/dts/src/arm/ste-ux500-samsung-golden.dts @@ -35,6 +35,14 @@ polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; diff --git a/dts/src/arm/ste-ux500-samsung-janice.dts b/dts/src/arm/ste-ux500-samsung-janice.dts index ed5c79c3d0..69387e8754 100644 --- a/dts/src/arm/ste-ux500-samsung-janice.dts +++ b/dts/src/arm/ste-ux500-samsung-janice.dts @@ -30,6 +30,14 @@ polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; diff --git a/dts/src/arm/ste-ux500-samsung-kyle.dts b/dts/src/arm/ste-ux500-samsung-kyle.dts index c57676faf1..167846df31 100644 --- a/dts/src/arm/ste-ux500-samsung-kyle.dts +++ b/dts/src/arm/ste-ux500-samsung-kyle.dts @@ -34,6 +34,14 @@ polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; diff --git a/dts/src/arm/ste-ux500-samsung-skomer.dts b/dts/src/arm/ste-ux500-samsung-skomer.dts index 81b341a5ae..93e5f5ed88 100644 --- a/dts/src/arm/ste-ux500-samsung-skomer.dts +++ b/dts/src/arm/ste-ux500-samsung-skomer.dts @@ -30,6 +30,14 @@ polling-delay = <0>; polling-delay-passive = <0>; thermal-sensors = <&bat_therm>; + + trips { + battery-crit-hi { + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; diff --git a/dts/src/arm/stm32mp13-pinctrl.dtsi b/dts/src/arm/stm32mp13-pinctrl.dtsi index d2472cd8f1..efdd163eba 100644 --- a/dts/src/arm/stm32mp13-pinctrl.dtsi +++ b/dts/src/arm/stm32mp13-pinctrl.dtsi @@ -6,6 +6,40 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + i2c1_pins_a: i2c1-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */ + }; + }; + + i2c5_pins_a: i2c5-0 { + pins { + pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ + <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_a: i2c5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -108,6 +142,29 @@ }; }; + spi5_pins_a: spi5-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ + <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */ + bias-disable; + }; + }; + + spi5_sleep_pins_a: spi5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */ + <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */ + <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */ + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ diff --git a/dts/src/arm/stm32mp131.dtsi b/dts/src/arm/stm32mp131.dtsi index 3a921db23e..dd35a60707 100644 --- a/dts/src/arm/stm32mp131.dtsi +++ b/dts/src/arm/stm32mp131.dtsi @@ -97,6 +97,34 @@ }; }; + spi2: spi@4000b000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; @@ -106,6 +134,56 @@ status = "disabled"; }; + i2c1: i2c@40012000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 33 0x400 0x1>, + <&dmamux1 34 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c2: i2c@40013000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 35 0x400 0x1>, + <&dmamux1 36 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + i2c-analog-filter; + status = "disabled"; + }; + + spi1: spi@44004000 { + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + dma1: dma-controller@48000000 { compatible = "st,stm32-dma"; reg = <0x48000000 0x400>; @@ -153,6 +231,88 @@ dma-channels = <16>; }; + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; diff --git a/dts/src/arm/stm32mp135f-dk.dts b/dts/src/arm/stm32mp135f-dk.dts index e6b8ffd332..de341d17e8 100644 --- a/dts/src/arm/stm32mp135f-dk.dts +++ b/dts/src/arm/stm32mp135f-dk.dts @@ -68,6 +68,32 @@ }; }; +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <1000000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <170>; + i2c-scl-falling-time-ns = <5>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; @@ -90,6 +116,13 @@ status = "okay"; }; +&spi5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_a>; + pinctrl-1 = <&spi5_sleep_pins_a>; + status = "disabled"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; diff --git a/dts/src/arm/stm32mp15-pinctrl.dtsi b/dts/src/arm/stm32mp15-pinctrl.dtsi index 2cc9341d43..a9d2bec990 100644 --- a/dts/src/arm/stm32mp15-pinctrl.dtsi +++ b/dts/src/arm/stm32mp15-pinctrl.dtsi @@ -1261,7 +1261,7 @@ }; qspi_bk1_pins_a: qspi-bk1-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ @@ -1270,12 +1270,6 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { - pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; }; qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { @@ -1283,13 +1277,12 @@ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ - <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ - <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */ }; }; qspi_bk2_pins_a: qspi-bk2-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ @@ -1298,7 +1291,34 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { + }; + + qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ + <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + + qspi_cs2_pins_a: qspi-cs2-0 { + pins { pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ bias-pull-up; drive-push-pull; @@ -1306,13 +1326,9 @@ }; }; - qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { pins { - pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ - <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ - <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ - <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ - <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ + pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ }; }; diff --git a/dts/src/arm/stm32mp151.dtsi b/dts/src/arm/stm32mp151.dtsi index 742fdeeff4..e02b3f5d44 100644 --- a/dts/src/arm/stm32mp151.dtsi +++ b/dts/src/arm/stm32mp151.dtsi @@ -127,6 +127,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40000000 0x400>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM2_K>; clock-names = "int"; dmas = <&dmamux1 18 0x400 0x1>, @@ -160,6 +162,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001000 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM3_K>; clock-names = "int"; dmas = <&dmamux1 23 0x400 0x1>, @@ -194,6 +198,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM4_K>; clock-names = "int"; dmas = <&dmamux1 29 0x400 0x1>, @@ -226,6 +232,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40003000 0x400>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM5_K>; clock-names = "int"; dmas = <&dmamux1 55 0x400 0x1>, @@ -260,6 +268,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40004000 0x400>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM6_K>; clock-names = "int"; dmas = <&dmamux1 69 0x400 0x1>; @@ -278,6 +288,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40005000 0x400>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM7_K>; clock-names = "int"; dmas = <&dmamux1 70 0x400 0x1>; @@ -296,6 +308,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40006000 0x400>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM12_K>; clock-names = "int"; status = "disabled"; @@ -318,6 +332,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40007000 0x400>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM13_K>; clock-names = "int"; status = "disabled"; @@ -340,6 +356,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40008000 0x400>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM14_K>; clock-names = "int"; status = "disabled"; @@ -623,6 +641,11 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44000000 0x400>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; clocks = <&rcc TIM1_K>; clock-names = "int"; dmas = <&dmamux1 11 0x400 0x1>, @@ -659,6 +682,11 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44001000 0x400>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; clocks = <&rcc TIM8_K>; clock-names = "int"; dmas = <&dmamux1 47 0x400 0x1>, @@ -746,6 +774,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44006000 0x400>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM15_K>; clock-names = "int"; dmas = <&dmamux1 105 0x400 0x1>, @@ -773,6 +803,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44007000 0x400>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM16_K>; clock-names = "int"; dmas = <&dmamux1 109 0x400 0x1>, @@ -797,6 +829,8 @@ #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x44008000 0x400>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; clocks = <&rcc TIM17_K>; clock-names = "int"; dmas = <&dmamux1 111 0x400 0x1>, diff --git a/dts/src/arm/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/dts/src/arm/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index 2a28292834..9a2a4bc7d0 100644 --- a/dts/src/arm/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/dts/src/arm/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; diff --git a/dts/src/arm/stm32mp157a-icore-stm32mp1-ctouch2.dts b/dts/src/arm/stm32mp157a-icore-stm32mp1-ctouch2.dts index 1f75f1d451..60ce4425a7 100644 --- a/dts/src/arm/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ b/dts/src/arm/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; diff --git a/dts/src/arm/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/dts/src/arm/stm32mp157a-icore-stm32mp1-edimm2.2.dts index ba92d7d8ed..390ee8c057 100644 --- a/dts/src/arm/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/dts/src/arm/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; diff --git a/dts/src/arm/stm32mp157a-icore-stm32mp1.dtsi b/dts/src/arm/stm32mp157a-icore-stm32mp1.dtsi index 01166ccacf..9de893101b 100644 --- a/dts/src/arm/stm32mp157a-icore-stm32mp1.dtsi +++ b/dts/src/arm/stm32mp157a-icore-stm32mp1.dtsi @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ / { diff --git a/dts/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/dts/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index fae656edd8..0d7560ba29 100644 --- a/dts/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/dts/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; diff --git a/dts/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/dts/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0.dts index b9d0d3d6ad..d949559be0 100644 --- a/dts/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ b/dts/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ /dts-v1/; diff --git a/dts/src/arm/stm32mp157a-microgea-stm32mp1.dtsi b/dts/src/arm/stm32mp157a-microgea-stm32mp1.dtsi index 0b85175f15..fb4600a598 100644 --- a/dts/src/arm/stm32mp157a-microgea-stm32mp1.dtsi +++ b/dts/src/arm/stm32mp157a-microgea-stm32mp1.dtsi @@ -2,7 +2,7 @@ /* * Copyright (c) STMicroelectronics 2019 - All Rights Reserved * Copyright (c) 2020 Engicam srl - * Copyright (c) 2020 Amarula Solutons(India) + * Copyright (c) 2020 Amarula Solutions(India) */ / { diff --git a/dts/src/arm/stm32mp157c-emstamp-argon.dtsi b/dts/src/arm/stm32mp157c-emstamp-argon.dtsi index ac53ee3c49..30156b7546 100644 --- a/dts/src/arm/stm32mp157c-emstamp-argon.dtsi +++ b/dts/src/arm/stm32mp157c-emstamp-argon.dtsi @@ -435,12 +435,6 @@ pinctrl-0 = <&spi1_pins_a>; cs-gpios = <&gpioz 3 0>; status = "disabled"; - - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <100000>; - }; }; &timers1 { diff --git a/dts/src/arm/stm32mp157c-ev1.dts b/dts/src/arm/stm32mp157c-ev1.dts index d142dd30e1..050c3c27a4 100644 --- a/dts/src/arm/stm32mp157c-ev1.dts +++ b/dts/src/arm/stm32mp157c-ev1.dts @@ -255,8 +255,16 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a + &qspi_bk2_pins_a + &qspi_cs2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a + &qspi_bk2_sleep_pins_a + &qspi_cs2_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/tegra30-apalis-v1.1.dtsi b/dts/src/arm/tegra30-apalis-v1.1.dtsi index 380f22a358..a1bcd67fa5 100644 --- a/dts/src/arm/tegra30-apalis-v1.1.dtsi +++ b/dts/src/arm/tegra30-apalis-v1.1.dtsi @@ -993,7 +993,7 @@ touchscreen@41 { compatible = "st,stmpe811"; reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; interrupt-controller; id = <0>; blocks = <0x5>; diff --git a/dts/src/arm/tegra30-apalis.dtsi b/dts/src/arm/tegra30-apalis.dtsi index 9bdc4cb714..99d7dad72d 100644 --- a/dts/src/arm/tegra30-apalis.dtsi +++ b/dts/src/arm/tegra30-apalis.dtsi @@ -976,7 +976,7 @@ touchscreen@41 { compatible = "st,stmpe811"; reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; interrupt-controller; id = <0>; blocks = <0x5>; diff --git a/dts/src/arm/tegra30-colibri.dtsi b/dts/src/arm/tegra30-colibri.dtsi index 310dff0591..2867a138e0 100644 --- a/dts/src/arm/tegra30-colibri.dtsi +++ b/dts/src/arm/tegra30-colibri.dtsi @@ -849,7 +849,7 @@ touchscreen@41 { compatible = "st,stmpe811"; reg = <0x41>; - irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; interrupt-controller; id = <0>; blocks = <0x5>; diff --git a/dts/src/arm/uniphier-ld4-ref.dts b/dts/src/arm/uniphier-ld4-ref.dts index c46c2e8a10..e007db0847 100644 --- a/dts/src/arm/uniphier-ld4-ref.dts +++ b/dts/src/arm/uniphier-ld4-ref.dts @@ -36,11 +36,11 @@ }; ðsc { - interrupts = <1 8>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; }; &serialsc { - interrupts = <1 8>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; }; &serial0 { @@ -56,7 +56,7 @@ }; &gpio { - xirq1 { + xirq1-hog { gpio-hog; gpios = <UNIPHIER_GPIO_IRQ(1) 0>; input; diff --git a/dts/src/arm/uniphier-ld4.dtsi b/dts/src/arm/uniphier-ld4.dtsi index b52957ccda..9dceff12a6 100644 --- a/dts/src/arm/uniphier-ld4.dtsi +++ b/dts/src/arm/uniphier-ld4.dtsi @@ -6,6 +6,7 @@ // Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "socionext,uniphier-ld4"; @@ -55,7 +56,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(512 * 1024)>; cache-sets = <256>; @@ -69,7 +71,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -80,7 +82,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -91,7 +93,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -102,7 +104,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -113,7 +115,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 29 4>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -140,7 +142,7 @@ reg = <0x58400000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 1>; + interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -154,7 +156,7 @@ reg = <0x58480000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 1>; + interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -168,7 +170,7 @@ reg = <0x58500000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 1>; + interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -182,7 +184,7 @@ reg = <0x58580000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 1>; + interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -240,8 +242,13 @@ dmac: dma-controller@5a000000 { compatible = "socionext,uniphier-mio-dmac"; reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mio_clk 7>; resets = <&mio_rst 7>; #dma-cells = <1>; @@ -251,7 +258,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; @@ -271,7 +278,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&mio_clk 1>; @@ -289,7 +296,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, @@ -303,7 +310,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, @@ -317,7 +324,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, @@ -358,14 +365,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -407,7 +416,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; diff --git a/dts/src/arm/uniphier-ld6b-ref.dts b/dts/src/arm/uniphier-ld6b-ref.dts index 5bc7fe11b5..223a78b4a7 100644 --- a/dts/src/arm/uniphier-ld6b-ref.dts +++ b/dts/src/arm/uniphier-ld6b-ref.dts @@ -40,11 +40,11 @@ }; ðsc { - interrupts = <4 8>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; }; &serialsc { - interrupts = <4 8>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; }; &serial0 { @@ -60,7 +60,7 @@ }; &gpio { - xirq4 { + xirq4-hog { gpio-hog; gpios = <UNIPHIER_GPIO_IRQ(4) 0>; input; diff --git a/dts/src/arm/uniphier-pinctrl.dtsi b/dts/src/arm/uniphier-pinctrl.dtsi index c0fd029b37..f909ec2e53 100644 --- a/dts/src/arm/uniphier-pinctrl.dtsi +++ b/dts/src/arm/uniphier-pinctrl.dtsi @@ -196,11 +196,21 @@ function = "usb0"; }; + pinctrl_usb0_device: usb0-device { + groups = "usb0_device"; + function = "usb0"; + }; + pinctrl_usb1: usb1 { groups = "usb1"; function = "usb1"; }; + pinctrl_usb1_device: usb1-device { + groups = "usb1_device"; + function = "usb1"; + }; + pinctrl_usb2: usb2 { groups = "usb2"; function = "usb2"; diff --git a/dts/src/arm/uniphier-pro4-ace.dts b/dts/src/arm/uniphier-pro4-ace.dts index 27ff2b7b9d..6baee4410d 100644 --- a/dts/src/arm/uniphier-pro4-ace.dts +++ b/dts/src/arm/uniphier-pro4-ace.dts @@ -99,3 +99,11 @@ &usb1 { status = "okay"; }; + +&ahci0 { + status = "okay"; +}; + +&ahci1 { + status = "okay"; +}; diff --git a/dts/src/arm/uniphier-pro4-ref.dts b/dts/src/arm/uniphier-pro4-ref.dts index 3b9b61314d..d2ce5c0398 100644 --- a/dts/src/arm/uniphier-pro4-ref.dts +++ b/dts/src/arm/uniphier-pro4-ref.dts @@ -39,11 +39,11 @@ }; ðsc { - interrupts = <2 8>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; }; &serialsc { - interrupts = <2 8>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; }; &serial0 { @@ -59,7 +59,7 @@ }; &gpio { - xirq2 { + xirq2-hog { gpio-hog; gpios = <UNIPHIER_GPIO_IRQ(2) 0>; input; @@ -108,3 +108,11 @@ reg = <0>; }; }; + +&ahci0 { + status = "okay"; +}; + +&ahci1 { + status = "okay"; +}; diff --git a/dts/src/arm/uniphier-pro4.dtsi b/dts/src/arm/uniphier-pro4.dtsi index a53b73ee93..a309e64c57 100644 --- a/dts/src/arm/uniphier-pro4.dtsi +++ b/dts/src/arm/uniphier-pro4.dtsi @@ -6,6 +6,7 @@ // Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "socionext,uniphier-pro4"; @@ -63,7 +64,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(768 * 1024)>; cache-sets = <256>; @@ -77,7 +79,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -88,7 +90,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -99,7 +101,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -110,7 +112,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -121,7 +123,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -148,7 +150,7 @@ reg = <0x58780000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 4>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -162,7 +164,7 @@ reg = <0x58781000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -176,7 +178,7 @@ reg = <0x58782000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 4>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -190,7 +192,7 @@ reg = <0x58783000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 4>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -206,7 +208,7 @@ reg = <0x58785000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 25 4>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 9>; resets = <&peri_rst 9>; clock-frequency = <400000>; @@ -218,7 +220,7 @@ reg = <0x58786000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 26 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 10>; resets = <&peri_rst 10>; clock-frequency = <400000>; @@ -274,8 +276,14 @@ dmac: dma-controller@5a000000 { compatible = "socionext,uniphier-mio-dmac"; reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mio_clk 7>; resets = <&mio_rst 7>; #dma-cells = <1>; @@ -285,7 +293,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; @@ -305,7 +313,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&mio_clk 1>; @@ -323,7 +331,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a600000 0x200>; - interrupts = <0 85 4>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd1>; clocks = <&mio_clk 2>; @@ -339,7 +347,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, @@ -355,7 +363,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, @@ -376,7 +384,7 @@ compatible = "socionext,uniphier-pro4-pinctrl"; }; - usb-phy { + usb-controller { compatible = "socionext,uniphier-pro4-usb2-phy"; #address-cells = <1>; #size-cells = <0>; @@ -403,6 +411,11 @@ vbus-supply = <&usb1_vbus>; }; }; + + sg_clk: clock { + compatible = "socionext,uniphier-pro4-sg-clock"; + #clock-cells = <1>; + }; }; soc-glue@5f900000 { @@ -431,7 +444,7 @@ xdmac: dma-controller@5fc10000 { compatible = "socionext,uniphier-xdmac"; reg = <0x5fc10000 0x5300>; - interrupts = <0 188 4>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <2>; }; @@ -446,14 +459,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -485,7 +500,7 @@ compatible = "socionext,uniphier-pro4-ave4"; status = "disabled"; reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ether_rgmii>; clock-names = "gio", "ether", "ether-gb", "ether-phy"; @@ -503,12 +518,105 @@ }; }; + ahci0: sata@65600000 { + compatible = "socionext,uniphier-pro4-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65600000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_clk 12>, <&sys_clk 28>; + resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>; + ports-implemented = <1>; + phys = <&ahci0_phy>; + assigned-clocks = <&sg_clk 0>; + assigned-clock-rates = <25000000>; + }; + + sata-controller@65700000 { + compatible = "socionext,uniphier-pxs2-ahci-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + ahci0_rst: reset-controller@0 { + compatible = "socionext,uniphier-pro4-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 28>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 28>; + #reset-cells = <1>; + }; + + ahci0_phy: sata-phy@10 { + compatible = "socionext,uniphier-pro4-ahci-phy"; + reg = <0x10 0x40>; + clock-names = "link", "gio"; + clocks = <&sys_clk 28>, <&sys_clk 12>; + reset-names = "link", "gio", "phy", + "pm", "tx", "rx"; + resets = <&sys_rst 28>, <&sys_rst 12>, + <&sys_rst 30>, + <&ahci0_rst 0>, <&ahci0_rst 1>, + <&ahci0_rst 2>; + #phy-cells = <0>; + }; + }; + + ahci1: sata@65800000 { + compatible = "socionext,uniphier-pro4-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65800000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_clk 12>, <&sys_clk 29>; + resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>; + ports-implemented = <1>; + phys = <&ahci1_phy>; + assigned-clocks = <&sg_clk 0>; + assigned-clock-rates = <25000000>; + }; + + sata-controller@65900000 { + compatible = "socionext,uniphier-pro4-ahci-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65900000 0x100>; + + ahci1_rst: reset-controller@0 { + compatible = "socionext,uniphier-pro4-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 29>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 29>; + #reset-cells = <1>; + }; + + ahci1_phy: sata-phy@10 { + compatible = "socionext,uniphier-pro4-ahci-phy"; + reg = <0x10 0x40>; + clock-names = "link", "gio"; + clocks = <&sys_clk 29>, <&sys_clk 12>; + reset-names = "link", "gio", "phy", + "pm", "tx", "rx"; + resets = <&sys_rst 29>, <&sys_rst 12>, + <&sys_rst 30>, + <&ahci1_rst 0>, <&ahci1_rst 1>, + <&ahci1_rst 2>; + #phy-cells = <0>; + }; + }; + usb0: usb@65a00000 { compatible = "socionext,uniphier-dwc3", "snps,dwc3"; status = "disabled"; reg = <0x65a00000 0xcd00>; interrupt-names = "host", "peripheral"; - interrupts = <0 134 4>, <0 135 4>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clock-names = "ref", "bus_early", "suspend"; @@ -518,7 +626,7 @@ dr_mode = "host"; }; - usb-glue@65b00000 { + usb-controller@65b00000 { compatible = "socionext,uniphier-pro4-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -561,7 +669,8 @@ status = "disabled"; reg = <0x65c00000 0xcd00>; interrupt-names = "host", "peripheral"; - interrupts = <0 137 4>, <0 138 4>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clock-names = "ref", "bus_early", "suspend"; @@ -571,7 +680,7 @@ dr_mode = "host"; }; - usb-glue@65d00000 { + usb-controller@65d00000 { compatible = "socionext,uniphier-pro4-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -605,7 +714,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; diff --git a/dts/src/arm/uniphier-pro5.dtsi b/dts/src/arm/uniphier-pro5.dtsi index 3525125832..100edd7438 100644 --- a/dts/src/arm/uniphier-pro5.dtsi +++ b/dts/src/arm/uniphier-pro5.dtsi @@ -5,6 +5,8 @@ // Copyright (C) 2015-2016 Socionext Inc. // Author: Masahiro Yamada <yamada.masahiro@socionext.com> +#include <dt-bindings/interrupt-controller/arm-gic.h> + / { compatible = "socionext,uniphier-pro5"; #address-cells = <1>; @@ -135,7 +137,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(2 * 1024 * 1024)>; cache-sets = <512>; @@ -148,7 +151,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(2 * 1024 * 1024)>; cache-sets = <512>; @@ -162,7 +166,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -175,7 +179,7 @@ reg = <0x54006100 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 216 4>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; clocks = <&peri_clk 11>; /* common with spi0 */ @@ -186,7 +190,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -197,7 +201,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -208,7 +212,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -219,7 +223,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -246,7 +250,7 @@ reg = <0x58780000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 4>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -260,7 +264,7 @@ reg = <0x58781000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -274,7 +278,7 @@ reg = <0x58782000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 4>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -288,7 +292,7 @@ reg = <0x58783000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 4>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -304,7 +308,7 @@ reg = <0x58785000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 25 4>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 9>; resets = <&peri_rst 9>; clock-frequency = <400000>; @@ -316,7 +320,7 @@ reg = <0x58786000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 26 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 10>; resets = <&peri_rst 10>; clock-frequency = <400000>; @@ -415,7 +419,7 @@ xdmac: dma-controller@5fc10000 { compatible = "socionext,uniphier-xdmac"; reg = <0x5fc10000 0x5300>; - interrupts = <0 188 4>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <2>; }; @@ -430,14 +434,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0x304>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0x304>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -470,7 +476,7 @@ status = "disabled"; reg = <0x65a00000 0xcd00>; interrupt-names = "host"; - interrupts = <0 134 4>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clock-names = "ref", "bus_early", "suspend"; @@ -480,7 +486,7 @@ dr_mode = "host"; }; - usb-glue@65b00000 { + usb-controller@65b00000 { compatible = "socionext,uniphier-pro5-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -534,7 +540,7 @@ status = "disabled"; reg = <0x65c00000 0xcd00>; interrupt-names = "host"; - interrupts = <0 137 4>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; clock-names = "ref", "bus_early", "suspend"; @@ -544,7 +550,7 @@ dr_mode = "host"; }; - usb-glue@65d00000 { + usb-controller@65d00000 { compatible = "socionext,uniphier-pro5-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -614,8 +620,7 @@ }; pcie_ep: pcie-ep@66000000 { - compatible = "socionext,uniphier-pro5-pcie-ep", - "snps,dw-pcie-ep"; + compatible = "socionext,uniphier-pro5-pcie-ep"; status = "disabled"; reg-names = "dbi", "dbi2", "link", "addr_space"; reg = <0x66000000 0x1000>, <0x66001000 0x1000>, @@ -650,7 +655,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; @@ -663,7 +668,7 @@ compatible = "socionext,uniphier-sd-v3.1"; status = "disabled"; reg = <0x68400000 0x800>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&sd_clk 1>; @@ -679,7 +684,7 @@ compatible = "socionext,uniphier-sd-v3.1"; status = "disabled"; reg = <0x68800000 0x800>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; diff --git a/dts/src/arm/uniphier-pxs2-gentil.dts b/dts/src/arm/uniphier-pxs2-gentil.dts index 759384b606..5f18b926c5 100644 --- a/dts/src/arm/uniphier-pxs2-gentil.dts +++ b/dts/src/arm/uniphier-pxs2-gentil.dts @@ -99,3 +99,7 @@ &usb1 { status = "okay"; }; + +&ahci { + status = "okay"; +}; diff --git a/dts/src/arm/uniphier-pxs2.dtsi b/dts/src/arm/uniphier-pxs2.dtsi index 03301ddb34..ca4dccf56a 100644 --- a/dts/src/arm/uniphier-pxs2.dtsi +++ b/dts/src/arm/uniphier-pxs2.dtsi @@ -6,6 +6,7 @@ // Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> / { @@ -161,7 +162,10 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(1280 * 1024)>; cache-sets = <512>; @@ -175,7 +179,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -188,7 +192,7 @@ reg = <0x54006100 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 216 4>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; clocks = <&peri_clk 12>; @@ -199,7 +203,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -210,7 +214,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -221,7 +225,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -232,7 +236,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -259,7 +263,7 @@ audio@56000000 { compatible = "socionext,uniphier-pxs2-aio"; reg = <0x56000000 0x80000>; - interrupts = <0 144 4>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ain1>, <&pinctrl_ain2>, @@ -317,7 +321,7 @@ reg = <0x58780000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 4>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -331,7 +335,7 @@ reg = <0x58781000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -345,7 +349,7 @@ reg = <0x58782000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 4>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -359,7 +363,7 @@ reg = <0x58783000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 4>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -373,7 +377,7 @@ reg = <0x58784000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 45 4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 8>; resets = <&peri_rst 8>; clock-frequency = <400000>; @@ -385,7 +389,7 @@ reg = <0x58785000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 25 4>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 9>; resets = <&peri_rst 9>; clock-frequency = <400000>; @@ -397,7 +401,7 @@ reg = <0x58786000 0x80>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 26 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&peri_clk 10>; resets = <&peri_rst 10>; clock-frequency = <400000>; @@ -454,7 +458,7 @@ compatible = "socionext,uniphier-sd-v3.1.1"; status = "disabled"; reg = <0x5a000000 0x800>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&sd_clk 1>; @@ -470,7 +474,7 @@ compatible = "socionext,uniphier-sd-v3.1.1"; status = "disabled"; reg = <0x5a400000 0x800>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; @@ -515,7 +519,7 @@ xdmac: dma-controller@5fc10000 { compatible = "socionext,uniphier-xdmac"; reg = <0x5fc10000 0x5300>; - interrupts = <0 188 4>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <2>; }; @@ -530,14 +534,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0xf04>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0xf04>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -564,9 +570,9 @@ #reset-cells = <1>; }; - pvtctl: pvtctl { + pvtctl: thermal-sensor { compatible = "socionext,uniphier-pxs2-thermal"; - interrupts = <0 3 4>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <0>; socionext,tmod-calibration = <0x0f86 0x6844>; }; @@ -576,7 +582,7 @@ compatible = "socionext,uniphier-pxs2-ave4"; status = "disabled"; reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ether_rgmii>; clock-names = "ether"; @@ -593,12 +599,52 @@ }; }; + ahci: sata@65600000 { + compatible = "socionext,uniphier-pxs2-ahci", + "generic-ahci"; + status = "disabled"; + reg = <0x65600000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_clk 28>; + resets = <&sys_rst 28>, <&ahci_rst 0>; + ports-implemented = <1>; + phys = <&ahci_phy>; + }; + + sata-controller@65700000 { + compatible = "socionext,uniphier-pxs2-ahci-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + ahci_rst: reset-controller@0 { + compatible = "socionext,uniphier-pxs2-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link"; + resets = <&sys_rst 28>; + #reset-cells = <1>; + }; + + ahci_phy: sata-phy@10 { + compatible = "socionext,uniphier-pxs2-ahci-phy"; + reg = <0x10 0x10>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link", "phy"; + resets = <&sys_rst 28>, <&sys_rst 30>; + #phy-cells = <0>; + }; + }; + usb0: usb@65a00000 { compatible = "socionext,uniphier-dwc3", "snps,dwc3"; status = "disabled"; reg = <0x65a00000 0xcd00>; interrupt-names = "dwc_usb3"; - interrupts = <0 134 4>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; clock-names = "ref", "bus_early", "suspend"; @@ -609,7 +655,7 @@ dr_mode = "host"; }; - usb-glue@65b00000 { + usb-controller@65b00000 { compatible = "socionext,uniphier-pxs2-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -694,7 +740,7 @@ status = "disabled"; reg = <0x65c00000 0xcd00>; interrupt-names = "dwc_usb3"; - interrupts = <0 137 4>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; clock-names = "ref", "bus_early", "suspend"; @@ -704,7 +750,7 @@ dr_mode = "host"; }; - usb-glue@65d00000 { + usb-controller@65d00000 { compatible = "socionext,uniphier-pxs2-dwc3-glue", "simple-mfd"; #address-cells = <1>; @@ -780,7 +826,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; diff --git a/dts/src/arm/uniphier-sld8-ref.dts b/dts/src/arm/uniphier-sld8-ref.dts index 6db949ec74..2446f9e153 100644 --- a/dts/src/arm/uniphier-sld8-ref.dts +++ b/dts/src/arm/uniphier-sld8-ref.dts @@ -36,11 +36,11 @@ }; ðsc { - interrupts = <0 8>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; &serialsc { - interrupts = <0 8>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; }; &serial0 { @@ -56,7 +56,7 @@ }; &gpio { - xirq0 { + xirq0-hog { gpio-hog; gpios = <UNIPHIER_GPIO_IRQ(0) 0>; input; diff --git a/dts/src/arm/uniphier-sld8.dtsi b/dts/src/arm/uniphier-sld8.dtsi index 96a766deb8..67b12dfe51 100644 --- a/dts/src/arm/uniphier-sld8.dtsi +++ b/dts/src/arm/uniphier-sld8.dtsi @@ -6,6 +6,7 @@ // Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "socionext,uniphier-sld8"; @@ -55,7 +56,8 @@ compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-size = <(256 * 1024)>; cache-sets = <256>; @@ -69,7 +71,7 @@ reg = <0x54006000 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 39 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; @@ -80,7 +82,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; - interrupts = <0 33 4>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; @@ -91,7 +93,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; @@ -102,7 +104,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; @@ -113,7 +115,7 @@ compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; - interrupts = <0 29 4>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; @@ -144,7 +146,7 @@ reg = <0x58400000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 41 1>; + interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; @@ -158,7 +160,7 @@ reg = <0x58480000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 42 1>; + interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; @@ -172,7 +174,7 @@ reg = <0x58500000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 43 1>; + interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; @@ -186,7 +188,7 @@ reg = <0x58580000 0x40>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 44 1>; + interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; @@ -244,8 +246,13 @@ dmac: dma-controller@5a000000 { compatible = "socionext,uniphier-mio-dmac"; reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mio_clk 7>; resets = <&mio_rst 7>; #dma-cells = <1>; @@ -255,7 +262,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default", "uhs"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_uhs>; @@ -275,7 +282,7 @@ compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&mio_clk 1>; @@ -293,7 +300,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, @@ -307,7 +314,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, @@ -321,7 +328,7 @@ compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, @@ -362,14 +369,16 @@ timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; - interrupts = <1 11 0x104>; + interrupts = <GIC_PPI 11 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; - interrupts = <1 13 0x104>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&arm_timer_clk>; }; @@ -411,7 +420,7 @@ reg = <0x68000000 0x20>, <0x68100000 0x1000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0 65 4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand>; clock-names = "nand", "nand_x", "ecc"; diff --git a/dts/src/arm/uniphier-support-card.dtsi b/dts/src/arm/uniphier-support-card.dtsi index 444802fee9..97e7d5db8e 100644 --- a/dts/src/arm/uniphier-support-card.dtsi +++ b/dts/src/arm/uniphier-support-card.dtsi @@ -8,13 +8,13 @@ &system_bus { status = "okay"; ranges = <1 0x00000000 0x42000000 0x02000000>; - interrupt-parent = <&gpio>; ethsc: ethernet@1,1f00000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <1 0x01f00000 0x1000>; phy-mode = "mii"; reg-io-width = <4>; + interrupt-parent = <&gpio>; }; serialsc: serial@1,1fb0000 { @@ -22,5 +22,6 @@ reg = <1 0x01fb0000 0x20>; clock-frequency = <12288000>; reg-shift = <1>; + interrupt-parent = <&gpio>; }; }; diff --git a/dts/src/arm/vf610-bk4.dts b/dts/src/arm/vf610-bk4.dts index 830c85476b..551a4c3ff4 100644 --- a/dts/src/arm/vf610-bk4.dts +++ b/dts/src/arm/vf610-bk4.dts @@ -61,7 +61,7 @@ regulator-max-microvolt = <3300000>; }; - spi-gpio { + spi { compatible = "spi-gpio"; pinctrl-0 = <&pinctrl_gpio_spi>; pinctrl-names = "default"; diff --git a/dts/src/arm/vf610-pinfunc.h b/dts/src/arm/vf610-pinfunc.h index f1e5a7cf58..b7b7322a2d 100644 --- a/dts/src/arm/vf610-pinfunc.h +++ b/dts/src/arm/vf610-pinfunc.h @@ -420,7 +420,7 @@ #define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 #define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 #define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 -#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 +#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 #define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 #define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 #define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 @@ -802,5 +802,55 @@ #define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 #define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 #define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 +#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A13__DDR_A_13 0x228 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A12__DDR_A_12 0x22c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A11__DDR_A_11 0x230 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A10__DDR_A_10 0x234 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A9__DDR_A_9 0x238 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A8__DDR_A_8 0x23c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A7__DDR_A_7 0x240 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A6__DDR_A_6 0x244 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A5__DDR_A_5 0x248 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A4__DDR_A_4 0x24c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A3__DDR_A_3 0x250 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A2__DDR_A_2 0x254 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A1__DDR_A_1 0x258 0x000 ALT0 0x0 +#define VF610_PAD_DDR_A0__DDR_A_0 0x25c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA2__DDR_BA_2 0x260 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA1__DDR_BA_1 0x264 0x000 ALT0 0x0 +#define VF610_PAD_DDR_BA0__DDR_BA_0 0x268 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x26c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x270 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x274 0x000 ALT0 0x0 +#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x278 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D15__DDR_D_15 0x27c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D14__DDR_D_14 0x280 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D13__DDR_D_13 0x284 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D12__DDR_D_12 0x288 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D11__DDR_D_11 0x28c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D10__DDR_D_10 0x290 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D9__DDR_D_9 0x294 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D8__DDR_D_8 0x298 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D7__DDR_D_7 0x29c 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D6__DDR_D_6 0x2a0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D5__DDR_D_5 0x2a4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D4__DDR_D_4 0x2a8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D3__DDR_D_3 0x2ac 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D2__DDR_D_2 0x2b0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D1__DDR_D_1 0x2b4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_D0__DDR_D_0 0x2b8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x2bc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x2c0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x2c4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x2c8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x2cc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_WE__DDR_WE_B 0x2d0 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x2d4 0x000 ALT0 0x0 +#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0 +#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0 #endif diff --git a/dts/src/arm/vf610-twr.dts b/dts/src/arm/vf610-twr.dts index dbb5ffcdce..6c246d5aa0 100644 --- a/dts/src/arm/vf610-twr.dts +++ b/dts/src/arm/vf610-twr.dts @@ -169,7 +169,7 @@ VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; clocks = <&clks VF610_CLK_SAI2>; - }; + }; }; &iomuxc { diff --git a/dts/src/arm/vf610-zii-dev-rev-b.dts b/dts/src/arm/vf610-zii-dev-rev-b.dts index 1f9686c33a..42ed4a04a1 100644 --- a/dts/src/arm/vf610-zii-dev-rev-b.dts +++ b/dts/src/arm/vf610-zii-dev-rev-b.dts @@ -288,7 +288,7 @@ }; }; - spi0 { + spi-0 { compatible = "spi-gpio"; pinctrl-0 = <&pinctrl_gpio_spi0>; pinctrl-names = "default"; diff --git a/dts/src/arm/vf610.dtsi b/dts/src/arm/vf610.dtsi index 956182d08e..2fba923821 100644 --- a/dts/src/arm/vf610.dtsi +++ b/dts/src/arm/vf610.dtsi @@ -2,7 +2,6 @@ // // Copyright 2013 Freescale Semiconductor, Inc. - #include "vf500.dtsi" &a5_cpu { |