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-rw-r--r--dts/src/arm/am335x-baltos-ir2110.dts14
-rw-r--r--dts/src/arm/am335x-baltos-ir3220.dts14
-rw-r--r--dts/src/arm/am335x-baltos-ir5221.dts13
-rw-r--r--dts/src/arm/am335x-pcm-953.dtsi22
-rw-r--r--dts/src/arm/am335x-phycore-rdk.dts4
-rw-r--r--dts/src/arm/am335x-phycore-som.dtsi47
-rw-r--r--dts/src/arm/am335x-regor-rdk.dts24
-rw-r--r--dts/src/arm/am335x-regor.dtsi223
-rw-r--r--dts/src/arm/am335x-wega-rdk.dts4
-rw-r--r--dts/src/arm/am335x-wega.dtsi16
-rw-r--r--dts/src/arm/arm-realview-eb.dtsi6
-rw-r--r--dts/src/arm/arm-realview-pb1176.dts6
-rw-r--r--dts/src/arm/arm-realview-pb11mp.dts6
-rw-r--r--dts/src/arm/arm-realview-pbx.dtsi6
-rw-r--r--dts/src/arm/armada-370-netgear-rn104.dts14
-rw-r--r--dts/src/arm/aspeed-bmc-facebook-cmm.dts8
-rw-r--r--dts/src/arm/aspeed-bmc-facebook-yamp.dts160
-rw-r--r--dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts846
-rw-r--r--dts/src/arm/aspeed-bmc-lenovo-hr630.dts566
-rw-r--r--dts/src/arm/aspeed-bmc-microsoft-olympus.dts207
-rw-r--r--dts/src/arm/aspeed-bmc-opp-lanyang.dts2
-rw-r--r--dts/src/arm/aspeed-bmc-opp-palmetto.dts22
-rw-r--r--dts/src/arm/aspeed-bmc-opp-romulus.dts14
-rw-r--r--dts/src/arm/aspeed-bmc-opp-swift.dts966
-rw-r--r--dts/src/arm/aspeed-bmc-opp-vesnin.dts224
-rw-r--r--dts/src/arm/aspeed-bmc-opp-witherspoon.dts14
-rw-r--r--dts/src/arm/aspeed-bmc-opp-zaius.dts123
-rw-r--r--dts/src/arm/aspeed-bmc-quanta-q71l.dts5
-rw-r--r--dts/src/arm/aspeed-g4.dtsi8
-rw-r--r--dts/src/arm/aspeed-g5.dtsi11
-rw-r--r--dts/src/arm/at91-wb50n.dtsi2
-rw-r--r--dts/src/arm/at91sam9261ek.dts8
-rw-r--r--dts/src/arm/at91sam9g45.dtsi25
-rw-r--r--dts/src/arm/at91sam9rl.dtsi25
-rw-r--r--dts/src/arm/at91sam9x5.dtsi23
-rw-r--r--dts/src/arm/bcm-cygnus-clock.dtsi12
-rw-r--r--dts/src/arm/bcm-cygnus.dtsi6
-rw-r--r--dts/src/arm/bcm-nsp.dtsi9
-rw-r--r--dts/src/arm/bcm11351.dtsi12
-rw-r--r--dts/src/arm/bcm21664-garnet.dts2
-rw-r--r--dts/src/arm/bcm21664.dtsi10
-rw-r--r--dts/src/arm/bcm23550-sparrow.dts2
-rw-r--r--dts/src/arm/bcm23550.dtsi8
-rw-r--r--dts/src/arm/bcm28155-ap.dts2
-rw-r--r--dts/src/arm/bcm283x.dtsi2
-rw-r--r--dts/src/arm/bcm4708-asus-rt-ac56u.dts4
-rw-r--r--dts/src/arm/bcm4708-asus-rt-ac68u.dts4
-rw-r--r--dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts4
-rw-r--r--dts/src/arm/bcm4708-linksys-ea6300-v1.dts4
-rw-r--r--dts/src/arm/bcm4708-linksys-ea6500-v2.dts4
-rw-r--r--dts/src/arm/bcm4708-luxul-xap-1510.dts4
-rw-r--r--dts/src/arm/bcm4708-luxul-xwc-1000.dts4
-rw-r--r--dts/src/arm/bcm4708-netgear-r6250.dts2
-rw-r--r--dts/src/arm/bcm4708-netgear-r6300-v2.dts4
-rw-r--r--dts/src/arm/bcm4708-smartrg-sr400ac.dts4
-rw-r--r--dts/src/arm/bcm47081-asus-rt-n18u.dts4
-rw-r--r--dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts4
-rw-r--r--dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts4
-rw-r--r--dts/src/arm/bcm47081-luxul-xap-1410.dts4
-rw-r--r--dts/src/arm/bcm47081-luxul-xwr-1200.dts4
-rw-r--r--dts/src/arm/bcm47081-tplink-archer-c5-v2.dts4
-rw-r--r--dts/src/arm/bcm47094-dlink-dir-885l.dts4
-rw-r--r--dts/src/arm/bcm47094-linksys-panamera.dts4
-rw-r--r--dts/src/arm/bcm47094-luxul-abr-4500.dts4
-rw-r--r--dts/src/arm/bcm47094-luxul-xap-1610.dts4
-rw-r--r--dts/src/arm/bcm47094-luxul-xbr-4500.dts4
-rw-r--r--dts/src/arm/bcm47094-luxul-xwr-3100.dts4
-rw-r--r--dts/src/arm/bcm47094-luxul-xwr-3150-v1.dts4
-rw-r--r--dts/src/arm/bcm47094-netgear-r8500.dts4
-rw-r--r--dts/src/arm/bcm47094-phicomm-k3.dts4
-rw-r--r--dts/src/arm/bcm47189-luxul-xap-1440.dts4
-rw-r--r--dts/src/arm/bcm47189-luxul-xap-810.dts4
-rw-r--r--dts/src/arm/bcm47189-tenda-ac9.dts4
-rw-r--r--dts/src/arm/bcm5301x.dtsi10
-rw-r--r--dts/src/arm/bcm53573.dtsi2
-rw-r--r--dts/src/arm/bcm63138.dtsi9
-rw-r--r--dts/src/arm/bcm7445-bcm97445svmb.dts2
-rw-r--r--dts/src/arm/bcm7445.dtsi8
-rw-r--r--dts/src/arm/bcm911360_entphn.dts2
-rw-r--r--dts/src/arm/bcm947189acdbmr.dts4
-rw-r--r--dts/src/arm/bcm953012er.dts4
-rw-r--r--dts/src/arm/bcm953012k.dts2
-rw-r--r--dts/src/arm/bcm958522er.dts2
-rw-r--r--dts/src/arm/bcm958525er.dts2
-rw-r--r--dts/src/arm/bcm958525xmc.dts2
-rw-r--r--dts/src/arm/bcm958622hr.dts2
-rw-r--r--dts/src/arm/bcm958623hr.dts2
-rw-r--r--dts/src/arm/bcm958625hr.dts2
-rw-r--r--dts/src/arm/bcm958625k.dts2
-rw-r--r--dts/src/arm/bcm963138dvt.dts2
-rw-r--r--dts/src/arm/bcm988312hr.dts2
-rw-r--r--dts/src/arm/da850-evm.dts13
-rw-r--r--dts/src/arm/da850-lcdk.dts36
-rw-r--r--dts/src/arm/da850-lego-ev3.dts30
-rw-r--r--dts/src/arm/da850.dtsi50
-rw-r--r--dts/src/arm/emev2-kzm9d.dts2
-rw-r--r--dts/src/arm/exynos3250-artik5.dtsi5
-rw-r--r--dts/src/arm/exynos3250-monk.dts5
-rw-r--r--dts/src/arm/exynos3250-rinato.dts5
-rw-r--r--dts/src/arm/exynos3250.dtsi33
-rw-r--r--dts/src/arm/exynos4.dtsi16
-rw-r--r--dts/src/arm/exynos4210-origen.dts5
-rw-r--r--dts/src/arm/exynos4210-trats.dts4
-rw-r--r--dts/src/arm/exynos4210-universal_c210.dts5
-rw-r--r--dts/src/arm/exynos4210.dtsi51
-rw-r--r--dts/src/arm/exynos4412-galaxy-s3.dtsi32
-rw-r--r--dts/src/arm/exynos4412-itop-scp-core.dtsi5
-rw-r--r--dts/src/arm/exynos4412-midas.dtsi5
-rw-r--r--dts/src/arm/exynos4412-odroid-common.dtsi5
-rw-r--r--dts/src/arm/exynos4412-prime.dtsi7
-rw-r--r--dts/src/arm/exynos4412.dtsi49
-rw-r--r--dts/src/arm/exynos5410-odroidxu.dts5
-rw-r--r--dts/src/arm/exynos5410.dtsi6
-rw-r--r--dts/src/arm/exynos5420-arndale-octa.dts102
-rw-r--r--dts/src/arm/exynos5420.dtsi234
-rw-r--r--dts/src/arm/exynos5422-odroid-core.dtsi108
-rw-r--r--dts/src/arm/exynos5422-odroidxu3-common.dtsi6
-rw-r--r--dts/src/arm/exynos54xx.dtsi9
-rw-r--r--dts/src/arm/gemini-dlink-dir-685.dts2
-rw-r--r--dts/src/arm/hip04.dtsi18
-rw-r--r--dts/src/arm/ibm-power9-dual.dtsi248
-rw-r--r--dts/src/arm/imx53-m53menlo.dts266
-rw-r--r--dts/src/arm/imx53-smd.dts73
-rw-r--r--dts/src/arm/imx53.dtsi12
-rw-r--r--dts/src/arm/imx6dl-kontron-samx6i.dtsi12
-rw-r--r--dts/src/arm/imx6q-kontron-samx6i.dtsi36
-rw-r--r--dts/src/arm/imx6qdl-kontron-samx6i.dtsi815
-rw-r--r--dts/src/arm/imx6qdl-sabresd.dtsi16
-rw-r--r--dts/src/arm/imx6qdl.dtsi11
-rw-r--r--dts/src/arm/imx6sl-evk.dts12
-rw-r--r--dts/src/arm/imx6sl.dtsi12
-rw-r--r--dts/src/arm/imx6sll-evk.dts12
-rw-r--r--dts/src/arm/imx6sll.dtsi2
-rw-r--r--dts/src/arm/imx6sx-sdb-reva.dts16
-rw-r--r--dts/src/arm/imx6sx-sdb.dts16
-rw-r--r--dts/src/arm/imx6sx-udoo-neo-basic.dts39
-rw-r--r--dts/src/arm/imx6sx-udoo-neo-extended.dts47
-rw-r--r--dts/src/arm/imx6sx-udoo-neo-full.dts47
-rw-r--r--dts/src/arm/imx6sx-udoo-neo.dtsi89
-rw-r--r--dts/src/arm/imx6sx.dtsi7
-rw-r--r--dts/src/arm/imx6ul-14x14-evk.dtsi4
-rw-r--r--dts/src/arm/imx6ul-geam.dts2
-rw-r--r--dts/src/arm/imx6ul-isiot.dtsi2
-rw-r--r--dts/src/arm/imx6ul.dtsi14
-rw-r--r--dts/src/arm/imx6ull-colibri-eval-v3.dtsi11
-rw-r--r--dts/src/arm/imx6ull-colibri.dtsi6
-rw-r--r--dts/src/arm/imx6ull.dtsi7
-rw-r--r--dts/src/arm/imx7d-meerkat96.dts375
-rw-r--r--dts/src/arm/imx7d-sdb.dts16
-rw-r--r--dts/src/arm/imx7d-zii-rpu2.dts16
-rw-r--r--dts/src/arm/imx7d.dtsi16
-rw-r--r--dts/src/arm/imx7s.dtsi11
-rw-r--r--dts/src/arm/imx7ulp-evk.dts55
-rw-r--r--dts/src/arm/imx7ulp.dtsi61
-rw-r--r--dts/src/arm/integrator.dtsi3
-rw-r--r--dts/src/arm/iwg20d-q7-common.dtsi2
-rw-r--r--dts/src/arm/logicpd-torpedo-37xx-devkit-28.dts32
-rw-r--r--dts/src/arm/ls1021a-tsn.dts289
-rw-r--r--dts/src/arm/meson.dtsi44
-rw-r--r--dts/src/arm/meson6-atv1200.dts44
-rw-r--r--dts/src/arm/meson6.dtsi44
-rw-r--r--dts/src/arm/meson8-minix-neo-x8.dts39
-rw-r--r--dts/src/arm/meson8.dtsi64
-rw-r--r--dts/src/arm/meson8b-ec100.dts9
-rw-r--r--dts/src/arm/meson8b-mxq.dts182
-rw-r--r--dts/src/arm/meson8b-odroidc1.dts51
-rw-r--r--dts/src/arm/meson8b.dtsi64
-rw-r--r--dts/src/arm/meson8m2-mxiii-plus.dts17
-rw-r--r--dts/src/arm/meson8m2.dtsi10
-rw-r--r--dts/src/arm/omap4-l4.dtsi9
-rw-r--r--dts/src/arm/pxa300-raumfeld-common.dtsi6
-rw-r--r--dts/src/arm/pxa300-raumfeld-controller.dts21
-rw-r--r--dts/src/arm/pxa300-raumfeld-speaker-one.dts3
-rw-r--r--dts/src/arm/pxa3xx.dtsi8
-rw-r--r--dts/src/arm/qcom-apq8064.dtsi4
-rw-r--r--dts/src/arm/qcom-msm8974-fairphone-fp2.dts6
-rw-r--r--dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts156
-rw-r--r--dts/src/arm/qcom-msm8974.dtsi138
-rw-r--r--dts/src/arm/r7s72100-genmai.dts2
-rw-r--r--dts/src/arm/r7s72100-rskrza1.dts38
-rw-r--r--dts/src/arm/r7s72100.dtsi19
-rw-r--r--dts/src/arm/r7s9210-rza2mevb.dts161
-rw-r--r--dts/src/arm/r7s9210.dtsi286
-rw-r--r--dts/src/arm/r8a73a4-ape6evm.dts2
-rw-r--r--dts/src/arm/r8a7740-armadillo800eva.dts2
-rw-r--r--dts/src/arm/r8a7743-sk-rzg1m.dts2
-rw-r--r--dts/src/arm/r8a7745-iwg22d-sodimm.dts2
-rw-r--r--dts/src/arm/r8a7745-sk-rzg1e.dts2
-rw-r--r--dts/src/arm/r8a77470-iwg23s-sbc.dts4
-rw-r--r--dts/src/arm/r8a7778-bockw.dts2
-rw-r--r--dts/src/arm/r8a7779-marzen.dts2
-rw-r--r--dts/src/arm/r8a7790-lager.dts9
-rw-r--r--dts/src/arm/r8a7790-stout.dts9
-rw-r--r--dts/src/arm/r8a7791-koelsch.dts9
-rw-r--r--dts/src/arm/r8a7791-porter.dts9
-rw-r--r--dts/src/arm/r8a7792-blanche.dts9
-rw-r--r--dts/src/arm/r8a7792-wheat.dts2
-rw-r--r--dts/src/arm/r8a7792.dtsi34
-rw-r--r--dts/src/arm/r8a7793-gose.dts9
-rw-r--r--dts/src/arm/r8a7794-alt.dts2
-rw-r--r--dts/src/arm/r8a7794-silk.dts2
-rw-r--r--dts/src/arm/rk322x.dtsi85
-rw-r--r--dts/src/arm/rk3288-veyron-chromebook.dtsi29
-rw-r--r--dts/src/arm/rk3288-veyron-jaq.dts207
-rw-r--r--dts/src/arm/rk3288-veyron-jerry.dts207
-rw-r--r--dts/src/arm/rk3288-veyron-mickey.dts234
-rw-r--r--dts/src/arm/rk3288-veyron-minnie.dts256
-rw-r--r--dts/src/arm/rk3288-veyron-pinky.dts2
-rw-r--r--dts/src/arm/rk3288-veyron-speedy.dts219
-rw-r--r--dts/src/arm/rk3288-veyron.dtsi78
-rw-r--r--dts/src/arm/rk3288.dtsi30
-rw-r--r--dts/src/arm/sama5d3.dtsi27
-rw-r--r--dts/src/arm/sh73a0-kzm9g.dts2
-rw-r--r--dts/src/arm/socfpga_arria10.dtsi21
-rw-r--r--dts/src/arm/socfpga_arria10_socdk.dtsi19
-rw-r--r--dts/src/arm/stm32746g-eval.dts66
-rw-r--r--dts/src/arm/stm32mp157-pinctrl.dtsi246
-rw-r--r--dts/src/arm/stm32mp157a-avenger96.dts321
-rw-r--r--dts/src/arm/stm32mp157a-dk1.dts70
-rw-r--r--dts/src/arm/stm32mp157c-ed1.dts18
-rw-r--r--dts/src/arm/stm32mp157c-ev1.dts125
-rw-r--r--dts/src/arm/stm32mp157c.dtsi180
-rw-r--r--dts/src/arm/stm32mp157xaa-pinctrl.dtsi90
-rw-r--r--dts/src/arm/stm32mp157xab-pinctrl.dtsi62
-rw-r--r--dts/src/arm/stm32mp157xac-pinctrl.dtsi78
-rw-r--r--dts/src/arm/stm32mp157xad-pinctrl.dtsi62
-rw-r--r--dts/src/arm/sun5i-gr8-evb.dts2
-rw-r--r--dts/src/arm/sun6i-a31.dtsi25
-rw-r--r--dts/src/arm/sun7i-a20-icnova-swac.dts3
-rw-r--r--dts/src/arm/sun7i-a20-olinuxino-lime2.dts8
-rw-r--r--dts/src/arm/sun8i-a83t-tbs-a711.dts4
-rw-r--r--dts/src/arm/sun8i-a83t.dtsi29
-rw-r--r--dts/src/arm/sun8i-h2-plus-bananapi-m2-zero.dts3
-rw-r--r--dts/src/arm/sun8i-h2-plus-orangepi-zero.dts3
-rw-r--r--dts/src/arm/sun8i-h3-beelink-x2.dts4
-rw-r--r--dts/src/arm/sun8i-h3-orangepi-one.dts3
-rw-r--r--dts/src/arm/sun8i-r40-bananapi-m2-ultra.dts7
-rw-r--r--dts/src/arm/sun8i-r40.dtsi3
-rw-r--r--dts/src/arm/sun8i-v3s.dtsi13
-rw-r--r--dts/src/arm/sun8i-v40-bananapi-m2-berry.dts123
-rw-r--r--dts/src/arm/sunxi-bananapi-m2-plus-v1.2.dtsi3
-rw-r--r--dts/src/arm/uniphier-ld4-ref.dts4
-rw-r--r--dts/src/arm/uniphier-ld4.dtsi4
-rw-r--r--dts/src/arm/uniphier-ld6b-ref.dts4
-rw-r--r--dts/src/arm/uniphier-pro4-ref.dts4
-rw-r--r--dts/src/arm/uniphier-pro4.dtsi2
-rw-r--r--dts/src/arm/uniphier-pro5.dtsi4
-rw-r--r--dts/src/arm/uniphier-pxs2.dtsi4
-rw-r--r--dts/src/arm/uniphier-sld8-ref.dts4
-rw-r--r--dts/src/arm/uniphier-sld8.dtsi4
-rw-r--r--dts/src/arm/versatile-ab.dts3
-rw-r--r--dts/src/arm/vexpress-v2m-rs1.dtsi5
-rw-r--r--dts/src/arm/vexpress-v2m.dtsi3
-rw-r--r--dts/src/arm/vexpress-v2p-ca15_a7.dts13
-rw-r--r--dts/src/arm/vf610-zii-dev.dtsi52
255 files changed, 10862 insertions, 1229 deletions
diff --git a/dts/src/arm/am335x-baltos-ir2110.dts b/dts/src/arm/am335x-baltos-ir2110.dts
index 49e46ba..386d5f8 100644
--- a/dts/src/arm/am335x-baltos-ir2110.dts
+++ b/dts/src/arm/am335x-baltos-ir2110.dts
@@ -30,6 +30,12 @@
AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
>;
};
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE7) /* MMC1 CD */
+ >;
+ };
};
&uart1 {
@@ -65,7 +71,13 @@
};
&cpsw_emac1 {
- phy-mode = "rgmii-txid";
+ phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
phy-handle = <&phy1>;
};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/am335x-baltos-ir3220.dts b/dts/src/arm/am335x-baltos-ir3220.dts
index 9e88bc2..b0df725 100644
--- a/dts/src/arm/am335x-baltos-ir3220.dts
+++ b/dts/src/arm/am335x-baltos-ir3220.dts
@@ -51,6 +51,12 @@
AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
>;
};
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */
+ >;
+ };
};
&uart1 {
@@ -107,7 +113,13 @@
};
&cpsw_emac1 {
- phy-mode = "rgmii-txid";
+ phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
phy-handle = <&phy1>;
};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/am335x-baltos-ir5221.dts b/dts/src/arm/am335x-baltos-ir5221.dts
index 28aa004..d6aa46e 100644
--- a/dts/src/arm/am335x-baltos-ir5221.dts
+++ b/dts/src/arm/am335x-baltos-ir5221.dts
@@ -60,6 +60,11 @@
>;
};
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */
+ >;
+ };
};
&uart1 {
@@ -125,7 +130,7 @@
};
&cpsw_emac1 {
- phy-mode = "rgmii-txid";
+ phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
phy-handle = <&phy1>;
};
@@ -136,3 +141,9 @@
status = "okay";
};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/am335x-pcm-953.dtsi b/dts/src/arm/am335x-pcm-953.dtsi
index d774bf7..9bfa032 100644
--- a/dts/src/arm/am335x-pcm-953.dtsi
+++ b/dts/src/arm/am335x-pcm-953.dtsi
@@ -36,15 +36,13 @@
pinctrl-names = "default";
pinctrl-0 = <&user_leds_pins>;
- green {
- label = "green:user";
+ user-led0 {
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "on";
};
- yellow {
- label = "yellow:user";
+ user-led1 {
gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
linux,default-trigger = "gpio";
default-state = "on";
@@ -135,22 +133,6 @@
&davinci_mdio {
phy1: ethernet-phy@2 {
reg = <2>;
-
- /* Register 260 (104h) – RGMII Clock and Control Pad Skew */
- rxc-skew-ps = <1400>;
- rxdv-skew-ps = <0>;
- txc-skew-ps = <1400>;
- txen-skew-ps = <0>;
- /* Register 261 (105h) – RGMII RX Data Pad Skew */
- rxd3-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd0-skew-ps = <0>;
- /* Register 262 (106h) – RGMII TX Data Pad Skew */
- txd3-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd0-skew-ps = <0>;
};
};
diff --git a/dts/src/arm/am335x-phycore-rdk.dts b/dts/src/arm/am335x-phycore-rdk.dts
index 672daf9..43907d0 100644
--- a/dts/src/arm/am335x-phycore-rdk.dts
+++ b/dts/src/arm/am335x-phycore-rdk.dts
@@ -10,6 +10,10 @@
#include "am335x-pcm-953.dtsi"
/* SoM */
+&gpmc {
+ status = "okay";
+};
+
&i2c_eeprom {
status = "okay";
};
diff --git a/dts/src/arm/am335x-phycore-som.dtsi b/dts/src/arm/am335x-phycore-som.dtsi
index ee6b1cb..3d0672b 100644
--- a/dts/src/arm/am335x-phycore-som.dtsi
+++ b/dts/src/arm/am335x-phycore-som.dtsi
@@ -27,17 +27,13 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
- regulators {
- compatible = "simple-bus";
-
- vcc5v: fixedregulator0 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- };
+ vcc5v: fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
};
};
@@ -50,6 +46,33 @@
status = "okay";
};
+/* EMMC */
+&am33xx_pinmux {
+ emmc_pins: pinmux_emmc_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+ >;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pins>;
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <8>;
+ ti,non-removable;
+ status = "disabled";
+};
+
/* Ethernet */
&am33xx_pinmux {
ethernet0_pins: pinmux_ethernet0 {
@@ -164,7 +187,7 @@
};
&gpmc {
- status = "okay";
+ status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
diff --git a/dts/src/arm/am335x-regor-rdk.dts b/dts/src/arm/am335x-regor-rdk.dts
new file mode 100644
index 0000000..66a1360
--- /dev/null
+++ b/dts/src/arm/am335x-regor-rdk.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "am335x-phycore-som.dtsi"
+#include "am335x-regor.dtsi"
+
+/* SoM */
+&gpmc {
+ status = "okay";
+};
+
+&i2c_eeprom {
+ status = "okay";
+};
+
+&serial_flash {
+ status = "okay";
+};
diff --git a/dts/src/arm/am335x-regor.dtsi b/dts/src/arm/am335x-regor.dtsi
new file mode 100644
index 0000000..5aff02a
--- /dev/null
+++ b/dts/src/arm/am335x-regor.dtsi
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ */
+
+/ {
+ model = "Phytec AM335x phyBOARD-REGOR";
+ compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";
+
+ vcc3v3: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ /* User IO */
+ user_leds: user_leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_pins>;
+
+ run_stop-led {
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "off";
+ };
+
+ error-led {
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "gpio";
+ default-state = "off";
+ };
+ };
+};
+
+/* User Leds */
+&am33xx_pinmux {
+ user_leds_pins: pinmux_user_leds {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */
+ >;
+ };
+};
+
+/* CAN Busses */
+&am33xx_pinmux {
+ dcan1_pins: pinmux_dcan1 {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+ >;
+ };
+};
+
+&dcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcan1_pins>;
+ status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+ ethernet1_pins: pinmux_ethernet1 {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */
+ >;
+ };
+};
+
+&cpsw_emac1 {
+ phy-handle = <&phy1>;
+ phy-mode = "mii";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mac {
+ slaves = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
+ dual_emac = <1>;
+};
+
+/* GPIOs */
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_gpios_pins>;
+
+ user_gpios_pins: pinmux_user_gpios {
+ pinctrl-single,pins = <
+ /* DIGIN 1-4 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */
+ /* DIGOUT 1-4 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */
+ >;
+ };
+};
+
+/* MMC */
+&am33xx_pinmux {
+ mmc1_pins: pinmux_mmc1 {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
+ >;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&vcc3v3>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* RTC */
+&i2c_rtc {
+ status = "okay";
+};
+
+/* UARTs */
+&am33xx_pinmux {
+ uart0_pins: pinmux_uart0 {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ >;
+ };
+
+ uart2_pins: pinmux_uart2 {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */
+ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+/* RS485 - UART1 */
+&am33xx_pinmux {
+ uart1_rs485_pins: pinmux_uart1_rs485_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0)
+ >;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_rs485_pins>;
+ status = "okay";
+ linux,rs485-enabled-at-boot-time;
+};
+
+/* USB */
+&cppi41dma {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
diff --git a/dts/src/arm/am335x-wega-rdk.dts b/dts/src/arm/am335x-wega-rdk.dts
index 2e04f6d..866b5f0 100644
--- a/dts/src/arm/am335x-wega-rdk.dts
+++ b/dts/src/arm/am335x-wega-rdk.dts
@@ -10,6 +10,10 @@
#include "am335x-wega.dtsi"
/* SoM */
+&gpmc {
+ status = "okay";
+};
+
&i2c_eeprom {
status = "okay";
};
diff --git a/dts/src/arm/am335x-wega.dtsi b/dts/src/arm/am335x-wega.dtsi
index 67bde56..61fc4cd 100644
--- a/dts/src/arm/am335x-wega.dtsi
+++ b/dts/src/arm/am335x-wega.dtsi
@@ -12,16 +12,12 @@
compatible = "ti,da830-evm-audio";
};
- regulators {
- compatible = "simple-bus";
-
- vcc3v3: fixedregulator1 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
+ vcc3v3: fixedregulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
};
diff --git a/dts/src/arm/arm-realview-eb.dtsi b/dts/src/arm/arm-realview-eb.dtsi
index 6105067..fe0207b 100644
--- a/dts/src/arm/arm-realview-eb.dtsi
+++ b/dts/src/arm/arm-realview-eb.dtsi
@@ -119,6 +119,9 @@
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x40000000 0x04000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
flash1@44000000 {
@@ -126,6 +129,9 @@
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x44000000 0x04000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
/* SMSC LAN91C111 ethernet with PHY and EEPROM */
diff --git a/dts/src/arm/arm-realview-pb1176.dts b/dts/src/arm/arm-realview-pb1176.dts
index cbbb887..2625ce6 100644
--- a/dts/src/arm/arm-realview-pb1176.dts
+++ b/dts/src/arm/arm-realview-pb1176.dts
@@ -120,12 +120,18 @@
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x30000000 0x4000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
fpga_flash@38000000 {
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x38000000 0x800000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
/*
diff --git a/dts/src/arm/arm-realview-pb11mp.dts b/dts/src/arm/arm-realview-pb11mp.dts
index 2015619..c69cf7d 100644
--- a/dts/src/arm/arm-realview-pb11mp.dts
+++ b/dts/src/arm/arm-realview-pb11mp.dts
@@ -235,6 +235,9 @@
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x40000000 0x04000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
flash1@44000000 {
@@ -242,6 +245,9 @@
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x44000000 0x04000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
bridge {
diff --git a/dts/src/arm/arm-realview-pbx.dtsi b/dts/src/arm/arm-realview-pbx.dtsi
index a81e9c2..09f3f54 100644
--- a/dts/src/arm/arm-realview-pbx.dtsi
+++ b/dts/src/arm/arm-realview-pbx.dtsi
@@ -134,6 +134,9 @@
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x40000000 0x04000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
flash1@44000000 {
@@ -141,6 +144,9 @@
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x44000000 0x04000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
/* SMSC 9118 ethernet with PHY and EEPROM */
diff --git a/dts/src/arm/armada-370-netgear-rn104.dts b/dts/src/arm/armada-370-netgear-rn104.dts
index 9fd1cb9..85e2e9e 100644
--- a/dts/src/arm/armada-370-netgear-rn104.dts
+++ b/dts/src/arm/armada-370-netgear-rn104.dts
@@ -143,6 +143,20 @@
};
};
+ auxdisplay {
+ compatible = "hit,hd44780";
+ data-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
+ <&gpio1 26 GPIO_ACTIVE_HIGH>,
+ <&gpio1 27 GPIO_ACTIVE_HIGH>,
+ <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+ rs-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ rw-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ backlight-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ display-height-chars = <2>;
+ display-width-chars = <16>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&backup_button_pin
diff --git a/dts/src/arm/aspeed-bmc-facebook-cmm.dts b/dts/src/arm/aspeed-bmc-facebook-cmm.dts
index 43aba40..d519d30 100644
--- a/dts/src/arm/aspeed-bmc-facebook-cmm.dts
+++ b/dts/src/arm/aspeed-bmc-facebook-cmm.dts
@@ -372,3 +372,11 @@
&adc {
status = "okay";
};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
diff --git a/dts/src/arm/aspeed-bmc-facebook-yamp.dts b/dts/src/arm/aspeed-bmc-facebook-yamp.dts
new file mode 100644
index 0000000..4e09a9c
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-facebook-yamp.dts
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2018 Facebook Inc.
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+
+/ {
+ model = "Facebook YAMP 100 BMC";
+ compatible = "facebook,yamp-bmc", "aspeed,ast2500";
+
+ aliases {
+ /*
+ * Override the default uart aliases to avoid breaking
+ * the legacy applications.
+ */
+ serial0 = &uart5;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS0,9600n8 root=/dev/ram rw";
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+/*
+ * Update reset type to "system" (full chip) to fix warm reboot hang issue
+ * when reset type is set to default ("soc", gated by reset mask registers).
+ */
+&wdt1 {
+ status = "okay";
+ aspeed,reset-type = "system";
+};
+
+/*
+ * wdt2 is not used by Yamp.
+ */
+&wdt2 {
+ status = "disabled";
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+#include "facebook-bmc-flash-layout.dtsi"
+ };
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default
+ &pinctrl_rxd2_default>;
+};
+
+&uart3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default
+ &pinctrl_rxd3_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+ use-ncsi;
+ no-hw-checksum;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ i2c-switch@75 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+};
diff --git a/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts b/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts
new file mode 100644
index 0000000..628195b
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-inspur-fp5280g2.dts
@@ -0,0 +1,846 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/leds/leds-pca955x.h>
+
+/ {
+ model = "FP5280G2 BMC";
+ compatible = "inspur,fp5280g2-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vga_memory: framebuffer@9f000000 {
+ no-map;
+ reg = <0x9f000000 0x01000000>; /* 16M */
+ };
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+
+ coldfire_memory: codefire_memory@9ef00000 {
+ reg = <0x9ef00000 0x00100000>;
+ no-map;
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ video_engine_memory: jpegbuffer {
+ size = <0x02000000>; /* 32M */
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ no-gpio-delays;
+
+ memory-region = <&coldfire_memory>;
+ aspeed,sram = <&sram>;
+ aspeed,cvic = <&cvic>;
+
+ clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(B, 3)>;
+ };
+
+ ps0-presence {
+ label = "ps0-presence";
+ gpios = <&gpio ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(F, 0)>;
+ };
+
+ ps1-presence {
+ label = "ps1-presence";
+ gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(F, 1)>;
+ };
+
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <1000>;
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&pca1 0 GPIO_ACTIVE_LOW>;
+ linux,code = <1>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&pca1 1 GPIO_ACTIVE_LOW>;
+ linux,code = <2>;
+ };
+
+ fan2-presence {
+ label = "fan2-presence";
+ gpios = <&pca1 2 GPIO_ACTIVE_LOW>;
+ linux,code = <3>;
+ };
+
+ fan3-presence {
+ label = "fan3-presence";
+ gpios = <&pca1 3 GPIO_ACTIVE_LOW>;
+ linux,code = <4>;
+ };
+
+ fan4-presence {
+ label = "fan4-presence";
+ gpios = <&pca1 4 GPIO_ACTIVE_LOW>;
+ linux,code = <5>;
+ };
+
+ fan5-presence {
+ label = "fan5-presence";
+ gpios = <&pca1 5 GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ fan6-presence {
+ label = "fan6-presence";
+ gpios = <&pca1 6 GPIO_ACTIVE_LOW>;
+ linux,code = <7>;
+ };
+
+ fan7-presence {
+ label = "fan7-presence";
+ gpios = <&pca1 7 GPIO_ACTIVE_LOW>;
+ linux,code = <8>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "power";
+ /* TODO: dummy gpio */
+ gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 15>;
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>,
+ <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>,
+ <&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&uart1 {
+ /* Rear RS-232 connector */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
+&uart2 {
+ /* Test Point */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
+};
+
+&uart3 {
+ /* APSS */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&i2c0 {
+ /* LCD */
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ label = "fru";
+ };
+
+};
+
+&i2c2 {
+ status = "okay";
+
+ tmp112@48 {
+ compatible = "ti,tmp112";
+ reg = <0x48>;
+ label = "inlet";
+ };
+
+ tmp112@49 {
+ compatible = "ti,tmp112";
+ reg = <0x49>;
+ label = "outlet";
+ };
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tmp112@4a {
+ compatible = "ti,tmp112";
+ reg = <0x4a>;
+ label = "psu_inlet";
+ };
+
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tmp112@4a {
+ compatible = "ti,tmp112";
+ reg = <0x4a>;
+ label = "ocp_zone";
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ tmp112@4a {
+ compatible = "ti,tmp112";
+ reg = <0x4a>;
+ label = "bmc_zone";
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ tmp112@7c {
+ compatible = "microchip,emc1413";
+ reg = <0x7c>;
+ };
+ };
+
+ };
+};
+
+&i2c3 {
+ /* Riser Card */
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ };
+};
+
+&i2c5 {
+ /* vr */
+ status = "okay";
+};
+
+&i2c6 {
+ /* bp card */
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ adm1278@10 {
+ compatible = "adi,adm1278";
+ reg = <0x10>;
+ };
+
+ adm1278@13 {
+ compatible = "adi,adm1278";
+ reg = <0x13>;
+ };
+
+ adm1278@50 {
+ compatible = "adi,adm1278";
+ reg = <0x50>;
+ };
+
+ adm1278@53 {
+ compatible = "adi,adm1278";
+ reg = <0x53>;
+ };
+
+ };
+
+ /*pcie riser*/
+
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ pca0: pca9555@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ };
+
+ pca1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ reg = <0x21>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ pca2: pca9555@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ pca3: pca9555@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ pca4: pca9555@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ pca5: pca9555@25 {
+ compatible = "nxp,pca9555";
+ reg = <0x25>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+};
+
+&i2c9 {
+ /* cpld */
+ status = "okay";
+};
+
+&i2c10 {
+ /* hdd bp */
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ power-supply@58 {
+ compatible = "pmbus";
+ reg = <0x58>;
+ };
+
+ power-supply@5a {
+ compatible = "pmbus";
+ reg = <0x5a>;
+ };
+};
+
+&i2c12 {
+ /* odcc */
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&gpio {
+ pin_gpio_b7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B,7) GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "BMC_INIT_OK";
+ };
+};
+
+&wdt1 {
+ aspeed,reset-type = "none";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+};
+
+&ibt {
+ status = "okay";
+
+};
+
+&adc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default &pinctrl_adc4_default
+ &pinctrl_adc5_default &pinctrl_adc6_default &pinctrl_adc7_default
+ &pinctrl_adc8_default &pinctrl_adc9_default &pinctrl_adc10_default
+ &pinctrl_adc11_default &pinctrl_adc12_default &pinctrl_adc13_default
+ &pinctrl_adc14_default &pinctrl_adc15_default>;
+};
+
+&vhub {
+ status = "okay";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
+ &pinctrl_pwm2_default &pinctrl_pwm3_default
+ &pinctrl_pwm4_default &pinctrl_pwm5_default
+ &pinctrl_pwm6_default &pinctrl_pwm7_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>;
+ };
+
+ fan@2 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>;
+ };
+
+ fan@4 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>;
+ };
+
+ fan@5 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>;
+ };
+
+ fan@6 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>;
+ };
+
+ fan@7 {
+ reg = <0x07>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>;
+ };
+
+};
+
+#include "ibm-power9-dual.dtsi"
diff --git a/dts/src/arm/aspeed-bmc-lenovo-hr630.dts b/dts/src/arm/aspeed-bmc-lenovo-hr630.dts
new file mode 100644
index 0000000..d3695a3
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-lenovo-hr630.dts
@@ -0,0 +1,566 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Lenovo Hr630 platform
+ *
+ * Copyright (C) 2019-present Lenovo
+ */
+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "HR630 BMC";
+ compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
+
+ aliases {
+ i2c14 = &i2c_rbp;
+ i2c15 = &i2c_fbp1;
+ i2c16 = &i2c_fbp2;
+ i2c17 = &i2c_fbp3;
+ i2c18 = &i2c_riser2;
+ i2c19 = &i2c_pcie4;
+ i2c20 = &i2c_riser1;
+ i2c21 = &i2c_ocp;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x00100000>; /* 1M */
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+ <&adc 8>, <&adc 9>, <&adc 10>,
+ <&adc 12>, <&adc 13>, <&adc 14>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&uart2 {
+ /* Rear RS-232 connector */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default
+ &pinctrl_rxd2_default
+ &pinctrl_nrts2_default
+ &pinctrl_ndtr2_default
+ &pinctrl_ndsr2_default
+ &pinctrl_ncts2_default
+ &pinctrl_ndcd2_default
+ &pinctrl_nri2_default>;
+};
+
+&uart3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default
+ &pinctrl_rxd3_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&ibt {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&adc {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default
+ &pinctrl_adc1_default
+ &pinctrl_adc2_default
+ &pinctrl_adc3_default
+ &pinctrl_adc4_default
+ &pinctrl_adc5_default
+ &pinctrl_adc6_default
+ &pinctrl_adc7_default
+ &pinctrl_adc8_default
+ &pinctrl_adc9_default
+ &pinctrl_adc10_default
+ &pinctrl_adc12_default
+ &pinctrl_adc13_default
+ &pinctrl_adc14_default>;
+};
+
+&i2c0 {
+ status = "okay";
+ /* temp1 inlet */
+ tmp75@4e {
+ compatible = "national,lm75";
+ reg = <0x4e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ /* temp2 outlet */
+ tmp75@4d {
+ compatible = "national,lm75";
+ reg = <0x4d>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux@70 next. */
+
+ i2c_rbp: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_fbp1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_fbp2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_fbp3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* Slot 0,
+ * Slot 1,
+ * Slot 2,
+ * Slot 3
+ */
+ i2c-switch@76 {
+ compatible = "nxp,pca9546";
+ reg = <0x76>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect; /* may use mux@76 next. */
+
+ i2c_riser2: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c_pcie4: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_riser1: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c_ocp: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ eeprom@57 {
+ compatible = "atmel,24c256";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan@2 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan@4 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan@5 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan@6 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan@7 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+
+ fan@8 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan@9 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+
+ fan@10 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
+ };
+
+ fan@11 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
+ };
+
+ fan@12 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
+ };
+
+ fan@13 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
+ };
+};
+
+&gpio {
+
+ pin_gpio_b5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "IRQ_BMC_PCH_SMI_LPC_N";
+ };
+
+ pin_gpio_f0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "IRQ_BMC_PCH_NMI_R";
+ };
+
+ pin_gpio_f3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS0_RST_OUT_N";
+ };
+
+ pin_gpio_f4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT0_FAULT_LED";
+ };
+
+ pin_gpio_f5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "FM_SKT1_FAULT_LED";
+ };
+
+ pin_gpio_g4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FAN_PWR_CTL_N";
+ };
+
+ pin_gpio_g7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_PCIE_I2CMUX_N";
+ };
+
+ pin_gpio_h2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU1_FFS_N_R";
+ };
+
+ pin_gpio_h3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PSU2_FFS_N_R";
+ };
+
+ pin_gpio_i3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_INTRUDED_COVER";
+ };
+
+ pin_gpio_j2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_BIOS_UPDATE_N";
+ };
+
+ pin_gpio_j3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "RST_BMC_HDD_I2CMUX_N";
+ };
+
+ pin_gpio_s2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "BMC_VGA_SW";
+ };
+
+ pin_gpio_s4 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
+ output;
+ line-name = "VBAT_EN_N";
+ };
+
+ pin_gpio_s6 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PU_BMC_GPIOS6";
+ };
+
+ pin_gpio_y0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S0";
+ };
+
+ pin_gpio_y1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Y, 1) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_NCSI_MUX_CTL_S1";
+ };
+
+ pin_gpio_z0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 0) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_INT_N";
+ };
+
+ pin_gpio_z2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_RISER2_RESET_N";
+ };
+
+ pin_gpio_z3 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "FM_BMC_PCH_SCI_LPC_N";
+ };
+
+ pin_gpio_z7 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(Z, 7) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "BMC_POST_CMPLT_N";
+ };
+
+ pin_gpio_aa0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "HOST_BMC_USB_SEL";
+ };
+
+ pin_gpio_aa5 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "I2C_BUS1_RST_OUT_N";
+ };
+
+};
diff --git a/dts/src/arm/aspeed-bmc-microsoft-olympus.dts b/dts/src/arm/aspeed-bmc-microsoft-olympus.dts
new file mode 100644
index 0000000..7331991
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-microsoft-olympus.dts
@@ -0,0 +1,207 @@
+//SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+#include "aspeed-g4.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Olympus BMC";
+ compatible = "microsoft,olympus-bmc", "aspeed,ast2400";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory@40000000 {
+ reg = <0x40000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vga_memory: framebuffer@5f000000 {
+ no-map;
+ reg = <0x5f000000 0x01000000>; /* 16M */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ bmc_heartbeat {
+ gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ power_green {
+ gpios = <&gpio ASPEED_GPIO(U, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ power_amber {
+ gpios = <&gpio ASPEED_GPIO(U, 3) GPIO_ACTIVE_HIGH>;
+ };
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+ };
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+ <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>;
+ };
+};
+
+&adc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default
+ &pinctrl_adc1_default
+ &pinctrl_adc2_default
+ &pinctrl_adc3_default
+ &pinctrl_adc4_default
+ &pinctrl_adc5_default
+ &pinctrl_adc6_default
+ &pinctrl_adc7_default>;
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ tmp421@4c {
+ compatible = "ti,tmp421";
+ reg = <0x4c>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+
+ tmp421@4c {
+ compatible = "ti,tmp421";
+ reg = <0x4c>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&wdt2 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan@2 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan@4 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan@5 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+};
diff --git a/dts/src/arm/aspeed-bmc-opp-lanyang.dts b/dts/src/arm/aspeed-bmc-opp-lanyang.dts
index 024e52a..de95112 100644
--- a/dts/src/arm/aspeed-bmc-opp-lanyang.dts
+++ b/dts/src/arm/aspeed-bmc-opp-lanyang.dts
@@ -322,3 +322,5 @@
&adc {
status = "okay";
};
+
+#include "ibm-power9-dual.dtsi"
diff --git a/dts/src/arm/aspeed-bmc-opp-palmetto.dts b/dts/src/arm/aspeed-bmc-opp-palmetto.dts
index b249da8..b0cb34c 100644
--- a/dts/src/arm/aspeed-bmc-opp-palmetto.dts
+++ b/dts/src/arm/aspeed-bmc-opp-palmetto.dts
@@ -347,3 +347,25 @@
line-name = "BMC_TPM_INT_N";
};
};
+
+&fsi {
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <0>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ fsi_hub0: hub@3400 {
+ compatible = "ibm,fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ no-scan-on-init;
+ };
+ };
+};
diff --git a/dts/src/arm/aspeed-bmc-opp-romulus.dts b/dts/src/arm/aspeed-bmc-opp-romulus.dts
index 418a198..9628ecb 100644
--- a/dts/src/arm/aspeed-bmc-opp-romulus.dts
+++ b/dts/src/arm/aspeed-bmc-opp-romulus.dts
@@ -42,6 +42,13 @@
compatible = "shared-dma-pool";
reusable;
};
+
+ video_engine_memory: jpegbuffer {
+ size = <0x02000000>; /* 32M */
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
};
leds {
@@ -304,3 +311,10 @@
&adc {
status = "okay";
};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+#include "ibm-power9-dual.dtsi"
diff --git a/dts/src/arm/aspeed-bmc-opp-swift.dts b/dts/src/arm/aspeed-bmc-opp-swift.dts
new file mode 100644
index 0000000..caac895
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-opp-swift.dts
@@ -0,0 +1,966 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/leds/leds-pca955x.h>
+
+/ {
+ model = "Swift BMC";
+ compatible = "ibm,swift-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ air-water {
+ label = "air-water";
+ gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(B, 5)>;
+ };
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(J, 2)>;
+ };
+
+ ps0-presence {
+ label = "ps0-presence";
+ gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(R, 7)>;
+ };
+
+ ps1-presence {
+ label = "ps1-presence";
+ gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(N, 0)>;
+ };
+
+ oppanel-presence {
+ label = "oppanel-presence";
+ gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(A, 7)>;
+ };
+
+ opencapi-riser-presence {
+ label = "opencapi-riser-presence";
+ gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(I, 0)>;
+ };
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 12>;
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <1000>;
+
+ scm0-presence {
+ label = "scm0-presence";
+ gpios = <&pca9552 6 GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ scm1-presence {
+ label = "scm1-presence";
+ gpios = <&pca9552 7 GPIO_ACTIVE_LOW>;
+ linux,code = <7>;
+ };
+
+ cpu0vrm-presence {
+ label = "cpu0vrm-presence";
+ gpios = <&pca9552 12 GPIO_ACTIVE_LOW>;
+ linux,code = <12>;
+ };
+
+ cpu1vrm-presence {
+ label = "cpu1vrm-presence";
+ gpios = <&pca9552 13 GPIO_ACTIVE_LOW>;
+ linux,code = <13>;
+ };
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
+ linux,code = <5>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ fan2-presence {
+ label = "fan2-presence";
+ gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
+ linux,code = <7>;
+ };
+
+ fan3-presence {
+ label = "fan3-presence";
+ gpios = <&pca0 8 GPIO_ACTIVE_LOW>;
+ linux,code = <8>;
+ };
+
+ fanboost-presence {
+ label = "fanboost-presence";
+ gpios = <&pca0 9 GPIO_ACTIVE_LOW>;
+ linux,code = <9>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ fan0 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ fan1 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
+ };
+
+ fan2 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 2 GPIO_ACTIVE_LOW>;
+ };
+
+ fan3 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 3 GPIO_ACTIVE_LOW>;
+ };
+
+ fanboost {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
+ };
+
+ front-fault {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ front-power {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca1 3 GPIO_ACTIVE_LOW>;
+ };
+
+ front-id {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca1 0 GPIO_ACTIVE_LOW>;
+ };
+
+ rear-fault {
+ gpios = <&gpio ASPEED_GPIO(N, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ rear-id {
+ gpios = <&gpio ASPEED_GPIO(N, 4) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ no-gpio-delays;
+
+ clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
+ };
+
+ iio-hwmon-dps310 {
+ compatible = "iio-hwmon";
+ io-channels = <&dps 0>;
+ };
+
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+ spi-max-frequency = <100000000>;
+ partitions {
+ #address-cells = < 1 >;
+ #size-cells = < 1 >;
+ compatible = "fixed-partitions";
+ u-boot@0 {
+ reg = < 0 0x60000 >;
+ label = "u-boot";
+ };
+ u-boot-env@60000 {
+ reg = < 0x60000 0x20000 >;
+ label = "u-boot-env";
+ };
+ obmc-ubi@80000 {
+ reg = < 0x80000 0x7F80000>;
+ label = "obmc-ubi";
+ };
+ };
+ };
+
+ flash@1 {
+ status = "okay";
+ label = "alt-bmc";
+ m25p,fast-read;
+ spi-max-frequency = <100000000>;
+ partitions {
+ #address-cells = < 1 >;
+ #size-cells = < 1 >;
+ compatible = "fixed-partitions";
+ u-boot@0 {
+ reg = < 0 0x60000 >;
+ label = "alt-u-boot";
+ };
+ u-boot-env@60000 {
+ reg = < 0x60000 0x20000 >;
+ label = "alt-u-boot-env";
+ };
+ obmc-ubi@80000 {
+ reg = < 0x80000 0x7F80000>;
+ label = "alt-obmc-ubi";
+ };
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&uart1 {
+ /* Rear RS-232 connector */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
+&uart2 {
+ /* APSS */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* MUX ->
+ * Samtec 1
+ * Samtec 2
+ */
+};
+
+&i2c3 {
+ status = "okay";
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan@0 {
+ compatible = "pmbus-fan";
+ reg = <0>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@1 {
+ compatible = "pmbus-fan";
+ reg = <1>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@2 {
+ compatible = "pmbus-fan";
+ reg = <2>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@3 {
+ compatible = "pmbus-fan";
+ reg = <3>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@4 {
+ compatible = "pmbus-fan";
+ reg = <4>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+ };
+
+ pca0: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps1";
+ reg = <0x69>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ si7021a20@20 {
+ compatible = "si,si7021a20";
+ reg = <0x20>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ pca1: pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
+ "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
+ "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
+ "P9_SCM0_PRES", "P9_SCM1_PRES",
+ "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
+ "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
+ "PRESENT_VRM_CP0_N", "PRESENT_VRM_CP1_N",
+ "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+
+ ir35221@72 {
+ compatible = "infineon,ir35221";
+ reg = <0x72>;
+ };
+
+ pca2: pca9539@74 {
+ compatible = "nxp,pca9539";
+ reg = <0x74>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ };
+ };
+};
+
+&i2c10 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+
+ ir35221@72 {
+ compatible = "infineon,ir35221";
+ reg = <0x72>;
+ };
+
+ pca3: pca9539@74 {
+ compatible = "nxp,pca9539";
+ reg = <0x74>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ };
+ };
+};
+
+&i2c11 {
+ /* MUX
+ * -> PCIe Slot 0
+ * -> PCIe Slot 1
+ * -> PCIe Slot 2
+ * -> PCIe Slot 3
+ */
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&wdt1 {
+ aspeed,reset-type = "none";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+};
+
+&wdt2 {
+ aspeed,alt-boot;
+};
+
+&ibt {
+ status = "okay";
+};
+
+&adc {
+ status = "okay";
+};
+
+#include "ibm-power9-dual.dtsi"
diff --git a/dts/src/arm/aspeed-bmc-opp-vesnin.dts b/dts/src/arm/aspeed-bmc-opp-vesnin.dts
new file mode 100644
index 0000000..0b9e29c
--- /dev/null
+++ b/dts/src/arm/aspeed-bmc-opp-vesnin.dts
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2019 YADRO
+/dts-v1/;
+
+#include "aspeed-g4.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Vesnin BMC";
+ compatible = "yadro,vesnin-bmc", "aspeed,ast2400";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory {
+ reg = <0x40000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vga_memory: framebuffer@5f000000 {
+ no-map;
+ reg = <0x5f000000 0x01000000>; /* 16MB */
+ };
+ flash_memory: region@5c000000 {
+ no-map;
+ reg = <0x5c000000 0x02000000>; /* 32M */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>;
+ };
+ power_red {
+ gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ id_blue {
+ gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ alarm_red {
+ gpios = <&gpio ASPEED_GPIO(N, 6) GPIO_ACTIVE_LOW>;
+ };
+
+ alarm_yel {
+ gpios = <&gpio ASPEED_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button_checkstop {
+ label = "checkstop";
+ linux,code = <74>;
+ gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>;
+ };
+
+ button_identify {
+ label = "identify";
+ linux,code = <152>;
+ gpios = <&gpio ASPEED_GPIO(O, 7) GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1debug_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+ };
+};
+
+&mac0 {
+ status = "okay";
+
+ use-ncsi;
+ no-hw-checksum;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+};
+
+
+&uart5 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
+};
+
+&ibt {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ tmp75@49 {
+ compatible = "ti,tmp75";
+ reg = <0x49>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+
+ occ-hwmon@50 {
+ compatible = "ibm,p8-occ-hwmon";
+ reg = <0x50>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ occ-hwmon@51 {
+ compatible = "ibm,p8-occ-hwmon";
+ reg = <0x51>;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ w83795g@2f {
+ compatible = "nuvoton,w83795g";
+ reg = <0x2f>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ occ-hwmon@56 {
+ compatible = "ibm,p8-occ-hwmon";
+ reg = <0x56>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ occ-hwmon@57 {
+ compatible = "ibm,p8-occ-hwmon";
+ reg = <0x57>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+
+ rtc@68 {
+ compatible = "maxim,ds3231";
+ reg = <0x68>;
+ };
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&vuart {
+ status = "okay";
+};
diff --git a/dts/src/arm/aspeed-bmc-opp-witherspoon.dts b/dts/src/arm/aspeed-bmc-opp-witherspoon.dts
index f1356ca..31ea34e 100644
--- a/dts/src/arm/aspeed-bmc-opp-witherspoon.dts
+++ b/dts/src/arm/aspeed-bmc-opp-witherspoon.dts
@@ -33,6 +33,13 @@
compatible = "shared-dma-pool";
reusable;
};
+
+ video_engine_memory: jpegbuffer {
+ size = <0x02000000>; /* 32MM */
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
};
gpio-keys {
@@ -640,3 +647,10 @@
&vhub {
status = "okay";
};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+#include "ibm-power9-dual.dtsi"
diff --git a/dts/src/arm/aspeed-bmc-opp-zaius.dts b/dts/src/arm/aspeed-bmc-opp-zaius.dts
index 2c5aa90..3062437 100644
--- a/dts/src/arm/aspeed-bmc-opp-zaius.dts
+++ b/dts/src/arm/aspeed-bmc-opp-zaius.dts
@@ -7,6 +7,14 @@
model = "Zaius BMC";
compatible = "ingrasys,zaius-bmc", "aspeed,ast2500";
+ aliases {
+ i2c15 = &i2cpcie0;
+ i2c16 = &i2cpcie1;
+ i2c17 = &i2cpcie2;
+ i2c19 = &i2cpcie3;
+ i2c20 = &i2cpcie4;
+ };
+
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
@@ -223,6 +231,27 @@
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
+
+ i2cpcie0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ i2cpcie1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ i2cpcie2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ i2ctpm: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
};
/* MUX1 PCA9546A @71h
@@ -253,6 +282,17 @@
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
+
+ i2cpcie3: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ i2cpcie4: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
};
/* MUX1 PCA9546A @71h
@@ -296,33 +336,98 @@
reg = <0x54>;
};
};
+
+ };
+
+ vrm@64 {
+ compatible = "isil,isl68137";
+ reg = <0x64>;
+ };
+
+ vrm@40 {
+ compatible = "isil,isl68137";
+ reg = <0x40>;
+ };
+
+ vrm@60 {
+ compatible = "isil,isl68137";
+ reg = <0x60>;
+ };
+
+ vrm@43 {
+ compatible = "infineon,ir38064";
+ reg = <0x43>;
+ };
+
+ vrm@41 {
+ compatible = "isil,isl68137";
+ reg = <0x41>;
};
/* Master selector PCA9541A @70h (other master: CPU0)
* LM5066I PMBUS @10h
*/
- /* 12V Quarter Brick DC/DC Converter Q54SJ12050 @61h */
- power-brick@61 {
+ /*
+ * Brick will be one of these types/addresses. Depending
+ * on the board SKU only one is actually present and will successfully
+ * instantiate while the others will fail the probe operation.
+ * These are the PVT (and presumably beyond) addresses:
+ * 12V Quarter Brick DC/DC Converter Q54SJ12050 @6Ah
+ * 12V Quarter Brick DC/DC Converter Q54SH12050 @30h
+ */
+ power-brick@6a {
+ compatible = "delta,dps800";
+ reg = <0x6a>;
+ };
+ power-brick@30 {
compatible = "delta,dps800";
- reg = <0x61>;
+ reg = <0x30>;
};
/* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */
/* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */
/* CPU0 VR ISL68137 0.8V PMBUS @60h */
- /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */
+ /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */
/* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */
+ /* Master selector PCA9541A @70h (other master: CPU0)
+ * LM5066I PMBUS @10h
+ */
};
&i2c8 {
status = "okay";
- /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */
- /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */
- /* CPU1 VR ISL68137 0.8V PMBUS @61h */
+ vrm@64 {
+ compatible = "isil,isl68137";
+ reg = <0x64>;
+ };
+
+ vrm@40 {
+ compatible = "isil,isl68137";
+ reg = <0x40>;
+ };
+
+ vrm@41 {
+ compatible = "isil,isl68137";
+ reg = <0x41>;
+ };
+
+ vrm@42 {
+ compatible = "infineon,ir38064";
+ reg = <0x42>;
+ };
+
+ vrm@60 {
+ compatible = "isil,isl68137";
+ reg = <0x60>;
+ };
+
+ /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */
+ /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */
+ /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */
/* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */
- /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */
+ /* CPU1 VR ISL68137 0.8V PMBUS @60h */
};
@@ -435,3 +540,5 @@
&ibt {
status = "okay";
};
+
+#include "ibm-power9-dual.dtsi"
diff --git a/dts/src/arm/aspeed-bmc-quanta-q71l.dts b/dts/src/arm/aspeed-bmc-quanta-q71l.dts
index 0d7c633..a68ff06 100644
--- a/dts/src/arm/aspeed-bmc-quanta-q71l.dts
+++ b/dts/src/arm/aspeed-bmc-quanta-q71l.dts
@@ -112,6 +112,11 @@
&pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
};
+&p2a {
+ status = "okay";
+ memory-region = <&vga_memory>;
+};
+
&ibt {
status = "okay";
};
diff --git a/dts/src/arm/aspeed-g4.dtsi b/dts/src/arm/aspeed-g4.dtsi
index 5d7050d..dd4b0b1 100644
--- a/dts/src/arm/aspeed-g4.dtsi
+++ b/dts/src/arm/aspeed-g4.dtsi
@@ -53,7 +53,7 @@
#size-cells = <1>;
ranges;
- fmc: flash-controller@1e620000 {
+ fmc: spi@1e620000 {
reg = < 0x1e620000 0x94
0x20000000 0x10000000 >;
#address-cells = <1>;
@@ -69,7 +69,7 @@
};
};
- spi: flash-controller@1e630000 {
+ spi: spi@1e630000 {
reg = < 0x1e630000 0x18
0x30000000 0x10000000 >;
#address-cells = <1>;
@@ -165,6 +165,10 @@
compatible = "aspeed,g4-pinctrl";
};
+ p2a: p2a-control {
+ compatible = "aspeed,ast2400-p2a-ctrl";
+ status = "disabled";
+ };
};
rng: hwrng@1e6e2078 {
diff --git a/dts/src/arm/aspeed-g5.dtsi b/dts/src/arm/aspeed-g5.dtsi
index 4345c31..5b1ca26 100644
--- a/dts/src/arm/aspeed-g5.dtsi
+++ b/dts/src/arm/aspeed-g5.dtsi
@@ -60,7 +60,7 @@
#size-cells = <1>;
ranges;
- fmc: flash-controller@1e620000 {
+ fmc: spi@1e620000 {
reg = < 0x1e620000 0xc4
0x20000000 0x10000000 >;
#address-cells = <1>;
@@ -86,7 +86,7 @@
};
};
- spi1: flash-controller@1e630000 {
+ spi1: spi@1e630000 {
reg = < 0x1e630000 0xc4
0x30000000 0x08000000 >;
#address-cells = <1>;
@@ -106,7 +106,7 @@
};
};
- spi2: flash-controller@1e631000 {
+ spi2: spi@1e631000 {
reg = < 0x1e631000 0xc4
0x38000000 0x08000000 >;
#address-cells = <1>;
@@ -219,6 +219,11 @@
aspeed,external-nodes = <&gfx &lhc>;
};
+
+ p2a: p2a-control {
+ compatible = "aspeed,ast2500-p2a-ctrl";
+ status = "disabled";
+ };
};
rng: hwrng@1e6e2078 {
diff --git a/dts/src/arm/at91-wb50n.dtsi b/dts/src/arm/at91-wb50n.dtsi
index 85692c8..4ed8500 100644
--- a/dts/src/arm/at91-wb50n.dtsi
+++ b/dts/src/arm/at91-wb50n.dtsi
@@ -42,7 +42,7 @@
clock-frequency = <12000000>;
};
-&slow_osc {
+&clk32k {
atmel,osc-bypass;
};
diff --git a/dts/src/arm/at91sam9261ek.dts b/dts/src/arm/at91sam9261ek.dts
index 1fa84d2..7debdea 100644
--- a/dts/src/arm/at91sam9261ek.dts
+++ b/dts/src/arm/at91sam9261ek.dts
@@ -14,14 +14,6 @@
chosen {
bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw";
stdout-path = "serial0:115200n8";
-
- clocksource {
- timer = <&timer0>;
- };
-
- clockevent {
- timer = <&timer1>;
- };
};
memory {
diff --git a/dts/src/arm/at91sam9g45.dtsi b/dts/src/arm/at91sam9g45.dtsi
index 9483609..691c95e 100644
--- a/dts/src/arm/at91sam9g45.dtsi
+++ b/dts/src/arm/at91sam9g45.dtsi
@@ -1258,30 +1258,11 @@
};
};
- sckc@fffffd50 {
+ clk32k: sckc@fffffd50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffd50 0x4>;
-
- slow_osc: slow_osc {
- compatible = "atmel,at91sam9x5-clk-slow-osc";
- #clock-cells = <0>;
- atmel,startup-time-usec = <1200000>;
- clocks = <&slow_xtal>;
- };
-
- slow_rc_osc: slow_rc_osc {
- compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
- #clock-cells = <0>;
- atmel,startup-time-usec = <75>;
- clock-frequency = <32768>;
- clock-accuracy = <50000000>;
- };
-
- clk32k: slck {
- compatible = "atmel,at91sam9x5-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc &slow_osc>;
- };
+ clocks = <&slow_xtal>;
+ #clock-cells = <0>;
};
rtc@fffffd20 {
diff --git a/dts/src/arm/at91sam9rl.dtsi b/dts/src/arm/at91sam9rl.dtsi
index e2d38ce..8643b71 100644
--- a/dts/src/arm/at91sam9rl.dtsi
+++ b/dts/src/arm/at91sam9rl.dtsi
@@ -868,30 +868,11 @@
status = "disabled";
};
- sckc@fffffd50 {
+ clk32k: sckc@fffffd50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffd50 0x4>;
-
- slow_osc: slow_osc {
- compatible = "atmel,at91sam9x5-clk-slow-osc";
- #clock-cells = <0>;
- atmel,startup-time-usec = <1200000>;
- clocks = <&slow_xtal>;
- };
-
- slow_rc_osc: slow_rc_osc {
- compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
- #clock-cells = <0>;
- atmel,startup-time-usec = <75>;
- clock-frequency = <32768>;
- clock-accuracy = <50000000>;
- };
-
- clk32k: slck {
- compatible = "atmel,at91sam9x5-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc &slow_osc>;
- };
+ clocks = <&slow_xtal>;
+ #clock-cells = <0>;
};
rtc@fffffd20 {
diff --git a/dts/src/arm/at91sam9x5.dtsi b/dts/src/arm/at91sam9x5.dtsi
index 9b7ce6b..ef47c00 100644
--- a/dts/src/arm/at91sam9x5.dtsi
+++ b/dts/src/arm/at91sam9x5.dtsi
@@ -149,28 +149,11 @@
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
- sckc@fffffe50 {
+ clk32k: sckc@fffffe50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffe50 0x4>;
-
- slow_osc: slow_osc {
- compatible = "atmel,at91sam9x5-clk-slow-osc";
- #clock-cells = <0>;
- clocks = <&slow_xtal>;
- };
-
- slow_rc_osc: slow_rc_osc {
- compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-accuracy = <50000000>;
- };
-
- clk32k: slck {
- compatible = "atmel,at91sam9x5-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc>, <&slow_osc>;
- };
+ clocks = <&slow_xtal>;
+ #clock-cells = <0>;
};
tcb0: timer@f8008000 {
diff --git a/dts/src/arm/bcm-cygnus-clock.dtsi b/dts/src/arm/bcm-cygnus-clock.dtsi
index 80b6ba4..52f91a1 100644
--- a/dts/src/arm/bcm-cygnus-clock.dtsi
+++ b/dts/src/arm/bcm-cygnus-clock.dtsi
@@ -42,7 +42,7 @@ clocks {
};
/* Cygnus ARM PLL */
- armpll: armpll {
+ armpll: armpll@19000000 {
#clock-cells = <0>;
compatible = "brcm,cygnus-armpll";
clocks = <&osc>;
@@ -67,7 +67,7 @@ clocks {
clock-mult = <1>;
};
- genpll: genpll {
+ genpll: genpll@301d000 {
#clock-cells = <1>;
compatible = "brcm,cygnus-genpll";
reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
@@ -94,7 +94,7 @@ clocks {
clock-mult = <1>;
};
- lcpll0: lcpll0 {
+ lcpll0: lcpll0@301d02c {
#clock-cells = <1>;
compatible = "brcm,cygnus-lcpll0";
reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
@@ -103,7 +103,7 @@ clocks {
"usb_phy", "smart_card", "ch5";
};
- mipipll: mipipll {
+ mipipll: mipipll@180a9800 {
#clock-cells = <1>;
compatible = "brcm,cygnus-mipipll";
reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
@@ -113,7 +113,7 @@ clocks {
"ch5_unused";
};
- asiu_clks: asiu_clks {
+ asiu_clks: asiu_clks@301d048 {
#clock-cells = <1>;
compatible = "brcm,cygnus-asiu-clk";
reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
@@ -122,7 +122,7 @@ clocks {
clock-output-names = "keypad", "adc/touch", "pwm";
};
- audiopll: audiopll {
+ audiopll: audiopll@180aeb00 {
#clock-cells = <1>;
compatible = "brcm,cygnus-audiopll";
reg = <0x180aeb00 0x68>;
diff --git a/dts/src/arm/bcm-cygnus.dtsi b/dts/src/arm/bcm-cygnus.dtsi
index 5f7b465..2dac3ef 100644
--- a/dts/src/arm/bcm-cygnus.dtsi
+++ b/dts/src/arm/bcm-cygnus.dtsi
@@ -45,7 +45,7 @@
ethernet0 = &eth0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0 0>;
};
@@ -69,7 +69,7 @@
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
};
- core {
+ core@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x1000000>;
#address-cells = <1>;
@@ -91,7 +91,7 @@
<0x20100 0x100>;
};
- L2: l2-cache {
+ L2: l2-cache@22000 {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;
diff --git a/dts/src/arm/bcm-nsp.dtsi b/dts/src/arm/bcm-nsp.dtsi
index 6925b30..da6d70f 100644
--- a/dts/src/arm/bcm-nsp.dtsi
+++ b/dts/src/arm/bcm-nsp.dtsi
@@ -77,7 +77,7 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
- mpcore {
+ mpcore@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
@@ -122,7 +122,7 @@
<0x20100 0x100>;
};
- L2: l2-cache {
+ L2: l2-cache@22000 {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;
@@ -166,7 +166,7 @@
};
};
- axi {
+ axi@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x0011c40c>;
#address-cells = <1>;
@@ -415,9 +415,6 @@
"imp_sleep_timer_p5",
"imp_sleep_timer_p7",
"imp_sleep_timer_p8";
- #address-cells = <1>;
- #size-cells = <0>;
-
status = "disabled";
/* ports are defined in board DTS */
diff --git a/dts/src/arm/bcm11351.dtsi b/dts/src/arm/bcm11351.dtsi
index b99c2e5..6197e7d 100644
--- a/dts/src/arm/bcm11351.dtsi
+++ b/dts/src/arm/bcm11351.dtsi
@@ -100,7 +100,7 @@
reg-io-width = <4>;
};
- L2: l2-cache {
+ L2: l2-cache@3ff20000 {
compatible = "brcm,bcm11351-a2-pl310-cache";
reg = <0x3ff20000 0x1000>;
cache-unified;
@@ -225,21 +225,21 @@
#size-cells = <1>;
ranges;
- root_ccu: root_ccu {
+ root_ccu: root_ccu@35001000 {
compatible = "brcm,bcm11351-root-ccu";
reg = <0x35001000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "frac_1m";
};
- hub_ccu: hub_ccu {
+ hub_ccu: hub_ccu@34000000 {
compatible = "brcm,bcm11351-hub-ccu";
reg = <0x34000000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "tmon_1m";
};
- aon_ccu: aon_ccu {
+ aon_ccu: aon_ccu@35002000 {
compatible = "brcm,bcm11351-aon-ccu";
reg = <0x35002000 0x0f00>;
#clock-cells = <1>;
@@ -248,7 +248,7 @@
"pmu_bsc_var";
};
- master_ccu: master_ccu {
+ master_ccu: master_ccu@3f001000 {
compatible = "brcm,bcm11351-master-ccu";
reg = <0x3f001000 0x0f00>;
#clock-cells = <1>;
@@ -261,7 +261,7 @@
"hsic2_12m";
};
- slave_ccu: slave_ccu {
+ slave_ccu: slave_ccu@3e011000 {
compatible = "brcm,bcm11351-slave-ccu";
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
diff --git a/dts/src/arm/bcm21664-garnet.dts b/dts/src/arm/bcm21664-garnet.dts
index 8b045cf..be468f4 100644
--- a/dts/src/arm/bcm21664-garnet.dts
+++ b/dts/src/arm/bcm21664-garnet.dts
@@ -21,7 +21,7 @@
model = "BCM21664 Garnet board";
compatible = "brcm,bcm21664-garnet", "brcm,bcm21664";
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
diff --git a/dts/src/arm/bcm21664.dtsi b/dts/src/arm/bcm21664.dtsi
index 758daa3..3cf66fa 100644
--- a/dts/src/arm/bcm21664.dtsi
+++ b/dts/src/arm/bcm21664.dtsi
@@ -90,7 +90,7 @@
reg-io-width = <4>;
};
- L2: l2-cache {
+ L2: l2-cache@3ff20000 {
compatible = "arm,pl310-cache";
reg = <0x3ff20000 0x1000>;
cache-unified;
@@ -295,21 +295,21 @@
clock-frequency = <156000000>;
};
- root_ccu: root_ccu {
+ root_ccu: root_ccu@35001000 {
compatible = BCM21664_DT_ROOT_CCU_COMPAT;
reg = <0x35001000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "frac_1m";
};
- aon_ccu: aon_ccu {
+ aon_ccu: aon_ccu@35002000 {
compatible = BCM21664_DT_AON_CCU_COMPAT;
reg = <0x35002000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "hub_timer";
};
- master_ccu: master_ccu {
+ master_ccu: master_ccu@3f001000 {
compatible = BCM21664_DT_MASTER_CCU_COMPAT;
reg = <0x3f001000 0x0f00>;
#clock-cells = <1>;
@@ -323,7 +323,7 @@
"sdio4_sleep";
};
- slave_ccu: slave_ccu {
+ slave_ccu: slave_ccu@3e011000 {
compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
diff --git a/dts/src/arm/bcm23550-sparrow.dts b/dts/src/arm/bcm23550-sparrow.dts
index 1c66b15..ace7770 100644
--- a/dts/src/arm/bcm23550-sparrow.dts
+++ b/dts/src/arm/bcm23550-sparrow.dts
@@ -45,7 +45,7 @@
bootargs = "console=ttyS0,115200n8";
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
diff --git a/dts/src/arm/bcm23550.dtsi b/dts/src/arm/bcm23550.dtsi
index 701198f..a36c9b1 100644
--- a/dts/src/arm/bcm23550.dtsi
+++ b/dts/src/arm/bcm23550.dtsi
@@ -371,21 +371,21 @@
clock-frequency = <156000000>;
};
- root_ccu: root_ccu {
+ root_ccu: root_ccu@35001000 {
compatible = BCM21664_DT_ROOT_CCU_COMPAT;
reg = <0x35001000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "frac_1m";
};
- aon_ccu: aon_ccu {
+ aon_ccu: aon_ccu@35002000 {
compatible = BCM21664_DT_AON_CCU_COMPAT;
reg = <0x35002000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "hub_timer";
};
- slave_ccu: slave_ccu {
+ slave_ccu: slave_ccu@3e011000 {
compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
@@ -398,7 +398,7 @@
"bsc4";
};
- master_ccu: master_ccu {
+ master_ccu: master_ccu@3f001000 {
compatible = BCM21664_DT_MASTER_CCU_COMPAT;
reg = <0x3f001000 0x0f00>;
#clock-cells = <1>;
diff --git a/dts/src/arm/bcm28155-ap.dts b/dts/src/arm/bcm28155-ap.dts
index fbfca83..ead6e98 100644
--- a/dts/src/arm/bcm28155-ap.dts
+++ b/dts/src/arm/bcm28155-ap.dts
@@ -21,7 +21,7 @@
model = "BCM28155 AP board";
compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
diff --git a/dts/src/arm/bcm283x.dtsi b/dts/src/arm/bcm283x.dtsi
index 9777644..4b21ddb 100644
--- a/dts/src/arm/bcm283x.dtsi
+++ b/dts/src/arm/bcm283x.dtsi
@@ -431,6 +431,8 @@
reg = <0x7e204000 0x1000>;
interrupts = <2 22>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
+ dmas = <&dma 6>, <&dma 7>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
diff --git a/dts/src/arm/bcm4708-asus-rt-ac56u.dts b/dts/src/arm/bcm4708-asus-rt-ac56u.dts
index 1c6f561..6a96655 100644
--- a/dts/src/arm/bcm4708-asus-rt-ac56u.dts
+++ b/dts/src/arm/bcm4708-asus-rt-ac56u.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -69,8 +69,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
rfkill {
label = "WiFi";
diff --git a/dts/src/arm/bcm4708-asus-rt-ac68u.dts b/dts/src/arm/bcm4708-asus-rt-ac68u.dts
index e550799..3b0029e 100644
--- a/dts/src/arm/bcm4708-asus-rt-ac68u.dts
+++ b/dts/src/arm/bcm4708-asus-rt-ac68u.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -53,8 +53,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
brightness {
label = "Backlight";
diff --git a/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts b/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts
index 7bfa223..90f57ba 100644
--- a/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
@@ -99,8 +99,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm4708-linksys-ea6300-v1.dts b/dts/src/arm/bcm4708-linksys-ea6300-v1.dts
index fd361c9..41548d6 100644
--- a/dts/src/arm/bcm4708-linksys-ea6300-v1.dts
+++ b/dts/src/arm/bcm4708-linksys-ea6300-v1.dts
@@ -16,15 +16,13 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
wps {
label = "WPS";
diff --git a/dts/src/arm/bcm4708-linksys-ea6500-v2.dts b/dts/src/arm/bcm4708-linksys-ea6500-v2.dts
index 7c34360..cd797b4 100644
--- a/dts/src/arm/bcm4708-linksys-ea6500-v2.dts
+++ b/dts/src/arm/bcm4708-linksys-ea6500-v2.dts
@@ -17,15 +17,13 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
wps {
label = "WPS";
diff --git a/dts/src/arm/bcm4708-luxul-xap-1510.dts b/dts/src/arm/bcm4708-luxul-xap-1510.dts
index 969b8d7..e58c807 100644
--- a/dts/src/arm/bcm4708-luxul-xap-1510.dts
+++ b/dts/src/arm/bcm4708-luxul-xap-1510.dts
@@ -15,7 +15,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -44,8 +44,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm4708-luxul-xwc-1000.dts b/dts/src/arm/bcm4708-luxul-xwc-1000.dts
index b62854e..766db61 100644
--- a/dts/src/arm/bcm4708-luxul-xwc-1000.dts
+++ b/dts/src/arm/bcm4708-luxul-xwc-1000.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -51,8 +51,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm4708-netgear-r6250.dts b/dts/src/arm/bcm4708-netgear-r6250.dts
index 75f7b4e..fed75e6 100644
--- a/dts/src/arm/bcm4708-netgear-r6250.dts
+++ b/dts/src/arm/bcm4708-netgear-r6250.dts
@@ -62,8 +62,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
wps {
label = "WPS";
diff --git a/dts/src/arm/bcm4708-netgear-r6300-v2.dts b/dts/src/arm/bcm4708-netgear-r6300-v2.dts
index 148d16a..79542e1 100644
--- a/dts/src/arm/bcm4708-netgear-r6300-v2.dts
+++ b/dts/src/arm/bcm4708-netgear-r6300-v2.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -58,8 +58,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
wps {
label = "WPS";
diff --git a/dts/src/arm/bcm4708-smartrg-sr400ac.dts b/dts/src/arm/bcm4708-smartrg-sr400ac.dts
index eed3aab..abd35a5 100644
--- a/dts/src/arm/bcm4708-smartrg-sr400ac.dts
+++ b/dts/src/arm/bcm4708-smartrg-sr400ac.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -93,8 +93,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
rfkill {
label = "WiFi";
diff --git a/dts/src/arm/bcm47081-asus-rt-n18u.dts b/dts/src/arm/bcm47081-asus-rt-n18u.dts
index fe842f2..c29950b 100644
--- a/dts/src/arm/bcm47081-asus-rt-n18u.dts
+++ b/dts/src/arm/bcm47081-asus-rt-n18u.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -59,8 +59,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts b/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts
index 6fcbb05..4dcec68 100644
--- a/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -90,8 +90,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
aoss {
label = "AOSS";
diff --git a/dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts b/dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts
index b3e8cc9..0e349e3 100644
--- a/dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts
+++ b/dts/src/arm/bcm47081-buffalo-wzr-900dhp.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -95,8 +95,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47081-luxul-xap-1410.dts b/dts/src/arm/bcm47081-luxul-xap-1410.dts
index fdeaa89..b9d9501 100644
--- a/dts/src/arm/bcm47081-luxul-xap-1410.dts
+++ b/dts/src/arm/bcm47081-luxul-xap-1410.dts
@@ -15,7 +15,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -44,8 +44,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47081-luxul-xwr-1200.dts b/dts/src/arm/bcm47081-luxul-xwr-1200.dts
index 0d510cb..0052e1b 100644
--- a/dts/src/arm/bcm47081-luxul-xwr-1200.dts
+++ b/dts/src/arm/bcm47081-luxul-xwr-1200.dts
@@ -16,7 +16,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -88,8 +88,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47081-tplink-archer-c5-v2.dts b/dts/src/arm/bcm47081-tplink-archer-c5-v2.dts
index 962e89e..01c390e 100644
--- a/dts/src/arm/bcm47081-tplink-archer-c5-v2.dts
+++ b/dts/src/arm/bcm47081-tplink-archer-c5-v2.dts
@@ -15,7 +15,7 @@
bootargs = "earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -76,8 +76,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
rfkill {
label = "WiFi";
diff --git a/dts/src/arm/bcm47094-dlink-dir-885l.dts b/dts/src/arm/bcm47094-dlink-dir-885l.dts
index 658a56f..911c65f 100644
--- a/dts/src/arm/bcm47094-dlink-dir-885l.dts
+++ b/dts/src/arm/bcm47094-dlink-dir-885l.dts
@@ -19,7 +19,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -85,8 +85,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
wps {
label = "WPS";
diff --git a/dts/src/arm/bcm47094-linksys-panamera.dts b/dts/src/arm/bcm47094-linksys-panamera.dts
index 5fd47ee..18d0ae4 100644
--- a/dts/src/arm/bcm47094-linksys-panamera.dts
+++ b/dts/src/arm/bcm47094-linksys-panamera.dts
@@ -16,7 +16,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -24,8 +24,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
wps {
label = "WPS";
diff --git a/dts/src/arm/bcm47094-luxul-abr-4500.dts b/dts/src/arm/bcm47094-luxul-abr-4500.dts
index 6604be6..50f7cd0 100644
--- a/dts/src/arm/bcm47094-luxul-abr-4500.dts
+++ b/dts/src/arm/bcm47094-luxul-abr-4500.dts
@@ -16,7 +16,7 @@
bootargs = "earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
@@ -43,8 +43,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47094-luxul-xap-1610.dts b/dts/src/arm/bcm47094-luxul-xap-1610.dts
index 567ebbd..b47fb07 100644
--- a/dts/src/arm/bcm47094-luxul-xap-1610.dts
+++ b/dts/src/arm/bcm47094-luxul-xap-1610.dts
@@ -15,7 +15,7 @@
bootargs = "earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -42,8 +42,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47094-luxul-xbr-4500.dts b/dts/src/arm/bcm47094-luxul-xbr-4500.dts
index ac2d136..bcc420f 100644
--- a/dts/src/arm/bcm47094-luxul-xbr-4500.dts
+++ b/dts/src/arm/bcm47094-luxul-xbr-4500.dts
@@ -16,7 +16,7 @@
bootargs = "earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
@@ -43,8 +43,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47094-luxul-xwr-3100.dts b/dts/src/arm/bcm47094-luxul-xwr-3100.dts
index 74371e8..ac75154 100644
--- a/dts/src/arm/bcm47094-luxul-xwr-3100.dts
+++ b/dts/src/arm/bcm47094-luxul-xwr-3100.dts
@@ -16,7 +16,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x08000000>;
@@ -83,8 +83,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47094-luxul-xwr-3150-v1.dts b/dts/src/arm/bcm47094-luxul-xwr-3150-v1.dts
index b44af63..6d28b7d 100644
--- a/dts/src/arm/bcm47094-luxul-xwr-3150-v1.dts
+++ b/dts/src/arm/bcm47094-luxul-xwr-3150-v1.dts
@@ -16,7 +16,7 @@
bootargs = "earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
@@ -58,8 +58,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47094-netgear-r8500.dts b/dts/src/arm/bcm47094-netgear-r8500.dts
index eebc0d4..f42a170 100644
--- a/dts/src/arm/bcm47094-netgear-r8500.dts
+++ b/dts/src/arm/bcm47094-netgear-r8500.dts
@@ -16,7 +16,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
@@ -64,8 +64,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
brightness {
label = "Backlight";
diff --git a/dts/src/arm/bcm47094-phicomm-k3.dts b/dts/src/arm/bcm47094-phicomm-k3.dts
index 456045f..ac3a448 100644
--- a/dts/src/arm/bcm47094-phicomm-k3.dts
+++ b/dts/src/arm/bcm47094-phicomm-k3.dts
@@ -13,7 +13,7 @@
compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708";
model = "Phicomm K3";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000
0x88000000 0x18000000>;
@@ -21,8 +21,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47189-luxul-xap-1440.dts b/dts/src/arm/bcm47189-luxul-xap-1440.dts
index eb59508..57ca1cf 100644
--- a/dts/src/arm/bcm47189-luxul-xap-1440.dts
+++ b/dts/src/arm/bcm47189-luxul-xap-1440.dts
@@ -15,7 +15,7 @@
bootargs = "earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -38,8 +38,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47189-luxul-xap-810.dts b/dts/src/arm/bcm47189-luxul-xap-810.dts
index 4c71f5e..2e1a7e3 100644
--- a/dts/src/arm/bcm47189-luxul-xap-810.dts
+++ b/dts/src/arm/bcm47189-luxul-xap-810.dts
@@ -15,7 +15,7 @@
bootargs = "earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -48,8 +48,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm47189-tenda-ac9.dts b/dts/src/arm/bcm47189-tenda-ac9.dts
index 5ad53ea..049cdfd 100644
--- a/dts/src/arm/bcm47189-tenda-ac9.dts
+++ b/dts/src/arm/bcm47189-tenda-ac9.dts
@@ -15,7 +15,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -58,8 +58,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
rfkill {
label = "WiFi";
diff --git a/dts/src/arm/bcm5301x.dtsi b/dts/src/arm/bcm5301x.dtsi
index ac5266e..372dc1e 100644
--- a/dts/src/arm/bcm5301x.dtsi
+++ b/dts/src/arm/bcm5301x.dtsi
@@ -19,7 +19,7 @@
#size-cells = <1>;
interrupt-parent = <&gic>;
- chipcommonA {
+ chipcommonA@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x00001000>;
#address-cells = <1>;
@@ -44,7 +44,7 @@
};
};
- mpcore {
+ mpcore@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
@@ -148,7 +148,7 @@
};
};
- usb2_phy: usb2-phy {
+ usb2_phy: usb2-phy@1800c000 {
compatible = "brcm,ns-usb2-phy";
reg = <0x1800c000 0x1000>;
reg-names = "dmu";
@@ -357,7 +357,7 @@
#address-cells = <0>;
};
- mdio-bus-mux {
+ mdio-bus-mux@18003000 {
compatible = "mdio-mux-mmioreg";
mdio-parent-bus = <&mdio>;
#address-cells = <1>;
@@ -464,8 +464,6 @@
srab: srab@18007000 {
compatible = "brcm,bcm5301x-srab";
reg = <0x18007000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
diff --git a/dts/src/arm/bcm53573.dtsi b/dts/src/arm/bcm53573.dtsi
index b29695b..4af8e32 100644
--- a/dts/src/arm/bcm53573.dtsi
+++ b/dts/src/arm/bcm53573.dtsi
@@ -32,7 +32,7 @@
};
};
- mpcore {
+ mpcore@18310000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18310000 0x00008000>;
#address-cells = <1>;
diff --git a/dts/src/arm/bcm63138.dtsi b/dts/src/arm/bcm63138.dtsi
index e6a41e1..9c0325c 100644
--- a/dts/src/arm/bcm63138.dtsi
+++ b/dts/src/arm/bcm63138.dtsi
@@ -41,9 +41,6 @@
};
clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
/* UBUS peripheral clock */
periph_clk: periph_clk {
#clock-cells = <0>;
@@ -94,7 +91,7 @@
reg = <0x1e000 0x100>;
};
- gic: interrupt-controller@1e100 {
+ gic: interrupt-controller@1f000 {
compatible = "arm,cortex-a9-gic";
reg = <0x1f000 0x1000
0x1e100 0x100>;
@@ -125,7 +122,7 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
- armpll: armpll {
+ armpll: armpll@20000 {
#clock-cells = <0>;
compatible = "brcm,bcm63138-armpll";
clocks = <&periph_clk>;
@@ -144,7 +141,7 @@
#reset-cells = <2>;
};
- ahci: sata@8000 {
+ ahci: sata@a000 {
compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0xa000 0x9ac>, <0x8040 0x24>;
diff --git a/dts/src/arm/bcm7445-bcm97445svmb.dts b/dts/src/arm/bcm7445-bcm97445svmb.dts
index 8006c69..8313b7c 100644
--- a/dts/src/arm/bcm7445-bcm97445svmb.dts
+++ b/dts/src/arm/bcm7445-bcm97445svmb.dts
@@ -6,7 +6,7 @@
model = "Broadcom STB (bcm7445), SVMB reference board";
compatible = "brcm,bcm7445", "brcm,brcmstb";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00 0x00000000 0x00 0x40000000>,
<0x00 0x40000000 0x00 0x40000000>,
diff --git a/dts/src/arm/bcm7445.dtsi b/dts/src/arm/bcm7445.dtsi
index 504a632..58f67c9 100644
--- a/dts/src/arm/bcm7445.dtsi
+++ b/dts/src/arm/bcm7445.dtsi
@@ -63,7 +63,7 @@
<GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
};
- rdb {
+ rdb@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -224,7 +224,7 @@
};
- memory_controllers {
+ memory_controllers@f1100000 {
compatible = "simple-bus";
ranges = <0x0 0x0 0xf1100000 0x200000>;
#address-cells = <1>;
@@ -252,7 +252,7 @@
};
};
- memc@1 {
+ memc@80000 {
compatible = "brcm,brcmstb-memc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -274,7 +274,7 @@
};
};
- memc@2 {
+ memc@100000 {
compatible = "brcm,brcmstb-memc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/src/arm/bcm911360_entphn.dts b/dts/src/arm/bcm911360_entphn.dts
index 53f990d..b2d323f 100644
--- a/dts/src/arm/bcm911360_entphn.dts
+++ b/dts/src/arm/bcm911360_entphn.dts
@@ -49,8 +49,6 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
hook {
label = "HOOK";
diff --git a/dts/src/arm/bcm947189acdbmr.dts b/dts/src/arm/bcm947189acdbmr.dts
index 4991700..b0b8c77 100644
--- a/dts/src/arm/bcm947189acdbmr.dts
+++ b/dts/src/arm/bcm947189acdbmr.dts
@@ -17,7 +17,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
@@ -43,8 +43,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
restart {
label = "Reset";
diff --git a/dts/src/arm/bcm953012er.dts b/dts/src/arm/bcm953012er.dts
index 250a1d6..9574682 100644
--- a/dts/src/arm/bcm953012er.dts
+++ b/dts/src/arm/bcm953012er.dts
@@ -39,15 +39,13 @@
model = "NorthStar Enterprise Router (BCM953012ER)";
compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
wps {
label = "WPS";
diff --git a/dts/src/arm/bcm953012k.dts b/dts/src/arm/bcm953012k.dts
index 52c4c6c..046c59f 100644
--- a/dts/src/arm/bcm953012k.dts
+++ b/dts/src/arm/bcm953012k.dts
@@ -43,7 +43,7 @@
serial1 = &uart1;
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
diff --git a/dts/src/arm/bcm958522er.dts b/dts/src/arm/bcm958522er.dts
index 21479b4..8c388eb 100644
--- a/dts/src/arm/bcm958522er.dts
+++ b/dts/src/arm/bcm958522er.dts
@@ -43,7 +43,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
diff --git a/dts/src/arm/bcm958525er.dts b/dts/src/arm/bcm958525er.dts
index cda3d79..c339771 100644
--- a/dts/src/arm/bcm958525er.dts
+++ b/dts/src/arm/bcm958525er.dts
@@ -43,7 +43,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
diff --git a/dts/src/arm/bcm958525xmc.dts b/dts/src/arm/bcm958525xmc.dts
index f866498..1c72ec8 100644
--- a/dts/src/arm/bcm958525xmc.dts
+++ b/dts/src/arm/bcm958525xmc.dts
@@ -43,7 +43,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
diff --git a/dts/src/arm/bcm958622hr.dts b/dts/src/arm/bcm958622hr.dts
index df60602..96a021c 100644
--- a/dts/src/arm/bcm958622hr.dts
+++ b/dts/src/arm/bcm958622hr.dts
@@ -43,7 +43,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
diff --git a/dts/src/arm/bcm958623hr.dts b/dts/src/arm/bcm958623hr.dts
index 3893e7a..b2c7f21 100644
--- a/dts/src/arm/bcm958623hr.dts
+++ b/dts/src/arm/bcm958623hr.dts
@@ -43,7 +43,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
diff --git a/dts/src/arm/bcm958625hr.dts b/dts/src/arm/bcm958625hr.dts
index cf226b0..a2c9de3 100644
--- a/dts/src/arm/bcm958625hr.dts
+++ b/dts/src/arm/bcm958625hr.dts
@@ -43,7 +43,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x20000000>;
};
diff --git a/dts/src/arm/bcm958625k.dts b/dts/src/arm/bcm958625k.dts
index 10b3d51..3fcca12 100644
--- a/dts/src/arm/bcm958625k.dts
+++ b/dts/src/arm/bcm958625k.dts
@@ -42,7 +42,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
diff --git a/dts/src/arm/bcm963138dvt.dts b/dts/src/arm/bcm963138dvt.dts
index 2952568..5b17727 100644
--- a/dts/src/arm/bcm963138dvt.dts
+++ b/dts/src/arm/bcm963138dvt.dts
@@ -16,7 +16,7 @@
stdout-path = &serial0;
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
diff --git a/dts/src/arm/bcm988312hr.dts b/dts/src/arm/bcm988312hr.dts
index e39db14..edd0f63 100644
--- a/dts/src/arm/bcm988312hr.dts
+++ b/dts/src/arm/bcm988312hr.dts
@@ -43,7 +43,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
diff --git a/dts/src/arm/da850-evm.dts b/dts/src/arm/da850-evm.dts
index f2d2b87..5b2b1ed 100644
--- a/dts/src/arm/da850-evm.dts
+++ b/dts/src/arm/da850-evm.dts
@@ -188,6 +188,19 @@
};
};
+&cpu {
+ cpu-supply = <&vdcdc3_reg>;
+};
+
+/*
+ * The standard da850-evm kits and SOM's are 375MHz so enable this operating
+ * point by default. Higher frequencies must be enabled for custom boards with
+ * other variants of the SoC.
+ */
+&opp_375 {
+ status = "okay";
+};
+
&sata {
status = "okay";
};
diff --git a/dts/src/arm/da850-lcdk.dts b/dts/src/arm/da850-lcdk.dts
index 2fd2a68..e379d6e 100644
--- a/dts/src/arm/da850-lcdk.dts
+++ b/dts/src/arm/da850-lcdk.dts
@@ -154,12 +154,48 @@
};
};
};
+
+ cvdd: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cvdd";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&ref_clk {
clock-frequency = <24000000>;
};
+&cpu {
+ cpu-supply = <&cvdd>;
+};
+
+/*
+ * LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are
+ * valid. Unfortunately due to a problem with the DA8XX OHCI controller, we
+ * can't enable more than one OPP by default, since the controller sometimes
+ * becomes unresponsive after a transition. Fix the frequency at 456 MHz.
+ */
+
+&opp_100 {
+ status = "disabled";
+};
+
+&opp_200 {
+ status = "disabled";
+};
+
+&opp_300 {
+ status = "disabled";
+};
+
+&opp_456 {
+ status = "okay";
+};
+
&pmx_core {
status = "okay";
diff --git a/dts/src/arm/da850-lego-ev3.dts b/dts/src/arm/da850-lego-ev3.dts
index 09c3666..afd04a4 100644
--- a/dts/src/arm/da850-lego-ev3.dts
+++ b/dts/src/arm/da850-lego-ev3.dts
@@ -122,6 +122,15 @@
amp-supply = <&amp>;
};
+ cvdd: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
/*
* This is a 5V current limiting regulator that is shared by USB,
* the sensor (input) ports, the motor (output) ports and the A/DC.
@@ -201,6 +210,27 @@
clock-frequency = <24000000>;
};
+&cpu {
+ cpu-supply = <&cvdd>;
+};
+
+/* since we have a fixed regulator, we can't run at these points */
+&opp_100 {
+ status = "disabled";
+};
+
+&opp_200 {
+ status = "disabled";
+};
+
+/*
+ * The SoC is actually the 456MHz version, but because of the fixed regulator
+ * This is the fastest we can go.
+ */
+&opp_375 {
+ status = "okay";
+};
+
&pmx_core {
status = "okay";
diff --git a/dts/src/arm/da850.dtsi b/dts/src/arm/da850.dtsi
index e6e78b8..7cf31b6 100644
--- a/dts/src/arm/da850.dtsi
+++ b/dts/src/arm/da850.dtsi
@@ -16,6 +16,56 @@
reg = <0xc0000000 0x0>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu: cpu@0 {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&psc0 14>;
+ operating-points-v2 = <&opp_table>;
+ };
+ };
+
+ opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp_100: opp100-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <1000000 950000 1050000>;
+ };
+
+ opp_200: opp110-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1100000 1050000 1160000>;
+ };
+
+ opp_300: opp120-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1200000 1140000 1320000>;
+ };
+
+ /*
+ * Original silicon was 300MHz max, so higher frequencies
+ * need to be enabled on a per-board basis if the chip is
+ * capable.
+ */
+
+ opp_375: opp120-375000000 {
+ status = "disabled";
+ opp-hz = /bits/ 64 <375000000>;
+ opp-microvolt = <1200000 1140000 1320000>;
+ };
+
+ opp_456: opp130-456000000 {
+ status = "disabled";
+ opp-hz = /bits/ 64 <456000000>;
+ opp-microvolt = <1300000 1250000 1350000>;
+ };
+ };
+
arm {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/src/arm/emev2-kzm9d.dts b/dts/src/arm/emev2-kzm9d.dts
index abfff54..0a27f03 100644
--- a/dts/src/arm/emev2-kzm9d.dts
+++ b/dts/src/arm/emev2-kzm9d.dts
@@ -25,7 +25,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial1:115200n8";
};
diff --git a/dts/src/arm/exynos3250-artik5.dtsi b/dts/src/arm/exynos3250-artik5.dtsi
index ace50e1..dee35e3 100644
--- a/dts/src/arm/exynos3250-artik5.dtsi
+++ b/dts/src/arm/exynos3250-artik5.dtsi
@@ -59,6 +59,11 @@
cpu0-supply = <&buck2_reg>;
};
+&gpu {
+ mali-supply = <&buck3_reg>;
+ status = "okay";
+};
+
&i2c_0 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/exynos3250-monk.dts b/dts/src/arm/exynos3250-monk.dts
index e257655..248bd37 100644
--- a/dts/src/arm/exynos3250-monk.dts
+++ b/dts/src/arm/exynos3250-monk.dts
@@ -172,6 +172,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&buck3_reg>;
+ status = "okay";
+};
+
&hsotg {
vusb_d-supply = <&ldo15_reg>;
vusb_a-supply = <&ldo12_reg>;
diff --git a/dts/src/arm/exynos3250-rinato.dts b/dts/src/arm/exynos3250-rinato.dts
index 7479993..86c26a4 100644
--- a/dts/src/arm/exynos3250-rinato.dts
+++ b/dts/src/arm/exynos3250-rinato.dts
@@ -244,6 +244,11 @@
};
};
+&gpu {
+ mali-supply = <&buck3_reg>;
+ status = "okay";
+};
+
&i2c_0 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/exynos3250.dtsi b/dts/src/arm/exynos3250.dtsi
index 8ce3a77..5659c4a 100644
--- a/dts/src/arm/exynos3250.dtsi
+++ b/dts/src/arm/exynos3250.dtsi
@@ -462,6 +462,39 @@
status = "disabled";
};
+ gpu: gpu@13000000 {
+ compatible = "samsung,exynos4210-mali", "arm,mali-400";
+ reg = <0x13000000 0x10000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3",
+ "pmu";
+ clocks = <&cmu CLK_G3D>,
+ <&cmu CLK_SCLK_G3D>;
+ clock-names = "bus", "core";
+ power-domains = <&pd_g3d>;
+ status = "disabled";
+ /* TODO: operating points for DVFS, assigned clock as 134 MHz */
+ };
+
mfc: codec@13400000 {
compatible = "samsung,mfc-v7";
reg = <0x13400000 0x10000>;
diff --git a/dts/src/arm/exynos4.dtsi b/dts/src/arm/exynos4.dtsi
index 36ccf22..1264cc4 100644
--- a/dts/src/arm/exynos4.dtsi
+++ b/dts/src/arm/exynos4.dtsi
@@ -54,7 +54,7 @@
pmu: pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
- interrupts = <2 2>, <3 2>;
+ status = "disabled";
};
soc: soc {
@@ -415,6 +415,20 @@
};
};
+ gpu: gpu@13000000 {
+ compatible = "samsung,exynos4210-mali", "arm,mali-400";
+ reg = <0x13000000 0x10000>;
+ /*
+ * CLK_G3D is not actually bus clock but a IP-level clock.
+ * The bus clock is not described in hardware manual.
+ */
+ clocks = <&clock CLK_G3D>,
+ <&clock CLK_SCLK_G3D>;
+ clock-names = "bus", "core";
+ power-domains = <&pd_g3d>;
+ status = "disabled";
+ };
+
i2s1: i2s@13960000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13960000 0x100>;
diff --git a/dts/src/arm/exynos4210-origen.dts b/dts/src/arm/exynos4210-origen.dts
index 36b1ede..0d1e1a9 100644
--- a/dts/src/arm/exynos4210-origen.dts
+++ b/dts/src/arm/exynos4210-origen.dts
@@ -132,6 +132,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&buck3_reg>;
+ status = "okay";
+};
+
&hsotg {
vusb_d-supply = <&ldo3_reg>;
vusb_a-supply = <&ldo8_reg>;
diff --git a/dts/src/arm/exynos4210-trats.dts b/dts/src/arm/exynos4210-trats.dts
index 6882480..7c39dd1 100644
--- a/dts/src/arm/exynos4210-trats.dts
+++ b/dts/src/arm/exynos4210-trats.dts
@@ -239,6 +239,10 @@
status = "okay";
};
+&gpu {
+ status = "okay";
+};
+
&hsotg {
vusb_d-supply = <&vusb_reg>;
vusb_a-supply = <&vusbdac_reg>;
diff --git a/dts/src/arm/exynos4210-universal_c210.dts b/dts/src/arm/exynos4210-universal_c210.dts
index bf092e9..82a8b54 100644
--- a/dts/src/arm/exynos4210-universal_c210.dts
+++ b/dts/src/arm/exynos4210-universal_c210.dts
@@ -262,6 +262,11 @@
};
};
+&gpu {
+ mali-supply = <&buck2_reg>;
+ status = "okay";
+};
+
&hdmi {
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
diff --git a/dts/src/arm/exynos4210.dtsi b/dts/src/arm/exynos4210.dtsi
index b491c34..f220716 100644
--- a/dts/src/arm/exynos4210.dtsi
+++ b/dts/src/arm/exynos4210.dtsi
@@ -8,7 +8,7 @@
* www.linaro.org
*
* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
- * based board files can include this file and provide values for board specfic
+ * based board files can include this file and provide values for board specific
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
@@ -381,13 +381,13 @@
trips {
cpu_alert0: cpu-alert-0 {
- temperature = <85000>; /* millicelsius */
+ temperature = <85000>; /* millicelsius */
};
cpu_alert1: cpu-alert-1 {
- temperature = <100000>; /* millicelsius */
+ temperature = <100000>; /* millicelsius */
};
cpu_alert2: cpu-alert-2 {
- temperature = <110000>; /* millicelsius */
+ temperature = <110000>; /* millicelsius */
};
};
};
@@ -449,6 +449,43 @@
samsung,lcd-wb;
};
+&gpu {
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3";
+ operating-points-v2 = <&gpu_opp_table>;
+
+ gpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+};
+
&mdma1 {
power-domains = <&pd_lcd0>;
};
@@ -461,6 +498,12 @@
<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
};
+&pmu {
+ interrupts = <2 2>, <3 2>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ status = "okay";
+};
+
&pmu_system_controller {
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
diff --git a/dts/src/arm/exynos4412-galaxy-s3.dtsi b/dts/src/arm/exynos4412-galaxy-s3.dtsi
index 30eee59..ce87d2f 100644
--- a/dts/src/arm/exynos4412-galaxy-s3.dtsi
+++ b/dts/src/arm/exynos4412-galaxy-s3.dtsi
@@ -15,6 +15,24 @@
i2c10 = &i2c_cm36651;
};
+ aat1290 {
+ compatible = "skyworks,aat1290";
+ flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>;
+ enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default", "host", "isp";
+ pinctrl-0 = <&camera_flash_host>;
+ pinctrl-1 = <&camera_flash_host>;
+ pinctrl-2 = <&camera_flash_isp>;
+
+ flash-led {
+ label = "flash";
+ led-max-microamp = <520833>;
+ flash-max-microamp = <1012500>;
+ flash-max-timeout-us = <1940000>;
+ };
+ };
+
lcd_vdd3_reg: voltage-regulator-6 {
compatible = "regulator-fixed";
regulator-name = "LCD_VDD_2.2V";
@@ -131,6 +149,20 @@
regulator-max-microvolt = <2800000>;
};
+&pinctrl_0 {
+ camera_flash_host: camera-flash-host {
+ samsung,pins = "gpj1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-val = <0>;
+ };
+
+ camera_flash_isp: camera-flash-isp {
+ samsung,pins = "gpj1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-val = <1>;
+ };
+};
+
&s5c73m3 {
standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>; /* ISP_STANDBY */
vdda-supply = <&ldo17_reg>;
diff --git a/dts/src/arm/exynos4412-itop-scp-core.dtsi b/dts/src/arm/exynos4412-itop-scp-core.dtsi
index 0038465..462a540 100644
--- a/dts/src/arm/exynos4412-itop-scp-core.dtsi
+++ b/dts/src/arm/exynos4412-itop-scp-core.dtsi
@@ -115,6 +115,11 @@
cpu0-supply = <&buck2_reg>;
};
+&gpu {
+ mali-supply = <&buck4_reg>;
+ status = "okay";
+};
+
&hsotg {
vusb_d-supply = <&ldo15_reg>;
vusb_a-supply = <&ldo12_reg>;
diff --git a/dts/src/arm/exynos4412-midas.dtsi b/dts/src/arm/exynos4412-midas.dtsi
index 4c15cb6..83be3a7 100644
--- a/dts/src/arm/exynos4412-midas.dtsi
+++ b/dts/src/arm/exynos4412-midas.dtsi
@@ -453,6 +453,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&buck4_reg>;
+ status = "okay";
+};
+
&hdmi {
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
diff --git a/dts/src/arm/exynos4412-odroid-common.dtsi b/dts/src/arm/exynos4412-odroid-common.dtsi
index 08d3a0a..ea55f37 100644
--- a/dts/src/arm/exynos4412-odroid-common.dtsi
+++ b/dts/src/arm/exynos4412-odroid-common.dtsi
@@ -229,6 +229,11 @@
assigned-clock-rates = <0>, <176000000>;
};
+&gpu {
+ mali-supply = <&buck4_reg>;
+ status = "okay";
+};
+
&hdmi {
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
diff --git a/dts/src/arm/exynos4412-prime.dtsi b/dts/src/arm/exynos4412-prime.dtsi
index d83fbd4..3731a22 100644
--- a/dts/src/arm/exynos4412-prime.dtsi
+++ b/dts/src/arm/exynos4412-prime.dtsi
@@ -38,3 +38,10 @@
cooling-device = <&cpu0 15 15>, <&cpu1 15 15>,
<&cpu2 15 15>, <&cpu3 15 15>;
};
+
+&gpu_opp_table {
+ opp-533000000 {
+ opp-hz = /bits/ 64 <533000000>;
+ opp-microvolt = <1075000>;
+ };
+};
diff --git a/dts/src/arm/exynos4412.dtsi b/dts/src/arm/exynos4412.dtsi
index e5c041e..d20db2d 100644
--- a/dts/src/arm/exynos4412.dtsi
+++ b/dts/src/arm/exynos4412.dtsi
@@ -716,6 +716,53 @@
cpu-offset = <0x4000>;
};
+&gpu {
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3",
+ "pmu";
+ operating-points-v2 = <&gpu_opp_table>;
+
+ gpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <875000>;
+ };
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-440000000 {
+ opp-hz = /bits/ 64 <440000000>;
+ opp-microvolt = <1025000>;
+ };
+ };
+};
+
&hdmi {
compatible = "samsung,exynos4212-hdmi";
};
@@ -737,6 +784,8 @@
&pmu {
interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ status = "okay";
};
&pmu_system_controller {
diff --git a/dts/src/arm/exynos5410-odroidxu.dts b/dts/src/arm/exynos5410-odroidxu.dts
index 8f9e08f..e0db251 100644
--- a/dts/src/arm/exynos5410-odroidxu.dts
+++ b/dts/src/arm/exynos5410-odroidxu.dts
@@ -85,6 +85,11 @@
};
};
+&adc {
+ vdd-supply = <&ldo10_reg>;
+ status = "okay";
+};
+
&audi2s0 {
status = "okay";
};
diff --git a/dts/src/arm/exynos5410.dtsi b/dts/src/arm/exynos5410.dtsi
index 57fc9c9..e6f78b1 100644
--- a/dts/src/arm/exynos5410.dtsi
+++ b/dts/src/arm/exynos5410.dtsi
@@ -260,6 +260,12 @@
};
};
+&adc {
+ clocks = <&clock CLK_TSADC>;
+ clock-names = "adc";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+};
+
&arm_a15_pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
status = "okay";
diff --git a/dts/src/arm/exynos5420-arndale-octa.dts b/dts/src/arm/exynos5420-arndale-octa.dts
index dbf0306..592d7b4 100644
--- a/dts/src/arm/exynos5420-arndale-octa.dts
+++ b/dts/src/arm/exynos5420-arndale-octa.dts
@@ -386,6 +386,10 @@
* (Linaro for Arndale Octa, v2012.07).
*/
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo4_reg: LDO4 {
@@ -411,6 +415,10 @@
regulator-name = "PVDD_ANAIP_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo8_reg: LDO8 {
@@ -451,6 +459,10 @@
regulator-name = "PVDD_APIO_MMCOFF_2V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo14_reg: LDO14 {
@@ -464,12 +476,20 @@
regulator-name = "PVDD_PERI_2V8";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
ldo16_reg: LDO16 {
regulator-name = "PVDD_PERI_3V3";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
ldo17_reg: LDO17 {
@@ -483,12 +503,28 @@
regulator-name = "PVDD_EMMC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ /*
+ * Must stay in "off" mode during shutdown for
+ * proper eMMC reset. The "off" mode is in
+ * fact controlled by LDO18EN. The eMMC does
+ * not have reset pin connected so the reset
+ * will be triggered by falling edge of
+ * LDO18EN.
+ */
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo19_reg: LDO19 {
regulator-name = "PVDD_TFLASH_2V8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo20_reg: LDO20 {
@@ -515,12 +551,20 @@
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
ldo24_reg: LDO24 {
regulator-name = "PVDD_CAM1_AVDD_2V8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
ldo25_reg: LDO25 {
@@ -540,6 +584,10 @@
regulator-name = "PVDD_G3DS_1V0";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
};
ldo28_reg: LDO28 {
@@ -615,55 +663,75 @@
buck1_reg: BUCK1 {
regulator-name = "PVDD_MIF_1V1";
regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck2_reg: BUCK2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck3_reg: BUCK3 {
regulator-name = "PVDD_INT_1V0";
regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck4_reg: BUCK4 {
regulator-name = "PVDD_G3D_1V0";
regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck5_reg: BUCK5 {
regulator-name = "PVDD_LPDDR3_1V2";
regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1200000>;
+ regulator-max-microvolt = <1400000>;
regulator-always-on;
};
buck6_reg: BUCK6 {
regulator-name = "PVDD_KFC_1V0";
regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck7_reg: BUCK7 {
regulator-name = "VIN_LLDO_1V4";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
regulator-always-on;
};
buck8_reg: BUCK8 {
regulator-name = "VIN_MLDO_2V0";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <2000000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
regulator-always-on;
};
@@ -678,6 +746,18 @@
regulator-name = "PVDD_EMMCF_2V8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
+ /*
+ * Must stay in "off" mode during shutdown for
+ * proper eMMC reset. The "off" mode is in
+ * fact controlled by BUCK10EN. The eMMC does
+ * not have reset pin connected so the reset
+ * will be triggered by falling edge of
+ * BUCK10EN.
+ */
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
};
};
@@ -700,7 +780,7 @@
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
- vmmc-supply = <&ldo10_reg>;
+ vmmc-supply = <&ldo18_reg>;
vqmmc-supply = <&ldo3_reg>;
bus-width = <8>;
cap-mmc-highspeed;
diff --git a/dts/src/arm/exynos5420.dtsi b/dts/src/arm/exynos5420.dtsi
index 5fb2326..55d4dbf 100644
--- a/dts/src/arm/exynos5420.dtsi
+++ b/dts/src/arm/exynos5420.dtsi
@@ -42,117 +42,119 @@
* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
*/
- soc: soc {
- cluster_a15_opp_table: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1250000>;
- clock-latency-ns = <140000>;
- };
- opp-1700000000 {
- opp-hz = /bits/ 64 <1700000000>;
- opp-microvolt = <1212500>;
- clock-latency-ns = <140000>;
- };
- opp-1600000000 {
- opp-hz = /bits/ 64 <1600000000>;
- opp-microvolt = <1175000>;
- clock-latency-ns = <140000>;
- };
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <1137500>;
- clock-latency-ns = <140000>;
- };
- opp-1400000000 {
- opp-hz = /bits/ 64 <1400000000>;
- opp-microvolt = <1112500>;
- clock-latency-ns = <140000>;
- };
- opp-1300000000 {
- opp-hz = /bits/ 64 <1300000000>;
- opp-microvolt = <1062500>;
- clock-latency-ns = <140000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1037500>;
- clock-latency-ns = <140000>;
- };
- opp-1100000000 {
- opp-hz = /bits/ 64 <1100000000>;
- opp-microvolt = <1012500>;
- clock-latency-ns = <140000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = < 987500>;
- clock-latency-ns = <140000>;
- };
- opp-900000000 {
- opp-hz = /bits/ 64 <900000000>;
- opp-microvolt = < 962500>;
- clock-latency-ns = <140000>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = < 937500>;
- clock-latency-ns = <140000>;
- };
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = < 912500>;
- clock-latency-ns = <140000>;
- };
+ cluster_a15_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1250000>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <1175000>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1137500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1037500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <1012500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = < 987500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = < 962500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = < 937500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = < 912500>;
+ clock-latency-ns = <140000>;
};
+ };
- cluster_a7_opp_table: opp_table1 {
- compatible = "operating-points-v2";
- opp-shared;
- opp-1300000000 {
- opp-hz = /bits/ 64 <1300000000>;
- opp-microvolt = <1275000>;
- clock-latency-ns = <140000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1212500>;
- clock-latency-ns = <140000>;
- };
- opp-1100000000 {
- opp-hz = /bits/ 64 <1100000000>;
- opp-microvolt = <1162500>;
- clock-latency-ns = <140000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <1112500>;
- clock-latency-ns = <140000>;
- };
- opp-900000000 {
- opp-hz = /bits/ 64 <900000000>;
- opp-microvolt = <1062500>;
- clock-latency-ns = <140000>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1025000>;
- clock-latency-ns = <140000>;
- };
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = <975000>;
- clock-latency-ns = <140000>;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <937500>;
- clock-latency-ns = <140000>;
- };
+ cluster_a7_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1275000>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <1162500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1025000>;
+ clock-latency-ns = <140000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <140000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <937500>;
+ clock-latency-ns = <140000>;
};
+ };
+ soc: soc {
cci: cci@10d20000 {
compatible = "arm,cci-400";
#address-cells = <1>;
@@ -548,18 +550,6 @@
status = "disabled";
};
- adc: adc@12d10000 {
- compatible = "samsung,exynos-adc-v2";
- reg = <0x12D10000 0x100>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_TSADC>;
- clock-names = "adc";
- #io-channel-cells = <1>;
- io-channel-ranges;
- samsung,syscon-phandle = <&pmu_system_controller>;
- status = "disabled";
- };
-
hsi2c_8: i2c@12e00000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E00000 0x1000>;
@@ -1363,6 +1353,12 @@
};
};
+&adc {
+ clocks = <&clock CLK_TSADC>;
+ clock-names = "adc";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+};
+
&dp {
clocks = <&clock CLK_DP1>;
clock-names = "dp";
diff --git a/dts/src/arm/exynos5422-odroid-core.dtsi b/dts/src/arm/exynos5422-odroid-core.dtsi
index 25d95de..829147e 100644
--- a/dts/src/arm/exynos5422-odroid-core.dtsi
+++ b/dts/src/arm/exynos5422-odroid-core.dtsi
@@ -177,6 +177,10 @@
regulator-name = "vdd_adc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo5_reg: LDO5 {
@@ -184,6 +188,10 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo6_reg: LDO6 {
@@ -191,6 +199,10 @@
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo7_reg: LDO7 {
@@ -198,6 +210,10 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo8_reg: LDO8 {
@@ -205,6 +221,10 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo9_reg: LDO9 {
@@ -212,6 +232,10 @@
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo10_reg: LDO10 {
@@ -219,6 +243,10 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo11_reg: LDO11 {
@@ -226,6 +254,10 @@
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo12_reg: LDO12 {
@@ -239,6 +271,10 @@
regulator-name = "vddq_mmc2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo14_reg: LDO14 {
@@ -253,6 +289,10 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo16_reg: LDO16 {
@@ -267,18 +307,30 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo18_reg: LDO18 {
regulator-name = "vdd_emmc_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo19_reg: LDO19 {
regulator-name = "vdd_sd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo20_reg: LDO20 {
@@ -307,6 +359,10 @@
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo24_reg: LDO24 {
@@ -328,6 +384,10 @@
regulator-name = "vdd_ldo26";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo27_reg: LDO27 {
@@ -335,6 +395,10 @@
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo28_reg: LDO28 {
@@ -342,6 +406,10 @@
regulator-name = "vdd_ldo28";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
ldo29_reg: LDO29 {
@@ -420,6 +488,10 @@
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck2_reg: BUCK2 {
@@ -428,6 +500,10 @@
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck3_reg: BUCK3 {
@@ -436,6 +512,10 @@
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck4_reg: BUCK4 {
@@ -444,6 +524,10 @@
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck5_reg: BUCK5 {
@@ -460,20 +544,24 @@
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck7_reg: BUCK7 {
- regulator-name = "vdd_1.0v_ldo";
- regulator-min-microvolt = <800000>;
+ regulator-name = "vdd_1.35v_ldo";
+ regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
buck8_reg: BUCK8 {
- regulator-name = "vdd_1.8v_ldo";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <2000000>;
+ regulator-name = "vdd_2.0v_ldo";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
regulator-always-on;
regulator-boot-on;
};
@@ -484,14 +572,20 @@
regulator-max-microvolt = <3750000>;
regulator-always-on;
regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
buck10_reg: BUCK10 {
regulator-name = "vdd_vmem";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
- regulator-always-on;
- regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
};
};
};
diff --git a/dts/src/arm/exynos5422-odroidxu3-common.dtsi b/dts/src/arm/exynos5422-odroidxu3-common.dtsi
index 93a48f2..8388720 100644
--- a/dts/src/arm/exynos5422-odroidxu3-common.dtsi
+++ b/dts/src/arm/exynos5422-odroidxu3-common.dtsi
@@ -360,6 +360,12 @@
};
};
+&buck10_reg {
+ /* Supplies vmmc-supply of mmc_0 */
+ regulator-always-on;
+ regulator-boot-on;
+};
+
&hdmi {
status = "okay";
ddc = <&i2c_2>;
diff --git a/dts/src/arm/exynos54xx.dtsi b/dts/src/arm/exynos54xx.dtsi
index ae866bc..0b27beb 100644
--- a/dts/src/arm/exynos54xx.dtsi
+++ b/dts/src/arm/exynos54xx.dtsi
@@ -96,6 +96,15 @@
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
+ adc: adc@12d10000 {
+ compatible = "samsung,exynos-adc-v2";
+ reg = <0x12d10000 0x100>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ status = "disabled";
+ };
+
/* i2c_0-3 are defined in exynos5.dtsi */
hsi2c_4: i2c@12ca0000 {
compatible = "samsung,exynos5250-hsi2c";
diff --git a/dts/src/arm/gemini-dlink-dir-685.dts b/dts/src/arm/gemini-dlink-dir-685.dts
index 3613f05..bfaa2de 100644
--- a/dts/src/arm/gemini-dlink-dir-685.dts
+++ b/dts/src/arm/gemini-dlink-dir-685.dts
@@ -64,7 +64,7 @@
gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
panel: display@0 {
diff --git a/dts/src/arm/hip04.dtsi b/dts/src/arm/hip04.dtsi
index bf0cb55..4263a93 100644
--- a/dts/src/arm/hip04.dtsi
+++ b/dts/src/arm/hip04.dtsi
@@ -347,7 +347,7 @@
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
- compatible = "arm,coresight-replicator";
+ compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
@@ -382,7 +382,7 @@
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
- compatible = "arm,coresight-replicator";
+ compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
@@ -417,7 +417,7 @@
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
- compatible = "arm,coresight-replicator";
+ compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
@@ -451,7 +451,7 @@
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
- compatible = "arm,coresight-replicator";
+ compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
@@ -482,7 +482,7 @@
};
funnel@0,e3c41000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3c41000 0 0x1000>;
clocks = <&clk_375m>;
@@ -531,7 +531,7 @@
};
funnel@0,e3c81000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3c81000 0 0x1000>;
clocks = <&clk_375m>;
@@ -580,7 +580,7 @@
};
funnel@0,e3cc1000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3cc1000 0 0x1000>;
clocks = <&clk_375m>;
@@ -629,7 +629,7 @@
};
funnel@0,e3d01000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3d01000 0 0x1000>;
clocks = <&clk_375m>;
@@ -678,7 +678,7 @@
};
funnel@0,e3c04000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0xe3c04000 0 0x1000>;
clocks = <&clk_375m>;
diff --git a/dts/src/arm/ibm-power9-dual.dtsi b/dts/src/arm/ibm-power9-dual.dtsi
new file mode 100644
index 0000000..2abc42e
--- /dev/null
+++ b/dts/src/arm/ibm-power9-dual.dtsi
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2018 IBM Corp
+
+&fsi {
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <0>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ };
+
+ cfam0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ };
+
+ cfam0_i2c2: i2c-bus@2 {
+ reg = <2>;
+ };
+
+ cfam0_i2c3: i2c-bus@3 {
+ reg = <3>;
+ };
+
+ cfam0_i2c4: i2c-bus@4 {
+ reg = <4>;
+ };
+
+ cfam0_i2c5: i2c-bus@5 {
+ reg = <5>;
+ };
+
+ cfam0_i2c6: i2c-bus@6 {
+ reg = <6>;
+ };
+
+ cfam0_i2c7: i2c-bus@7 {
+ reg = <7>;
+ };
+
+ cfam0_i2c8: i2c-bus@8 {
+ reg = <8>;
+ };
+
+ cfam0_i2c9: i2c-bus@9 {
+ reg = <9>;
+ };
+
+ cfam0_i2c10: i2c-bus@a {
+ reg = <10>;
+ };
+
+ cfam0_i2c11: i2c-bus@b {
+ reg = <11>;
+ };
+
+ cfam0_i2c12: i2c-bus@c {
+ reg = <12>;
+ };
+
+ cfam0_i2c13: i2c-bus@d {
+ reg = <13>;
+ };
+
+ cfam0_i2c14: i2c-bus@e {
+ reg = <14>;
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ0: occ {
+ compatible = "ibm,p9-occ";
+ };
+ };
+
+ fsi_hub0: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+};
+
+&fsi_hub0 {
+ cfam@1,0 {
+ reg = <1 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <1>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ };
+
+ cfam1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ };
+
+ cfam1_i2c2: i2c-bus@2 {
+ reg = <2>;
+ };
+
+ cfam1_i2c3: i2c-bus@3 {
+ reg = <3>;
+ };
+
+ cfam1_i2c4: i2c-bus@4 {
+ reg = <4>;
+ };
+
+ cfam1_i2c5: i2c-bus@5 {
+ reg = <5>;
+ };
+
+ cfam1_i2c6: i2c-bus@6 {
+ reg = <6>;
+ };
+
+ cfam1_i2c7: i2c-bus@7 {
+ reg = <7>;
+ };
+
+ cfam1_i2c8: i2c-bus@8 {
+ reg = <8>;
+ };
+
+ cfam1_i2c9: i2c-bus@9 {
+ reg = <9>;
+ };
+
+ cfam1_i2c10: i2c-bus@a {
+ reg = <10>;
+ };
+
+ cfam1_i2c11: i2c-bus@b {
+ reg = <11>;
+ };
+
+ cfam1_i2c12: i2c-bus@c {
+ reg = <12>;
+ };
+
+ cfam1_i2c13: i2c-bus@d {
+ reg = <13>;
+ };
+
+ cfam1_i2c14: i2c-bus@e {
+ reg = <14>;
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ1: occ {
+ compatible = "ibm,p9-occ";
+ };
+ };
+
+ fsi_hub1: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+};
+
+/* Legacy OCC numbering (to get rid of when userspace is fixed) */
+&fsi_occ0 {
+ reg = <1>;
+};
+
+&fsi_occ1 {
+ reg = <2>;
+};
+
+/ {
+ aliases {
+ i2c100 = &cfam0_i2c0;
+ i2c101 = &cfam0_i2c1;
+ i2c102 = &cfam0_i2c2;
+ i2c103 = &cfam0_i2c3;
+ i2c104 = &cfam0_i2c4;
+ i2c105 = &cfam0_i2c5;
+ i2c106 = &cfam0_i2c6;
+ i2c107 = &cfam0_i2c7;
+ i2c108 = &cfam0_i2c8;
+ i2c109 = &cfam0_i2c9;
+ i2c110 = &cfam0_i2c10;
+ i2c111 = &cfam0_i2c11;
+ i2c112 = &cfam0_i2c12;
+ i2c113 = &cfam0_i2c13;
+ i2c114 = &cfam0_i2c14;
+ i2c200 = &cfam1_i2c0;
+ i2c201 = &cfam1_i2c1;
+ i2c202 = &cfam1_i2c2;
+ i2c203 = &cfam1_i2c3;
+ i2c204 = &cfam1_i2c4;
+ i2c205 = &cfam1_i2c5;
+ i2c206 = &cfam1_i2c6;
+ i2c207 = &cfam1_i2c7;
+ i2c208 = &cfam1_i2c8;
+ i2c209 = &cfam1_i2c9;
+ i2c210 = &cfam1_i2c10;
+ i2c211 = &cfam1_i2c11;
+ i2c212 = &cfam1_i2c12;
+ i2c213 = &cfam1_i2c13;
+ i2c214 = &cfam1_i2c14;
+ };
+};
diff --git a/dts/src/arm/imx53-m53menlo.dts b/dts/src/arm/imx53-m53menlo.dts
index f0a3fde..10acc53 100644
--- a/dts/src/arm/imx53-m53menlo.dts
+++ b/dts/src/arm/imx53-m53menlo.dts
@@ -10,6 +10,25 @@
model = "MENLO M53 EMBEDDED DEVICE";
compatible = "menlo,m53menlo", "fsl,imx53";
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&pinctrl_power_button>;
+ pinctrl-names = "default";
+
+ power-button {
+ label = "Power button";
+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&pinctrl_power_out>;
+ pinctrl-names = "default";
+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -30,7 +49,7 @@
eth {
label = "EthLedYe";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "none";
+ linux,default-trigger = "netdev";
};
};
@@ -45,12 +64,19 @@
};
};
+ beeper {
+ compatible = "gpio-beeper";
+ pinctrl-0 = <&pinctrl_beeper>;
+ gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+ };
+
reg_usbh1_vbus: regulator-usbh1-vbus {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
};
@@ -74,6 +100,25 @@
assigned-clock-rates = <133333334>, <33333334>, <33333334>;
};
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spidev@0 {
+ compatible = "menlo,m53cpld";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+
+ spidev@1 {
+ compatible = "menlo,m53cpld";
+ spi-max-frequency = <25000000>;
+ reg = <1>;
+ };
+};
+
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
@@ -86,9 +131,82 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
+ phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "TestPin_SV2_3", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "",
+ "", "CPLD_JTAG_TDO", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "CPLD_JTAG_TCK", "KBD_intK",
+ "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]",
+ "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]",
+ "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI";
+};
+
+&gpio6 {
+ gpio-line-names =
+ "", "", "", "",
+ "CPLD_reset", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio7 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "USB-OTG_OverCurrent", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -136,27 +254,37 @@
imx53-m53evk {
hoggrp {
fsl,pins = <
- MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
- MX53_PAD_EIM_EB3__GPIO2_31 0x1d5
- MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5
- MX53_PAD_GPIO_19__CCM_CLKO 0x1d5
- MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5
- MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5
- MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5
- MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5
- MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5
- MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5
- MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5
- MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5
- MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5
- MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5
+ MX53_PAD_GPIO_19__CCM_CLKO 0x1e4
+ MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4
+ MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4
+ MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4
+ MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4
+ MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4
+ MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4
+ MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4
+ MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4
+ MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4
+ MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4
+ MX53_PAD_EIM_D24__GPIO3_24 0x1e4
+ MX53_PAD_EIM_D25__GPIO3_25 0x1e4
+ MX53_PAD_EIM_D29__GPIO3_29 0x1e4
+ MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4
+ MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4
+ MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4
+ MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
- MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5
- MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5
+ MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4
+ MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4
+ >;
+ };
+
+ pinctrl_beeper: beepergrp {
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4
>;
};
@@ -169,49 +297,66 @@
pinctrl_can2: can2grp {
fsl,pins = <
- MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4
+ MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4
>;
};
pinctrl_display_gpio: display-gpiogrp {
fsl,pins = <
- MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */
- MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */
+ MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */
+ MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */
+ MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */
+
+ MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */
>;
};
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
- MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */
- MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */
- MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */
+ MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */
+ MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */
+ MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4
+ MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4
+ MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4
+ MX53_PAD_EIM_RW__GPIO2_26 0xe4
+ MX53_PAD_EIM_LBA__GPIO2_27 0xe4
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4
+ MX53_PAD_GPIO_1__GPIO1_1 0x1c4
+ MX53_PAD_GPIO_9__GPIO1_9 0x1e4
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
- MX53_PAD_FEC_MDC__FEC_MDC 0x4
- MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
- MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
- MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
- MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
- MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
- MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
- MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
- MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
- MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+ MX53_PAD_FEC_MDC__FEC_MDC 0x1e4
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4
+ MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4
+ MX53_PAD_EIM_EB3__GPIO2_31 0x1e4
>;
};
@@ -240,10 +385,24 @@
>;
};
+ pinctrl_power_button: powerbutgrp {
+ fsl,pins = <
+ MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4
+ >;
+ };
+
+ pinctrl_power_out: poweroutgrp {
+ fsl,pins = <
+ MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
+ MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4
+ MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4
>;
};
@@ -251,13 +410,25 @@
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
+ MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4
+ MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
+ MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
+ MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
>;
};
pinctrl_usb: usbgrp {
fsl,pins = <
- MX53_PAD_GPIO_2__GPIO1_2 0x1d5
- MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5
+ MX53_PAD_GPIO_2__GPIO1_2 0x1c4
+ MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4
+ MX53_PAD_GPIO_4__GPIO1_4 0x1c4
+ MX53_PAD_GPIO_18__GPIO7_13 0x1c4
>;
};
};
@@ -287,12 +458,21 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ linux,rs485-enabled-at-boot-time;
status = "okay";
};
@@ -301,7 +481,7 @@
pinctrl-0 = <&pinctrl_usb>;
vbus-supply = <&reg_usbh1_vbus>;
phy_type = "utmi";
- dr_mode = "peripheral";
+ dr_mode = "host";
status = "okay";
};
diff --git a/dts/src/arm/imx53-smd.dts b/dts/src/arm/imx53-smd.dts
index 09071ca..ec9fb89 100644
--- a/dts/src/arm/imx53-smd.dts
+++ b/dts/src/arm/imx53-smd.dts
@@ -185,6 +185,31 @@
>;
};
+ pinctrl_ipu_csi0: ipucsi0grp {
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4
+ MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4
+ MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4
+ MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4
+ MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4
+ MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4
+ MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4
+ MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4
+ MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4
+ MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4
+ MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4
+ MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4
+ >;
+ };
+
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4
+ MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4
+ MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
@@ -256,11 +281,47 @@
camera: ov5642@3c {
compatible = "ovti,ov5642";
reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>,
+ <&clks IMX5_CLK_SSI_EXT1_COM_SEL>;
+ assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>,
+ <&clks IMX5_CLK_SSI_EXT1_PODF>;
+ assigned-clock-rates = <0>, <24000000>;
+ clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
+ clock-names = "xclk";
+ DVDD-supply = <&ldo9_reg>;
+ AVDD-supply = <&ldo7_reg>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov5642_to_ipu_csi0: endpoint {
+ remote-endpoint = <&ipu_csi0_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
};
pmic: dialog@48 {
compatible = "dlg,da9053", "dlg,da9052";
reg = <0x48>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ ldo7_reg: ldo7 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <3650000>;
+ };
+ };
};
};
@@ -271,3 +332,15 @@
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
+
+&ipu_csi0_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu_csi0>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vsync-active = <1>;
+};
+
+&ipu_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu_csi0>;
+};
diff --git a/dts/src/arm/imx53.dtsi b/dts/src/arm/imx53.dtsi
index 9b672ed..ed341cf 100644
--- a/dts/src/arm/imx53.dtsi
+++ b/dts/src/arm/imx53.dtsi
@@ -31,6 +31,7 @@
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
+ ipu0 = &ipu;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
mmc2 = &esdhc3;
@@ -71,6 +72,11 @@
ports = <&ipu_di0>, <&ipu_di1>;
};
+ capture_subsystem {
+ compatible = "fsl,imx-capture-subsystem";
+ ports = <&ipu_csi0>, <&ipu_csi1>;
+ };
+
tzic: tz-interrupt-controller@fffc000 {
compatible = "fsl,imx53-tzic", "fsl,tzic";
interrupt-controller;
@@ -158,10 +164,16 @@
ipu_csi0: port@0 {
reg = <0>;
+
+ ipu_csi0_from_parallel_sensor: endpoint {
+ };
};
ipu_csi1: port@1 {
reg = <1>;
+
+ ipu_csi1_from_parallel_sensor: endpoint {
+ };
};
ipu_di0: port@2 {
diff --git a/dts/src/arm/imx6dl-kontron-samx6i.dtsi b/dts/src/arm/imx6dl-kontron-samx6i.dtsi
new file mode 100644
index 0000000..a864fdb
--- /dev/null
+++ b/dts/src/arm/imx6dl-kontron-samx6i.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-kontron-samx6i.dtsi"
+
+/ {
+ model = "Kontron SMARC sAMX6i Dual-Lite/Solo";
+ compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl";
+};
diff --git a/dts/src/arm/imx6q-kontron-samx6i.dtsi b/dts/src/arm/imx6q-kontron-samx6i.dtsi
new file mode 100644
index 0000000..2618ecc
--- /dev/null
+++ b/dts/src/arm/imx6q-kontron-samx6i.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
+ */
+
+#include "imx6q.dtsi"
+#include "imx6qdl-kontron-samx6i.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Kontron SMARC sAMX6i Quad/Dual";
+ compatible = "kontron,imx6q-samx6i", "fsl,imx6q";
+};
+
+/* Quad/Dual SoMs have 3 chip-select signals */
+&ecspi4 {
+ fsl,spi-num-chipselects = <3>;
+ cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
+ <&gpio3 29 GPIO_ACTIVE_HIGH>,
+ <&gpio3 25 GPIO_ACTIVE_HIGH>;
+};
+
+&pinctrl_ecspi4 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+
+ /* SPI4_IMX_CS2# - connected to internal flash */
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
+ /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+ /* SPI4_CS3# - connected to SMARC SPI0_CS1# */
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0
+ >;
+};
diff --git a/dts/src/arm/imx6qdl-kontron-samx6i.dtsi b/dts/src/arm/imx6qdl-kontron-samx6i.dtsi
new file mode 100644
index 0000000..81c7ebb
--- /dev/null
+++ b/dts/src/arm/imx6qdl-kontron-samx6i.dtsi
@@ -0,0 +1,815 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
+ * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
+ * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
+ *
+ * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
+
+/ {
+ reg_1p0v_s0: regulator-1p0v-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V0_S0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_smarc_suppy>;
+ };
+
+ reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V35_VCOREDIG_S5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_3p3v_s5>;
+ };
+
+ reg_1p8v_s5: regulator-1p8v-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V8_S5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_3p3v_s5>;
+ };
+
+ reg_3p3v_s0: regulator-3p3v-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_S0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_3p3v_s5>;
+ };
+
+ reg_3p3v_s0: regulator-3p3v-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_S0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_3p3v_s5>;
+ };
+
+ reg_3p3v_s5: regulator-3p3v-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_S5";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_smarc_suppy>;
+ };
+
+ reg_smarc_lcdbklt: regulator-smarc-lcdbklt {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdbklt_en>;
+ regulator-name = "LCD_BKLT_EN";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_smarc_lcdvdd: regulator-smarc-lcdvdd {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdvdd_en>;
+ regulator-name = "LCD_VDD_EN";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_smarc_rtc: regulator-smarc-rtc {
+ compatible = "regulator-fixed";
+ regulator-name = "V_IN_RTC_BATT";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* Module supply range can be 3.00V ... 5.25V */
+ reg_smarc_suppy: regulator-smarc-supply {
+ compatible = "regulator-fixed";
+ regulator-name = "V_IN_WIDE";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lcd: lcd {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx-parallel-display";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_out: endpoint {
+ };
+ };
+ };
+
+ lcd_backlight: lcd-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 5000000>;
+ pwm-names = "LCD_BKLT_PWM";
+
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <4>;
+
+ power-supply = <&reg_smarc_lcdbklt>;
+ status = "disabled";
+ };
+
+ i2c_intern: i2c-gpio-intern {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
+ sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c_lcd: i2c-gpio-lcd {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_gpio_lcd>;
+ sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabld";
+ };
+
+ i2c_cam: i2c-gpio-cam {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_gpio_cam>;
+ sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabld";
+ };
+};
+
+/* I2S0, I2S1 */
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+
+ audmux_ssi1 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) |
+ IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) |
+ IMX_AUDMUX_V2_PTCR_SYN |
+ IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TCLKDIR)
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3)
+ >;
+ };
+
+ audmux_adu3 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT3>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
+ >;
+ };
+
+ audmux_ssi2 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
+ IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
+ IMX_AUDMUX_V2_PTCR_SYN |
+ IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TCLKDIR)
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
+ >;
+ };
+
+ audmux_adu4 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT4>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1)
+ >;
+ };
+};
+
+/* CAN0 */
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+/* CAN1 */
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+/* SPI1 */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>,
+ <&gpio2 27 GPIO_ACTIVE_HIGH>;
+};
+
+/* SPI0 */
+&ecspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
+ <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ /* default boot source: workaround #1 for errata ERR006282 */
+ smarc_flash: spi-flash@0 {
+ compatible = "winbond,w25q16dw", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+/* GBE */
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+};
+
+&i2c_intern {
+ pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ reg_v_core_s0: sw1ab {
+ regulator-name = "V_CORE_S0";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vddsoc_s0: sw1c {
+ regulator-name = "V_VDDSOC_S0";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p15v_s0: sw2 {
+ regulator-name = "V_3V15_S0";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* sw3a/b is used in dual mode, but driver does not
+ * support it. Although, there's no need to control
+ * DDR power - so just leaving dummy entries for sw3a
+ * and sw3b for now.
+ */
+ sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_1p8v_s0: sw4 {
+ regulator-name = "V_1V8_S0";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* Regulator for USB */
+ reg_5p0v_s0: swbst {
+ regulator-name = "V_5V0_S0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-boot-on;
+ };
+
+ reg_vsnvs: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vrefddr: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /*
+ * Per schematics, of all VGEN's, only VGEN5 has some
+ * usage ... but even that - over DNI resistor
+ */
+ vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_2p5v_s0: vgen5 {
+ regulator-name = "V_2V5_S0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+/* I2C_GP */
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+};
+
+/* HDMI_CTRL */
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+};
+
+/* I2C_PM */
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ smarc_eeprom: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>;
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+
+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
+
+ /* AUDIO MCLK */
+ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
+
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */
+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */
+ >;
+ };
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+
+ /* SPI_IMX_CS2# - connected to internal flash */
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
+ /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */
+ MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */
+ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */
+ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */
+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */
+ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */
+ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */
+ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */
+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */
+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */
+ MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */
+ MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
+ >;
+ };
+
+ pinctrl_i2c_gpio_cam: i2c-gpiocamgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */
+ >;
+ };
+
+ pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
+ >;
+ };
+
+ pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */
+ MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_lcd: lcdgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1
+
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */
+ >;
+ };
+
+ pinctrl_lcdbklt_en: lcdbkltengrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1
+ >;
+ };
+
+ pinctrl_lcdvdd_en: lcdvddengrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
+ >;
+ };
+
+ pinctrl_mipi_csi: mipi-csigrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */
+ >;
+ };
+
+ pinctrl_mgmt_gpios: mgmt-gpiosgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */
+ MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
+ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */
+ MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
+ /* power, oc muxed but not used by the driver */
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_wdog1: wdog1rp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
+ >;
+ };
+};
+
+&mipi_csi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mipi_csi>;
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+};
+
+/* LCD_BKLT_PWM */
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+};
+
+&reg_arm {
+ vin-supply = <&reg_v_core_s0>;
+};
+
+&reg_pu {
+ vin-supply = <&reg_vddsoc_s0>;
+};
+
+&reg_soc {
+ vin-supply = <&reg_vddsoc_s0>;
+};
+
+/* SER0 */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+};
+
+/* SER1 */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
+
+/* SER2 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ uart-has-rtscts;
+};
+
+/* SER3 */
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+};
+
+/* USB0 */
+&usbotg {
+ /*
+ * no 'imx6-usb-charger-detection'
+ * since USB_OTG_CHD_B pin is not wired
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+};
+
+/* USB1/2 via hub */
+&usbh1 {
+ vbus-supply = <&reg_5p0v_s0>;
+};
+
+/* SDIO */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ no-1-8-v;
+};
+
+/* SDMMC */
+&usdhc4 {
+ /* Internal eMMC, optional on some boards */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ vmmc-supply = <&reg_3p3v_s0>;
+ vqmmc-supply = <&reg_1p8v_s0>;
+};
+
+&wdog1 {
+ /* CPLD is feeded by watchdog (hardwired) */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog1>;
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6qdl-sabresd.dtsi b/dts/src/arm/imx6qdl-sabresd.dtsi
index 185fb17..71ca76a 100644
--- a/dts/src/arm/imx6qdl-sabresd.dtsi
+++ b/dts/src/arm/imx6qdl-sabresd.dtsi
@@ -745,10 +745,26 @@
vin-supply = <&sw1c_reg>;
};
+&reg_vdd1p1 {
+ vin-supply = <&vgen5_reg>;
+};
+
+&reg_vdd3p0 {
+ vin-supply = <&sw2_reg>;
+};
+
+&reg_vdd2p5 {
+ vin-supply = <&vgen5_reg>;
+};
+
&snvs_poweroff {
status = "okay";
};
+&snvs_pwrkey {
+ status = "okay";
+};
+
&ssi2 {
status = "okay";
};
diff --git a/dts/src/arm/imx6qdl.dtsi b/dts/src/arm/imx6qdl.dtsi
index b3a77bc..4b80193 100644
--- a/dts/src/arm/imx6qdl.dtsi
+++ b/dts/src/arm/imx6qdl.dtsi
@@ -675,14 +675,14 @@
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_DUMMY>;
+ clocks = <&clks IMX6QDL_CLK_IPG>;
};
wdog2: wdog@20c0000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_DUMMY>;
+ clocks = <&clks IMX6QDL_CLK_IPG>;
status = "disabled";
};
@@ -701,7 +701,7 @@
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
- regulator-1p1 {
+ reg_vdd1p1: regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <1000000>;
@@ -716,7 +716,7 @@
anatop-enable-bit = <0>;
};
- regulator-3p0 {
+ reg_vdd3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@@ -731,7 +731,7 @@
anatop-enable-bit = <0>;
};
- regulator-2p5 {
+ reg_vdd2p5: regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2250000>;
@@ -841,6 +841,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
+ status = "disabled";
};
snvs_lpgpr: snvs-lpgpr {
diff --git a/dts/src/arm/imx6sl-evk.dts b/dts/src/arm/imx6sl-evk.dts
index f7a48e4..4829aa6 100644
--- a/dts/src/arm/imx6sl-evk.dts
+++ b/dts/src/arm/imx6sl-evk.dts
@@ -580,6 +580,18 @@
status = "okay";
};
+&reg_vdd1p1 {
+ vin-supply = <&sw2_reg>;
+};
+
+&reg_vdd3p0 {
+ vin-supply = <&sw2_reg>;
+};
+
+&reg_vdd2p5 {
+ vin-supply = <&sw2_reg>;
+};
+
&snvs_poweroff {
status = "okay";
};
diff --git a/dts/src/arm/imx6sl.dtsi b/dts/src/arm/imx6sl.dtsi
index 9ddbeea..b36fc01 100644
--- a/dts/src/arm/imx6sl.dtsi
+++ b/dts/src/arm/imx6sl.dtsi
@@ -495,7 +495,7 @@
compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_DUMMY>;
+ clocks = <&clks IMX6SL_CLK_IPG>;
status = "disabled";
};
@@ -503,14 +503,14 @@
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_DUMMY>;
+ clocks = <&clks IMX6SL_CLK_IPG>;
};
wdog2: wdog@20c0000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_DUMMY>;
+ clocks = <&clks IMX6SL_CLK_IPG>;
status = "disabled";
};
@@ -531,7 +531,7 @@
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
- regulator-1p1 {
+ reg_vdd1p1: regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <1000000>;
@@ -546,7 +546,7 @@
anatop-enable-bit = <0>;
};
- regulator-3p0 {
+ reg_vdd3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@@ -561,7 +561,7 @@
anatop-enable-bit = <0>;
};
- regulator-2p5 {
+ reg_vdd2p5: regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2250000>;
diff --git a/dts/src/arm/imx6sll-evk.dts b/dts/src/arm/imx6sll-evk.dts
index 4a31a41..3e1d32f 100644
--- a/dts/src/arm/imx6sll-evk.dts
+++ b/dts/src/arm/imx6sll-evk.dts
@@ -265,6 +265,18 @@
status = "okay";
};
+&reg_3p0 {
+ vin-supply = <&sw2_reg>;
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
diff --git a/dts/src/arm/imx6sll.dtsi b/dts/src/arm/imx6sll.dtsi
index 1b4899f..b0a77ff 100644
--- a/dts/src/arm/imx6sll.dtsi
+++ b/dts/src/arm/imx6sll.dtsi
@@ -568,6 +568,7 @@
regmap = <&snvs>;
offset = <0x38>;
mask = <0x61>;
+ status = "disabled";
};
snvs_pwrkey: snvs-powerkey {
@@ -576,6 +577,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
+ status = "disabled";
};
};
diff --git a/dts/src/arm/imx6sx-sdb-reva.dts b/dts/src/arm/imx6sx-sdb-reva.dts
index 00c4854..f1830ed 100644
--- a/dts/src/arm/imx6sx-sdb-reva.dts
+++ b/dts/src/arm/imx6sx-sdb-reva.dts
@@ -154,3 +154,19 @@
enable-active-high;
vin-supply = <&reg_can_en>;
};
+
+&reg_vdd1p1 {
+ vin-supply = <&vgen6_reg>;
+};
+
+&reg_vdd3p0 {
+ vin-supply = <&sw2_reg>;
+};
+
+&reg_vdd2p5 {
+ vin-supply = <&vgen6_reg>;
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6sx-sdb.dts b/dts/src/arm/imx6sx-sdb.dts
index 998e3e1..a8ee708 100644
--- a/dts/src/arm/imx6sx-sdb.dts
+++ b/dts/src/arm/imx6sx-sdb.dts
@@ -137,7 +137,23 @@
vin-supply = <&sw1a_reg>;
};
+&reg_vdd1p1 {
+ vin-supply = <&vgen6_reg>;
+};
+
+&reg_vdd3p0 {
+ vin-supply = <&sw2_reg>;
+};
+
+&reg_vdd2p5 {
+ vin-supply = <&vgen6_reg>;
+};
+
&reg_can_stby {
/* Transceiver EN/STBY is active low on RevB board */
gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
};
+
+&snvs_pwrkey {
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6sx-udoo-neo-basic.dts b/dts/src/arm/imx6sx-udoo-neo-basic.dts
index db0feb9..205ea26 100644
--- a/dts/src/arm/imx6sx-udoo-neo-basic.dts
+++ b/dts/src/arm/imx6sx-udoo-neo-basic.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/dts/src/arm/imx6sx-udoo-neo-extended.dts b/dts/src/arm/imx6sx-udoo-neo-extended.dts
index 5c7a2bb..5817b49 100644
--- a/dts/src/arm/imx6sx-udoo-neo-extended.dts
+++ b/dts/src/arm/imx6sx-udoo-neo-extended.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -53,3 +16,11 @@
reg = <0x80000000 0x40000000>;
};
};
+
+&i2c4 { /* Onboard Motion sensors */
+ status = "okay";
+};
+
+&uart3 { /* Bluetooth */
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6sx-udoo-neo-full.dts b/dts/src/arm/imx6sx-udoo-neo-full.dts
index 13dfe2a..96f4d89 100644
--- a/dts/src/arm/imx6sx-udoo-neo-full.dts
+++ b/dts/src/arm/imx6sx-udoo-neo-full.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -68,3 +31,11 @@
};
};
};
+
+&i2c4 { /* Onboard Motion sensors */
+ status = "okay";
+};
+
+&uart3 { /* Bluetooth */
+ status = "okay";
+};
diff --git a/dts/src/arm/imx6sx-udoo-neo.dtsi b/dts/src/arm/imx6sx-udoo-neo.dtsi
index 53b3eac..25d4aa9 100644
--- a/dts/src/arm/imx6sx-udoo-neo.dtsi
+++ b/dts/src/arm/imx6sx-udoo-neo.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6sx.dtsi"
@@ -107,18 +70,6 @@
startup-delay-us = <70000>;
enable-active-high;
};
-
- reg_bt: regulator-bt {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_bt_reg>;
- enable-active-high;
- gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>;
- regulator-name = "bt_reg";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
};
&fec1 {
@@ -225,6 +176,20 @@
};
};
+&i2c2 { /* Brick snap in sensors connector */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c4 { /* Onboard Motion sensors */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ clock-frequency = <100000>;
+ status = "disabled";
+};
+
&iomuxc {
pinctrl_bt_reg: btreggrp {
fsl,pins =
@@ -256,6 +221,18 @@
<MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1>;
};
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins =
+ <MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1>,
+ <MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1>;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins =
+ <MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x4001b8b1>,
+ <MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x4001b8b1>;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins =
<MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1>,
@@ -354,11 +331,19 @@
status = "disabled";
};
-&uart3 { /* Bluetooth */
+&uart3 { /* Bluetooth - only on Extended/Full versions */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
- status = "okay";
+ status = "disabled";
+
+ bluetooth {
+ compatible = "ti,wl1831-st";
+ enable-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bt_reg>;
+ max-speed = <921600>;
+ };
};
/* Arduino serial */
diff --git a/dts/src/arm/imx6sx.dtsi b/dts/src/arm/imx6sx.dtsi
index b16a123..bb25add 100644
--- a/dts/src/arm/imx6sx.dtsi
+++ b/dts/src/arm/imx6sx.dtsi
@@ -600,7 +600,7 @@
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- regulator-1p1 {
+ reg_vdd1p1: regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <1000000>;
@@ -615,7 +615,7 @@
anatop-enable-bit = <0>;
};
- regulator-3p0 {
+ reg_vdd3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
@@ -630,7 +630,7 @@
anatop-enable-bit = <0>;
};
- regulator-2p5 {
+ reg_vdd2p5: regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2250000>;
@@ -738,6 +738,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
+ status = "disabled";
};
};
diff --git a/dts/src/arm/imx6ul-14x14-evk.dtsi b/dts/src/arm/imx6ul-14x14-evk.dtsi
index 9207d5d..cbe61b6 100644
--- a/dts/src/arm/imx6ul-14x14-evk.dtsi
+++ b/dts/src/arm/imx6ul-14x14-evk.dtsi
@@ -238,6 +238,10 @@
status = "okay";
};
+&snvs_pwrkey {
+ status = "okay";
+};
+
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
diff --git a/dts/src/arm/imx6ul-geam.dts b/dts/src/arm/imx6ul-geam.dts
index bc77f26..21ddd35 100644
--- a/dts/src/arm/imx6ul-geam.dts
+++ b/dts/src/arm/imx6ul-geam.dts
@@ -169,7 +169,7 @@
display = <&display0>;
status = "okay";
- display0: display {
+ display0: display0 {
bits-per-pixel = <16>;
bus-width = <18>;
diff --git a/dts/src/arm/imx6ul-isiot.dtsi b/dts/src/arm/imx6ul-isiot.dtsi
index 213e802..b26d4f5 100644
--- a/dts/src/arm/imx6ul-isiot.dtsi
+++ b/dts/src/arm/imx6ul-isiot.dtsi
@@ -161,7 +161,7 @@
display = <&display0>;
status = "okay";
- display0: display {
+ display0: display0 {
bits-per-pixel = <16>;
bus-width = <18>;
diff --git a/dts/src/arm/imx6ul.dtsi b/dts/src/arm/imx6ul.dtsi
index a7f6d1d..81d4b49 100644
--- a/dts/src/arm/imx6ul.dtsi
+++ b/dts/src/arm/imx6ul.dtsi
@@ -59,6 +59,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
+ clock-frequency = <696000000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
operating-points = <
@@ -649,6 +650,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
+ status = "disabled";
};
snvs_lpgpr: snvs-lpgpr {
@@ -856,6 +858,8 @@
<&clks IMX6UL_CLK_USDHC1>,
<&clks IMX6UL_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
+ fsl,tuning-step= <2>;
+ fsl,tuning-start-tap = <20>;
bus-width = <4>;
status = "disabled";
};
@@ -869,6 +873,8 @@
<&clks IMX6UL_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
+ fsl,tuning-step= <2>;
+ fsl,tuning-start-tap = <20>;
status = "disabled";
};
@@ -962,6 +968,14 @@
status = "disabled";
};
+ pxp: pxp@21cc000 {
+ compatible = "fsl,imx6ul-pxp";
+ reg = <0x021cc000 0x4000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_PXP>;
+ clock-names = "axi";
+ };
+
qspi: spi@21e0000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/imx6ull-colibri-eval-v3.dtsi b/dts/src/arm/imx6ull-colibri-eval-v3.dtsi
index 006690e..b6147c7 100644
--- a/dts/src/arm/imx6ull-colibri-eval-v3.dtsi
+++ b/dts/src/arm/imx6ull-colibri-eval-v3.dtsi
@@ -145,13 +145,20 @@
};
&usdhc1 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
- no-1-8-v;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
disable-wp;
wakeup-source;
keep-power-in-suspend;
vmmc-supply = <&reg_3v3>;
+ vqmmc-supply = <&reg_sd1_vmmc>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
diff --git a/dts/src/arm/imx6ull-colibri.dtsi b/dts/src/arm/imx6ull-colibri.dtsi
index 9ad1da1..d56728f 100644
--- a/dts/src/arm/imx6ull-colibri.dtsi
+++ b/dts/src/arm/imx6ull-colibri.dtsi
@@ -545,6 +545,12 @@
>;
};
+ pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
+ >;
+ };
+
pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14
diff --git a/dts/src/arm/imx6ull.dtsi b/dts/src/arm/imx6ull.dtsi
index 22e4a30..b7e67d1 100644
--- a/dts/src/arm/imx6ull.dtsi
+++ b/dts/src/arm/imx6ull.dtsi
@@ -12,6 +12,7 @@
/delete-node/ &crypto;
&cpu0 {
+ clock-frequency = <900000000>;
operating-points = <
/* kHz uV */
900000 1275000
@@ -34,6 +35,12 @@
compatible = "fsl,imx6ull-ocotp", "syscon";
};
+&pxp {
+ compatible = "fsl,imx6ull-pxp";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&usdhc1 {
compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
};
diff --git a/dts/src/arm/imx7d-meerkat96.dts b/dts/src/arm/imx7d-meerkat96.dts
new file mode 100644
index 0000000..5339210
--- /dev/null
+++ b/dts/src/arm/imx7d-meerkat96.dts
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2019 Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include "imx7d.dtsi"
+
+/ {
+ model = "96Boards Meerkat96 Board";
+ compatible = "novtech,imx7d-meerkat96", "fsl,imx7d";
+
+ chosen {
+ stdout-path = &uart6;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512MB */
+ };
+
+ reg_wlreg_on: regulator-wlreg-on {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wlreg_on>;
+ regulator-name = "wlreg_on";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100>;
+ gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "green:user1";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "green:user2";
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "green:user3";
+ gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "green:user4";
+ gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ panic-indicator;
+ };
+
+ led5 {
+ label = "yellow:wlan";
+ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ led6 {
+ label = "blue:bt";
+ gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7 &pinctrl_bt_gpios>;
+ assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ uart-has-rtscts;
+ fsl,dte-mode;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ device-wakeup-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usbotg1 {
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usb_otg2_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ keep-power-in-suspend;
+ tuning-step = <2>;
+ vmmc-supply = <&reg_3p3v>;
+ no-1-8-v;
+ broken-cd;
+ status = "okay";
+};
+
+&usdhc3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <4>;
+ no-1-8-v;
+ no-mmc;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <&reg_wlreg_on>;
+ vqmmc-supply =<&reg_3p3v>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wlan_irq>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&iomuxc {
+ pinctrl_bt_gpios: btgpiosgrp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x59
+ MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x1f
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59
+ MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
+ MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59
+ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
+ MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f
+ MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
+ MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
+ MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
+ MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
+ MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
+ MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
+ MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
+ MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
+ MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
+ MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
+ MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
+ MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
+ MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
+ MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
+ MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
+ MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
+ MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
+ MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
+ MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
+ MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
+ MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
+ MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
+ MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
+ MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
+ MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
+ MX7D_PAD_LCD_CLK__LCD_CLK 0x79
+ MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
+ MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
+ MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
+ MX7D_PAD_LCD_RESET__LCD_RESET 0x79
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x79
+ MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x79
+ MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x79
+ MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x79
+ >;
+ };
+
+ pinctrl_uart6: uart6grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x79
+ MX7D_PAD_SD1_WP__UART6_DCE_TX 0x79
+ >;
+ };
+
+ pinctrl_uart7: uart7grp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x79
+ MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x79
+ MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x79
+ MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x79
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x0D
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ >;
+ };
+
+ pinctrl_wlan_irq: wlanirqgrp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19
+ >;
+ };
+
+ pinctrl_wlreg_on: wlregongrp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x19
+ >;
+ };
+};
diff --git a/dts/src/arm/imx7d-sdb.dts b/dts/src/arm/imx7d-sdb.dts
index 202922e..869efbc 100644
--- a/dts/src/arm/imx7d-sdb.dts
+++ b/dts/src/arm/imx7d-sdb.dts
@@ -263,8 +263,8 @@
};
sw2_reg: sw2 {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1850000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
@@ -379,6 +379,18 @@
status = "okay";
};
+&reg_1p0d {
+ vin-supply = <&sw2_reg>;
+};
+
+&reg_1p2 {
+ vin-supply = <&sw2_reg>;
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
diff --git a/dts/src/arm/imx7d-zii-rpu2.dts b/dts/src/arm/imx7d-zii-rpu2.dts
index 3e467a9..4a78ddc 100644
--- a/dts/src/arm/imx7d-zii-rpu2.dts
+++ b/dts/src/arm/imx7d-zii-rpu2.dts
@@ -16,7 +16,7 @@
compatible = "zii,imx7d-rpu2", "fsl,imx7d";
chosen {
- stdout-path = &uart1;
+ stdout-path = &uart2;
};
cs2000_ref: oscillator {
@@ -775,13 +775,6 @@
>;
};
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f
- MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f
- >;
- };
-
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
@@ -789,13 +782,6 @@
>;
};
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f
- MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f
- >;
- };
-
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
diff --git a/dts/src/arm/imx7d.dtsi b/dts/src/arm/imx7d.dtsi
index f33b560..42528d2 100644
--- a/dts/src/arm/imx7d.dtsi
+++ b/dts/src/arm/imx7d.dtsi
@@ -12,6 +12,8 @@
clock-frequency = <996000000>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
cpu1: cpu@1 {
@@ -39,15 +41,23 @@
opp-792000000 {
opp-hz = /bits/ 64 <792000000>;
- opp-microvolt = <975000>;
+ opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
+ opp-supported-hw = <0xf>, <0xf>;
};
opp-996000000 {
opp-hz = /bits/ 64 <996000000>;
- opp-microvolt = <1075000>;
+ opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
- opp-suspend;
+ opp-supported-hw = <0xc>, <0xf>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1225000>;
+ clock-latency-ns = <150000>;
+ opp-supported-hw = <0x8>, <0xf>;
};
};
diff --git a/dts/src/arm/imx7s.dtsi b/dts/src/arm/imx7s.dtsi
index 106711d..c1a4fff 100644
--- a/dts/src/arm/imx7s.dtsi
+++ b/dts/src/arm/imx7s.dtsi
@@ -117,7 +117,7 @@
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell"
*/
- compatible = "arm,coresight-replicator";
+ compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
@@ -175,7 +175,7 @@
ranges;
funnel@30041000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x30041000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
@@ -217,7 +217,7 @@
};
funnel@30083000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x30083000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
@@ -551,6 +551,10 @@
tempmon_temp_grade: temp-grade@10 {
reg = <0x10 0x4>;
};
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 0x4>;
+ };
};
anatop: anatop@30360000 {
@@ -609,6 +613,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
+ status = "disabled";
};
};
diff --git a/dts/src/arm/imx7ulp-evk.dts b/dts/src/arm/imx7ulp-evk.dts
index a09026a..4245b33 100644
--- a/dts/src/arm/imx7ulp-evk.dts
+++ b/dts/src/arm/imx7ulp-evk.dts
@@ -22,6 +22,25 @@
reg = <0x60000000 0x40000000>;
};
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&tpm4 1 50000 0>;
+ brightness-levels = <0 20 25 30 35 40 100>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_vsd_3v3: regulator-vsd-3v3 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
@@ -40,6 +59,23 @@
status = "okay";
};
+&tpm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ over-current-active-low;
+ status = "okay";
+};
+
&usdhc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
@@ -57,6 +93,25 @@
bias-pull-up;
};
+ pinctrl_pwm0: pwm0grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTF2__TPM4_CH1 0x2
+ >;
+ };
+
+ pinctrl_usbotg1_vbus: otg1vbusgrp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC0__PTC0 0x20000
+ >;
+ };
+
+ pinctrl_usbotg1_id: otg1idgrp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC13__USB0_ID 0x10003
+ IMX7ULP_PAD_PTC16__USB1_OC2 0x10003
+ >;
+ };
+
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
diff --git a/dts/src/arm/imx7ulp.dtsi b/dts/src/arm/imx7ulp.dtsi
index d6b7110..992747a 100644
--- a/dts/src/arm/imx7ulp.dtsi
+++ b/dts/src/arm/imx7ulp.dtsi
@@ -30,6 +30,7 @@
serial1 = &lpuart5;
serial2 = &lpuart6;
serial3 = &lpuart7;
+ usbphy0 = &usbphy1;
};
cpus {
@@ -100,6 +101,29 @@
reg = <0x40000000 0x800000>;
ranges;
+ crypto: crypto@40240000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40240000 0x10000>;
+ ranges = <0 0x40240000 0x10000>;
+ clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
+ <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
+ clock-names = "aclk", "ipg";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
lpuart4: serial@402d0000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x402d0000 0x1000>;
@@ -124,6 +148,16 @@
status = "disabled";
};
+ tpm4: pwm@40250000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x40250000 0x1000>;
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+ clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
@@ -133,6 +167,33 @@
clock-names = "ipg", "per";
};
+ usbotg1: usb@40330000 {
+ compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
+ reg = <0x40330000 0x200>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc2 IMX7ULP_CLK_USB0>;
+ phys = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x8>;
+ rx-burst-size-dword = <0x8>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@40330200 {
+ compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
+ #index-cells = <1>;
+ reg = <0x40330200 0x200>;
+ };
+
+ usbphy1: usb-phy@0x40350000 {
+ compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
+ reg = <0x40350000 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
+ #phy-cells = <0>;
+ };
+
usdhc0: mmc@40370000 {
compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
reg = <0x40370000 0x10000>;
diff --git a/dts/src/arm/integrator.dtsi b/dts/src/arm/integrator.dtsi
index 1612a86..602f74d 100644
--- a/dts/src/arm/integrator.dtsi
+++ b/dts/src/arm/integrator.dtsi
@@ -62,6 +62,9 @@
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x24000000 0x02000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
fpga {
diff --git a/dts/src/arm/iwg20d-q7-common.dtsi b/dts/src/arm/iwg20d-q7-common.dtsi
index e2b1ab9..ae75a1d 100644
--- a/dts/src/arm/iwg20d-q7-common.dtsi
+++ b/dts/src/arm/iwg20d-q7-common.dtsi
@@ -87,7 +87,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
- gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
diff --git a/dts/src/arm/logicpd-torpedo-37xx-devkit-28.dts b/dts/src/arm/logicpd-torpedo-37xx-devkit-28.dts
new file mode 100644
index 0000000..07ac99b
--- /dev/null
+++ b/dts/src/arm/logicpd-torpedo-37xx-devkit-28.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+/*
+ * There are two types of 4.3" LCD, Type 15 and Type 28.
+ * By default, type 15 was used. This device tree file
+ * uses the timing for the type 28 LCD
+ */
+
+#include "logicpd-torpedo-37xx-devkit.dts"
+
+&lcd0 {
+
+ label = "28";
+
+ panel-timing {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <3>;
+ hback-porch = <2>;
+ hsync-len = <42>;
+ vback-porch = <3>;
+ vfront-porch = <2>;
+ vsync-len = <11>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+};
diff --git a/dts/src/arm/ls1021a-tsn.dts b/dts/src/arm/ls1021a-tsn.dts
new file mode 100644
index 0000000..5b76890
--- /dev/null
+++ b/dts/src/arm/ls1021a-tsn.dts
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2016-2018 NXP Semiconductors
+ * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+ model = "NXP LS1021A-TSN Board";
+
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ reg_vdda_codec: regulator-3V3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_vddio_codec: regulator-2V5 {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ /* ADG704BRMZ 1:4 SPI mux/demux */
+ sja1105: ethernet-switch@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,sja1105t";
+ /* 12 MHz */
+ spi-max-frequency = <12000000>;
+ /* Sample data on trailing clock edge */
+ spi-cpha;
+ /* SPI controller settings for SJA1105 timing requirements */
+ fsl,spi-cs-sck-delay = <1000>;
+ fsl,spi-sck-cs-delay = <1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ /* ETH5 written on chassis */
+ label = "swp5";
+ phy-handle = <&rgmii_phy6>;
+ phy-mode = "rgmii-id";
+ reg = <0>;
+ };
+
+ port@1 {
+ /* ETH2 written on chassis */
+ label = "swp2";
+ phy-handle = <&rgmii_phy3>;
+ phy-mode = "rgmii-id";
+ reg = <1>;
+ };
+
+ port@2 {
+ /* ETH3 written on chassis */
+ label = "swp3";
+ phy-handle = <&rgmii_phy4>;
+ phy-mode = "rgmii-id";
+ reg = <2>;
+ };
+
+ port@3 {
+ /* ETH4 written on chassis */
+ label = "swp4";
+ phy-handle = <&rgmii_phy5>;
+ phy-mode = "rgmii-id";
+ reg = <3>;
+ };
+
+ port@4 {
+ /* Internal port connected to eth2 */
+ ethernet = <&enet2>;
+ phy-mode = "rgmii";
+ reg = <4>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy2>;
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy1>;
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+/* RGMII delays added via PCB traces */
+&enet2 {
+ phy-mode = "rgmii";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&esdhc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ /* 3 axis accelerometer */
+ accelerometer@1e {
+ compatible = "fsl,fxls8471";
+ position = <0>;
+ reg = <0x1e>;
+ };
+
+ /* Audio codec (SAI2) */
+ audio-codec@2a {
+ compatible = "fsl,sgtl5000";
+ VDDIO-supply = <&reg_vddio_codec>;
+ VDDA-supply = <&reg_vdda_codec>;
+ #sound-dai-cells = <0>;
+ clocks = <&sys_mclk>;
+ reg = <0x2a>;
+ };
+
+ /* Current sensing circuit for 1V VDDCORE PMIC rail */
+ current-sensor@44 {
+ compatible = "ti,ina220";
+ shunt-resistor = <1000>;
+ reg = <0x44>;
+ };
+
+ /* Current sensing circuit for 12V VCC rail */
+ current-sensor@45 {
+ compatible = "ti,ina220";
+ shunt-resistor = <1000>;
+ reg = <0x45>;
+ };
+
+ /* Thermal monitor - case */
+ temperature-sensor@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ };
+
+ /* Thermal monitor - chip */
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ };
+
+ /* Unsupported devices:
+ * - FXAS21002C Gyroscope at 0x20
+ * - TI ADS7924 4-channel ADC at 0x49
+ */
+};
+
+&ifc {
+ status = "disabled";
+};
+
+&lpuart0 {
+ status = "okay";
+};
+
+&lpuart3 {
+ status = "okay";
+};
+
+&mdio0 {
+ /* AR8031 */
+ sgmii_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ /* AR8031 */
+ sgmii_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ /* BCM5464 quad PHY */
+ rgmii_phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+
+ rgmii_phy4: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+
+ rgmii_phy5: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+
+ rgmii_phy6: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+
+ /* SGMII PCS for enet0 */
+ tbi0: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&mdio1 {
+ /* SGMII PCS for enet1 */
+ tbi1: tbi-phy@1f {
+ reg = <0x1f>;
+ device_type = "tbi-phy";
+ };
+};
+
+&qspi {
+ status = "okay";
+
+ flash@0 {
+ /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */
+ compatible = "jedec,spi-nor", "s25fl256s1", "s25fl512s";
+ spi-max-frequency = <20000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "RCW";
+ reg = <0x0 0x40000>;
+ };
+
+ partition@40000 {
+ label = "U-Boot";
+ reg = <0x40000 0x300000>;
+ };
+
+ partition@340000 {
+ label = "U-Boot Env";
+ reg = <0x340000 0x100000>;
+ };
+ };
+ };
+};
+
+&sai2 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/meson.dtsi b/dts/src/arm/meson.dtsi
index 8841783..c4447f6 100644
--- a/dts/src/arm/meson.dtsi
+++ b/dts/src/arm/meson.dtsi
@@ -1,48 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2014 Carlo Caione <carlo@caione.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this library; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/dts/src/arm/meson6-atv1200.dts b/dts/src/arm/meson6-atv1200.dts
index 997e69c..98e1c94 100644
--- a/dts/src/arm/meson6-atv1200.dts
+++ b/dts/src/arm/meson6-atv1200.dts
@@ -1,48 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2014 Carlo Caione <carlo@caione.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this library; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/dts/src/arm/meson6.dtsi b/dts/src/arm/meson6.dtsi
index 6558525..2d31b7c 100644
--- a/dts/src/arm/meson6.dtsi
+++ b/dts/src/arm/meson6.dtsi
@@ -1,48 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2014 Carlo Caione <carlo@caione.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this library; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson.dtsi"
diff --git a/dts/src/arm/meson8-minix-neo-x8.dts b/dts/src/arm/meson8-minix-neo-x8.dts
index 8686abd..61ec929 100644
--- a/dts/src/arm/meson8-minix-neo-x8.dts
+++ b/dts/src/arm/meson8-minix-neo-x8.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2014 Beniamino Galvani <b.galvani@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/dts/src/arm/meson8.dtsi b/dts/src/arm/meson8.dtsi
index 40c11b6..5a7e3e5 100644
--- a/dts/src/arm/meson8.dtsi
+++ b/dts/src/arm/meson8.dtsi
@@ -1,46 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2014 Carlo Caione <carlo@caione.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/meson8b-clkc.h>
@@ -228,6 +188,28 @@
};
};
+ mmcbus: bus@c8000000 {
+ compatible = "simple-bus";
+ reg = <0xc8000000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc8000000 0x8000>;
+
+ dmcbus: bus@6000 {
+ compatible = "simple-bus";
+ reg = <0x6000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x400>;
+
+ canvas: video-lut@20 {
+ compatible = "amlogic,meson8-canvas",
+ "amlogic,canvas";
+ reg = <0x20 0x14>;
+ };
+ };
+ };
+
apb: bus@d0000000 {
compatible = "simple-bus";
reg = <0xd0000000 0x200000>;
diff --git a/dts/src/arm/meson8b-ec100.dts b/dts/src/arm/meson8b-ec100.dts
index 9bf4249..96d239d 100644
--- a/dts/src/arm/meson8b-ec100.dts
+++ b/dts/src/arm/meson8b-ec100.dts
@@ -234,10 +234,6 @@
phy-handle = <&eth_phy0>;
phy-mode = "rmii";
- snps,reset-gpio = <&gpio GPIOH_4 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -246,6 +242,11 @@
eth_phy0: ethernet-phy@0 {
/* IC Plus IP101A/G (0x02430c54) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
icplus,select-interrupt;
interrupt-parent = <&gpio_intc>;
/* GPIOH_3 */
diff --git a/dts/src/arm/meson8b-mxq.dts b/dts/src/arm/meson8b-mxq.dts
index 08ddd7f..bb27b34 100644
--- a/dts/src/arm/meson8b-mxq.dts
+++ b/dts/src/arm/meson8b-mxq.dts
@@ -1,50 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2015 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
#include "meson8b.dtsi"
/ {
@@ -63,6 +26,127 @@
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&saradc 8>;
+ };
+
+ vcck: regulator-vcck {
+ compatible = "pwm-regulator";
+
+ regulator-name = "VCCK";
+ regulator-min-microvolt = <860000>;
+ regulator-max-microvolt = <1140000>;
+
+ pwms = <&pwm_cd 0 1148 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc1v8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ vin-supply = <&vcc_3v3>;
+ };
+
+ vcc_3v3: regulator-vcc3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vcc_5v>;
+ };
+
+ vcc_5v: regulator-vcc5v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vcck>;
+};
+
+&ethmac {
+ status = "okay";
+
+ pinctrl-0 = <&eth_rmii_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&eth_phy0>;
+ phy-mode = "rmii";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ /* IC Plus IP101A/G (0x02430c54) */
+ reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
+ icplus,select-interrupt;
+ interrupt-parent = <&gpio_intc>;
+ /* GPIOH_3 */
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vcc_1v8>;
+};
+
+&sdio {
+ status = "okay";
+
+ pinctrl-0 = <&sd_b_pins>;
+ pinctrl-names = "default";
+
+ /* SD card */
+ sd_card_slot: slot@1 {
+ compatible = "mmc-slot";
+ reg = <1>;
+ status = "okay";
+
+ bus-width = <4>;
+ no-sdio;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vcc_3v3>;
+ };
+};
+
+&pwm_cd {
+ status = "okay";
+ pinctrl-0 = <&pwm_c1_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_XTAL>;
+ clock-names = "clkin0";
};
&uart_AO {
@@ -70,3 +154,19 @@
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
diff --git a/dts/src/arm/meson8b-odroidc1.dts b/dts/src/arm/meson8b-odroidc1.dts
index f3ad939..86c4614 100644
--- a/dts/src/arm/meson8b-odroidc1.dts
+++ b/dts/src/arm/meson8b-odroidc1.dts
@@ -1,47 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2015 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -216,10 +176,6 @@
&ethmac {
status = "okay";
- snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 30000>;
-
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
@@ -235,6 +191,11 @@
/* Realtek RTL8211F (0x001cc916) */
eth_phy: ethernet-phy@0 {
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+
interrupt-parent = <&gpio_intc>;
/* GPIOH_3 */
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/src/arm/meson8b.dtsi b/dts/src/arm/meson8b.dtsi
index ec67f49..fba2c70 100644
--- a/dts/src/arm/meson8b.dtsi
+++ b/dts/src/arm/meson8b.dtsi
@@ -1,47 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2015 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/meson8b-clkc.h>
@@ -205,6 +165,28 @@
};
};
+ mmcbus: bus@c8000000 {
+ compatible = "simple-bus";
+ reg = <0xc8000000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc8000000 0x8000>;
+
+ dmcbus: bus@6000 {
+ compatible = "simple-bus";
+ reg = <0x6000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x6000 0x400>;
+
+ canvas: video-lut@48 {
+ compatible = "amlogic,meson8b-canvas",
+ "amlogic,canvas";
+ reg = <0x48 0x14>;
+ };
+ };
+ };
+
apb: bus@d0000000 {
compatible = "simple-bus";
reg = <0xd0000000 0x200000>;
diff --git a/dts/src/arm/meson8m2-mxiii-plus.dts b/dts/src/arm/meson8m2-mxiii-plus.dts
index 29d830a..d54477b 100644
--- a/dts/src/arm/meson8m2-mxiii-plus.dts
+++ b/dts/src/arm/meson8m2-mxiii-plus.dts
@@ -73,10 +73,6 @@
amlogic,tx-delay-ns = <4>;
- snps,reset-gpio = <&gpio GPIOH_4 0>;
- snps,reset-delays-us = <0 10000 1000000>;
- snps,reset-active-low;
-
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
@@ -85,6 +81,10 @@
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
};
};
};
@@ -114,8 +114,9 @@
regulator-always-on;
};
- DCDC2 {
- regulator-name = "VDDAO";
+ vddee: DCDC2 {
+ /* the output is also used as VDDAO */
+ regulator-name = "VDD_EE";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
@@ -189,6 +190,10 @@
};
};
+&mali {
+ mali-supply = <&vddee>;
+};
+
&saradc {
status = "okay";
vref-supply = <&vddio_ao1v8>;
diff --git a/dts/src/arm/meson8m2.dtsi b/dts/src/arm/meson8m2.dtsi
index bb87b25..5bde7f5 100644
--- a/dts/src/arm/meson8m2.dtsi
+++ b/dts/src/arm/meson8m2.dtsi
@@ -14,6 +14,16 @@
compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
};
+&dmcbus {
+ /* the offset of the canvas registers has changed compared to Meson8 */
+ /delete-node/ video-lut@20;
+
+ canvas: video-lut@48 {
+ compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
+ reg = <0x48 0x14>;
+ };
+};
+
&ethmac {
compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
reg = <0xc9410000 0x10000
diff --git a/dts/src/arm/omap4-l4.dtsi b/dts/src/arm/omap4-l4.dtsi
index 5059eca..bea05dc 100644
--- a/dts/src/arm/omap4-l4.dtsi
+++ b/dts/src/arm/omap4-l4.dtsi
@@ -1371,7 +1371,6 @@
target-module@20000 { /* 0x48020000, ap 3 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart3";
reg = <0x20050 0x4>,
<0x20054 0x4>,
<0x20058 0x4>;
@@ -1728,7 +1727,6 @@
target-module@6a000 { /* 0x4806a000, ap 26 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart1";
reg = <0x6a050 0x4>,
<0x6a054 0x4>,
<0x6a058 0x4>;
@@ -1758,7 +1756,6 @@
target-module@6c000 { /* 0x4806c000, ap 28 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart2";
reg = <0x6c050 0x4>,
<0x6c054 0x4>,
<0x6c058 0x4>;
@@ -1788,7 +1785,6 @@
target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart4";
reg = <0x6e050 0x4>,
<0x6e054 0x4>,
<0x6e058 0x4>;
@@ -2107,7 +2103,6 @@
target-module@9c000 { /* 0x4809c000, ap 53 36.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc1";
reg = <0x9c000 0x4>,
<0x9c010 0x4>;
reg-names = "rev", "sysc";
@@ -2175,7 +2170,6 @@
target-module@ad000 { /* 0x480ad000, ap 63 50.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc3";
reg = <0xad000 0x4>,
<0xad010 0x4>;
reg-names = "rev", "sysc";
@@ -2241,7 +2235,6 @@
target-module@b4000 { /* 0x480b4000, ap 67 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc2";
reg = <0xb4000 0x4>,
<0xb4010 0x4>;
reg-names = "rev", "sysc";
@@ -2336,7 +2329,6 @@
target-module@d1000 { /* 0x480d1000, ap 73 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc4";
reg = <0xd1000 0x4>,
<0xd1010 0x4>;
reg-names = "rev", "sysc";
@@ -2369,7 +2361,6 @@
target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc5";
reg = <0xd5000 0x4>,
<0xd5010 0x4>;
reg-names = "rev", "sysc";
diff --git a/dts/src/arm/pxa300-raumfeld-common.dtsi b/dts/src/arm/pxa300-raumfeld-common.dtsi
index 8ac24e3..8a6721d 100644
--- a/dts/src/arm/pxa300-raumfeld-common.dtsi
+++ b/dts/src/arm/pxa300-raumfeld-common.dtsi
@@ -319,9 +319,9 @@
gpio_keys_pins: gpio-keys-pins {
pinctrl-single,pins = <
- MFP_PIN_PXA300(14) MFP_AF0 /* SCK */
- MFP_PIN_PXA300(115) MFP_AF0 /* MOSI */
- MFP_PIN_PXA300(119) MFP_AF0 /* MISO */
+ MFP_PIN_PXA300(14) MFP_AF0 /* on-off */
+ MFP_PIN_PXA300(115) MFP_AF0 /* rescue boot */
+ MFP_PIN_PXA300(119) MFP_AF0 /* setup */
>;
pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT);
};
diff --git a/dts/src/arm/pxa300-raumfeld-controller.dts b/dts/src/arm/pxa300-raumfeld-controller.dts
index 65d8250..12b1594 100644
--- a/dts/src/arm/pxa300-raumfeld-controller.dts
+++ b/dts/src/arm/pxa300-raumfeld-controller.dts
@@ -41,6 +41,8 @@
};
charger: charger {
+ pinctrl-names = "default";
+ pinctrl-0 = <&charger_pins>;
compatible = "gpio-charger";
charger-type = "mains";
gpios = <&gpio 101 GPIO_ACTIVE_LOW>;
@@ -109,9 +111,10 @@
};
&keys {
+ pinctrl-0 = <&gpio_keys_pins &dock_detect_pins>;
dock-detect {
label = "dock detect";
- gpios = <&gpio 116 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio 116 GPIO_ACTIVE_LOW>;
linux,code = <KEY_F5>;
};
};
@@ -236,6 +239,22 @@
pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT);
};
+ charger_pins: charger_pins {
+ pinctrl-single,pins = <
+ MFP_PIN_PXA300(31) MFP_AF0 /* PEN2 */
+ >;
+ pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH);
+ pinctrl-single,bias-pullup = MPF_PULL_UP;
+ };
+
+ dock_detect_pins: dock_detect_pins {
+ pinctrl-single,pins = <
+ MFP_PIN_PXA300(116) MFP_AF0 /* DOCK_DETECT */
+ >;
+ pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH);
+ pinctrl-single,bias-pullup = MPF_PULL_UP;
+ };
+
lcdc_pins: lcdc-pins {
pinctrl-single,pins = <
MFP_PIN_PXA300(54) MFP_AF1 /* LDD_0 */
diff --git a/dts/src/arm/pxa300-raumfeld-speaker-one.dts b/dts/src/arm/pxa300-raumfeld-speaker-one.dts
index 5f9e375..a70560a 100644
--- a/dts/src/arm/pxa300-raumfeld-speaker-one.dts
+++ b/dts/src/arm/pxa300-raumfeld-speaker-one.dts
@@ -116,6 +116,9 @@
st,invalid-input-detect-mute;
/* 2 (half-bridge) and 1 (full-bridge) on-board power */
st,output-conf = /bits/ 8 <0x1>;
+ st,ch1-output-mapping = /bits/ 8 <0>;
+ st,ch2-output-mapping = /bits/ 8 <1>;
+ st,ch3-output-mapping = /bits/ 8 <2>;
st,needs_esd_watchdog;
};
};
diff --git a/dts/src/arm/pxa3xx.dtsi b/dts/src/arm/pxa3xx.dtsi
index e1e607f..c237a0e 100644
--- a/dts/src/arm/pxa3xx.dtsi
+++ b/dts/src/arm/pxa3xx.dtsi
@@ -71,6 +71,14 @@
#define MFP_DS13X < (0x7 << 10) MFP_DSMSK >
/*
+ * MFP bias pull mode for pins.
+ * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP;
+ */
+#define MPF_PULL_MSK (0x7 << 13)
+#define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK >
+#define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK >
+
+/*
* MFP low power mode for pins.
* Example of use:
* pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL);
diff --git a/dts/src/arm/qcom-apq8064.dtsi b/dts/src/arm/qcom-apq8064.dtsi
index 65975df..8b79b41 100644
--- a/dts/src/arm/qcom-apq8064.dtsi
+++ b/dts/src/arm/qcom-apq8064.dtsi
@@ -1603,7 +1603,7 @@
};
replicator {
- compatible = "arm,coresight-replicator";
+ compatible = "arm,coresight-static-replicator";
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
@@ -1636,7 +1636,7 @@
};
funnel@1a04000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x1a04000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
diff --git a/dts/src/arm/qcom-msm8974-fairphone-fp2.dts b/dts/src/arm/qcom-msm8974-fairphone-fp2.dts
index 643c57f..bf402ae 100644
--- a/dts/src/arm/qcom-msm8974-fairphone-fp2.dts
+++ b/dts/src/arm/qcom-msm8974-fairphone-fp2.dts
@@ -50,6 +50,12 @@
};
};
+ vibrator {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&msmgpio 86 GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&pm8941_l18>;
+ };
+
smd {
rpm {
rpm_requests {
diff --git a/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts b/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts
index b3b0473..3487daf 100644
--- a/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/dts/src/arm/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -280,6 +280,16 @@
};
};
+ i2c2_pins: i2c2 {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
i2c3_pins: i2c3 {
mux {
pins = "gpio10", "gpio11";
@@ -289,6 +299,16 @@
};
};
+ i2c11_pins: i2c11 {
+ mux {
+ pins = "gpio83", "gpio84";
+ function = "blsp_i2c11";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
i2c12_pins: i2c12 {
mux {
pins = "gpio87", "gpio88";
@@ -306,6 +326,35 @@
input-enable;
};
};
+
+ touch_pin: touch {
+ int {
+ pins = "gpio5";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+
+ reset {
+ pins = "gpio8";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ panel_pin: panel {
+ te {
+ pins = "gpio12";
+ function = "mdp_vsync";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
};
sdhci@f9824900 {
@@ -369,6 +418,30 @@
};
};
+ i2c@f9967000 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c11_pins>;
+ clock-frequency = <355000>;
+ qcom,src-freq = <50000000>;
+
+ led-controller@38 {
+ compatible = "ti,lm3630a";
+ status = "ok";
+ reg = <0x38>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ led-sources = <0 1>;
+ label = "lcd-backlight";
+ default-brightness = <200>;
+ };
+ };
+ };
+
i2c@f9968000 {
status = "ok";
pinctrl-names = "default";
@@ -424,6 +497,41 @@
};
};
+ i2c@f9924000 {
+ status = "ok";
+
+ clock-frequency = <355000>;
+ qcom,src-freq = <50000000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ synaptics@70 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x70>;
+
+ interrupts-extended = <&msmgpio 5 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8941_l22>;
+ vio-supply = <&pm8941_lvs3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_pin>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
+ };
+
i2c@f9925000 {
status = "ok";
pinctrl-names = "default";
@@ -466,6 +574,54 @@
};
};
};
+
+ mdss@fd900000 {
+ status = "ok";
+
+ mdp@fd900000 {
+ status = "ok";
+ };
+
+ dsi@fd922800 {
+ status = "ok";
+
+ vdda-supply = <&pm8941_l2>;
+ vdd-supply = <&pm8941_lvs3>;
+ vddio-supply = <&pm8941_l12>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+
+ panel: panel@0 {
+ reg = <0>;
+ compatible = "lg,acx467akm-7";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_pin>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+
+ dsi-phy@fd922a00 {
+ status = "ok";
+
+ vddio-supply = <&pm8941_l12>;
+ };
+ };
};
&spmi_bus {
diff --git a/dts/src/arm/qcom-msm8974.dtsi b/dts/src/arm/qcom-msm8974.dtsi
index 45b5c8e..369e58f 100644
--- a/dts/src/arm/qcom-msm8974.dtsi
+++ b/dts/src/arm/qcom-msm8974.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
+#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
#include <dt-bindings/gpio/gpio.h>
@@ -897,7 +898,7 @@
};
funnel@fc31b000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0xfc31b000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
@@ -931,7 +932,7 @@
};
funnel@fc31a000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0xfc31a000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
@@ -969,7 +970,7 @@
};
funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0xfc345000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
@@ -1085,6 +1086,137 @@
};
};
};
+
+ mdss: mdss@fd900000 {
+ status = "disabled";
+
+ compatible = "qcom,mdss";
+ reg = <0xfd900000 0x100>,
+ <0xfd924000 0x1000>;
+ reg-names = "mdss_phys",
+ "vbif_phys";
+
+ power-domains = <&mmcc MDSS_GDSC>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "vsync";
+
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mdp: mdp@fd900000 {
+ status = "disabled";
+
+ compatible = "qcom,mdp5";
+ reg = <0xfd900100 0x22000>;
+ reg-names = "mdp_phys";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0 0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "vsync";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp5_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@fd922800 {
+ status = "disabled";
+
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0xfd922800 0x1f8>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
+ <&mmcc PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi_phy0 0>,
+ <&dsi_phy0 1>;
+
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>,
+ <&mmcc MDSS_ESC0_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core",
+ "core_mmss";
+
+ phys = <&dsi_phy0>;
+ phy-names = "dsi-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp5_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi_phy0: dsi-phy@fd922a00 {
+ status = "disabled";
+
+ compatible = "qcom,dsi-phy-28nm-hpm";
+ reg = <0xfd922a00 0xd4>,
+ <0xfd922b00 0x280>,
+ <0xfd922d80 0x30>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ qcom,dsi-phy-index = <0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>;
+ clock-names = "iface";
+ };
+ };
};
smd {
diff --git a/dts/src/arm/r7s72100-genmai.dts b/dts/src/arm/r7s72100-genmai.dts
index 474baa0..07d611d 100644
--- a/dts/src/arm/r7s72100-genmai.dts
+++ b/dts/src/arm/r7s72100-genmai.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/r7s72100-rskrza1.dts b/dts/src/arm/r7s72100-rskrza1.dts
index ff24301..99acfe4 100644
--- a/dts/src/arm/r7s72100-rskrza1.dts
+++ b/dts/src/arm/r7s72100-rskrza1.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
@@ -28,6 +29,37 @@
reg = <0x08000000 0x02000000>;
};
+ keyboard {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&keyboard_pins>;
+
+ key-1 {
+ interrupt-parent = <&irqc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_1>;
+ label = "SW1";
+ wakeup-source;
+ };
+
+ key-2 {
+ interrupt-parent = <&irqc>;
+ interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_2>;
+ label = "SW2";
+ wakeup-source;
+ };
+
+ key-3 {
+ interrupt-parent = <&irqc>;
+ interrupts = <5 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_3>;
+ label = "SW3";
+ wakeup-source;
+ };
+ };
+
lbsc {
#address-cells = <1>;
#size-cells = <1>;
@@ -101,6 +133,12 @@
<RZA1_PINMUX(1, 7, 1)>; /* RIIC3SDA */
};
+ keyboard_pins: keyboard {
+ pinmux = <RZA1_PINMUX(1, 9, 3)>, /* IRQ3 */
+ <RZA1_PINMUX(1, 8, 3)>, /* IRQ2 */
+ <RZA1_PINMUX(1, 11, 3)>; /* IRQ5 */
+ };
+
/* Serial Console */
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
diff --git a/dts/src/arm/r7s72100.dtsi b/dts/src/arm/r7s72100.dtsi
index 2211f88..d03dcd9 100644
--- a/dts/src/arm/r7s72100.dtsi
+++ b/dts/src/arm/r7s72100.dtsi
@@ -670,6 +670,25 @@
status = "disabled";
};
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc",
+ "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
+
mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
diff --git a/dts/src/arm/r7s9210-rza2mevb.dts b/dts/src/arm/r7s9210-rza2mevb.dts
index 991e09d..d062d02 100644
--- a/dts/src/arm/r7s9210-rza2mevb.dts
+++ b/dts/src/arm/r7s9210-rza2mevb.dts
@@ -9,6 +9,7 @@
/dts-v1/;
#include "r7s9210.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
/ {
@@ -17,6 +18,8 @@
aliases {
serial0 = &scif4;
+ ethernet0 = &ether0;
+ ethernet1 = &ether1;
};
chosen {
@@ -24,9 +27,19 @@
stdout-path = "serial0:115200n8";
};
- memory@40000000 {
- device_type = "memory";
- reg = <0x40000000 0x00800000>; /* HyperRAM */
+ keyboard {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&keyboard_pins>;
+
+ key-3 {
+ interrupt-parent = <&irqc>;
+ interrupts = <0 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_3>;
+ label = "SW3";
+ wakeup-source;
+ };
};
lbsc {
@@ -44,6 +57,41 @@
gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
};
};
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x00800000>; /* HyperRAM */
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ether0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth0_pins>;
+ status = "okay";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&ether1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth1_pins>;
+ status = "okay";
+ renesas,no-ether-link;
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
};
/* EXTAL */
@@ -51,26 +99,80 @@
clock-frequency = <24000000>; /* 24MHz */
};
-/* RTC_X1 */
-&rtc_x1_clk {
- clock-frequency = <32768>;
+/* High resolution System tick timers */
+&ostm0 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
};
&pinctrl {
+ eth0_pins: eth0 {
+ pinmux = <RZA2_PINMUX(PORTE, 0, 7)>, /* REF50CK0 */
+ <RZA2_PINMUX(PORT6, 1, 7)>, /* RMMI0_TXDEN */
+ <RZA2_PINMUX(PORT6, 2, 7)>, /* RMII0_TXD0 */
+ <RZA2_PINMUX(PORT6, 3, 7)>, /* RMII0_TXD1 */
+ <RZA2_PINMUX(PORTE, 4, 7)>, /* RMII0_CRSDV */
+ <RZA2_PINMUX(PORTE, 1, 7)>, /* RMII0_RXD0 */
+ <RZA2_PINMUX(PORTE, 2, 7)>, /* RMII0_RXD1 */
+ <RZA2_PINMUX(PORTE, 3, 7)>, /* RMII0_RXER */
+ <RZA2_PINMUX(PORTE, 5, 1)>, /* ET0_MDC */
+ <RZA2_PINMUX(PORTE, 6, 1)>, /* ET0_MDIO */
+ <RZA2_PINMUX(PORTL, 0, 5)>; /* IRQ4 */
+ };
+
+ eth1_pins: eth1 {
+ pinmux = <RZA2_PINMUX(PORTK, 3, 7)>, /* REF50CK1 */
+ <RZA2_PINMUX(PORTK, 0, 7)>, /* RMMI1_TXDEN */
+ <RZA2_PINMUX(PORTK, 1, 7)>, /* RMII1_TXD0 */
+ <RZA2_PINMUX(PORTK, 2, 7)>, /* RMII1_TXD1 */
+ <RZA2_PINMUX(PORT3, 2, 7)>, /* RMII1_CRSDV */
+ <RZA2_PINMUX(PORTK, 4, 7)>, /* RMII1_RXD0 */
+ <RZA2_PINMUX(PORT3, 5, 7)>, /* RMII1_RXD1 */
+ <RZA2_PINMUX(PORT3, 1, 7)>, /* RMII1_RXER */
+ <RZA2_PINMUX(PORT3, 3, 1)>, /* ET1_MDC */
+ <RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */
+ <RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
+ };
+
+ keyboard_pins: keyboard {
+ pinmux = <RZA2_PINMUX(PORTJ, 1, 6)>; /* IRQ0 */
+ };
+
/* Serial Console */
scif4_pins: serial4 {
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
};
-};
-/* High resolution System tick timers */
-&ostm0 {
- status = "okay";
+ sdhi0_pins: sdhi0 {
+ pinmux = <RZA2_PINMUX(PORT5, 0, 3)>, /* SD0_CD */
+ <RZA2_PINMUX(PORT5, 1, 3)>; /* SD0_WP */
+ };
+
+ sdhi1_pins: sdhi1 {
+ pinmux = <RZA2_PINMUX(PORT5, 4, 3)>, /* SD1_CD */
+ <RZA2_PINMUX(PORT5, 5, 3)>; /* SD1_WP */
+ };
+
+ usb0_pins: usb0 {
+ pinmux = <RZA2_PINMUX(PORT5, 2, 3)>, /* VBUSIN0 */
+ <RZA2_PINMUX(PORTC, 6, 1)>, /* VBUSEN0 */
+ <RZA2_PINMUX(PORTC, 7, 1)>; /* OVRCUR0 */
+ };
+
+ usb1_pins: usb1 {
+ pinmux = <RZA2_PINMUX(PORTC, 0, 1)>, /* VBUSIN1 */
+ <RZA2_PINMUX(PORTC, 5, 1)>, /* VBUSEN1 */
+ <RZA2_PINMUX(PORT7, 5, 5)>; /* OVRCUR1 */
+ };
};
-&ostm1 {
- status = "okay";
+/* RTC_X1 */
+&rtc_x1_clk {
+ clock-frequency = <32768>;
};
/* Serial Console */
@@ -80,3 +182,38 @@
status = "okay";
};
+
+&sdhi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhi0_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhi1_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* USB-0 as Host */
+&usb2_phy0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins>;
+ dr_mode = "host"; /* Requires JP3 to be fitted */
+ status = "okay";
+};
+
+/* USB-1 as Host */
+&usb2_phy1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* USB_X1 */
+&usb_x1_clk {
+ clock-frequency = <48000000>;
+};
diff --git a/dts/src/arm/r7s9210.dtsi b/dts/src/arm/r7s9210.dtsi
index 22baa96..72b7977 100644
--- a/dts/src/arm/r7s9210.dtsi
+++ b/dts/src/arm/r7s9210.dtsi
@@ -30,6 +30,13 @@
clock-frequency = <0>;
};
+ usb_x1_clk: usb_x1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ /* If clk present, value (48000000) must be set by board */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -146,6 +153,152 @@
status = "disabled";
};
+ spi0: spi@e800c800 {
+ compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
+ reg = <0xe800c800 0x24>;
+ interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD 97>;
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@e800d000 {
+ compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
+ reg = <0xe800d000 0x24>;
+ interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD 96>;
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@e800d800 {
+ compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
+ reg = <0xe800d800 0x24>;
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD 95>;
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ether0: ethernet@e8204000 {
+ compatible = "renesas,ether-r7s9210";
+ reg = <0xe8204000 0x200>;
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 65>;
+ power-domains = <&cpg>;
+
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ether1: ethernet@e8204200 {
+ compatible = "renesas,ether-r7s9210";
+ reg = <0xe8204200 0x200>;
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 64>;
+ power-domains = <&cpg>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@e803a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
+ reg = <0xe803a000 0x44>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 87>;
+ power-domains = <&cpg>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e803a400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
+ reg = <0xe803a400 0x44>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 86>;
+ power-domains = <&cpg>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e803a800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
+ reg = <0xe803a800 0x44>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 85>;
+ power-domains = <&cpg>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e803ac00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
+ reg = <0xe803ac00 0x44>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 84>;
+ power-domains = <&cpg>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
ostm0: timer@e803b000 {
compatible = "renesas,r7s9210-ostm", "renesas,ostm";
reg = <0xe803b000 0x30>;
@@ -176,6 +329,120 @@
status = "disabled";
};
+ ohci0: usb@e8218000 {
+ compatible = "generic-ohci";
+ reg = <0xe8218000 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 61>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@e8218100 {
+ compatible = "generic-ehci";
+ reg = <0xe8218100 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 61>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@e8218200 {
+ compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
+ reg = <0xe8218200 0x700>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>;
+ clock-names = "fck", "usb_x1";
+ power-domains = <&cpg>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbhs0: usb@e8219000 {
+ compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
+ reg = <0xe8219000 0x724>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 61>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@e821a000 {
+ compatible = "generic-ohci";
+ reg = <0xe821a000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 60>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@e821a100 {
+ compatible = "generic-ehci";
+ reg = <0xe821a100 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 60>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@e821a200 {
+ compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
+ reg = <0xe821a200 0x700>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>;
+ clock-names = "fck", "usb_x1";
+ power-domains = <&cpg>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usbhs1: usb@e821b000 {
+ compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
+ reg = <0xe821b000 0x724>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 60>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sdhi0: sd@e8228000 {
+ compatible = "renesas,sdhi-r7s9210";
+ reg = <0xe8228000 0x8c0>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>;
+ clock-names = "core", "cd";
+ power-domains = <&cpg>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ status = "disabled";
+ };
+
+ sdhi1: sd@e822a000 {
+ compatible = "renesas,sdhi-r7s9210";
+ reg = <0xe822a000 0x8c0>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>;
+ clock-names = "core", "cd";
+ power-domains = <&cpg>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ status = "disabled";
+ };
+
gic: interrupt-controller@e8221000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -206,6 +473,25 @@
reg = <0xfcfe8004 4>;
};
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s9210-irqc",
+ "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
+
pinctrl: pin-controller@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;
diff --git a/dts/src/arm/r8a73a4-ape6evm.dts b/dts/src/arm/r8a73a4-ape6evm.dts
index f70f4a3..a5351dd 100644
--- a/dts/src/arm/r8a73a4-ape6evm.dts
+++ b/dts/src/arm/r8a73a4-ape6evm.dts
@@ -19,7 +19,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/r8a7740-armadillo800eva.dts b/dts/src/arm/r8a7740-armadillo800eva.dts
index 32757ca..758360a 100644
--- a/dts/src/arm/r8a7740-armadillo800eva.dts
+++ b/dts/src/arm/r8a7740-armadillo800eva.dts
@@ -21,7 +21,7 @@
};
chosen {
- bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=dhcp rw";
+ bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=on rw";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/r8a7743-sk-rzg1m.dts b/dts/src/arm/r8a7743-sk-rzg1m.dts
index ca0e0fc..807e7d0 100644
--- a/dts/src/arm/r8a7743-sk-rzg1m.dts
+++ b/dts/src/arm/r8a7743-sk-rzg1m.dts
@@ -17,7 +17,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/r8a7745-iwg22d-sodimm.dts b/dts/src/arm/r8a7745-iwg22d-sodimm.dts
index 1db220c..ce6603b 100644
--- a/dts/src/arm/r8a7745-iwg22d-sodimm.dts
+++ b/dts/src/arm/r8a7745-iwg22d-sodimm.dts
@@ -42,7 +42,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial3:115200n8";
};
diff --git a/dts/src/arm/r8a7745-sk-rzg1e.dts b/dts/src/arm/r8a7745-sk-rzg1e.dts
index 655b10b..db72a80 100644
--- a/dts/src/arm/r8a7745-sk-rzg1e.dts
+++ b/dts/src/arm/r8a7745-sk-rzg1e.dts
@@ -17,7 +17,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/r8a77470-iwg23s-sbc.dts b/dts/src/arm/r8a77470-iwg23s-sbc.dts
index 2840eb0..450efe9 100644
--- a/dts/src/arm/r8a77470-iwg23s-sbc.dts
+++ b/dts/src/arm/r8a77470-iwg23s-sbc.dts
@@ -18,7 +18,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial1:115200n8";
};
@@ -63,7 +63,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
- gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
diff --git a/dts/src/arm/r8a7778-bockw.dts b/dts/src/arm/r8a7778-bockw.dts
index 0b49956..6c7b07c 100644
--- a/dts/src/arm/r8a7778-bockw.dts
+++ b/dts/src/arm/r8a7778-bockw.dts
@@ -25,7 +25,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/r8a7779-marzen.dts b/dts/src/arm/r8a7779-marzen.dts
index d4bee1e..c755f0b 100644
--- a/dts/src/arm/r8a7779-marzen.dts
+++ b/dts/src/arm/r8a7779-marzen.dts
@@ -21,7 +21,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/r8a7790-lager.dts b/dts/src/arm/r8a7790-lager.dts
index 7b9508e..83cc619 100644
--- a/dts/src/arm/r8a7790-lager.dts
+++ b/dts/src/arm/r8a7790-lager.dts
@@ -56,7 +56,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
@@ -423,6 +423,8 @@
*/
i2cpwr: i2c-13 {
compatible = "i2c-demux-pinctrl";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
i2c-parent = <&iic3>, <&i2c3>;
i2c-bus-name = "i2c-pwr";
#address-cells = <1>;
@@ -615,6 +617,11 @@
function = "iic3";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
hsusb_pins: hsusb {
groups = "usb0_ovc_vbus";
function = "usb0";
diff --git a/dts/src/arm/r8a7790-stout.dts b/dts/src/arm/r8a7790-stout.dts
index 7a7d3b8..a315ba7 100644
--- a/dts/src/arm/r8a7790-stout.dts
+++ b/dts/src/arm/r8a7790-stout.dts
@@ -19,7 +19,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
@@ -179,6 +179,11 @@
function = "iic3";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
@@ -317,7 +322,7 @@
&iic3 {
pinctrl-names = "default";
- pinctrl-0 = <&iic3_pins>;
+ pinctrl-0 = <&iic3_pins &pmic_irq_pins>;
status = "okay";
pmic@58 {
diff --git a/dts/src/arm/r8a7791-koelsch.dts b/dts/src/arm/r8a7791-koelsch.dts
index e6580aa..af6bd8f 100644
--- a/dts/src/arm/r8a7791-koelsch.dts
+++ b/dts/src/arm/r8a7791-koelsch.dts
@@ -56,7 +56,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
@@ -540,6 +540,11 @@
function = "intc";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@@ -776,6 +781,8 @@
};
&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
status = "okay";
clock-frequency = <100000>;
diff --git a/dts/src/arm/r8a7791-porter.dts b/dts/src/arm/r8a7791-porter.dts
index fefdf82..d6cf16a 100644
--- a/dts/src/arm/r8a7791-porter.dts
+++ b/dts/src/arm/r8a7791-porter.dts
@@ -31,7 +31,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
@@ -228,6 +228,11 @@
function = "intc";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@@ -373,6 +378,8 @@
};
&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
status = "okay";
clock-frequency = <100000>;
diff --git a/dts/src/arm/r8a7792-blanche.dts b/dts/src/arm/r8a7792-blanche.dts
index b6fa80c..248eb71 100644
--- a/dts/src/arm/r8a7792-blanche.dts
+++ b/dts/src/arm/r8a7792-blanche.dts
@@ -21,7 +21,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
@@ -234,6 +234,11 @@
groups = "du1_rgb666", "du1_sync", "du1_disp";
function = "du1";
};
+
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
};
&rwdt {
@@ -314,6 +319,8 @@
pmic@58 {
compatible = "dlg,da9063";
reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
interrupt-parent = <&irqc>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
diff --git a/dts/src/arm/r8a7792-wheat.dts b/dts/src/arm/r8a7792-wheat.dts
index f46f456..bd2a63b 100644
--- a/dts/src/arm/r8a7792-wheat.dts
+++ b/dts/src/arm/r8a7792-wheat.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/r8a7792.dtsi b/dts/src/arm/r8a7792.dtsi
index 38fb43d..c4ea2d6 100644
--- a/dts/src/arm/r8a7792.dtsi
+++ b/dts/src/arm/r8a7792.dtsi
@@ -875,6 +875,40 @@
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
+
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7792-cmt0",
+ "renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7792-cmt1",
+ "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+
+ status = "disabled";
+ };
};
timer {
diff --git a/dts/src/arm/r8a7793-gose.dts b/dts/src/arm/r8a7793-gose.dts
index f51601a..42f3313 100644
--- a/dts/src/arm/r8a7793-gose.dts
+++ b/dts/src/arm/r8a7793-gose.dts
@@ -52,7 +52,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
@@ -514,6 +514,11 @@
function = "intc";
};
+ pmic_irq_pins: pmicirq {
+ groups = "intc_irq2";
+ function = "intc";
+ };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@@ -711,6 +716,8 @@
};
&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins>;
status = "okay";
clock-frequency = <100000>;
diff --git a/dts/src/arm/r8a7794-alt.dts b/dts/src/arm/r8a7794-alt.dts
index 0ab3d8d..1d22fcd 100644
--- a/dts/src/arm/r8a7794-alt.dts
+++ b/dts/src/arm/r8a7794-alt.dts
@@ -22,7 +22,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/r8a7794-silk.dts b/dts/src/arm/r8a7794-silk.dts
index 60e91eb..b3177ae 100644
--- a/dts/src/arm/r8a7794-silk.dts
+++ b/dts/src/arm/r8a7794-silk.dts
@@ -34,7 +34,7 @@
};
chosen {
- bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/rk322x.dtsi b/dts/src/arm/rk322x.dtsi
index da102ff..340ed6c 100644
--- a/dts/src/arm/rk322x.dtsi
+++ b/dts/src/arm/rk322x.dtsi
@@ -143,6 +143,11 @@
#clock-cells = <0>;
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
i2s1: i2s1@100b0000 {
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100b0000 0x4000>;
@@ -529,6 +534,17 @@
status = "disabled";
};
+ hdmi_phy: hdmi-phy@12030000 {
+ compatible = "rockchip,rk3228-hdmi-phy";
+ reg = <0x12030000 0x10000>;
+ clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
+ clock-names = "sysclk", "refoclk", "refpclk";
+ #clock-cells = <0>;
+ clock-output-names = "hdmiphy_phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
gpu: gpu@20000000 {
compatible = "rockchip,rk3228-mali", "arm,mali-400";
reg = <0x20000000 0x10000>;
@@ -572,6 +588,28 @@
status = "disabled";
};
+ vop: vop@20050000 {
+ compatible = "rockchip,rk3228-vop";
+ reg = <0x20050000 0x1ffc>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
+ reset-names = "axi", "ahb", "dclk";
+ iommus = <&vop_mmu>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_in_vop>;
+ };
+ };
+ };
+
vop_mmu: iommu@20053f00 {
compatible = "rockchip,iommu";
reg = <0x20053f00 0x100>;
@@ -579,7 +617,7 @@
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
+ #iommu-cells = <0>;
status = "disabled";
};
@@ -594,6 +632,36 @@
status = "disabled";
};
+ hdmi: hdmi@200a0000 {
+ compatible = "rockchip,rk3228-dw-hdmi";
+ reg = <0x200a0000 0x20000>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru SCLK_HDMI_PHY>;
+ assigned-clock-parents = <&hdmi_phy>;
+ clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
+ clock-names = "isfr", "iahb", "cec";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
+ resets = <&cru SRST_HDMI_P>;
+ reset-names = "hdmi";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi_in_vop: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
+ };
+ };
+
sdmmc: dwmmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
@@ -922,6 +990,21 @@
};
};
+ hdmi {
+ hdmi_hpd: hdmi-hpd {
+ rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
+ };
+
+ hdmii2c_xfer: hdmii2c-xfer {
+ rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
+ <0 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ hdmi_cec: hdmi-cec {
+ rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
diff --git a/dts/src/arm/rk3288-veyron-chromebook.dtsi b/dts/src/arm/rk3288-veyron-chromebook.dtsi
index fbef345..1cadb52 100644
--- a/dts/src/arm/rk3288-veyron-chromebook.dtsi
+++ b/dts/src/arm/rk3288-veyron-chromebook.dtsi
@@ -70,6 +70,21 @@
pinctrl-0 = <&ac_present_ap>;
};
+ lid_switch: lid-switch {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_lid_int_l>;
+
+ lid {
+ label = "Lid";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ debounce-interval = <1>;
+ };
+ };
+
panel: panel {
compatible ="innolux,n116bge", "simple-panel";
status = "okay";
@@ -149,18 +164,6 @@
status = "okay";
};
-&gpio_keys {
- pinctrl-0 = <&pwr_key_l &ap_lid_int_l>;
- lid {
- label = "Lid";
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
- wakeup-source;
- linux,code = <0>; /* SW_LID */
- linux,input-type = <5>; /* EV_SW */
- debounce-interval = <1>;
- };
-};
-
&pwm0 {
status = "okay";
};
@@ -234,6 +237,7 @@
/* Wake only */
&suspend_l_wake
+ &bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
@@ -243,6 +247,7 @@
/* Sleep only */
&suspend_l_sleep
+ &bt_dev_wake_sleep
>;
backlight {
diff --git a/dts/src/arm/rk3288-veyron-jaq.dts b/dts/src/arm/rk3288-veyron-jaq.dts
index e248f55..fcd1191 100644
--- a/dts/src/arm/rk3288-veyron-jaq.dts
+++ b/dts/src/arm/rk3288-veyron-jaq.dts
@@ -135,6 +135,213 @@
pinctrl-0 = <&vcc50_hdmi_en>;
};
+&gpio0 {
+ gpio-line-names = "PMIC_SLEEP_AP",
+ "DDRIO_PWROFF",
+ "DDRIO_RETEN",
+ "TS3A227E_INT_L",
+ "PMIC_INT_L",
+ "PWR_KEY_L",
+ "AP_LID_INT_L",
+ "EC_IN_RW",
+
+ "AC_PRESENT_AP",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
+ "OTP_OUT",
+ "HOST1_PWR_EN",
+ "USBOTG_PWREN_H",
+ "AP_WARM_RESET_H",
+ "nFALUT2",
+ "I2C0_SDA_PMIC",
+
+ "I2C0_SCL_PMIC",
+ "SUSPEND_L",
+ "USB_INT";
+};
+
+&gpio2 {
+ gpio-line-names = "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "",
+ "",
+ "",
+ "",
+ "CONFIG3",
+
+ "",
+ "EMMC_RST_L",
+ "",
+ "",
+ "BL_PWR_EN",
+ "AVDD_1V8_DISP_EN";
+};
+
+&gpio3 {
+ gpio-line-names = "FLASH0_D0",
+ "FLASH0_D1",
+ "FLASH0_D2",
+ "FLASH0_D3",
+ "FLASH0_D4",
+ "FLASH0_D5",
+ "FLASH0_D6",
+ "FLASH0_D7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "FLASH0_CS2/EMMC_CMD",
+ "",
+ "FLASH0_DQS/EMMC_CLKO";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "UART0_RXD",
+ "UART0_TXD",
+ "UART0_CTS",
+ "UART0_RTS",
+ "SDIO0_D0",
+ "SDIO0_D1",
+ "SDIO0_D2",
+ "SDIO0_D3",
+
+ "SDIO0_CMD",
+ "SDIO0_CLK",
+ "BT_DEV_WAKE", /* Maybe missing from mighty? */
+ "",
+ "WIFI_ENABLE_H",
+ "BT_ENABLE_L",
+ "WIFI_HOST_WAKE",
+ "BT_HOST_WAKE";
+};
+
+&gpio5 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "SPI0_CLK",
+ "SPI0_CS0",
+ "SPI0_TXD",
+ "SPI0_RXD",
+
+ "",
+ "",
+ "",
+ "VCC50_HDMI_EN";
+};
+
+&gpio6 {
+ gpio-line-names = "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI",
+ "I2S0_SDO0",
+ "HP_DET_H",
+ "ALS_INT",
+ "INT_CODEC",
+
+ "I2S0_CLK",
+ "I2C2_SDA",
+ "I2C2_SCL",
+ "MICDET",
+ "",
+ "",
+ "",
+ "",
+
+ "SDMMC_D0",
+ "SDMMC_D1",
+ "SDMMC_D2",
+ "SDMMC_D3",
+ "SDMMC_CLK",
+ "SDMMC_CMD";
+};
+
+&gpio7 {
+ gpio-line-names = "LCDC_BL",
+ "PWM_LOG",
+ "BL_EN",
+ "TRACKPAD_INT",
+ "TPM_INT_H",
+ "SDMMC_DET_L",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
+ "EC_INT",
+
+ "CPU_NMI",
+ "DVSOK",
+ "SDMMC_WP", /* mighty only */
+ "EDP_HPD",
+ "DVS1",
+ "nFALUT1", /* nFAULT1 on jaq */
+ "LCD_EN",
+ "DVS2",
+
+ "VCC5V_GOOD_H",
+ "I2C4_SDA_TP",
+ "I2C4_SCL_TP",
+ "I2C5_SDA_HDMI",
+ "I2C5_SCL_HDMI",
+ "5V_DRV",
+ "UART2_RXD",
+ "UART2_TXD";
+};
+
+&gpio8 {
+ gpio-line-names = "RAM_ID0",
+ "RAM_ID1",
+ "RAM_ID2",
+ "RAM_ID3",
+ "I2C1_SDA_TPM",
+ "I2C1_SCL_TPM",
+ "SPI2_CLK",
+ "SPI2_CS0",
+
+ "SPI2_RXD",
+ "SPI2_TXD";
+};
+
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
diff --git a/dts/src/arm/rk3288-veyron-jerry.dts b/dts/src/arm/rk3288-veyron-jerry.dts
index b1613af..164561f 100644
--- a/dts/src/arm/rk3288-veyron-jerry.dts
+++ b/dts/src/arm/rk3288-veyron-jerry.dts
@@ -103,6 +103,213 @@
pinctrl-0 = <&vcc50_hdmi_en>;
};
+&gpio0 {
+ gpio-line-names = "PMIC_SLEEP_AP",
+ "DDRIO_PWROFF",
+ "DDRIO_RETEN",
+ "TS3A227E_INT_L",
+ "PMIC_INT_L",
+ "PWR_KEY_L",
+ "AP_LID_INT_L",
+ "EC_IN_RW",
+
+ "AC_PRESENT_AP",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
+ "OTP_OUT",
+ "HOST1_PWR_EN",
+ "USBOTG_PWREN_H",
+ "AP_WARM_RESET_H",
+ "nFAULT2",
+ "I2C0_SDA_PMIC",
+
+ "I2C0_SCL_PMIC",
+ "SUSPEND_L",
+ "USB_INT";
+};
+
+&gpio2 {
+ gpio-line-names = "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "",
+ "",
+ "",
+ "",
+ "CONFIG3",
+
+ "",
+ "EMMC_RST_L",
+ "",
+ "",
+ "BL_PWR_EN",
+ "AVDD_1V8_DISP_EN";
+};
+
+&gpio3 {
+ gpio-line-names = "FLASH0_D0",
+ "FLASH0_D1",
+ "FLASH0_D2",
+ "FLASH0_D3",
+ "FLASH0_D4",
+ "FLASH0_D5",
+ "FLASH0_D6",
+ "FLASH0_D7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "FLASH0_CS2/EMMC_CMD",
+ "",
+ "FLASH0_DQS/EMMC_CLKO";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "UART0_RXD",
+ "UART0_TXD",
+ "UART0_CTS",
+ "UART0_RTS",
+ "SDIO0_D0",
+ "SDIO0_D1",
+ "SDIO0_D2",
+ "SDIO0_D3",
+
+ "SDIO0_CMD",
+ "SDIO0_CLK",
+ "BT_DEV_WAKE",
+ "",
+ "WIFI_ENABLE_H",
+ "BT_ENABLE_L",
+ "WIFI_HOST_WAKE",
+ "BT_HOST_WAKE";
+};
+
+&gpio5 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "SPI0_CLK",
+ "SPI0_CS0",
+ "SPI0_TXD",
+ "SPI0_RXD",
+
+ "",
+ "",
+ "",
+ "VCC50_HDMI_EN";
+};
+
+&gpio6 {
+ gpio-line-names = "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI",
+ "I2S0_SDO0",
+ "HP_DET_H",
+ "",
+ "INT_CODEC",
+
+ "I2S0_CLK",
+ "I2C2_SDA",
+ "I2C2_SCL",
+ "MICDET",
+ "",
+ "",
+ "",
+ "",
+
+ "SDMMC_D0",
+ "SDMMC_D1",
+ "SDMMC_D2",
+ "SDMMC_D3",
+ "SDMMC_CLK",
+ "SDMMC_CMD";
+};
+
+&gpio7 {
+ gpio-line-names = "LCDC_BL",
+ "PWM_LOG",
+ "BL_EN",
+ "TRACKPAD_INT",
+ "TPM_INT_H",
+ "SDMMC_DET_L",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
+ "EC_INT",
+
+ "CPU_NMI",
+ "DVSOK",
+ "",
+ "EDP_HPD",
+ "DVS1",
+ "nFAULT1",
+ "LCD_EN",
+ "DVS2",
+
+ "VCC5V_GOOD_H",
+ "I2C4_SDA_TP",
+ "I2C4_SCL_TP",
+ "I2C5_SDA_HDMI",
+ "I2C5_SCL_HDMI",
+ "5V_DRV",
+ "UART2_RXD",
+ "UART2_TXD";
+};
+
+&gpio8 {
+ gpio-line-names = "RAM_ID0",
+ "RAM_ID1",
+ "RAM_ID2",
+ "RAM_ID3",
+ "I2C1_SDA_TPM",
+ "I2C1_SCL_TPM",
+ "SPI2_CLK",
+ "SPI2_CS0",
+
+ "SPI2_RXD",
+ "SPI2_TXD";
+};
+
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
diff --git a/dts/src/arm/rk3288-veyron-mickey.dts b/dts/src/arm/rk3288-veyron-mickey.dts
index e852594..aa352d4 100644
--- a/dts/src/arm/rk3288-veyron-mickey.dts
+++ b/dts/src/arm/rk3288-veyron-mickey.dts
@@ -75,9 +75,7 @@
cooling-maps {
/*
* After 1st level, throttle the CPU down to as low as 1.4 GHz
- * and don't let the GPU go faster than 400 MHz. Note that we
- * won't throttle the GPU lower than 400 MHz due to CPU
- * heat--we'll let the GPU do the rest itself.
+ * and don't let the GPU go faster than 400 MHz.
*/
cpu_warm_limit_cpu {
trip = <&cpu_alert_warm>;
@@ -86,6 +84,10 @@
<&cpu2 THERMAL_NO_LIMIT 4>,
<&cpu3 THERMAL_NO_LIMIT 4>;
};
+ cpu_warm_limit_gpu {
+ trip = <&cpu_alert_warm>;
+ cooling-device = <&gpu 1 1>;
+ };
/*
* Add some discrete steps to help throttling system deal
@@ -125,11 +127,80 @@
<&cpu2 8 THERMAL_NO_LIMIT>,
<&cpu3 8 THERMAL_NO_LIMIT>;
};
+
+ /* At very hot, don't let GPU go over 300 MHz */
+ cpu_very_hot_limit_gpu {
+ trip = <&cpu_alert_very_hot>;
+ cooling-device = <&gpu 2 2>;
+ };
};
};
-&emmc {
- /delete-property/mmc-hs200-1_8v;
+&gpu_thermal {
+ /delete-node/ trips;
+ /delete-node/ cooling-maps;
+
+ trips {
+ gpu_alert_warmish: gpu_alert_warmish {
+ temperature = <60000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_alert_warm: gpu_alert_warm {
+ temperature = <65000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_alert_hotter: gpu_alert_hotter {
+ temperature = <84000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_alert_very_very_hot: gpu_alert_very_very_hot {
+ temperature = <86000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_crit: gpu_crit {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ /* After 1st level throttle the GPU down to as low as 400 MHz */
+ gpu_warmish_limit_gpu {
+ trip = <&gpu_alert_warmish>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT 1>;
+ };
+
+ /*
+ * Slightly after we throttle the GPU, we'll also make sure that
+ * the CPU can't go faster than 1.4 GHz. Note that we won't
+ * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll
+ * let the CPU do the rest itself.
+ */
+ gpu_warm_limit_cpu {
+ trip = <&gpu_alert_warm>;
+ cooling-device = <&cpu0 4 4>,
+ <&cpu1 4 4>,
+ <&cpu2 4 4>,
+ <&cpu3 4 4>;
+ };
+
+ /* When hot, GPU goes down to 300 MHz */
+ gpu_hotter_limit_gpu {
+ trip = <&gpu_alert_hotter>;
+ cooling-device = <&gpu 2 2>;
+ };
+
+ /* When really hot, don't let GPU go _above_ 300 MHz */
+ gpu_very_very_hot_limit_gpu {
+ trip = <&gpu_alert_very_very_hot>;
+ cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
+ };
+ };
};
&i2c2 {
@@ -142,8 +213,6 @@
&i2s {
status = "okay";
- clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
};
&rk808 {
@@ -183,6 +252,157 @@
};
};
+&gpio0 {
+ gpio-line-names = "PMIC_SLEEP_AP",
+ "",
+ "",
+ "",
+ "PMIC_INT_L",
+ "POWER_BUTTON_L",
+ "",
+ "",
+
+ "",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
+ "OT_RESET",
+ "",
+ "",
+ "AP_WARM_RESET_H",
+ "",
+ "I2C0_SDA_PMIC",
+
+ "I2C0_SCL_PMIC",
+ "",
+ "nFALUT";
+};
+
+&gpio2 {
+ gpio-line-names = "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "",
+ "",
+ "",
+ "",
+ "CONFIG3",
+
+ "",
+ "EMMC_RST_L";
+};
+
+&gpio3 {
+ gpio-line-names = "FLASH0_D0",
+ "FLASH0_D1",
+ "FLASH0_D2",
+ "FLASH0_D3",
+ "FLASH0_D4",
+ "FLASH0_D5",
+ "FLASH0_D6",
+ "FLASH0_D7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "FLASH0_CS2/EMMC_CMD",
+ "",
+ "FLASH0_DQS/EMMC_CLKO";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "UART0_RXD",
+ "UART0_TXD",
+ "UART0_CTS_L",
+ "UART0_RTS_L",
+ "SDIO0_D0",
+ "SDIO0_D1",
+ "SDIO0_D2",
+ "SDIO0_D3",
+
+ "SDIO0_CMD",
+ "SDIO0_CLK",
+ "BT_DEV_WAKE",
+ "",
+ "WIFI_ENABLE_H",
+ "BT_ENABLE_L",
+ "WIFI_HOST_WAKE",
+ "BT_HOST_WAKE";
+};
+
+&gpio7 {
+ gpio-line-names = "",
+ "PWM_LOG",
+ "",
+ "",
+ "TPM_INT_H",
+ "SDMMC_DET_L",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
+ "",
+
+ "CPU_NMI",
+ "DVSOK",
+ "HDMI_WAKE",
+ "POWER_HDMI_ON",
+ "DVS1",
+ "",
+ "",
+ "DVS2",
+
+ "HDMI_CEC",
+ "",
+ "",
+ "I2C5_SDA_HDMI",
+ "I2C5_SCL_HDMI",
+ "",
+ "UART2_RXD",
+ "UART2_TXD";
+};
+
+&gpio8 {
+ gpio-line-names = "RAM_ID0",
+ "RAM_ID1",
+ "RAM_ID2",
+ "RAM_ID3",
+ "I2C1_SDA_TPM",
+ "I2C1_SCL_TPM",
+ "SPI2_CLK",
+ "SPI2_CS0",
+
+ "SPI2_RXD",
+ "SPI2_TXD";
+};
+
&pinctrl {
hdmi {
power_hdmi_on: power-hdmi-on {
diff --git a/dts/src/arm/rk3288-veyron-minnie.dts b/dts/src/arm/rk3288-veyron-minnie.dts
index 468a181..9008e70 100644
--- a/dts/src/arm/rk3288-veyron-minnie.dts
+++ b/dts/src/arm/rk3288-veyron-minnie.dts
@@ -48,6 +48,26 @@
regulator-boot-on;
vin-supply = <&vcc18_wl>;
};
+
+ volume_buttons: volume-buttons {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&volum_down_l &volum_up_l>;
+
+ volum_down {
+ label = "Volum_down";
+ gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <100>;
+ };
+
+ volum_up {
+ label = "Volum_up";
+ gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <100>;
+ };
+ };
};
&backlight {
@@ -86,30 +106,6 @@
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
power-supply = <&backlight_regulator>;
- post-pwm-on-delay-ms = <200>;
- pwm-off-delay-ms = <200>;
-};
-
-&emmc {
- /delete-property/mmc-hs200-1_8v;
-};
-
-&gpio_keys {
- pinctrl-0 = <&pwr_key_l &ap_lid_int_l &volum_down_l &volum_up_l>;
-
- volum_down {
- label = "Volum_down";
- gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEDOWN>;
- debounce-interval = <100>;
- };
-
- volum_up {
- label = "Volum_up";
- gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_VOLUMEUP>;
- debounce-interval = <100>;
- };
};
&i2c_tunnel {
@@ -188,6 +184,218 @@
pinctrl-0 = <&vcc50_hdmi_en>;
};
+&gpio0 {
+ gpio-line-names = "PMIC_SLEEP_AP",
+ "DDRIO_PWROFF",
+ "DDRIO_RETEN",
+ "TS3A227E_INT_L",
+ "PMIC_INT_L",
+ "PWR_KEY_L",
+ "AP_LID_INT_L",
+ "EC_IN_RW",
+
+ "AC_PRESENT_AP",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
+ "OTP_OUT",
+ "HOST1_PWR_EN",
+ "USBOTG_PWREN_H",
+ "AP_WARM_RESET_H",
+ "nFALUT2",
+ "I2C0_SDA_PMIC",
+
+ "I2C0_SCL_PMIC",
+ "SUSPEND_L",
+ "USB_INT";
+};
+
+&gpio2 {
+ gpio-line-names = "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "",
+ "",
+ "",
+ "",
+ "CONFIG3",
+
+ "PROCHOT#",
+ "EMMC_RST_L",
+ "",
+ "",
+ "BL_PWR_EN",
+ "AVDD_1V8_DISP_EN",
+ "TOUCH_INT",
+ "TOUCH_RST",
+
+ "I2C3_SCL_TP",
+ "I2C3_SDA_TP";
+};
+
+&gpio3 {
+ gpio-line-names = "FLASH0_D0",
+ "FLASH0_D1",
+ "FLASH0_D2",
+ "FLASH0_D3",
+ "FLASH0_D4",
+ "FLASH0_D5",
+ "FLASH0_D6",
+ "FLASH0_D7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "FLASH0_CS2/EMMC_CMD",
+ "",
+ "FLASH0_DQS/EMMC_CLKO";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "UART0_RXD",
+ "UART0_TXD",
+ "UART0_CTS",
+ "UART0_RTS",
+ "SDIO0_D0",
+ "SDIO0_D1",
+ "SDIO0_D2",
+ "SDIO0_D3",
+
+ "SDIO0_CMD",
+ "SDIO0_CLK",
+ "dev_wake",
+ "",
+ "WIFI_ENABLE_H",
+ "BT_ENABLE_L",
+ "WIFI_HOST_WAKE",
+ "BT_HOST_WAKE";
+};
+
+&gpio5 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "Volum_Up#",
+ "Volum_Down#",
+ "SPI0_CLK",
+ "SPI0_CS0",
+ "SPI0_TXD",
+ "SPI0_RXD",
+
+ "",
+ "",
+ "",
+ "VCC50_HDMI_EN";
+};
+
+&gpio6 {
+ gpio-line-names = "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI",
+ "I2S0_SDO0",
+ "HP_DET_H",
+ "",
+ "INT_CODEC",
+
+ "I2S0_CLK",
+ "I2C2_SDA",
+ "I2C2_SCL",
+ "MICDET",
+ "",
+ "",
+ "",
+ "",
+
+ "SDMMC_D0",
+ "SDMMC_D1",
+ "SDMMC_D2",
+ "SDMMC_D3",
+ "SDMMC_CLK",
+ "SDMMC_CMD";
+};
+
+&gpio7 {
+ gpio-line-names = "LCDC_BL",
+ "PWM_LOG",
+ "BL_EN",
+ "TRACKPAD_INT",
+ "TPM_INT_H",
+ "SDMMC_DET_L",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
+ "EC_INT",
+
+ "CPU_NMI",
+ "DVS_OK",
+ "SDMMC_WP",
+ "EDP_HPD",
+ "DVS1",
+ "nFALUT1",
+ "LCD_EN",
+ "DVS2",
+
+ "VCC5V_GOOD_H",
+ "I2C4_SDA_TP",
+ "I2C4_SCL_TP",
+ "I2C5_SDA_HDMI",
+ "I2C5_SCL_HDMI",
+ "5V_DRV",
+ "UART2_RXD",
+ "UART2_TXD";
+};
+
+&gpio8 {
+ gpio-line-names = "RAM_ID0",
+ "RAM_ID1",
+ "RAM_ID2",
+ "RAM_ID3",
+ "I2C1_SDA_TPM",
+ "I2C1_SCL_TPM",
+ "SPI2_CLK",
+ "SPI2_CS0",
+
+ "SPI2_RXD",
+ "SPI2_TXD";
+};
+
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
diff --git a/dts/src/arm/rk3288-veyron-pinky.dts b/dts/src/arm/rk3288-veyron-pinky.dts
index 9645be7..9b6f4d9 100644
--- a/dts/src/arm/rk3288-veyron-pinky.dts
+++ b/dts/src/arm/rk3288-veyron-pinky.dts
@@ -35,7 +35,7 @@
force-hpd;
};
-&gpio_keys {
+&lid_switch {
pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
power {
diff --git a/dts/src/arm/rk3288-veyron-speedy.dts b/dts/src/arm/rk3288-veyron-speedy.dts
index 2ac8748..9b140db 100644
--- a/dts/src/arm/rk3288-veyron-speedy.dts
+++ b/dts/src/arm/rk3288-veyron-speedy.dts
@@ -64,6 +64,10 @@
temperature = <70000>;
};
+&cpu_crit {
+ temperature = <90000>;
+};
+
&edp {
/delete-property/pinctrl-names;
/delete-property/pinctrl-0;
@@ -71,6 +75,14 @@
force-hpd;
};
+&gpu_alert0 {
+ temperature = <80000>;
+};
+
+&gpu_crit {
+ temperature = <90000>;
+};
+
&panel {
power-supply= <&panel_regulator>;
};
@@ -101,6 +113,213 @@
pinctrl-0 = <&vcc50_hdmi_en>;
};
+&gpio0 {
+ gpio-line-names = "PMIC_SLEEP_AP",
+ "DDRIO_PWROFF",
+ "DDRIO_RETEN",
+ "TS3A227E_INT_L",
+ "PMIC_INT_L",
+ "PWR_KEY_L",
+ "AP_LID_INT_L",
+ "EC_IN_RW",
+
+ "AC_PRESENT_AP",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
+ "OTP_OUT",
+ "HOST1_PWR_EN",
+ "USBOTG_PWREN_H",
+ "AP_WARM_RESET_H",
+ "nFALUT2",
+ "I2C0_SDA_PMIC",
+
+ "I2C0_SCL_PMIC",
+ "SUSPEND_L",
+ "USB_INT";
+};
+
+&gpio2 {
+ gpio-line-names = "CONFIG0",
+ "CONFIG1",
+ "CONFIG2",
+ "",
+ "",
+ "",
+ "",
+ "CONFIG3",
+
+ "PWRLIMIT#_CPU",
+ "EMMC_RST_L",
+ "",
+ "",
+ "BL_PWR_EN",
+ "AVDD_1V8_DISP_EN";
+};
+
+&gpio3 {
+ gpio-line-names = "FLASH0_D0",
+ "FLASH0_D1",
+ "FLASH0_D2",
+ "FLASH0_D3",
+ "FLASH0_D4",
+ "FLASH0_D5",
+ "FLASH0_D6",
+ "FLASH0_D7",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "FLASH0_CS2/EMMC_CMD",
+ "",
+ "FLASH0_DQS/EMMC_CLKO";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "UART0_RXD",
+ "UART0_TXD",
+ "UART0_CTS",
+ "UART0_RTS",
+ "SDIO0_D0",
+ "SDIO0_D1",
+ "SDIO0_D2",
+ "SDIO0_D3",
+
+ "SDIO0_CMD",
+ "SDIO0_CLK",
+ "BT_DEV_WAKE",
+ "",
+ "WIFI_ENABLE_H",
+ "BT_ENABLE_L",
+ "WIFI_HOST_WAKE",
+ "BT_HOST_WAKE";
+};
+
+&gpio5 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "",
+ "",
+ "",
+ "",
+ "SPI0_CLK",
+ "SPI0_CS0",
+ "SPI0_TXD",
+ "SPI0_RXD",
+
+ "",
+ "",
+ "",
+ "VCC50_HDMI_EN";
+};
+
+&gpio6 {
+ gpio-line-names = "I2S0_SCLK",
+ "I2S0_LRCK_RX",
+ "I2S0_LRCK_TX",
+ "I2S0_SDI",
+ "I2S0_SDO0",
+ "HP_DET_H",
+ "ALS_INT", /* not connected */
+ "INT_CODEC",
+
+ "I2S0_CLK",
+ "I2C2_SDA",
+ "I2C2_SCL",
+ "MICDET",
+ "",
+ "",
+ "",
+ "",
+
+ "SDMMC_D0",
+ "SDMMC_D1",
+ "SDMMC_D2",
+ "SDMMC_D3",
+ "SDMMC_CLK",
+ "SDMMC_CMD";
+};
+
+&gpio7 {
+ gpio-line-names = "LCDC_BL",
+ "PWM_LOG",
+ "BL_EN",
+ "TRACKPAD_INT",
+ "TPM_INT_H",
+ "SDMMC_DET_L",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
+ "EC_INT",
+
+ "CPU_NMI",
+ "DVS_OK",
+ "",
+ "EDP_HOTPLUG",
+ "DVS1",
+ "nFALUT1",
+ "LCD_EN",
+ "DVS2",
+
+ "VCC5V_GOOD_H",
+ "I2C4_SDA_TP",
+ "I2C4_SCL_TP",
+ "I2C5_SDA_HDMI",
+ "I2C5_SCL_HDMI",
+ "5V_DRV",
+ "UART2_RXD",
+ "UART2_TXD";
+};
+
+&gpio8 {
+ gpio-line-names = "RAM_ID0",
+ "RAM_ID1",
+ "RAM_ID2",
+ "RAM_ID3",
+ "I2C1_SDA_TPM",
+ "I2C1_SCL_TPM",
+ "SPI2_CLK",
+ "SPI2_CS0",
+
+ "SPI2_RXD",
+ "SPI2_TXD";
+};
+
&pinctrl {
backlight {
bl_pwr_en: bl_pwr_en {
diff --git a/dts/src/arm/rk3288-veyron.dtsi b/dts/src/arm/rk3288-veyron.dtsi
index 1252522..8fc8eac 100644
--- a/dts/src/arm/rk3288-veyron.dtsi
+++ b/dts/src/arm/rk3288-veyron.dtsi
@@ -23,11 +23,36 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
- gpio_keys: gpio-keys {
+ bt_activity: bt-activity {
compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake>;
+
+ /*
+ * HACK: until we have an LPM driver, we'll use an
+ * ugly GPIO key to allow Bluetooth to wake from S3.
+ * This is expected to only be used by BT modules that
+ * use UART for comms. For BT modules that talk over
+ * SDIO we should use a wakeup mechanism related to SDIO.
+ *
+ * Use KEY_RESERVED here since that will work as a wakeup but
+ * doesn't get reported to higher levels (so doesn't confuse
+ * Chrome).
+ */
+ bt-wake {
+ label = "BT Wakeup";
+ gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_RESERVED>;
+ wakeup-source;
+ };
+
+ };
+ power_button: power-button {
+ compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pwr_key_l>;
+
power {
label = "Power";
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
@@ -123,6 +148,10 @@
cpu0-supply = <&vdd_cpu>;
};
+&cpu_crit {
+ temperature = <100000>;
+};
+
/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
&cpu_opp_table {
/delete-node/ opp-312000000;
@@ -162,8 +191,18 @@
status = "okay";
};
+&gpu_alert0 {
+ temperature = <72500>;
+};
+
+&gpu_crit {
+ temperature = <100000>;
+};
+
&hdmi {
- ddc-i2c-bus = <&i2c5>;
+ pinctrl-names = "default", "unwedge";
+ pinctrl-0 = <&hdmi_ddc>;
+ pinctrl-1 = <&hdmi_ddc_unwedge>;
status = "okay";
};
@@ -334,14 +373,6 @@
i2c-scl-rising-time-ns = <300>; /* 225ns measured */
};
-&i2c5 {
- status = "okay";
-
- clock-frequency = <100000>;
- i2c-scl-falling-time-ns = <300>;
- i2c-scl-rising-time-ns = <1000>;
-};
-
&io_domains {
status = "okay";
@@ -394,6 +425,7 @@
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-temp = <125000>;
};
&uart0 {
@@ -424,6 +456,7 @@
&usb_host1 {
status = "okay";
+ snps,need-phy-for-wake;
};
&usb_otg {
@@ -432,6 +465,7 @@
assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
assigned-clock-parents = <&usbphy0>;
dr_mode = "host";
+ snps,need-phy-for-wake;
};
&vopb {
@@ -453,12 +487,18 @@
&ddr0_retention
&ddrio_pwroff
&global_pwroff
+
+ /* Wake only */
+ &bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
+
+ /* Sleep only */
+ &bt_dev_wake_sleep
>;
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
@@ -542,6 +582,10 @@
rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
+ bt_host_wake: bt-host-wake {
+ rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
/*
* We run sdio0 at max speed; bump up drive strength.
* We also have external pulls, so disable the internal ones.
@@ -560,6 +604,20 @@
sdio0_clk: sdio0-clk {
rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
};
+
+ /*
+ * These pins are only present on very new veyron boards; on
+ * older boards bt_dev_wake is simply always high. Note that
+ * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
+ * to map this pin everywhere
+ */
+ bt_dev_wake_sleep: bt-dev-wake-sleep {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+
+ bt_dev_wake_awake: bt-dev-wake-awake {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
+ };
};
tpm {
diff --git a/dts/src/arm/rk3288.dtsi b/dts/src/arm/rk3288.dtsi
index aa017ab..cc893e1 100644
--- a/dts/src/arm/rk3288.dtsi
+++ b/dts/src/arm/rk3288.dtsi
@@ -231,6 +231,7 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
+ arm,no-tick-in-suspend;
};
timer: timer@ff810000 {
@@ -551,10 +552,7 @@
map0 {
trip = <&gpu_alert0>;
cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -682,7 +680,7 @@
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
- clocks = <&cru PCLK_PWM>;
+ clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
@@ -693,7 +691,7 @@
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
- clocks = <&cru PCLK_PWM>;
+ clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
@@ -704,7 +702,7 @@
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
- clocks = <&cru PCLK_PWM>;
+ clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
@@ -712,10 +710,10 @@
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
- clocks = <&cru PCLK_PWM>;
+ clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
@@ -1285,6 +1283,7 @@
interrupt-names = "job", "mmu", "gpu";
clocks = <&cru ACLK_GPU>;
operating-points-v2 = <&gpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
power-domains = <&power RK3288_PD_GPU>;
status = "disabled";
};
@@ -1308,10 +1307,6 @@
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1100000>;
};
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <1200000>;
- };
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1250000>;
@@ -1552,6 +1547,15 @@
rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
<7 RK_PC4 2 &pcfg_pull_none>;
};
+
+ hdmi_ddc_unwedge: hdmi-ddc-unwedge {
+ rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
+ <7 RK_PC4 2 &pcfg_pull_none>;
+ };
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
};
pcfg_pull_up: pcfg-pull-up {
diff --git a/dts/src/arm/sama5d3.dtsi b/dts/src/arm/sama5d3.dtsi
index 3bbc84b..f770aac 100644
--- a/dts/src/arm/sama5d3.dtsi
+++ b/dts/src/arm/sama5d3.dtsi
@@ -1371,30 +1371,11 @@
status = "disabled";
};
- sckc@fffffe50 {
- compatible = "atmel,at91sam9x5-sckc";
+ clk32k: sckc@fffffe50 {
+ compatible = "atmel,sama5d3-sckc";
reg = <0xfffffe50 0x4>;
-
- slow_rc_osc: slow_rc_osc {
- compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-accuracy = <50000000>;
- atmel,startup-time-usec = <75>;
- };
-
- slow_osc: slow_osc {
- compatible = "atmel,at91sam9x5-clk-slow-osc";
- #clock-cells = <0>;
- clocks = <&slow_xtal>;
- atmel,startup-time-usec = <1200000>;
- };
-
- clk32k: slowck {
- compatible = "atmel,at91sam9x5-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc &slow_osc>;
- };
+ clocks = <&slow_xtal>;
+ #clock-cells = <0>;
};
rtc@fffffeb0 {
diff --git a/dts/src/arm/sh73a0-kzm9g.dts b/dts/src/arm/sh73a0-kzm9g.dts
index daac0c6..1916f31 100644
--- a/dts/src/arm/sh73a0-kzm9g.dts
+++ b/dts/src/arm/sh73a0-kzm9g.dts
@@ -36,7 +36,7 @@
};
chosen {
- bootargs = "root=/dev/nfs ip=dhcp ignore_loglevel rw";
+ bootargs = "root=/dev/nfs ip=on ignore_loglevel rw";
stdout-path = "serial0:115200n8";
};
diff --git a/dts/src/arm/socfpga_arria10.dtsi b/dts/src/arm/socfpga_arria10.dtsi
index ae24599..a0a6d85 100644
--- a/dts/src/arm/socfpga_arria10.dtsi
+++ b/dts/src/arm/socfpga_arria10.dtsi
@@ -418,7 +418,7 @@
};
gmac0: ethernet@ff800000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+ compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
reg = <0xff800000 0x2000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -431,15 +431,15 @@
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
clock-names = "stmmaceth";
- resets = <&rst EMAC0_RESET>;
- reset-names = "stmmaceth";
+ resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
gmac1: ethernet@ff802000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x48 8>;
reg = <0xff802000 0x2000>;
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -451,15 +451,15 @@
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
clock-names = "stmmaceth";
- resets = <&rst EMAC1_RESET>;
- reset-names = "stmmaceth";
+ resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
gmac2: ethernet@ff804000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
+ compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
reg = <0xff804000 0x2000>;
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -470,8 +470,9 @@
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
clocks = <&l4_mp_clk>;
- resets = <&rst EMAC2_RESET>;
clock-names = "stmmaceth";
+ resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
diff --git a/dts/src/arm/socfpga_arria10_socdk.dtsi b/dts/src/arm/socfpga_arria10_socdk.dtsi
index 360dae5..0efbecc 100644
--- a/dts/src/arm/socfpga_arria10_socdk.dtsi
+++ b/dts/src/arm/socfpga_arria10_socdk.dtsi
@@ -48,6 +48,13 @@
};
};
+ ref_033v: 033-v-ref {
+ compatible = "regulator-fixed";
+ regulator-name = "0.33V";
+ regulator-min-microvolt = <330000>;
+ regulator-max-microvolt = <330000>;
+ };
+
soc {
clkmgr@ffd04000 {
clocks {
@@ -128,6 +135,18 @@
i2c-sda-falling-time-ns = <6000>;
i2c-scl-falling-time-ns = <6000>;
+ adc@14 {
+ compatible = "lltc,ltc2497";
+ reg = <0x14>;
+ vref-supply = <&ref_033v>;
+ };
+
+ adc@16 {
+ compatible = "lltc,ltc2497";
+ reg = <0x16>;
+ vref-supply = <&ref_033v>;
+ };
+
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
diff --git a/dts/src/arm/stm32746g-eval.dts b/dts/src/arm/stm32746g-eval.dts
index d90b0d1..2b16648 100644
--- a/dts/src/arm/stm32746g-eval.dts
+++ b/dts/src/arm/stm32746g-eval.dts
@@ -44,6 +44,7 @@
#include "stm32f746.dtsi"
#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "STMicroelectronics STM32746g-EVAL board";
@@ -69,9 +70,15 @@
gpios = <&gpiof 10 1>;
linux,default-trigger = "heartbeat";
};
+ orange {
+ gpios = <&stmfx_pinctrl 17 1>;
+ };
red {
gpios = <&gpiob 7 1>;
};
+ blue {
+ gpios = <&stmfx_pinctrl 19 1>;
+ };
};
gpio_keys {
@@ -86,6 +93,43 @@
};
};
+ joystick {
+ compatible = "gpio-keys";
+ #size-cells = <0>;
+ pinctrl-0 = <&joystick_pins>;
+ pinctrl-names = "default";
+ button-0 {
+ label = "JoySel";
+ linux,code = <KEY_ENTER>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ };
+ button-1 {
+ label = "JoyDown";
+ linux,code = <KEY_DOWN>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+ button-2 {
+ label = "JoyLeft";
+ linux,code = <KEY_LEFT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ };
+ button-3 {
+ label = "JoyRight";
+ linux,code = <KEY_RIGHT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ };
+ button-4 {
+ label = "JoyUp";
+ linux,code = <KEY_UP>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
@@ -115,6 +159,28 @@
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
+
+ stmfx: stmfx@42 {
+ compatible = "st,stmfx-0300";
+ reg = <0x42>;
+ interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpioi>;
+
+ stmfx_pinctrl: stmfx-pin-controller {
+ compatible = "st,stmfx-0300-pinctrl";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&stmfx_pinctrl 0 0 24>;
+
+ joystick_pins: joystick {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+ };
};
&rtc {
diff --git a/dts/src/arm/stm32mp157-pinctrl.dtsi b/dts/src/arm/stm32mp157-pinctrl.dtsi
index 85c417d..df64701 100644
--- a/dts/src/arm/stm32mp157-pinctrl.dtsi
+++ b/dts/src/arm/stm32mp157-pinctrl.dtsi
@@ -26,6 +26,7 @@
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
+ status = "disabled";
};
gpiob: gpio@50003000 {
@@ -38,6 +39,7 @@
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
+ status = "disabled";
};
gpioc: gpio@50004000 {
@@ -50,6 +52,7 @@
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
+ status = "disabled";
};
gpiod: gpio@50005000 {
@@ -62,6 +65,7 @@
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
+ status = "disabled";
};
gpioe: gpio@50006000 {
@@ -74,6 +78,7 @@
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
+ status = "disabled";
};
gpiof: gpio@50007000 {
@@ -86,6 +91,7 @@
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
+ status = "disabled";
};
gpiog: gpio@50008000 {
@@ -98,6 +104,7 @@
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
+ status = "disabled";
};
gpioh: gpio@50009000 {
@@ -110,6 +117,7 @@
st,bank-name = "GPIOH";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
+ status = "disabled";
};
gpioi: gpio@5000a000 {
@@ -122,6 +130,7 @@
st,bank-name = "GPIOI";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 128 16>;
+ status = "disabled";
};
gpioj: gpio@5000b000 {
@@ -134,6 +143,7 @@
st,bank-name = "GPIOJ";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 144 16>;
+ status = "disabled";
};
gpiok: gpio@5000c000 {
@@ -146,6 +156,7 @@
st,bank-name = "GPIOK";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
+ status = "disabled";
};
cec_pins_a: cec-0 {
@@ -178,6 +189,47 @@
};
};
+ dcmi_pins_a: dcmi-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_a: dcmi-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
+ };
+ };
+
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
@@ -241,6 +293,23 @@
};
};
+ i2c1_pins_b: i2c1-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_pins_sleep_b: i2c1-3 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
@@ -258,6 +327,21 @@
};
};
+ i2c2_pins_b1: i2c2-2 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_pins_sleep_b1: i2c2-3 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
i2c5_pins_a: i2c5-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
@@ -276,6 +360,25 @@
};
};
+ i2s2_pins_a: i2s2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ i2s2_pins_sleep_a: i2s2-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
+ };
+ };
+
ltdc_pins_a: ltdc-a-0 {
pins {
pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
@@ -470,6 +573,12 @@
};
};
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
qspi_bk1_pins_a: qspi-bk1-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
@@ -488,6 +597,16 @@
};
};
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
+ <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
qspi_bk2_pins_a: qspi-bk2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
@@ -506,6 +625,89 @@
};
};
+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
+ <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+ };
+ };
+
+ sai2a_pins_a: sai2a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai2a_sleep_pins_a: sai2a-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
+ };
+ };
+
+ sai2b_pins_a: sai2b-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_a: sai2b-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
+ };
+ };
+
+ sai2b_pins_b: sai2b-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_b: sai2b-3 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
+ };
+ };
+
+ sai4a_pins_a: sai4a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai4a_sleep_pins_a: sai4a-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
+ };
+ };
+
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -599,6 +801,34 @@
bias-disable;
};
};
+
+ uart4_pins_b: uart4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
+ <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
+ <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
+ bias-disable;
+ };
+ };
};
pinctrl_z: pin-controller-z@54004000 {
@@ -621,6 +851,22 @@
st,bank-ioport = <11>;
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
+ status = "disabled";
+ };
+
+ i2c2_pins_b2: i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_pins_sleep_b2: i2c2-1 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
+ };
};
i2c4_pins_a: i2c4-0 {
diff --git a/dts/src/arm/stm32mp157a-avenger96.dts b/dts/src/arm/stm32mp157a-avenger96.dts
new file mode 100644
index 0000000..2e4742c
--- /dev/null
+++ b/dts/src/arm/stm32mp157a-avenger96.dts
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c.dtsi"
+#include "stm32mp157xac-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ model = "Arrow Electronics STM32MP157A Avenger96 board";
+ compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
+
+ aliases {
+ ethernet0 = &ethernet0;
+ mmc0 = &sdmmc1;
+ serial0 = &uart4;
+ serial1 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x40000000>;
+ };
+
+ led {
+ compatible = "gpio-leds";
+ led1 {
+ label = "green:user1";
+ gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "green:user2";
+ gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "green:user3";
+ gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "green:user3";
+ gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ panic-indicator;
+ };
+
+ led5 {
+ label = "yellow:wifi";
+ gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ led6 {
+ label = "blue:bt";
+ gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+ };
+};
+
+&ethernet0 {
+ status = "okay";
+ pinctrl-0 = <&ethernet0_rgmii_pins_a>;
+ pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@7 {
+ reg = <7>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_b>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ st,main-control-register = <0x04>;
+ st,vin-control-register = <0xc0>;
+ st,usb-control-register = <0x30>;
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+
+ ldo1-supply = <&v3v3>;
+ ldo2-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo5-supply = <&v3v3>;
+ ldo6-supply = <&v3v3>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask_reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ vdda: ldo1 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ interrupt-parent = <&pmic>;
+ };
+
+ v2v8: ldo2 {
+ regulator-name = "v2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ interrupt-parent = <&pmic>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO4 0>;
+ interrupt-parent = <&pmic>;
+ };
+
+ vdd_sd: ldo5 {
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ interrupt-parent = <&pmic>;
+ regulator-boot-on;
+ };
+
+ v1v8: ldo6 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ interrupt-parent = <&pmic>;
+ regulator-enable-ramp-delay = <300000>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ interrupt-parent = <&pmic>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ interrupt-parent = <&pmic>;
+ regulator-active-discharge;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ interrupt-parent = <&pmic>;
+ regulator-active-discharge;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ broken-cd;
+ st,sig-dir;
+ st,neg-edge;
+ st,use-ckin;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ status = "okay";
+};
+
+&uart4 {
+ /* On Low speed expansion header */
+ label = "LS-UART1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_b>;
+ status = "okay";
+};
+
+&uart7 {
+ /* On Low speed expansion header */
+ label = "LS-UART0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
diff --git a/dts/src/arm/stm32mp157a-dk1.dts b/dts/src/arm/stm32mp157a-dk1.dts
index 098dbfb..f3f0e37 100644
--- a/dts/src/arm/stm32mp157a-dk1.dts
+++ b/dts/src/arm/stm32mp157a-dk1.dts
@@ -7,7 +7,7 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
-#include "stm32mp157-pinctrl.dtsi"
+#include "stm32mp157xac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -28,6 +28,17 @@
reg = <0xc0000000 0x20000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpu_reserved: gpu@d4000000 {
+ reg = <0xd4000000 0x4000000>;
+ no-map;
+ };
+ };
+
led {
compatible = "gpio-leds";
blue {
@@ -51,7 +62,7 @@
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
@@ -65,6 +76,47 @@
};
};
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_pins_sleep_a>;
+ i2c-scl-rising-time-ns = <100>;
+ i2c-scl-falling-time-ns = <7>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ hdmi-transmitter@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+ iovcc-supply = <&v3v3_hdmi>;
+ cvcc12-supply = <&v1v2_hdmi>;
+ reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpiog>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ltdc_pins_a>;
+ pinctrl-1 = <&ltdc_pins_sleep_a>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ sii9022_in: endpoint {
+ remote-endpoint = <&ltdc_ep0_out>;
+ };
+ };
+ };
+ };
+};
&i2c4 {
pinctrl-names = "default";
@@ -223,6 +275,20 @@
status = "okay";
};
+&ltdc {
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
+
&rng1 {
status = "okay";
};
diff --git a/dts/src/arm/stm32mp157c-ed1.dts b/dts/src/arm/stm32mp157c-ed1.dts
index 62a8c78..4fe7f71 100644
--- a/dts/src/arm/stm32mp157c-ed1.dts
+++ b/dts/src/arm/stm32mp157c-ed1.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include "stm32mp157c.dtsi"
-#include "stm32mp157-pinctrl.dtsi"
+#include "stm32mp157xaa-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -23,6 +23,17 @@
reg = <0xC0000000 0x40000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpu_reserved: gpu@e8000000 {
+ reg = <0xe8000000 0x8000000>;
+ no-map;
+ };
+ };
+
aliases {
serial0 = &uart4;
};
@@ -61,6 +72,11 @@
status = "okay";
};
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+ status = "okay";
+};
+
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
diff --git a/dts/src/arm/stm32mp157c-ev1.dts b/dts/src/arm/stm32mp157c-ev1.dts
index b6aca40..feb8f77 100644
--- a/dts/src/arm/stm32mp157c-ev1.dts
+++ b/dts/src/arm/stm32mp157c-ev1.dts
@@ -7,6 +7,7 @@
#include "stm32mp157c-ed1.dts"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
@@ -21,6 +22,51 @@
ethernet0 = &ethernet0;
};
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ joystick {
+ compatible = "gpio-keys";
+ #size-cells = <0>;
+ pinctrl-0 = <&joystick_pins>;
+ pinctrl-names = "default";
+ button-0 {
+ label = "JoySel";
+ linux,code = <KEY_ENTER>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-1 {
+ label = "JoyDown";
+ linux,code = <KEY_DOWN>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <1 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-2 {
+ label = "JoyLeft";
+ linux,code = <KEY_LEFT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-3 {
+ label = "JoyRight";
+ linux,code = <KEY_RIGHT>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+ button-4 {
+ label = "JoyUp";
+ linux,code = <KEY_UP>;
+ interrupt-parent = <&stmfx_pinctrl>;
+ interrupts = <4 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
panel_backlight: panel-backlight {
compatible = "gpio-backlight";
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
@@ -35,6 +81,23 @@
status = "okay";
};
+&dcmi {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmi_pins_a>;
+ pinctrl-1 = <&dcmi_sleep_pins_a>;
+
+ port {
+ dcmi_0: endpoint {
+ remote-endpoint = <&ov5640_0>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ };
+ };
+};
+
&dsi {
#address-cells = <1>;
#size-cells = <0>;
@@ -64,6 +127,7 @@
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
backlight = <&panel_backlight>;
+ power-supply = <&v3v3>;
status = "okay";
port {
@@ -79,7 +143,7 @@
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
@@ -99,6 +163,60 @@
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ov5640_pins>;
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ clock-names = "xclk";
+ DOVDD-supply = <&v2v8>;
+ powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>;
+ rotation = <180>;
+ status = "okay";
+
+ port {
+ ov5640_0: endpoint {
+ remote-endpoint = <&dcmi_0>;
+ bus-width = <8>;
+ data-shift = <2>; /* lines 9:2 are used */
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ };
+ };
+ };
+
+ stmfx: stmfx@42 {
+ compatible = "st,stmfx-0300";
+ reg = <0x42>;
+ interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpioi>;
+ vdd-supply = <&v3v3>;
+
+ stmfx_pinctrl: stmfx-pin-controller {
+ compatible = "st,stmfx-0300-pinctrl";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&stmfx_pinctrl 0 0 24>;
+
+ joystick_pins: joystick {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
+ drive-push-pull;
+ bias-pull-down;
+ };
+
+ ov5640_pins: camera {
+ pins = "agpio2", "agpio3"; /* stmfx pins 18 & 19 */
+ drive-push-pull;
+ output-low;
+ };
+ };
+ };
};
&i2c5 {
@@ -131,14 +249,16 @@
};
&qspi {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: mx66l51235l@0 {
+ compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
@@ -147,6 +267,7 @@
};
flash1: mx66l51235l@1 {
+ compatible = "jedec,spi-nor";
reg = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
diff --git a/dts/src/arm/stm32mp157c.dtsi b/dts/src/arm/stm32mp157c.dtsi
index 2afeee6..0c4e6eb 100644
--- a/dts/src/arm/stm32mp157c.dtsi
+++ b/dts/src/arm/stm32mp157c.dtsi
@@ -365,6 +365,17 @@
status = "disabled";
};
+ i2s2: audio-controller@4000b000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4000b000 0x400>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spi3: spi@4000c000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -379,6 +390,17 @@
status = "disabled";
};
+ i2s3: audio-controller@4000c000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x4000c000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spdifrx: audio-controller@4000d000 {
compatible = "st,stm32h7-spdifrx";
#sound-dai-cells = <0>;
@@ -607,6 +629,17 @@
status = "disabled";
};
+ i2s1: audio-controller@44004000 {
+ compatible = "st,stm32h7-i2s";
+ #sound-dai-cells = <0>;
+ reg = <0x44004000 0x400>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
spi4: spi@44005000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -708,6 +741,100 @@
status = "disabled";
};
+ sai1: sai@4400a000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400a000 0x400>;
+ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI1_R>;
+ status = "disabled";
+
+ sai1a: audio-controller@4400a004 {
+ #sound-dai-cells = <0>;
+
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x1c>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 87 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai1b: audio-controller@4400a024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
+ clocks = <&rcc SAI1_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 88 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ sai2: sai@4400b000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400b000 0x400>;
+ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI2_R>;
+ status = "disabled";
+
+ sai2a: audio-controller@4400b004 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x1c>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 89 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai2b: audio-controller@4400b024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 90 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
+ sai3: sai@4400c000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400c000 0x400>;
+ reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI3_R>;
+ status = "disabled";
+
+ sai3a: audio-controller@4400c004 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x04 0x1c>;
+ clocks = <&rcc SAI3_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 113 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai3b: audio-controller@4400c024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
+ clocks = <&rcc SAI3_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 114 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
dfsdm: dfsdm@4400d000 {
compatible = "st,stm32mp1-dfsdm";
reg = <0x4400d000 0x800>;
@@ -914,6 +1041,18 @@
status = "disabled";
};
+ dcmi: dcmi@4c006000 {
+ compatible = "st,stm32-dcmi";
+ reg = <0x4c006000 0x400>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc CAMITF_R>;
+ clocks = <&rcc DCMI>;
+ clock-names = "mclk";
+ dmas = <&dmamux1 75 0x400 0x0d>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
@@ -1020,6 +1159,37 @@
status = "disabled";
};
+ sai4: sai@50027000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50027000 0x400>;
+ reg = <0x50027000 0x4>, <0x500273f0 0x10>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI4_R>;
+ status = "disabled";
+
+ sai4a: audio-controller@50027004 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x04 0x1c>;
+ clocks = <&rcc SAI4_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 99 0x400 0x01>;
+ status = "disabled";
+ };
+
+ sai4b: audio-controller@50027024 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-b";
+ reg = <0x24 0x1c>;
+ clocks = <&rcc SAI4_K>;
+ clock-names = "sai_ck";
+ dmas = <&dmamux1 100 0x400 0x01>;
+ status = "disabled";
+ };
+ };
+
dts: thermal@50028000 {
compatible = "st,stm32-thermal";
reg = <0x50028000 0x100>;
@@ -1149,6 +1319,16 @@
status = "disabled";
};
+ gpu: gpu@59000000 {
+ compatible = "vivante,gc";
+ reg = <0x59000000 0x800>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc GPU>, <&rcc GPU_K>;
+ clock-names = "bus" ,"core";
+ resets = <&rcc GPU_R>;
+ status = "disabled";
+ };
+
dsi: dsi@5a000000 {
compatible = "st,stm32-dsi";
reg = <0x5a000000 0x800>;
diff --git a/dts/src/arm/stm32mp157xaa-pinctrl.dtsi b/dts/src/arm/stm32mp157xaa-pinctrl.dtsi
new file mode 100644
index 0000000..875adf5
--- /dev/null
+++ b/dts/src/arm/stm32mp157xaa-pinctrl.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ */
+
+#include "stm32mp157-pinctrl.dtsi"
+/ {
+ soc {
+ pinctrl: pin-controller@50002000 {
+ st,package = <STM32MP_PKG_AA>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@5000a000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@5000b000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@5000c000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+ };
+
+ pinctrl_z: pin-controller-z@54004000 {
+ st,package = <STM32MP_PKG_AA>;
+
+ gpioz: gpio@54004000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/stm32mp157xab-pinctrl.dtsi b/dts/src/arm/stm32mp157xab-pinctrl.dtsi
new file mode 100644
index 0000000..961fa12
--- /dev/null
+++ b/dts/src/arm/stm32mp157xab-pinctrl.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ */
+
+#include "stm32mp157-pinctrl.dtsi"
+/ {
+ soc {
+ pinctrl: pin-controller@50002000 {
+ st,package = <STM32MP_PKG_AB>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <6>;
+ gpio-ranges = <&pinctrl 6 86 6>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl 6 102 10>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <2>;
+ gpio-ranges = <&pinctrl 0 112 2>;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/stm32mp157xac-pinctrl.dtsi b/dts/src/arm/stm32mp157xac-pinctrl.dtsi
new file mode 100644
index 0000000..26600f1
--- /dev/null
+++ b/dts/src/arm/stm32mp157xac-pinctrl.dtsi
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ */
+
+#include "stm32mp157-pinctrl.dtsi"
+/ {
+ soc {
+ pinctrl: pin-controller@50002000 {
+ st,package = <STM32MP_PKG_AC>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@5000a000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+ };
+
+ pinctrl_z: pin-controller-z@54004000 {
+ st,package = <STM32MP_PKG_AC>;
+
+ gpioz: gpio@54004000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/stm32mp157xad-pinctrl.dtsi b/dts/src/arm/stm32mp157xad-pinctrl.dtsi
new file mode 100644
index 0000000..910113f
--- /dev/null
+++ b/dts/src/arm/stm32mp157xad-pinctrl.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ */
+
+#include "stm32mp157-pinctrl.dtsi"
+/ {
+ soc {
+ pinctrl: pin-controller@50002000 {
+ st,package = <STM32MP_PKG_AD>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <6>;
+ gpio-ranges = <&pinctrl 6 86 6>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl 6 102 10>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <2>;
+ gpio-ranges = <&pinctrl 0 112 2>;
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/sun5i-gr8-evb.dts b/dts/src/arm/sun5i-gr8-evb.dts
index d003b89..4c20d73 100644
--- a/dts/src/arm/sun5i-gr8-evb.dts
+++ b/dts/src/arm/sun5i-gr8-evb.dts
@@ -150,7 +150,7 @@
};
pcf8563: rtc@51 {
- compatible = "phg,pcf8563";
+ compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
diff --git a/dts/src/arm/sun6i-a31.dtsi b/dts/src/arm/sun6i-a31.dtsi
index c04efad..dcddc33 100644
--- a/dts/src/arm/sun6i-a31.dtsi
+++ b/dts/src/arm/sun6i-a31.dtsi
@@ -216,6 +216,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
+ clock-accuracy = <50000>;
clock-output-names = "osc24M";
};
@@ -223,7 +224,8 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
- clock-output-names = "osc32k";
+ clock-accuracy = <50000>;
+ clock-output-names = "ext_osc32k";
};
/*
@@ -588,7 +590,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun6i-a31-ccu";
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&osc32k>;
+ clocks = <&osc24M>, <&rtc 0>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -601,7 +603,7 @@
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@@ -987,6 +989,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI0>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
spi1: spi@1c69000 {
@@ -999,6 +1003,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI1>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
spi2: spi@1c6a000 {
@@ -1011,6 +1017,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI2>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
spi3: spi@1c6b000 {
@@ -1023,6 +1031,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI3>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
gic: interrupt-controller@1c81000 {
@@ -1279,10 +1289,13 @@
};
rtc: rtc@1f00000 {
+ #clock-cells = <1>;
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc32k>;
+ clock-output-names = "osc32k";
};
nmi_intc: interrupt-controller@1f00c00 {
@@ -1300,7 +1313,7 @@
ar100: ar100_clk {
compatible = "allwinner,sun6i-a31-ar100-clk";
#clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>,
+ clocks = <&rtc 0>, <&osc24M>,
<&ccu CLK_PLL_PERIPH>,
<&ccu CLK_PLL_PERIPH>;
clock-output-names = "ar100";
@@ -1335,7 +1348,7 @@
ir_clk: ir_clk {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
- clocks = <&osc32k>, <&osc24M>;
+ clocks = <&rtc 0>, <&osc24M>;
clock-output-names = "ir";
};
@@ -1365,7 +1378,7 @@
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+ clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
diff --git a/dts/src/arm/sun7i-a20-icnova-swac.dts b/dts/src/arm/sun7i-a20-icnova-swac.dts
index 9494947..7449aac 100644
--- a/dts/src/arm/sun7i-a20-icnova-swac.dts
+++ b/dts/src/arm/sun7i-a20-icnova-swac.dts
@@ -49,7 +49,8 @@
/ {
model = "ICnova-A20 SWAC";
- compatible = "swac,icnova-a20-swac", "incircuit,icnova-a20", "allwinner,sun7i-a20";
+ compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20",
+ "allwinner,sun7i-a20";
aliases {
serial0 = &uart0;
diff --git a/dts/src/arm/sun7i-a20-olinuxino-lime2.dts b/dts/src/arm/sun7i-a20-olinuxino-lime2.dts
index 95c6f89..56f451c 100644
--- a/dts/src/arm/sun7i-a20-olinuxino-lime2.dts
+++ b/dts/src/arm/sun7i-a20-olinuxino-lime2.dts
@@ -194,6 +194,14 @@
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
diff --git a/dts/src/arm/sun8i-a83t-tbs-a711.dts b/dts/src/arm/sun8i-a83t-tbs-a711.dts
index 66d0780..568b90e 100644
--- a/dts/src/arm/sun8i-a83t-tbs-a711.dts
+++ b/dts/src/arm/sun8i-a83t-tbs-a711.dts
@@ -224,14 +224,14 @@
vref-supply = <&reg_aldo2>;
status = "okay";
- button@210 {
+ button-210 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <210000>;
};
- button@410 {
+ button-410 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
diff --git a/dts/src/arm/sun8i-a83t.dtsi b/dts/src/arm/sun8i-a83t.dtsi
index 392b0ca..ada6d08 100644
--- a/dts/src/arm/sun8i-a83t.dtsi
+++ b/dts/src/arm/sun8i-a83t.dtsi
@@ -679,6 +679,20 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ /omit-if-no-ref/
+ csi_8bit_parallel_pins: csi-8bit-parallel-pins {
+ pins = "PE0", "PE2", "PE3", "PE6", "PE7",
+ "PE8", "PE9", "PE10", "PE11",
+ "PE12", "PE13";
+ function = "csi";
+ };
+
+ /omit-if-no-ref/
+ csi_mclk_pin: csi-mclk-pin {
+ pins = "PE1";
+ function = "csi";
+ };
+
emac_rgmii_pins: emac-rgmii-pins {
pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
"PD11", "PD12", "PD13", "PD14", "PD18",
@@ -997,6 +1011,21 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ csi: camera@1cb0000 {
+ compatible = "allwinner,sun8i-a83t-csi";
+ reg = <0x01cb0000 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+
+ csi_in: port {
+ };
+ };
+
hdmi: hdmi@1ee0000 {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee0000 0x10000>;
diff --git a/dts/src/arm/sun8i-h2-plus-bananapi-m2-zero.dts b/dts/src/arm/sun8i-h2-plus-bananapi-m2-zero.dts
index 78a37a4..d277d04 100644
--- a/dts/src/arm/sun8i-h2-plus-bananapi-m2-zero.dts
+++ b/dts/src/arm/sun8i-h2-plus-bananapi-m2-zero.dts
@@ -59,8 +59,7 @@
gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
enable-active-high;
gpios-states = <0x1>;
- states = <1100000 0x0
- 1300000 0x1>;
+ states = <1100000 0>, <1300000 1>;
};
wifi_pwrseq: wifi_pwrseq {
diff --git a/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts b/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts
index 4970eda..f19ed98 100644
--- a/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts
+++ b/dts/src/arm/sun8i-h2-plus-orangepi-zero.dts
@@ -102,8 +102,7 @@
gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
enable-active-high;
gpios-states = <1>;
- states = <1100000 0
- 1300000 1>;
+ states = <1100000 0>, <1300000 1>;
};
wifi_pwrseq: wifi_pwrseq {
diff --git a/dts/src/arm/sun8i-h3-beelink-x2.dts b/dts/src/arm/sun8i-h3-beelink-x2.dts
index 6277f13..ac9e26b 100644
--- a/dts/src/arm/sun8i-h3-beelink-x2.dts
+++ b/dts/src/arm/sun8i-h3-beelink-x2.dts
@@ -90,6 +90,8 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
};
sound_spdif {
@@ -155,6 +157,8 @@
&mmc1 {
vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
diff --git a/dts/src/arm/sun8i-h3-orangepi-one.dts b/dts/src/arm/sun8i-h3-orangepi-one.dts
index 8408491..4759ba3 100644
--- a/dts/src/arm/sun8i-h3-orangepi-one.dts
+++ b/dts/src/arm/sun8i-h3-orangepi-one.dts
@@ -109,8 +109,7 @@
gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
enable-active-high;
gpios-states = <0x1>;
- states = <1100000 0x0
- 1300000 0x1>;
+ states = <1100000 0>, <1300000 1>;
};
};
diff --git a/dts/src/arm/sun8i-r40-bananapi-m2-ultra.dts b/dts/src/arm/sun8i-r40-bananapi-m2-ultra.dts
index c488aaa..42d62d1 100644
--- a/dts/src/arm/sun8i-r40-bananapi-m2-ultra.dts
+++ b/dts/src/arm/sun8i-r40-bananapi-m2-ultra.dts
@@ -201,10 +201,15 @@
&pio {
pinctrl-names = "default";
pinctrl-0 = <&clk_out_a_pin>;
+ vcc-pa-supply = <&reg_aldo2>;
+ vcc-pc-supply = <&reg_dcdc1>;
+ vcc-pd-supply = <&reg_dcdc1>;
+ vcc-pe-supply = <&reg_eldo1>;
+ vcc-pf-supply = <&reg_dcdc1>;
+ vcc-pg-supply = <&reg_dldo1>;
};
&reg_aldo2 {
- regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc-pa";
diff --git a/dts/src/arm/sun8i-r40.dtsi b/dts/src/arm/sun8i-r40.dtsi
index bb856e5..6007d0c 100644
--- a/dts/src/arm/sun8i-r40.dtsi
+++ b/dts/src/arm/sun8i-r40.dtsi
@@ -318,8 +318,7 @@
};
rtc: rtc@1c20400 {
- compatible = "allwinner,sun8i-r40-rtc",
- "allwinner,sun8i-h3-rtc";
+ compatible = "allwinner,sun8i-r40-rtc";
reg = <0x01c20400 0x400>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "osc32k", "osc32k-out";
diff --git a/dts/src/arm/sun8i-v3s.dtsi b/dts/src/arm/sun8i-v3s.dtsi
index df72b17..d7aef12 100644
--- a/dts/src/arm/sun8i-v3s.dtsi
+++ b/dts/src/arm/sun8i-v3s.dtsi
@@ -84,6 +84,7 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
+ clock-accuracy = <50000>;
clock-output-names = "osc24M";
};
@@ -91,7 +92,8 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
- clock-output-names = "osc32k";
+ clock-accuracy = <50000>;
+ clock-output-names = "ext-osc32k";
};
};
@@ -264,17 +266,20 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&osc32k>;
+ clocks = <&osc24M>, <&rtc 0>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
rtc: rtc@1c20400 {
- compatible = "allwinner,sun6i-a31-rtc";
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-v3-rtc";
reg = <0x01c20400 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc32k>;
+ clock-output-names = "osc32k", "osc32k-out";
};
pio: pinctrl@1c20800 {
@@ -282,7 +287,7 @@
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
diff --git a/dts/src/arm/sun8i-v40-bananapi-m2-berry.dts b/dts/src/arm/sun8i-v40-bananapi-m2-berry.dts
index f05cabd..15c22b0 100644
--- a/dts/src/arm/sun8i-v40-bananapi-m2-berry.dts
+++ b/dts/src/arm/sun8i-v40-bananapi-m2-berry.dts
@@ -50,6 +50,7 @@
compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";
aliases {
+ ethernet0 = &gmac;
serial0 = &uart0;
};
@@ -57,6 +58,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -84,14 +96,52 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+ clocks = <&ccu CLK_OUTA>;
+ clock-names = "ext_clock";
};
};
+&ahci {
+ ahci-supply = <&reg_dldo4>;
+ phy-supply = <&reg_eldo3>;
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
&ehci1 {
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
};
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <&reg_dc1sw>;
+ status = "okay";
+};
+
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
status = "okay";
@@ -123,6 +173,23 @@
status = "okay";
};
+&pio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_out_a_pin>;
+ vcc-pa-supply = <&reg_aldo2>;
+ vcc-pc-supply = <&reg_dcdc1>;
+ vcc-pd-supply = <&reg_dcdc1>;
+ vcc-pe-supply = <&reg_eldo1>;
+ vcc-pf-supply = <&reg_dcdc1>;
+ vcc-pg-supply = <&reg_dldo1>;
+};
+
+&reg_aldo2 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-pa";
+};
+
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <2700000>;
@@ -130,6 +197,12 @@
regulator-name = "avcc";
};
+&reg_dc1sw {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-gmac-phy";
+};
+
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
@@ -164,18 +237,68 @@
regulator-name = "vcc-wifi-io";
};
+/*
+ * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same
+ * time, with the two being in sync, to be able to meet maximum power
+ * consumption during transmits. Since this is not really supported
+ * right now, just use the two as always on, and we will fix it later.
+ */
+
&reg_dldo2 {
+ regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
+&reg_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vdd2v5-sata";
+};
+
+&reg_eldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd1v2-sata";
+};
+
+&tcon_tv0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&ccu CLK_OUTA>;
+ clock-names = "lpo";
+ vbat-supply = <&reg_dldo2>;
+ vddio-supply = <&reg_dldo1>;
+ device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
+ /* TODO host wake line connected to PMIC GPIO pins */
+ shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
+ max-speed = <1500000>;
+ };
+};
+
&usbphy {
usb1_vbus-supply = <&reg_vcc5v0>;
status = "okay";
diff --git a/dts/src/arm/sunxi-bananapi-m2-plus-v1.2.dtsi b/dts/src/arm/sunxi-bananapi-m2-plus-v1.2.dtsi
index 53edd1f..22466af 100644
--- a/dts/src/arm/sunxi-bananapi-m2-plus-v1.2.dtsi
+++ b/dts/src/arm/sunxi-bananapi-m2-plus-v1.2.dtsi
@@ -21,8 +21,7 @@
regulator-ramp-delay = <50>; /* 4ms */
gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
gpios-states = <0x1>;
- states = <1100000 0x0
- 1300000 0x1>;
+ states = <1100000 0>, <1300000 1>;
};
};
diff --git a/dts/src/arm/uniphier-ld4-ref.dts b/dts/src/arm/uniphier-ld4-ref.dts
index 3aaca10..f2d060f 100644
--- a/dts/src/arm/uniphier-ld4-ref.dts
+++ b/dts/src/arm/uniphier-ld4-ref.dts
@@ -77,4 +77,8 @@
&nand {
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
};
diff --git a/dts/src/arm/uniphier-ld4.dtsi b/dts/src/arm/uniphier-ld4.dtsi
index c2706ce..58cd4e8 100644
--- a/dts/src/arm/uniphier-ld4.dtsi
+++ b/dts/src/arm/uniphier-ld4.dtsi
@@ -403,9 +403,11 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 65 4>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand2cs>;
+ pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
diff --git a/dts/src/arm/uniphier-ld6b-ref.dts b/dts/src/arm/uniphier-ld6b-ref.dts
index 3d9080e..60994b6 100644
--- a/dts/src/arm/uniphier-ld6b-ref.dts
+++ b/dts/src/arm/uniphier-ld6b-ref.dts
@@ -90,4 +90,8 @@
&nand {
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
};
diff --git a/dts/src/arm/uniphier-pro4-ref.dts b/dts/src/arm/uniphier-pro4-ref.dts
index 28038b1..854f2eb 100644
--- a/dts/src/arm/uniphier-pro4-ref.dts
+++ b/dts/src/arm/uniphier-pro4-ref.dts
@@ -98,4 +98,8 @@
&nand {
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
};
diff --git a/dts/src/arm/uniphier-pro4.dtsi b/dts/src/arm/uniphier-pro4.dtsi
index 97d051e..7f64e5a 100644
--- a/dts/src/arm/uniphier-pro4.dtsi
+++ b/dts/src/arm/uniphier-pro4.dtsi
@@ -593,6 +593,8 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
diff --git a/dts/src/arm/uniphier-pro5.dtsi b/dts/src/arm/uniphier-pro5.dtsi
index 3657387..eff7471 100644
--- a/dts/src/arm/uniphier-pro5.dtsi
+++ b/dts/src/arm/uniphier-pro5.dtsi
@@ -458,9 +458,11 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 65 4>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand2cs>;
+ pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
diff --git a/dts/src/arm/uniphier-pxs2.dtsi b/dts/src/arm/uniphier-pxs2.dtsi
index 06a049f..4eddbb8 100644
--- a/dts/src/arm/uniphier-pxs2.dtsi
+++ b/dts/src/arm/uniphier-pxs2.dtsi
@@ -766,9 +766,11 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 65 4>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand2cs>;
+ pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
diff --git a/dts/src/arm/uniphier-sld8-ref.dts b/dts/src/arm/uniphier-sld8-ref.dts
index 01bf94c..cf9ea0b 100644
--- a/dts/src/arm/uniphier-sld8-ref.dts
+++ b/dts/src/arm/uniphier-sld8-ref.dts
@@ -81,4 +81,8 @@
&nand {
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ };
};
diff --git a/dts/src/arm/uniphier-sld8.dtsi b/dts/src/arm/uniphier-sld8.dtsi
index efce027..cbebb6e 100644
--- a/dts/src/arm/uniphier-sld8.dtsi
+++ b/dts/src/arm/uniphier-sld8.dtsi
@@ -407,9 +407,11 @@
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 65 4>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand2cs>;
+ pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
resets = <&sys_rst 2>;
diff --git a/dts/src/arm/versatile-ab.dts b/dts/src/arm/versatile-ab.dts
index 269e6bf..37bd41f 100644
--- a/dts/src/arm/versatile-ab.dts
+++ b/dts/src/arm/versatile-ab.dts
@@ -161,6 +161,9 @@
compatible = "arm,versatile-flash", "cfi-flash";
reg = <0x34000000 0x04000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
i2c0: i2c@10002000 {
diff --git a/dts/src/arm/vexpress-v2m-rs1.dtsi b/dts/src/arm/vexpress-v2m-rs1.dtsi
index d3963e9..d6a1fc2 100644
--- a/dts/src/arm/vexpress-v2m-rs1.dtsi
+++ b/dts/src/arm/vexpress-v2m-rs1.dtsi
@@ -30,11 +30,14 @@
#interrupt-cells = <1>;
ranges;
- flash@0,00000000 {
+ nor_flash: flash@0,00000000 {
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0 0x00000000 0x04000000>,
<4 0x00000000 0x04000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
psram@1,00000000 {
diff --git a/dts/src/arm/vexpress-v2m.dtsi b/dts/src/arm/vexpress-v2m.dtsi
index 798c97a..8e57e15 100644
--- a/dts/src/arm/vexpress-v2m.dtsi
+++ b/dts/src/arm/vexpress-v2m.dtsi
@@ -35,6 +35,9 @@
reg = <0 0x00000000 0x04000000>,
<1 0x00000000 0x04000000>;
bank-width = <4>;
+ partitions {
+ compatible = "arm,arm-firmware-suite";
+ };
};
psram@2,00000000 {
diff --git a/dts/src/arm/vexpress-v2p-ca15_a7.dts b/dts/src/arm/vexpress-v2p-ca15_a7.dts
index 00cd9f5..1de0a65 100644
--- a/dts/src/arm/vexpress-v2p-ca15_a7.dts
+++ b/dts/src/arm/vexpress-v2p-ca15_a7.dts
@@ -440,7 +440,7 @@
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
- compatible = "arm,coresight-replicator";
+ compatible = "arm,coresight-static-replicator";
out-ports {
#address-cells = <1>;
@@ -471,7 +471,7 @@
};
funnel@20040000 {
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x20040000 0 0x1000>;
clocks = <&oscclk6a>;
@@ -680,3 +680,12 @@
<0 3 &gic 0 39 4>;
};
};
+
+&nor_flash {
+ /*
+ * Unfortunately, accessing the flash disturbs the CPU idle states
+ * (suspend) and CPU hotplug of this platform. For this reason, flash
+ * hardware access is disabled by default on this platform alone.
+ */
+ status = "disabled";
+};
diff --git a/dts/src/arm/vf610-zii-dev.dtsi b/dts/src/arm/vf610-zii-dev.dtsi
index 0507e6d..a1b4cce 100644
--- a/dts/src/arm/vf610-zii-dev.dtsi
+++ b/dts/src/arm/vf610-zii-dev.dtsi
@@ -177,6 +177,36 @@
status = "okay";
};
+&qspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0>;
+ status = "okay";
+
+ /*
+ * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR
+ * modes, so, spi-max-frequency is limited to 90MHz
+ */
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <90000000>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ m25p,fast-read;
+ };
+
+ flash@2 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <90000000>;
+ spi-rx-bus-width = <4>;
+ reg = <2>;
+ m25p,fast-read;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
@@ -360,12 +390,18 @@
pinctrl_qspi0: qspi0grp {
fsl,pins = <
- VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
- VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
- VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
- VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
- VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
- VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
+ VF610_PAD_PTD0__QSPI0_A_QSCK 0x38c2
+ VF610_PAD_PTD1__QSPI0_A_CS0 0x38c2
+ VF610_PAD_PTD2__QSPI0_A_DATA3 0x38c3
+ VF610_PAD_PTD3__QSPI0_A_DATA2 0x38c3
+ VF610_PAD_PTD4__QSPI0_A_DATA1 0x38c3
+ VF610_PAD_PTD5__QSPI0_A_DATA0 0x38c3
+ VF610_PAD_PTD7__QSPI0_B_QSCK 0x38c2
+ VF610_PAD_PTD8__QSPI0_B_CS0 0x38c2
+ VF610_PAD_PTD9__QSPI0_B_DATA3 0x38c3
+ VF610_PAD_PTD10__QSPI0_B_DATA2 0x38c3
+ VF610_PAD_PTD11__QSPI0_B_DATA1 0x38c3
+ VF610_PAD_PTD12__QSPI0_B_DATA0 0x38c3
>;
};
@@ -385,8 +421,8 @@
pinctrl_uart2: uart2grp {
fsl,pins = <
- VF610_PAD_PTD0__UART2_TX 0x21a2
- VF610_PAD_PTD1__UART2_RX 0x21a1
+ VF610_PAD_PTD23__UART2_TX 0x21a2
+ VF610_PAD_PTD22__UART2_RX 0x21a1
>;
};