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-rw-r--r--dts/src/mips/mscc/jaguar2.dtsi167
-rw-r--r--dts/src/mips/mscc/jaguar2_common.dtsi25
-rw-r--r--dts/src/mips/mscc/jaguar2_pcb110.dts267
-rw-r--r--dts/src/mips/mscc/jaguar2_pcb111.dts107
-rw-r--r--dts/src/mips/mscc/jaguar2_pcb118.dts57
-rw-r--r--dts/src/mips/mscc/luton.dtsi116
-rw-r--r--dts/src/mips/mscc/luton_pcb091.dts30
-rw-r--r--dts/src/mips/mscc/serval.dtsi153
-rw-r--r--dts/src/mips/mscc/serval_common.dtsi127
-rw-r--r--dts/src/mips/mscc/serval_pcb105.dts17
-rw-r--r--dts/src/mips/mscc/serval_pcb106.dts17
11 files changed, 1083 insertions, 0 deletions
diff --git a/dts/src/mips/mscc/jaguar2.dtsi b/dts/src/mips/mscc/jaguar2.dtsi
new file mode 100644
index 0000000000..42b2b0a51d
--- /dev/null
+++ b/dts/src/mips/mscc/jaguar2.dtsi
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,jr2";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart2;
+ gpio0 = &gpio;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&cpu_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ ahb: ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
+
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,jaguar2-icpu-intr";
+ reg = <0x70000070 0x94>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@70100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x70100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@70100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x70100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@71010038 {
+ compatible = "mscc,jaguar2-pinctrl";
+ reg = <0x71010038 0x90>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 64>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_10", "GPIO_11";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_24", "GPIO_25";
+ function = "uart2";
+ };
+
+ cs1_pins: cs1-pins {
+ pins = "GPIO_16";
+ function = "si";
+ };
+
+ cs2_pins: cs2-pins {
+ pins = "GPIO_17";
+ function = "si";
+ };
+
+ cs3_pins: cs3-pins {
+ pins = "GPIO_18";
+ function = "si";
+ };
+
+ i2c_pins: i2c-pins {
+ pins = "GPIO_14", "GPIO_15";
+ function = "twi";
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins = "GPIO_28", "GPIO_29";
+ function = "twi2";
+ };
+ };
+
+ i2c0: i2c@70100400 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ reg = <0x70100400 0x100>, <0x700001b8 0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
+ };
+
+ i2c2: i2c@70100c00 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ reg = <0x70100c00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
+ };
+ };
+};
diff --git a/dts/src/mips/mscc/jaguar2_common.dtsi b/dts/src/mips/mscc/jaguar2_common.dtsi
new file mode 100644
index 0000000000..679ff0d8ed
--- /dev/null
+++ b/dts/src/mips/mscc/jaguar2_common.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+#include "jaguar2.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ i2c-sda-hold-time-ns = <300>;
+};
diff --git a/dts/src/mips/mscc/jaguar2_pcb110.dts b/dts/src/mips/mscc/jaguar2_pcb110.dts
new file mode 100644
index 0000000000..d80cd6842b
--- /dev/null
+++ b/dts/src/mips/mscc/jaguar2_pcb110.dts
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "jaguar2_common.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
+ compatible = "mscc,jr2-pcb110", "mscc,jr2";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c108 = &i2c108;
+ i2c109 = &i2c109;
+ i2c110 = &i2c110;
+ i2c111 = &i2c111;
+ i2c112 = &i2c112;
+ i2c113 = &i2c113;
+ i2c114 = &i2c114;
+ i2c115 = &i2c115;
+ i2c116 = &i2c116;
+ i2c117 = &i2c117;
+ i2c118 = &i2c118;
+ i2c119 = &i2c119;
+ i2c120 = &i2c120;
+ i2c121 = &i2c121;
+ i2c122 = &i2c122;
+ i2c123 = &i2c123;
+ i2c124 = &i2c124;
+ i2c125 = &i2c125;
+ i2c126 = &i2c126;
+ i2c127 = &i2c127;
+ i2c128 = &i2c128;
+ i2c129 = &i2c129;
+ i2c130 = &i2c130;
+ i2c131 = &i2c131;
+ i2c149 = &i2c149;
+ i2c150 = &i2c150;
+ i2c151 = &i2c151;
+ i2c152 = &i2c152;
+ };
+ i2c0_imux: i2c0-imux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ pinctrl-names =
+ "i2c149", "i2c150", "i2c151", "i2c152", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_2>;
+ pinctrl-3 = <&i2cmux_3>;
+ pinctrl-4 = <&i2cmux_pins_i>;
+ i2c149: i2c@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c150: i2c@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c151: i2c@2 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c152: i2c@3 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ i2c0_emux: i2c0-emux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ mux-gpios = <&gpio 51 GPIO_ACTIVE_HIGH
+ &gpio 52 GPIO_ACTIVE_HIGH
+ &gpio 53 GPIO_ACTIVE_HIGH
+ &gpio 58 GPIO_ACTIVE_HIGH
+ &gpio 59 GPIO_ACTIVE_HIGH>;
+ idle-state = <0x0>;
+ i2c108: i2c@10 {
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c109: i2c@11 {
+ reg = <0x11>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c110: i2c@12 {
+ reg = <0x12>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c111: i2c@13 {
+ reg = <0x13>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c112: i2c@14 {
+ reg = <0x14>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c113: i2c@15 {
+ reg = <0x15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c114: i2c@16 {
+ reg = <0x16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c115: i2c@17 {
+ reg = <0x17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c116: i2c@8 {
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c117: i2c@9 {
+ reg = <0x9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c118: i2c@a {
+ reg = <0xa>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c119: i2c@b {
+ reg = <0xb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c120: i2c@c {
+ reg = <0xc>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c121: i2c@d {
+ reg = <0xd>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c122: i2c@e {
+ reg = <0xe>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c123: i2c@f {
+ reg = <0xf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&gpio {
+ synce_pins: synce-pins {
+ // GPIO 16 == SI_nCS1
+ pins = "GPIO_16";
+ function = "si";
+ };
+ synce_builtin_pins: synce-builtin-pins {
+ // GPIO 49 == SI_nCS13
+ pins = "GPIO_49";
+ function = "si";
+ };
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_17";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_18";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_2: i2cmux-2 {
+ pins = "GPIO_20";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_3: i2cmux-3 {
+ pins = "GPIO_21";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&i2c0 {
+ pca9545@70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+ i2c124: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ i2c125: i2c@1 {
+ /* FMC B */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ i2c126: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ i2c127: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+ pca9545@71 {
+ compatible = "nxp,pca9545";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+ i2c128: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ i2c129: i2c@1 {
+ /* FMC B */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ i2c130: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ i2c131: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
diff --git a/dts/src/mips/mscc/jaguar2_pcb111.dts b/dts/src/mips/mscc/jaguar2_pcb111.dts
new file mode 100644
index 0000000000..813c5e1601
--- /dev/null
+++ b/dts/src/mips/mscc/jaguar2_pcb111.dts
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "jaguar2_common.dtsi"
+
+/ {
+ model = "Jaguar2 Cu48 PCB111 Reference Board";
+ compatible = "mscc,jr2-pcb111", "mscc,jr2";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c149 = &i2c149;
+ i2c150 = &i2c150;
+ i2c151 = &i2c151;
+ i2c152 = &i2c152;
+ i2c203 = &i2c203;
+ };
+
+ i2c0_imux: i2c0-imux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ pinctrl-names =
+ "i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_2>;
+ pinctrl-3 = <&i2cmux_3>;
+ pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE
+ pinctrl-5 = <&i2cmux_pins_i>;
+ i2c149: i2c@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c150: i2c@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c151: i2c@2 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c152: i2c@3 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c203: i2c@4 {
+ reg = <0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&gpio {
+ synce_builtin_pins: synce-builtin-pins {
+ // GPIO 49 == SI_nCS13
+ pins = "GPIO_49";
+ function = "si";
+ };
+ cpld_pins: cpld-pins {
+ // GPIO 50 == SI_nCS14
+ pins = "GPIO_50";
+ function = "si";
+ };
+ cpld_fifo_pins: synce-builtin-pins {
+ // GPIO 51 == SI_nCS15
+ pins = "GPIO_51";
+ function = "si";
+ };
+};
+
+&gpio {
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_17", "GPIO_18";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_17";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_18";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_2: i2cmux-2 {
+ pins = "GPIO_20";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_3: i2cmux-3 {
+ pins = "GPIO_21";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
diff --git a/dts/src/mips/mscc/jaguar2_pcb118.dts b/dts/src/mips/mscc/jaguar2_pcb118.dts
new file mode 100644
index 0000000000..27c644f2d1
--- /dev/null
+++ b/dts/src/mips/mscc/jaguar2_pcb118.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "jaguar2_common.dtsi"
+
+/ {
+ model = "Jaguar2/Aquantia PCB118 Reference Board";
+ compatible = "mscc,jr2-pcb118", "mscc,jr2";
+
+ aliases {
+ i2c150 = &i2c150;
+ i2c151 = &i2c151;
+ };
+
+ i2c0_imux: i2c0-imux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ pinctrl-names =
+ "i2c150", "i2c151", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_pins_i>;
+ i2c150: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c151: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&gpio {
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_17", "GPIO_16";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_17";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_16";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
diff --git a/dts/src/mips/mscc/luton.dtsi b/dts/src/mips/mscc/luton.dtsi
new file mode 100644
index 0000000000..2a170b84c5
--- /dev/null
+++ b/dts/src/mips/mscc/luton.dtsi
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microsemi Corporation */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,luton";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <416666666>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&cpu_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ ahb@60000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x60000000 0x20000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@10000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x10000000 0x2c>;
+ };
+
+ intc: interrupt-controller@10000084 {
+ compatible = "mscc,luton-icpu-intr";
+ reg = <0x10000084 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@10100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x10100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ i2c0: i2c@10100400 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ reg = <0x10100400 0x100>, <0x100002a4 0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <11>;
+ clocks = <&ahb_clk>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@70068 {
+ compatible = "mscc,luton-pinctrl";
+ reg = <0x70068 0x28>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 32>;
+ interrupt-controller;
+ interrupts = <13>;
+ #interrupt-cells = <2>;
+
+ i2c_pins: i2c-pins {
+ pins = "GPIO_5", "GPIO_6";
+ function = "twi";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_30", "GPIO_31";
+ function = "uart";
+ };
+
+ };
+ };
+};
diff --git a/dts/src/mips/mscc/luton_pcb091.dts b/dts/src/mips/mscc/luton_pcb091.dts
new file mode 100644
index 0000000000..26ef6285d7
--- /dev/null
+++ b/dts/src/mips/mscc/luton_pcb091.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+/dts-v1/;
+
+#include "luton.dtsi"
+
+/ {
+ model = "Luton10 PCB091 Reference Board";
+ compatible = "mscc,luton-pcb091", "mscc,luton";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ i2c-sda-hold-time-ns = <300>;
+};
diff --git a/dts/src/mips/mscc/serval.dtsi b/dts/src/mips/mscc/serval.dtsi
new file mode 100644
index 0000000000..089ce89df1
--- /dev/null
+++ b/dts/src/mips/mscc/serval.dtsi
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,serval";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ gpio0 = &gpio;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <416666666>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&cpu_clk>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ ahb: ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };
+
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,serval-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@70100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x70100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@70100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x70100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@71070034 {
+ compatible = "mscc,serval-pinctrl";
+ reg = <0x71070034 0x28>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
+ function = "sg0";
+ };
+
+ i2c_pins: i2c-pins {
+ pins = "GPIO_6", "GPIO_7";
+ function = "twi";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_26", "GPIO_27";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_13", "GPIO_14";
+ function = "uart2";
+ };
+
+ cs1_pins: cs1-pins {
+ pins = "GPIO_8";
+ function = "si";
+ };
+
+ irqext0_pins: irqext0-pins {
+ pins = "GPIO_28";
+ function = "irq0";
+ };
+
+ irqext1_pins: irqext1-pins {
+ pins = "GPIO_29";
+ function = "irq1";
+ };
+ };
+
+ i2c0: i2c@70100400 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ reg = <0x70100400 0x100>, <0x70000190 0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
+ };
+ };
+};
diff --git a/dts/src/mips/mscc/serval_common.dtsi b/dts/src/mips/mscc/serval_common.dtsi
new file mode 100644
index 0000000000..5b404836db
--- /dev/null
+++ b/dts/src/mips/mscc/serval_common.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microsemi Corporation
+ */
+
+#include "serval.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ i2c104 = &i2c104;
+ i2c105 = &i2c105;
+ i2c106 = &i2c106;
+ i2c107 = &i2c107;
+ i2c108 = &i2c108;
+ i2c109 = &i2c109;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ i2c0_imux: i2c0-imux{
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ pinctrl-names =
+ "i2c104", "i2c105", "i2c106", "i2c107",
+ "i2c108", "i2c109", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_2>;
+ pinctrl-3 = <&i2cmux_3>;
+ pinctrl-4 = <&i2cmux_4>;
+ pinctrl-5 = <&i2cmux_5>;
+ pinctrl-6 = <&i2cmux_pins_i>;
+ i2c104: i2c_sfp0@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c105: i2c_sfp1@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c106: i2c_sfp2@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c107: i2c_sfp3@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c108: i2c_sfp4@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c109: i2c_sfp5@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&gpio {
+ i2c_pins: i2c-pins {
+ pins = "GPIO_7"; /* No "default" scl for i2c0 */
+ function = "twi";
+ };
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19",
+ "GPIO_20", "GPIO_21";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_11";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_12";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_2: i2cmux-2 {
+ pins = "GPIO_18";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_3: i2cmux-3 {
+ pins = "GPIO_19";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_4: i2cmux-4 {
+ pins = "GPIO_20";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_5: i2cmux-5 {
+ pins = "GPIO_21";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ i2c-sda-hold-time-ns = <300>;
+};
+
diff --git a/dts/src/mips/mscc/serval_pcb105.dts b/dts/src/mips/mscc/serval_pcb105.dts
new file mode 100644
index 0000000000..a1b0012b79
--- /dev/null
+++ b/dts/src/mips/mscc/serval_pcb105.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "serval_common.dtsi"
+
+/ {
+ model = "Serval PCB105 Reference Board";
+ compatible = "mscc,serval-pcb105", "mscc,serval";
+
+ aliases {
+ };
+
+};
+
diff --git a/dts/src/mips/mscc/serval_pcb106.dts b/dts/src/mips/mscc/serval_pcb106.dts
new file mode 100644
index 0000000000..237be7c8da
--- /dev/null
+++ b/dts/src/mips/mscc/serval_pcb106.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "serval_common.dtsi"
+
+/ {
+ model = "Serval PCB106 Reference Board";
+ compatible = "mscc,serval-pcb106", "mscc,serval";
+
+ aliases {
+ };
+
+};
+
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-30 17:55:21 +0000