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-rw-r--r--dts/src/mips/ingenic/ci20.dts8
-rw-r--r--dts/src/mips/ingenic/jz4740.dtsi2
-rw-r--r--dts/src/mips/xilfpga/nexys4ddr.dts8
3 files changed, 9 insertions, 9 deletions
diff --git a/dts/src/mips/ingenic/ci20.dts b/dts/src/mips/ingenic/ci20.dts
index 50cff3c..4f7b1fa 100644
--- a/dts/src/mips/ingenic/ci20.dts
+++ b/dts/src/mips/ingenic/ci20.dts
@@ -76,7 +76,7 @@
status = "okay";
pinctrl-names = "default";
- pinctrl-0 = <&pins_uart2>;
+ pinctrl-0 = <&pins_uart3>;
};
&uart4 {
@@ -196,9 +196,9 @@
bias-disable;
};
- pins_uart2: uart2 {
- function = "uart2";
- groups = "uart2-data", "uart2-hwflow";
+ pins_uart3: uart3 {
+ function = "uart3";
+ groups = "uart3-data", "uart3-hwflow";
bias-disable;
};
diff --git a/dts/src/mips/ingenic/jz4740.dtsi b/dts/src/mips/ingenic/jz4740.dtsi
index 6fb16fd..2beb78a 100644
--- a/dts/src/mips/ingenic/jz4740.dtsi
+++ b/dts/src/mips/ingenic/jz4740.dtsi
@@ -161,7 +161,7 @@
#dma-cells = <2>;
interrupt-parent = <&intc>;
- interrupts = <29>;
+ interrupts = <20>;
clocks = <&cgu JZ4740_CLK_DMA>;
diff --git a/dts/src/mips/xilfpga/nexys4ddr.dts b/dts/src/mips/xilfpga/nexys4ddr.dts
index 2152b7b..cc8dbea 100644
--- a/dts/src/mips/xilfpga/nexys4ddr.dts
+++ b/dts/src/mips/xilfpga/nexys4ddr.dts
@@ -90,11 +90,11 @@
interrupts = <0>;
};
- axi_i2c: i2c@10A00000 {
+ axi_i2c: i2c@10a00000 {
compatible = "xlnx,xps-iic-2.00.a";
interrupt-parent = <&axi_intc>;
interrupts = <4>;
- reg = < 0x10A00000 0x10000 >;
+ reg = < 0x10a00000 0x10000 >;
clocks = <&ext>;
xlnx,clk-freq = <0x5f5e100>;
xlnx,family = "Artix7";
@@ -106,9 +106,9 @@
#address-cells = <1>;
#size-cells = <0>;
- ad7420@4B {
+ ad7420@4b {
compatible = "adi,adt7420";
- reg = <0x4B>;
+ reg = <0x4b>;
};
} ;
};