1 files changed, 0 insertions, 80 deletions
diff --git a/dts/src/riscv/microchip/microchip-mpfs-icicle-kit.dts b/dts/src/riscv/microchip/microchip-mpfs-icicle-kit.dts
deleted file mode 100644
index b254c60589..0000000000
--- a/dts/src/riscv/microchip/microchip-mpfs-icicle-kit.dts
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
-
-/dts-v1/;
-
-#include "microchip-mpfs.dtsi"
-
-/* Clock frequency (in Hz) of the rtcclk */
-#define RTCCLK_FREQ		1000000
-
-/ {
-	#address-cells = <2>;
-	#size-cells = <2>;
-	model = "Microchip PolarFire-SoC Icicle Kit";
-	compatible = "microchip,mpfs-icicle-kit";
-
-	aliases {
-		ethernet0 = &emac1;
-		serial0 = &serial0;
-		serial1 = &serial1;
-		serial2 = &serial2;
-		serial3 = &serial3;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	cpus {
-		timebase-frequency = <RTCCLK_FREQ>;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0x0 0x40000000>;
-		clocks = <&clkcfg 26>;
-	};
-
-	soc {
-	};
-};
-
-&serial0 {
-	status = "okay";
-};
-
-&serial1 {
-	status = "okay";
-};
-
-&serial2 {
-	status = "okay";
-};
-
-&serial3 {
-	status = "okay";
-};
-
-&sdcard {
-	status = "okay";
-};
-
-&emac0 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy0>;
-	phy0: ethernet-phy@8 {
-		reg = <8>;
-		ti,fifo-depth = <0x01>;
-	};
-};
-
-&emac1 {
-	status = "okay";
-	phy-mode = "sgmii";
-	phy-handle = <&phy1>;
-	phy1: ethernet-phy@9 {
-		reg = <9>;
-		ti,fifo-depth = <0x01>;
-	};
-};