diff options
Diffstat (limited to 'dts')
1255 files changed, 55129 insertions, 12369 deletions
diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile index 129cf698fa..5e08e3a6a9 100644 --- a/dts/Bindings/Makefile +++ b/dts/Bindings/Makefile @@ -64,9 +64,6 @@ override DTC_FLAGS := \ -Wno-unique_unit_address \ -Wunique_unit_address_if_enabled -# Disable undocumented compatible checks until warning free -override DT_CHECKER_FLAGS ?= - $(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE $(call if_changed_rule,chkdt) diff --git a/dts/Bindings/arm/amlogic.yaml b/dts/Bindings/arm/amlogic.yaml index caab7ceeda..949537cea6 100644 --- a/dts/Bindings/arm/amlogic.yaml +++ b/dts/Bindings/arm/amlogic.yaml @@ -7,19 +7,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic SoC based Platforms maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Martin Blumenstingl <martin.blumenstingl@googlemail.com> + - Jerome Brunet <jbrunet@baylibre.com> - Kevin Hilman <khilman@baylibre.com> -description: |+ - Work in progress statement: - - Device tree files and bindings applying to Amlogic SoCs and boards are - considered "unstable". Any Amlogic device tree binding may change at - any time. Be sure to use a device tree binary and a kernel image - generated from the same source tree. - - Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a - stable binding/ABI. - properties: $nodename: const: '/' @@ -146,6 +138,7 @@ properties: - enum: - amediatech,x96-max - amlogic,u200 + - freebox,fbx8am - radxa,zero - seirobotics,sei510 - const: amlogic,g12a diff --git a/dts/Bindings/arm/arm,realview.yaml b/dts/Bindings/arm/arm,realview.yaml index d1bdee98f9..3c5f1688db 100644 --- a/dts/Bindings/arm/arm,realview.yaml +++ b/dts/Bindings/arm/arm,realview.yaml @@ -10,9 +10,9 @@ maintainers: - Linus Walleij <linus.walleij@linaro.org> description: |+ - The ARM RealView series of reference designs were built to explore the ARM - 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to - the earlier CPUs such as TrustZone and multicore (MPCore). + The ARM RealView series of reference designs were built to explore the Arm11, + Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the + earlier CPUs such as TrustZone and multicore (MPCore). properties: $nodename: diff --git a/dts/Bindings/arm/atmel-at91.yaml b/dts/Bindings/arm/atmel-at91.yaml index 89d75fbb1d..82f37328cc 100644 --- a/dts/Bindings/arm/atmel-at91.yaml +++ b/dts/Bindings/arm/atmel-at91.yaml @@ -179,6 +179,12 @@ properties: - const: microchip,sama7g5 - const: microchip,sama7 + - description: Microchip SAMA7G54 Curiosity Board + items: + - const: microchip,sama7g54-curiosity + - const: microchip,sama7g5 + - const: microchip,sama7 + - description: Microchip LAN9662 Evaluation Boards. items: - enum: diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml index 228dcc5c7d..0027201e19 100644 --- a/dts/Bindings/arm/fsl.yaml +++ b/dts/Bindings/arm/fsl.yaml @@ -384,7 +384,8 @@ properties: - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board - toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board - - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board + - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.0/v1.1 + - toradex,apalis_imx6q-eval-v1.2 # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2 - const: toradex,apalis_imx6q - const: fsl,imx6q @@ -469,6 +470,7 @@ properties: - prt,prtvt7 # Protonic VT7 board - rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board - riot,imx6s-riotboard # RIoTboard i.MX6S + - sielaff,imx6dl-board # Sielaff i.MX6 Solo Board - skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2 - skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6 - solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite @@ -708,6 +710,7 @@ properties: - toradex,colibri-imx6ull # Colibri iMX6ULL Modules - toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module - toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules + - uni-t,uti260b # UNI-T UTi260B Thermal Camera - const: fsl,imx6ull - description: i.MX6ULL Armadeus Systems OPOS6ULDev Board @@ -1026,7 +1029,7 @@ properties: items: - enum: - dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board - - rve,rve-gateway # i.MX8MN RVE Gateway Board + - rve,gateway # i.MX8MN RVE Gateway Board - variscite,var-som-mx8mn-symphony - const: variscite,var-som-mx8mn - const: fsl,imx8mn @@ -1194,7 +1197,8 @@ properties: - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules items: - enum: - - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation Board + - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation V1.0/V1.1 Board + - toradex,apalis-imx8-eval-v1.2 # Apalis iMX8 Module on Apalis Evaluation V1.2 Board - toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board - const: toradex,apalis-imx8 - const: fsl,imx8qm @@ -1202,7 +1206,8 @@ properties: - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules items: - enum: - - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. Board + - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board + - toradex,apalis-imx8-v1.1-eval-v1.2 # Apalis iMX8 V1.1 Module on Apalis Eval. V1.2 Board - toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board - toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board - const: toradex,apalis-imx8-v1.1 @@ -1232,6 +1237,22 @@ properties: - const: toradex,colibri-imx8x - const: fsl,imx8qxp + - description: + TQMa8Xx is a series of SOM featuring NXP i.MX8X system-on-chip + variants. It is designed to be clicked on different carrier boards + MBa8Xx is the starterkit + oneOf: + - items: + - enum: + - tq,imx8dxp-tqma8xdp-mba8xx # TQ-Systems GmbH TQMa8XDP SOM on MBa8Xx + - const: tq,imx8dxp-tqma8xdp # TQ-Systems GmbH TQMa8XDP SOM (with i.MX8DXP) + - const: fsl,imx8dxp + - items: + - enum: + - tq,imx8qxp-tqma8xqp-mba8xx # TQ-Systems GmbH TQMa8XQP SOM on MBa8Xx + - const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP) + - const: fsl,imx8qxp + - description: i.MX8ULP based Boards items: - enum: @@ -1275,6 +1296,18 @@ properties: - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM - const: fsl,imx93 + - description: PHYTEC phyCORE-i.MX93 SoM based boards + items: + - const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93 + - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM + - const: fsl,imx93 + + - description: Variscite VAR-SOM-MX93 based boards + items: + - const: variscite,var-som-mx93-symphony + - const: variscite,var-som-mx93 + - const: fsl,imx93 + - description: Freescale Vybrid Platform Device Tree Bindings diff --git a/dts/Bindings/arm/marvell/armada-38x.txt b/dts/Bindings/arm/marvell/armada-38x.txt deleted file mode 100644 index 202953f188..0000000000 --- a/dts/Bindings/arm/marvell/armada-38x.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell Armada 38x Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 38x family shall have the -following property: - -Required root node property: - - - compatible: must contain "marvell,armada380" - -In addition, boards using the Marvell Armada 385 SoC shall have the -following property before the previous one: - -Required root node property: - -compatible: must contain "marvell,armada385" - -In addition, boards using the Marvell Armada 388 SoC shall have the -following property before the previous one: - -Required root node property: - -compatible: must contain "marvell,armada388" - -Example: - -compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380"; diff --git a/dts/Bindings/arm/marvell/armada-38x.yaml b/dts/Bindings/arm/marvell/armada-38x.yaml new file mode 100644 index 0000000000..cdf805b5db --- /dev/null +++ b/dts/Bindings/arm/marvell/armada-38x.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-38x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 38x Platforms + +maintainers: + - Gregory CLEMENT <gregory.clement@bootlin.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: + Netgear Armada 380 GS110EM Managed Switch. + items: + - const: netgear,gs110emx + - const: marvell,armada380 + + - description: + Marvell Armada 385 Development Boards. + items: + - enum: + - marvell,a385-db-amc + - marvell,a385-db-ap + - const: marvell,armada385 + - const: marvell,armada380 + + - description: + SolidRun Armada 385 based single-board computers. + items: + - enum: + - solidrun,clearfog-gtr-l8 + - solidrun,clearfog-gtr-s4 + - const: marvell,armada385 + - const: marvell,armada380 + + - description: + Kobol Armada 388 based Helios-4 NAS. + items: + - const: kobol,helios4 + - const: marvell,armada388 + - const: marvell,armada385 + - const: marvell,armada380 + + - description: + Marvell Armada 388 Development Boards. + items: + - enum: + - marvell,a388-gp + - const: marvell,armada388 + - const: marvell,armada385 + - const: marvell,armada380 + + - description: + SolidRun Armada 388 clearfog family single-board computers. + items: + - enum: + - solidrun,clearfog-base-a1 + - solidrun,clearfog-pro-a1 + - const: solidrun,clearfog-a1 + - const: marvell,armada388 + - const: marvell,armada385 + - const: marvell,armada380 + +additionalProperties: true diff --git a/dts/Bindings/arm/mediatek.yaml b/dts/Bindings/arm/mediatek.yaml index 6f2f64ae76..09f9ffd3ff 100644 --- a/dts/Bindings/arm/mediatek.yaml +++ b/dts/Bindings/arm/mediatek.yaml @@ -17,6 +17,7 @@ properties: const: '/' compatible: oneOf: + # Sort by SoC (last) compatible, then board compatible - items: - enum: - mediatek,mt2701-evb @@ -84,6 +85,11 @@ properties: - const: mediatek,mt7629 - items: - enum: + - xiaomi,ax3000t + - const: mediatek,mt7981b + - items: + - enum: + - acelink,ew-7886cax - bananapi,bpi-r3 - mediatek,mt7986a-rfb - const: mediatek,mt7986a @@ -93,6 +99,10 @@ properties: - const: mediatek,mt7986b - items: - enum: + - bananapi,bpi-r4 + - const: mediatek,mt7988a + - items: + - enum: - mediatek,mt8127-moose - const: mediatek,mt8127 - items: @@ -129,75 +139,10 @@ properties: - enum: - mediatek,mt8173-evb - const: mediatek,mt8173 - - items: - - enum: - - mediatek,mt8183-evb - - const: mediatek,mt8183 - - description: Google Hayato rev5 - items: - - const: google,hayato-rev5-sku2 - - const: google,hayato-sku2 - - const: google,hayato - - const: mediatek,mt8192 - - description: Google Hayato - items: - - const: google,hayato-rev1 - - const: google,hayato - - const: mediatek,mt8192 - - description: Google Spherion rev4 (Acer Chromebook 514) - items: - - const: google,spherion-rev4 - - const: google,spherion - - const: mediatek,mt8192 - - description: Google Spherion (Acer Chromebook 514) - items: - - const: google,spherion-rev3 - - const: google,spherion-rev2 - - const: google,spherion-rev1 - - const: google,spherion-rev0 - - const: google,spherion - - const: mediatek,mt8192 - - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H) - items: - - enum: - - google,tomato-rev2 - - google,tomato-rev1 - - const: google,tomato - - const: mediatek,mt8195 - - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H) - items: - - const: google,tomato-rev4 - - const: google,tomato-rev3 - - const: google,tomato - - const: mediatek,mt8195 - - items: - - enum: - - mediatek,mt8186-evb - - const: mediatek,mt8186 - - items: - - enum: - - mediatek,mt8188-evb - - const: mediatek,mt8188 - - items: - - enum: - - mediatek,mt8192-evb - - const: mediatek,mt8192 - - items: - - enum: - - mediatek,mt8195-demo - - mediatek,mt8195-evb - - const: mediatek,mt8195 - description: Google Burnet (HP Chromebook x360 11MK G3 EE) items: - const: google,burnet - const: mediatek,mt8183 - - description: Google Krane (Lenovo IdeaPad Duet, 10e,...) - items: - - enum: - - google,krane-sku0 - - google,krane-sku176 - - const: google,krane - - const: mediatek,mt8183 - description: Google Cozmo (Acer Chromebook 314) items: - const: google,cozmo @@ -255,6 +200,13 @@ properties: - google,kodama-sku32 - const: google,kodama - const: mediatek,mt8183 + - description: Google Krane (Lenovo IdeaPad Duet, 10e,...) + items: + - enum: + - google,krane-sku0 + - google,krane-sku176 + - const: google,krane + - const: mediatek,mt8183 - description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2) items: - enum: @@ -278,8 +230,123 @@ properties: - const: mediatek,mt8183 - items: - enum: + - mediatek,mt8183-evb + - const: mediatek,mt8183 + - items: + - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868)) + items: + - const: google,steelix-sku393219 + - const: google,steelix-sku393216 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868)) + items: + - const: google,steelix-sku393220 + - const: google,steelix-sku393217 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868)) + items: + - const: google,steelix-sku393221 + - const: google,steelix-sku393218 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Rusty (Lenovo 100e Chromebook Gen 4) + items: + - const: google,steelix-sku196609 + - const: google,steelix-sku196608 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4) + items: + - enum: + - google,steelix-sku131072 + - google,steelix-sku131073 + - const: google,steelix + - const: mediatek,mt8186 + - description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F) + items: + - const: google,tentacruel-sku262147 + - const: google,tentacruel-sku262146 + - const: google,tentacruel-sku262145 + - const: google,tentacruel-sku262144 + - const: google,tentacruel + - const: mediatek,mt8186 + - description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F) + items: + - const: google,tentacruel-sku262151 + - const: google,tentacruel-sku262150 + - const: google,tentacruel-sku262149 + - const: google,tentacruel-sku262148 + - const: google,tentacruel + - const: mediatek,mt8186 + - description: Google Tentacool (ASUS Chromebook CM14 CM1402C) + items: + - const: google,tentacruel-sku327681 + - const: google,tentacruel + - const: mediatek,mt8186 + - description: Google Tentacool (ASUS Chromebook CM14 CM1402C) + items: + - const: google,tentacruel-sku327683 + - const: google,tentacruel + - const: mediatek,mt8186 + - items: + - enum: + - mediatek,mt8186-evb + - const: mediatek,mt8186 + - items: + - enum: + - mediatek,mt8188-evb + - const: mediatek,mt8188 + - description: Google Hayato + items: + - const: google,hayato-rev1 + - const: google,hayato + - const: mediatek,mt8192 + - description: Google Hayato rev5 + items: + - const: google,hayato-rev5-sku2 + - const: google,hayato-sku2 + - const: google,hayato + - const: mediatek,mt8192 + - description: Google Spherion (Acer Chromebook 514) + items: + - const: google,spherion-rev3 + - const: google,spherion-rev2 + - const: google,spherion-rev1 + - const: google,spherion-rev0 + - const: google,spherion + - const: mediatek,mt8192 + - description: Google Spherion rev4 (Acer Chromebook 514) + items: + - const: google,spherion-rev4 + - const: google,spherion + - const: mediatek,mt8192 + - items: + - enum: + - mediatek,mt8192-evb + - const: mediatek,mt8192 + - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H) + items: + - enum: + - google,tomato-rev2 + - google,tomato-rev1 + - const: google,tomato + - const: mediatek,mt8195 + - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H) + items: + - const: google,tomato-rev4 + - const: google,tomato-rev3 + - const: google,tomato + - const: mediatek,mt8195 + - items: + - enum: + - mediatek,mt8195-demo + - mediatek,mt8195-evb + - const: mediatek,mt8195 - items: - enum: - mediatek,mt8365-evk @@ -287,6 +354,7 @@ properties: - items: - enum: - mediatek,mt8395-evk + - radxa,nio-12l - const: mediatek,mt8395 - const: mediatek,mt8195 - items: diff --git a/dts/Bindings/arm/mediatek/mediatek,hifsys.txt b/dts/Bindings/arm/mediatek/mediatek,hifsys.txt deleted file mode 100644 index 323905af82..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,hifsys.txt +++ /dev/null @@ -1,26 +0,0 @@ -Mediatek hifsys controller -============================ - -The Mediatek hifsys controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-hifsys", "syscon" - - "mediatek,mt7622-hifsys", "syscon" - - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" -- #clock-cells: Must be 1 - -The hifsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -hifsys: clock-controller@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/arm/mediatek/mediatek,pciesys.txt b/dts/Bindings/arm/mediatek/mediatek,pciesys.txt deleted file mode 100644 index d179a61536..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,pciesys.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek PCIESYS controller -============================ - -The MediaTek PCIESYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-pciesys", "syscon" - - "mediatek,mt7629-pciesys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The PCIESYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -pciesys: pciesys@1a100800 { - compatible = "mediatek,mt7622-pciesys", "syscon"; - reg = <0 0x1a100800 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt b/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt deleted file mode 100644 index 7cb02c9306..0000000000 --- a/dts/Bindings/arm/mediatek/mediatek,ssusbsys.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek SSUSBSYS controller -============================ - -The MediaTek SSUSBSYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-ssusbsys", "syscon" - - "mediatek,mt7629-ssusbsys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The SSUSBSYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -ssusbsys: ssusbsys@1a000000 { - compatible = "mediatek,mt7622-ssusbsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/arm/msm/qcom,saw2.txt b/dts/Bindings/arm/msm/qcom,saw2.txt deleted file mode 100644 index c0e3c3a42b..0000000000 --- a/dts/Bindings/arm/msm/qcom,saw2.txt +++ /dev/null @@ -1,58 +0,0 @@ -SPM AVS Wrapper 2 (SAW2) - -The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the -Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -power-controller that transitions a piece of hardware (like a processor or -subsystem) into and out of low power modes via a direct connection to -the PMIC. It can also be wired up to interact with other processors in the -system, notifying them when a low power state is entered or exited. - -Multiple revisions of the SAW hardware are supported using these Device Nodes. -SAW2 revisions differ in the register offset and configuration data. Also, the -same revision of the SAW in different SoCs may have different configuration -data due the differences in hardware capabilities. Hence the SoC name, the -version of the SAW hardware in that SoC and the distinction between cpu (big -or Little) or cache, may be needed to uniquely identify the SAW register -configuration and initialization data. The compatible string is used to -indicate this parameter. - -PROPERTIES - -- compatible: - Usage: required - Value type: <string> - Definition: Must have - "qcom,saw2" - A more specific value could be one of: - "qcom,apq8064-saw2-v1.1-cpu" - "qcom,msm8226-saw2-v2.1-cpu" - "qcom,msm8974-saw2-v2.1-cpu" - "qcom,apq8084-saw2-v2.1-cpu" - -- reg: - Usage: required - Value type: <prop-encoded-array> - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- regulator: - Usage: optional - Value type: boolean - Definition: Indicates that this SPM device acts as a regulator device - device for the core (CPU or Cache) the SPM is attached - to. - -Example 1: - - power-controller@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -Example 2: - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; diff --git a/dts/Bindings/arm/qcom,coresight-tpdm.yaml b/dts/Bindings/arm/qcom,coresight-tpdm.yaml index 61ddc3b5b2..8eec07d9d4 100644 --- a/dts/Bindings/arm/qcom,coresight-tpdm.yaml +++ b/dts/Bindings/arm/qcom,coresight-tpdm.yaml @@ -44,14 +44,21 @@ properties: minItems: 1 maxItems: 2 - qcom,dsb-element-size: + qcom,dsb-element-bits: description: Specifies the DSB(Discrete Single Bit) element size supported by the monitor. The associated aggregator will read this size before it is enabled. DSB element size currently only supports 32-bit and 64-bit. - $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64] + qcom,cmb-element-bits: + description: + Specifies the CMB(Continuous Multi-Bit) element size supported by + the monitor. The associated aggregator will read this size before it + is enabled. CMB element size currently only supports 8-bit, 32-bit + and 64-bit. + enum: [8, 32, 64] + qcom,dsb-msrs-num: description: Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) @@ -61,6 +68,15 @@ properties: minimum: 0 maximum: 32 + qcom,cmb-msrs-num: + description: + Specifies the number of CMB MSR(mux select register) registers supported + by the monitor. If this property is not configured or set to 0, it means + this TPDM doesn't support CMB MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + clocks: maxItems: 1 @@ -94,7 +110,7 @@ examples: compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0684c000 0x1000>; - qcom,dsb-element-size = /bits/ 8 <32>; + qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <16>; clocks = <&aoss_qmp>; @@ -110,4 +126,22 @@ examples: }; }; + tpdm@6c29000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x06c29000 0x1000>; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_out_funnel_center: endpoint { + remote-endpoint = <&funnel_center_in_tpdm_ipcc>; + }; + }; + }; + }; ... diff --git a/dts/Bindings/arm/qcom.yaml b/dts/Bindings/arm/qcom.yaml index 1a5fb889a4..66beaac60e 100644 --- a/dts/Bindings/arm/qcom.yaml +++ b/dts/Bindings/arm/qcom.yaml @@ -10,17 +10,10 @@ maintainers: - Bjorn Andersson <bjorn.andersson@linaro.org> description: | - Some qcom based bootloaders identify the dtb blob based on a set of - device properties like SoC and platform and revisions of those components. - To support this scheme, we encode this information into the board compatible - string. - - Each board must specify a top-level board compatible string with the following - format: - - compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]" - - The 'SoC' and 'board' elements are required. All other elements are optional. + For devices using the Qualcomm SoC the "compatible" properties consists of + one or several "manufacturer,model" strings, describing the device itself, + followed by one or several "qcom,<SoC>" strings, describing the SoC used in + the device. The 'SoC' element must be one of the following strings: @@ -90,43 +83,9 @@ description: | sm8650 x1e80100 - The 'board' element must be one of the following strings: - - adp - cdp - dragonboard - idp - liquid - mtp - qcp - qrd - rb2 - ride - sbc - x100 - - The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> - where the minor number may be omitted when it's zero, i.e. v1.0 is the same - as v1. If all versions of the 'board_version' elements match, then a - wildcard '*' should be used, e.g. 'v*'. - - The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9. - - Examples: - - "qcom,msm8916-v1-cdp-pm8916-v2.1" - - A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version - 2.1. - - "qcom,apq8074-v2.0-2-dragonboard/1-v0.1" - - A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in - foundry 2. - There are many devices in the list below that run the standard ChromeOS bootloader setup and use the open source depthcharge bootloader to boot the - OS. These devices do not use the scheme described above. For details, see: + OS. These devices use the bootflow explained at https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html properties: @@ -187,6 +146,7 @@ properties: - microsoft,superman-lte - microsoft,tesla - motorola,peregrine + - samsung,matisselte - const: qcom,msm8926 - const: qcom,msm8226 @@ -244,11 +204,15 @@ properties: - samsung,a5u-eur - samsung,e5 - samsung,e7 + - samsung,fortuna3g + - samsung,gprimeltecan - samsung,grandmax + - samsung,grandprimelte - samsung,gt510 - samsung,gt58 - samsung,j5 - samsung,j5x + - samsung,rossa - samsung,serranove - thwc,uf896 - thwc,ufi001c @@ -988,6 +952,7 @@ properties: - items: - enum: + - xiaomi,curtana - xiaomi,joyeuse - const: qcom,sm7125 @@ -1035,6 +1000,7 @@ properties: - items: - enum: + - qcom,sm8550-hdk - qcom,sm8550-mtp - qcom,sm8550-qrd - const: qcom,sm8550 diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml index 5cf5cbef2c..fcf7316ecd 100644 --- a/dts/Bindings/arm/rockchip.yaml +++ b/dts/Bindings/arm/rockchip.yaml @@ -37,29 +37,16 @@ properties: - anbernic,rg351v - const: rockchip,rk3326 - - description: Anbernic RG353P + - description: Anbernic RK3566 Handheld Gaming Console items: - - const: anbernic,rg353p - - const: rockchip,rk3566 - - - description: Anbernic RG353PS - items: - - const: anbernic,rg353ps - - const: rockchip,rk3566 - - - description: Anbernic RG353V - items: - - const: anbernic,rg353v - - const: rockchip,rk3566 - - - description: Anbernic RG353VS - items: - - const: anbernic,rg353vs - - const: rockchip,rk3566 - - - description: Anbernic RG503 - items: - - const: anbernic,rg503 + - enum: + - anbernic,rg353p + - anbernic,rg353ps + - anbernic,rg353v + - anbernic,rg353vs + - anbernic,rg503 + - anbernic,rg-arc-d + - anbernic,rg-arc-s - const: rockchip,rk3566 - description: Asus Tinker board @@ -237,6 +224,13 @@ properties: - friendlyarm,nanopi-r5s - const: rockchip,rk3568 + - description: FriendlyElec NanoPi R6 series boards + items: + - enum: + - friendlyarm,nanopi-r6c + - friendlyarm,nanopi-r6s + - const: rockchip,rk3588s + - description: FriendlyElec NanoPC T6 items: - const: friendlyarm,nanopc-t6 @@ -626,9 +620,9 @@ properties: - const: openailab,eaidk-610 - const: rockchip,rk3399 - - description: Orange Pi RK3399 board + - description: Xunlong Orange Pi RK3399 board items: - - const: rockchip,rk3399-orangepi + - const: xunlong,rk3399-orangepi - const: rockchip,rk3399 - description: Phytec phyCORE-RK3288 Rapid Development Kit @@ -655,6 +649,14 @@ properties: - const: pine64,pinephone-pro - const: rockchip,rk3399 + - description: Pine64 PineTab2 + items: + - enum: + - pine64,pinetab2-v0.1 + - pine64,pinetab2-v2.0 + - const: pine64,pinetab2 + - const: rockchip,rk3566 + - description: Pine64 Rock64 items: - const: pine64,rock64 @@ -692,11 +694,17 @@ properties: - description: Powkiddy RK3566 Handheld Gaming Console items: - enum: + - powkiddy,rgb10max3 - powkiddy,rgb30 - powkiddy,rk2023 - powkiddy,x55 - const: rockchip,rk3566 + - description: QNAP TS-433-4G 4-Bay NAS + items: + - const: qnap,ts433 + - const: rockchip,rk3568 + - description: Radxa Compute Module 3(CM3) items: - enum: @@ -878,6 +886,11 @@ properties: - const: rockchip,rv1108-evb - const: rockchip,rv1108 + - description: Rockchip Toybrick TB-RK3588X board + items: + - const: rockchip,rk3588-toybrick-x0 + - const: rockchip,rk3588 + - description: Theobroma Systems PX30-uQ7 with Haikou baseboard items: - const: tsd,px30-ringneck-haikou @@ -898,6 +911,12 @@ properties: - const: tsd,rk3588-jaguar - const: rockchip,rk3588 + - description: Theobroma Systems RK3588-Q7 with Haikou baseboard + items: + - const: tsd,rk3588-tiger-haikou + - const: tsd,rk3588-tiger + - const: rockchip,rk3588 + - description: Tronsmart Orion R68 Meta items: - const: tronsmart,orion-r68-meta @@ -940,9 +959,9 @@ properties: - const: rockchip,rk3568-evb1-v10 - const: rockchip,rk3568 - - description: Rockchip RK3568 Banana Pi R2 Pro + - description: Sinovoip RK3568 Banana Pi R2 Pro items: - - const: rockchip,rk3568-bpi-r2pro + - const: sinovoip,rk3568-bpi-r2pro - const: rockchip,rk3568 - description: Sonoff iHost Smart Home Hub diff --git a/dts/Bindings/arm/sunxi.yaml b/dts/Bindings/arm/sunxi.yaml index a9d8e85565..09d835db6d 100644 --- a/dts/Bindings/arm/sunxi.yaml +++ b/dts/Bindings/arm/sunxi.yaml @@ -815,6 +815,12 @@ properties: - const: allwinner,r7-tv-dongle - const: allwinner,sun5i-a10s + - description: Remix Mini PC + items: + - const: jide,remix-mini-pc + - const: allwinner,sun50i-h64 + - const: allwinner,sun50i-a64 + - description: RerVision H3-DVK items: - const: rervision,h3-dvk @@ -835,6 +841,12 @@ properties: - const: sinlinx,sina33 - const: allwinner,sun8i-a33 + - description: Sipeed Longan Pi 3H board for the Sipeed Longan Module 3H + items: + - const: sipeed,longan-pi-3h + - const: sipeed,longan-module-3h + - const: allwinner,sun50i-h618 + - description: SourceParts PopStick v1.1 items: - const: sourceparts,popstick-v1.1 diff --git a/dts/Bindings/arm/syna.txt b/dts/Bindings/arm/syna.txt index 851f48ead9..f53c430f64 100644 --- a/dts/Bindings/arm/syna.txt +++ b/dts/Bindings/arm/syna.txt @@ -6,18 +6,6 @@ berlin SoCs are now Synaptics' SoCs now. --------------------------------------------------------------- -Work in progress statement: - -Device tree files and bindings applying to Marvell Berlin SoCs and boards are -considered "unstable". Any Marvell Berlin device tree binding may change at any -time. Be sure to use a device tree binary and a kernel image generated from the -same source tree. - -Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a -stable binding/ABI. - ---------------------------------------------------------------- - Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: diff --git a/dts/Bindings/arm/tegra.yaml b/dts/Bindings/arm/tegra.yaml index fcf9564061..8fb4923517 100644 --- a/dts/Bindings/arm/tegra.yaml +++ b/dts/Bindings/arm/tegra.yaml @@ -64,6 +64,14 @@ properties: - items: - const: asus,tf700t - const: nvidia,tegra30 + - description: LG Optimus 4X P880 + items: + - const: lg,p880 + - const: nvidia,tegra30 + - description: LG Optimus Vu P895 + items: + - const: lg,p895 + - const: nvidia,tegra30 - items: - const: toradex,apalis_t30-eval - const: toradex,apalis_t30 diff --git a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml index 0faa403f68..ea4fbf6552 100644 --- a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml +++ b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -27,7 +27,7 @@ properties: - const: pmc - const: wake - const: aotag - - const: scratch + - enum: [ scratch, misc ] - const: misc interrupt-controller: true @@ -41,25 +41,43 @@ properties: description: If present, inverts the PMU interrupt signal. $ref: /schemas/types.yaml#/definitions/flag -if: - properties: - compatible: - contains: - const: nvidia,tegra186-pmc -then: - properties: - reg: - maxItems: 4 - - reg-names: - maxItems: 4 -else: - properties: - reg: - minItems: 5 - - reg-names: - minItems: 5 +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra186-pmc + then: + properties: + reg: + maxItems: 4 + reg-names: + maxItems: 4 + contains: + const: scratch + + - if: + properties: + compatible: + contains: + const: nvidia,tegra194-pmc + then: + properties: + reg: + minItems: 5 + reg-names: + minItems: 5 + + - if: + properties: + compatible: + contains: + const: nvidia,tegra234-pmc + then: + properties: + reg-names: + contains: + const: misc patternProperties: "^[a-z0-9]+-[a-z0-9]+$": diff --git a/dts/Bindings/arm/ti/k3.yaml b/dts/Bindings/arm/ti/k3.yaml index c6506bccfe..52b51fd704 100644 --- a/dts/Bindings/arm/ti/k3.yaml +++ b/dts/Bindings/arm/ti/k3.yaml @@ -87,12 +87,20 @@ properties: - const: tq,am642-tqma6442l - const: ti,am642 + - description: K3 AM642 SoC SolidRun SoM based boards + items: + - enum: + - solidrun,am642-hummingboard-t + - const: solidrun,am642-sr-som + - const: ti,am642 + - description: K3 AM654 SoC items: - enum: - siemens,iot2050-advanced - siemens,iot2050-advanced-m2 - siemens,iot2050-advanced-pg2 + - siemens,iot2050-advanced-sm - siemens,iot2050-basic - siemens,iot2050-basic-pg2 - ti,am654-evm @@ -123,6 +131,12 @@ properties: - ti,j721s2-evm - const: ti,j721s2 + - description: K3 J722S SoC and Boards + items: + - enum: + - ti,j722s-evm + - const: ti,j722s + - description: K3 J784s4 SoC items: - enum: diff --git a/dts/Bindings/ata/ahci-mtk.txt b/dts/Bindings/ata/ahci-mtk.txt deleted file mode 100644 index d2aa696b16..0000000000 --- a/dts/Bindings/ata/ahci-mtk.txt +++ /dev/null @@ -1,51 +0,0 @@ -MediaTek Serial ATA controller - -Required properties: - - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci". - When using "mediatek,mtk-ahci" compatible strings, you - need SoC specific ones in addition, one of: - - "mediatek,mt7622-ahci" - - reg : Physical base addresses and length of register sets. - - interrupts : Interrupt associated with the SATA device. - - interrupt-names : Associated name must be: "hostc". - - clocks : A list of phandle and clock specifier pairs, one for each - entry in clock-names. - - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm". - - phys : A phandle and PHY specifier pair for the PHY port. - - phy-names : Associated name must be: "sata-phy". - - ports-implemented : See ./ahci-platform.txt for details. - -Optional properties: - - power-domains : A phandle and power domain specifier pair to the power - domain which is responsible for collapsing and restoring - power to the peripheral. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Associated names must be: "axi", "sw", "reg". - - mediatek,phy-mode : A phandle to the system controller, used to enable - SATA function. - -Example: - - sata: sata@1a200000 { - compatible = "mediatek,mt7622-ahci", - "mediatek,mtk-ahci"; - reg = <0 0x1a200000 0 0x1100>; - interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hostc"; - clocks = <&pciesys CLK_SATA_AHB_EN>, - <&pciesys CLK_SATA_AXI_EN>, - <&pciesys CLK_SATA_ASIC_EN>, - <&pciesys CLK_SATA_RBC_EN>, - <&pciesys CLK_SATA_PM_EN>; - clock-names = "ahb", "axi", "asic", "rbc", "pm"; - phys = <&u3port1 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, - <&pciesys MT7622_SATA_PHY_SW_RST>, - <&pciesys MT7622_SATA_PHY_REG_RST>; - reset-names = "axi", "sw", "reg"; - mediatek,phy-mode = <&pciesys>; - }; diff --git a/dts/Bindings/ata/atmel-at91_cf.txt b/dts/Bindings/ata/atmel-at91_cf.txt deleted file mode 100644 index c1d22b3ae1..0000000000 --- a/dts/Bindings/ata/atmel-at91_cf.txt +++ /dev/null @@ -1,19 +0,0 @@ -Atmel AT91RM9200 CompactFlash - -Required properties: -- compatible : "atmel,at91rm9200-cf". -- reg : should specify localbus address and size used. -- gpios : specifies the gpio pins to control the CF device. Detect - and reset gpio's are mandatory while irq and vcc gpio's are - optional and may be set to 0 if not present. - -Example: -compact-flash@50000000 { - compatible = "atmel,at91rm9200-cf"; - reg = <0x50000000 0x30000000>; - gpios = <&pioC 13 0 /* irq */ - &pioC 15 0 /* detect */ - 0 /* vcc */ - &pioC 5 0 /* reset */ - >; -}; diff --git a/dts/Bindings/ata/mediatek,mtk-ahci.yaml b/dts/Bindings/ata/mediatek,mtk-ahci.yaml new file mode 100644 index 0000000000..a34bd2e9c3 --- /dev/null +++ b/dts/Bindings/ata/mediatek,mtk-ahci.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Serial ATA controller + +maintainers: + - Ryder Lee <ryder.lee@mediatek.com> + +allOf: + - $ref: ahci-common.yaml# + +properties: + compatible: + items: + - enum: + - mediatek,mt7622-ahci + - const: mediatek,mtk-ahci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + const: hostc + + clocks: + maxItems: 5 + + clock-names: + items: + - const: ahb + - const: axi + - const: asic + - const: rbc + - const: pm + + power-domains: + maxItems: 1 + + resets: + maxItems: 3 + + reset-names: + items: + - const: axi + - const: sw + - const: reg + + mediatek,phy-mode: + description: System controller phandle, used to enable SATA function + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - phys + - phy-names + - ports-implemented + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt7622-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/power/mt7622-power.h> + #include <dt-bindings/reset/mt7622-reset.h> + + sata@1a200000 { + compatible = "mediatek,mt7622-ahci", "mediatek,mtk-ahci"; + reg = <0x1a200000 0x1100>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hostc"; + clocks = <&pciesys CLK_SATA_AHB_EN>, + <&pciesys CLK_SATA_AXI_EN>, + <&pciesys CLK_SATA_ASIC_EN>, + <&pciesys CLK_SATA_RBC_EN>, + <&pciesys CLK_SATA_PM_EN>; + clock-names = "ahb", "axi", "asic", "rbc", "pm"; + phys = <&u3port1 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi", "sw", "reg"; + mediatek,phy-mode = <&pciesys>; + }; diff --git a/dts/Bindings/auxdisplay/arm,versatile-lcd.yaml b/dts/Bindings/auxdisplay/arm,versatile-lcd.yaml index 5d02bd032a..439f7b811a 100644 --- a/dts/Bindings/auxdisplay/arm,versatile-lcd.yaml +++ b/dts/Bindings/auxdisplay/arm,versatile-lcd.yaml @@ -39,6 +39,6 @@ additionalProperties: false examples: - | lcd@10008000 { - compatible = "arm,versatile-lcd"; - reg = <0x10008000 0x1000>; + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; }; diff --git a/dts/Bindings/auxdisplay/gpio-7-segment.yaml b/dts/Bindings/auxdisplay/gpio-7-segment.yaml new file mode 100644 index 0000000000..328954893c --- /dev/null +++ b/dts/Bindings/auxdisplay/gpio-7-segment.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/auxdisplay/gpio-7-segment.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO based LED segment display + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +properties: + compatible: + const: gpio-7-segment + + segment-gpios: + description: | + An array of GPIOs one per segment. The first GPIO corresponds to the A + segment, the seventh GPIO corresponds to the G segment. Some LED blocks + also have a decimal point which can be specified as an optional eighth + segment. + + -a- + | | + f b + | | + -g- + | | + e c + | | + -d- dp + + minItems: 7 + maxItems: 8 + +required: + - segment-gpios + +additionalProperties: false + +examples: + - | + + #include <dt-bindings/gpio/gpio.h> + + led-7seg { + compatible = "gpio-7-segment"; + segment-gpios = <&gpio 0 GPIO_ACTIVE_LOW>, + <&gpio 1 GPIO_ACTIVE_LOW>, + <&gpio 2 GPIO_ACTIVE_LOW>, + <&gpio 3 GPIO_ACTIVE_LOW>, + <&gpio 4 GPIO_ACTIVE_LOW>, + <&gpio 5 GPIO_ACTIVE_LOW>, + <&gpio 6 GPIO_ACTIVE_LOW>; + }; diff --git a/dts/Bindings/auxdisplay/hit,hd44780.yaml b/dts/Bindings/auxdisplay/hit,hd44780.yaml index 406a922a71..3ca0e9863d 100644 --- a/dts/Bindings/auxdisplay/hit,hd44780.yaml +++ b/dts/Bindings/auxdisplay/hit,hd44780.yaml @@ -84,42 +84,44 @@ additionalProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> - auxdisplay { - compatible = "hit,hd44780"; - - data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>, - <&hc595 1 GPIO_ACTIVE_HIGH>, - <&hc595 2 GPIO_ACTIVE_HIGH>, - <&hc595 3 GPIO_ACTIVE_HIGH>; - enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - - display-height-chars = <2>; - display-width-chars = <16>; + display-controller { + compatible = "hit,hd44780"; + + data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>, + <&hc595 1 GPIO_ACTIVE_HIGH>, + <&hc595 2 GPIO_ACTIVE_HIGH>, + <&hc595 3 GPIO_ACTIVE_HIGH>; + enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + + display-height-chars = <2>; + display-width-chars = <16>; }; + - | #include <dt-bindings/gpio/gpio.h> i2c { - #address-cells = <1>; - #size-cells = <0>; - - pcf8574: pcf8574@27 { - compatible = "nxp,pcf8574"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - }; + #address-cells = <1>; + #size-cells = <0>; + + pcf8574: gpio-expander@27 { + compatible = "nxp,pcf8574"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + }; }; - hd44780 { - compatible = "hit,hd44780"; - display-height-chars = <2>; - display-width-chars = <16>; - data-gpios = <&pcf8574 4 0>, - <&pcf8574 5 0>, - <&pcf8574 6 0>, - <&pcf8574 7 0>; - enable-gpios = <&pcf8574 2 0>; - rs-gpios = <&pcf8574 0 0>; - rw-gpios = <&pcf8574 1 0>; - backlight-gpios = <&pcf8574 3 0>; + + display-controller { + compatible = "hit,hd44780"; + display-height-chars = <2>; + display-width-chars = <16>; + data-gpios = <&pcf8574 4 GPIO_ACTIVE_HIGH>, + <&pcf8574 5 GPIO_ACTIVE_HIGH>, + <&pcf8574 6 GPIO_ACTIVE_HIGH>, + <&pcf8574 7 GPIO_ACTIVE_HIGH>; + enable-gpios = <&pcf8574 2 GPIO_ACTIVE_HIGH>; + rs-gpios = <&pcf8574 0 GPIO_ACTIVE_HIGH>; + rw-gpios = <&pcf8574 1 GPIO_ACTIVE_HIGH>; + backlight-gpios = <&pcf8574 3 GPIO_ACTIVE_HIGH>; }; diff --git a/dts/Bindings/auxdisplay/holtek,ht16k33.yaml b/dts/Bindings/auxdisplay/holtek,ht16k33.yaml index be95f6b97b..b90eec2077 100644 --- a/dts/Bindings/auxdisplay/holtek,ht16k33.yaml +++ b/dts/Bindings/auxdisplay/holtek,ht16k33.yaml @@ -74,31 +74,31 @@ examples: #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> i2c { - #address-cells = <1>; - #size-cells = <0>; - - ht16k33: ht16k33@70 { - compatible = "holtek,ht16k33"; - reg = <0x70>; - refresh-rate-hz = <20>; - interrupt-parent = <&gpio4>; - interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; - debounce-delay-ms = <50>; - linux,keymap = <MATRIX_KEY(2, 0, KEY_F6)>, - <MATRIX_KEY(3, 0, KEY_F8)>, - <MATRIX_KEY(4, 0, KEY_F10)>, - <MATRIX_KEY(5, 0, KEY_F4)>, - <MATRIX_KEY(6, 0, KEY_F2)>, - <MATRIX_KEY(2, 1, KEY_F5)>, - <MATRIX_KEY(3, 1, KEY_F7)>, - <MATRIX_KEY(4, 1, KEY_F9)>, - <MATRIX_KEY(5, 1, KEY_F3)>, - <MATRIX_KEY(6, 1, KEY_F1)>; - - led { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_BACKLIGHT; - linux,default-trigger = "backlight"; - }; + #address-cells = <1>; + #size-cells = <0>; + + display-controller@70 { + compatible = "holtek,ht16k33"; + reg = <0x70>; + refresh-rate-hz = <20>; + interrupt-parent = <&gpio4>; + interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + debounce-delay-ms = <50>; + linux,keymap = <MATRIX_KEY(2, 0, KEY_F6)>, + <MATRIX_KEY(3, 0, KEY_F8)>, + <MATRIX_KEY(4, 0, KEY_F10)>, + <MATRIX_KEY(5, 0, KEY_F4)>, + <MATRIX_KEY(6, 0, KEY_F2)>, + <MATRIX_KEY(2, 1, KEY_F5)>, + <MATRIX_KEY(3, 1, KEY_F7)>, + <MATRIX_KEY(4, 1, KEY_F9)>, + <MATRIX_KEY(5, 1, KEY_F3)>, + <MATRIX_KEY(6, 1, KEY_F1)>; + + led { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_BACKLIGHT; + linux,default-trigger = "backlight"; }; - }; + }; + }; diff --git a/dts/Bindings/auxdisplay/img,ascii-lcd.yaml b/dts/Bindings/auxdisplay/img,ascii-lcd.yaml index 1899b23de7..55e9831b3f 100644 --- a/dts/Bindings/auxdisplay/img,ascii-lcd.yaml +++ b/dts/Bindings/auxdisplay/img,ascii-lcd.yaml @@ -50,6 +50,6 @@ additionalProperties: false examples: - | lcd: lcd@17fff000 { - compatible = "img,boston-lcd"; - reg = <0x17fff000 0x8>; + compatible = "img,boston-lcd"; + reg = <0x17fff000 0x8>; }; diff --git a/dts/Bindings/auxdisplay/maxim,max6959.yaml b/dts/Bindings/auxdisplay/maxim,max6959.yaml new file mode 100644 index 0000000000..20dd9e8c81 --- /dev/null +++ b/dts/Bindings/auxdisplay/maxim,max6959.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/auxdisplay/maxim,max6959.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MAX6958/6959 7-segment LED display controller + +maintainers: + - Andy Shevchenko <andriy.shevchenko@linux.intel.com> + +description: + The Maxim MAX6958/6959 7-segment LED display controller provides + an I2C interface to up to four 7-segment LED digits. The MAX6959, + in comparison to MAX6958, adds input support. Type of the chip can + be autodetected via specific register read, and hence the features + may be enabled in the driver at run-time, in case they are requested + via Device Tree. A given hardware is simple and does not provide + any additional pins, such as reset or power enable. + +properties: + compatible: + const: maxim,max6959 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + display-controller@38 { + compatible = "maxim,max6959"; + reg = <0x38>; + }; + }; diff --git a/dts/Bindings/bus/brcm,gisb-arb.yaml b/dts/Bindings/bus/brcm,gisb-arb.yaml index 3aaefdbe36..9017c5a3f3 100644 --- a/dts/Bindings/bus/brcm,gisb-arb.yaml +++ b/dts/Bindings/bus/brcm,gisb-arb.yaml @@ -18,6 +18,7 @@ properties: - const: brcm,gisb-arb - items: - enum: + - brcm,bcm74165-gisb-arb # for V7 new style 16nm chips - brcm,bcm7278-gisb-arb # for V7 28nm chips - brcm,bcm7435-gisb-arb # for newer 40nm chips - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips diff --git a/dts/Bindings/bus/imx-weim.txt b/dts/Bindings/bus/imx-weim.txt deleted file mode 100644 index e7f502070d..0000000000 --- a/dts/Bindings/bus/imx-weim.txt +++ /dev/null @@ -1,117 +0,0 @@ -Device tree bindings for i.MX Wireless External Interface Module (WEIM) - -The term "wireless" does not imply that the WEIM is literally an interface -without wires. It simply means that this module was originally designed for -wireless and mobile applications that use low-power technology. - -The actual devices are instantiated from the child nodes of a WEIM node. - -Required properties: - - - compatible: Should contain one of the following: - "fsl,imx1-weim" - "fsl,imx27-weim" - "fsl,imx51-weim" - "fsl,imx50-weim" - "fsl,imx6q-weim" - - reg: A resource specifier for the register space - (see the example below) - - clocks: the clock, see the example below. - - #address-cells: Must be set to 2 to allow memory address translation - - #size-cells: Must be set to 1 to allow CS address passing - - ranges: Must be set up to reflect the memory layout with four - integer values for each chip-select line in use: - - <cs-number> 0 <physical address of mapping> <size> - -Optional properties: - - - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of - devices, it should be the phandle to the system General - Purpose Register controller that contains WEIM CS GPR - register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] - should be set up as one of the following 4 possible - values depending on the CS space configuration. - - IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 - --------------------------------------------- - 05 128M 0M 0M 0M - 033 64M 64M 0M 0M - 0113 64M 32M 32M 0M - 01111 32M 32M 32M 32M - - In case that the property is absent, the reset value or - what bootloader sets up in IOMUXC_GPR1[11:0] will be - used. - - - fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of - devices, the presence of this property indicates that - the weim bus should operate in Burst Clock Mode. - - - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. - Without this option Burst Clock will output clock - only when necessary. This takes effect only if - "fsl,burst-clk-enable" is set. - -Timing property for child nodes. It is mandatory, not optional. - - - fsl,weim-cs-timing: The timing array, contains timing values for the - child node. We get the CS indexes from the address - ranges in the child node's "reg" property. - The number of registers depends on the selected chip: - For i.MX1, i.MX21 ("fsl,imx1-weim") there are two - registers: CSxU, CSxL. - For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim") - there are three registers: CSCRxU, CSCRxL, CSCRxA. - For i.MX50, i.MX53 ("fsl,imx50-weim"), - i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim") - there are six registers: CSxGCR1, CSxGCR2, CSxRCR1, - CSxRCR2, CSxWCR1, CSxWCR2. - -Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: - - weim: weim@21b8000 { - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - clocks = <&clks 196>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x08000000>; - fsl,weim-cs-gpr = <&gpr>; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x02000000>; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 - 0x0000c000 0x1404a38e 0x00000000>; - }; - }; - -Example for an imx6q-based board, a multi-chipselect device connected to WEIM: - -In this case, both chip select 0 and 1 will be configured with the same timing -array values. - - weim: weim@21b8000 { - compatible = "fsl,imx6q-weim"; - reg = <0x021b8000 0x4000>; - clocks = <&clks 196>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x02000000 - 1 0 0x0a000000 0x02000000 - 2 0 0x0c000000 0x02000000 - 3 0 0x0e000000 0x02000000>; - fsl,weim-cs-gpr = <&gpr>; - - acme@0 { - compatible = "acme,whatever"; - reg = <0 0 0x100>, <0 0x400000 0x800>, - <1 0x400000 0x800>; - fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100 - 0x00000000 0xa0000240 0x00000000>; - }; - }; diff --git a/dts/Bindings/clock/google,gs101-clock.yaml b/dts/Bindings/clock/google,gs101-clock.yaml index ca7fdada3f..1d2bcea41c 100644 --- a/dts/Bindings/clock/google,gs101-clock.yaml +++ b/dts/Bindings/clock/google,gs101-clock.yaml @@ -30,14 +30,16 @@ properties: - google,gs101-cmu-top - google,gs101-cmu-apm - google,gs101-cmu-misc + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 clocks: minItems: 1 - maxItems: 2 + maxItems: 3 clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 "#clock-cells": const: 1 @@ -88,6 +90,28 @@ allOf: - const: bus - const: sss + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip + additionalProperties: false examples: diff --git a/dts/Bindings/clock/keystone-gate.txt b/dts/Bindings/clock/keystone-gate.txt index c5aa187026..43f6fb6c93 100644 --- a/dts/Bindings/clock/keystone-gate.txt +++ b/dts/Bindings/clock/keystone-gate.txt @@ -1,5 +1,3 @@ -Status: Unstable - ABI compatibility may be broken in the future - Binding for Keystone gate control driver which uses PSC controller IP. This binding uses the common clock binding[1]. diff --git a/dts/Bindings/clock/keystone-pll.txt b/dts/Bindings/clock/keystone-pll.txt index 9a3fbc6656..69b0eb7c03 100644 --- a/dts/Bindings/clock/keystone-pll.txt +++ b/dts/Bindings/clock/keystone-pll.txt @@ -1,5 +1,3 @@ -Status: Unstable - ABI compatibility may be broken in the future - Binding for keystone PLLs. The main PLL IP typically has a multiplier, a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where as the Main diff --git a/dts/Bindings/clock/mediatek,mt2701-hifsys.yaml b/dts/Bindings/clock/mediatek,mt2701-hifsys.yaml new file mode 100644 index 0000000000..9e7c725093 --- /dev/null +++ b/dts/Bindings/clock/mediatek,mt2701-hifsys.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt2701-hifsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek HIFSYS clock and reset controller + +description: + The MediaTek HIFSYS controller provides various clocks and reset outputs to + the system. + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-hifsys + - mediatek,mt7622-hifsys + - items: + - enum: + - mediatek,mt7623-hifsys + - const: mediatek,mt2701-hifsys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a000000 { + compatible = "mediatek,mt2701-hifsys"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/dts/Bindings/clock/mediatek,mt7622-pciesys.yaml b/dts/Bindings/clock/mediatek,mt7622-pciesys.yaml new file mode 100644 index 0000000000..c77111d10f --- /dev/null +++ b/dts/Bindings/clock/mediatek,mt7622-pciesys.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIESYS clock and reset controller + +description: + The MediaTek PCIESYS controller provides various clocks to the system. + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +properties: + compatible: + enum: + - mediatek,mt7622-pciesys + - mediatek,mt7629-pciesys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a100800 { + compatible = "mediatek,mt7622-pciesys"; + reg = <0x1a100800 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/dts/Bindings/clock/mediatek,mt7622-ssusbsys.yaml b/dts/Bindings/clock/mediatek,mt7622-ssusbsys.yaml new file mode 100644 index 0000000000..da93eccdcf --- /dev/null +++ b/dts/Bindings/clock/mediatek,mt7622-ssusbsys.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7622-ssusbsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SSUSBSYS clock and reset controller + +description: + The MediaTek SSUSBSYS controller provides various clocks to the system. + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +properties: + compatible: + enum: + - mediatek,mt7622-ssusbsys + - mediatek,mt7629-ssusbsys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a000000 { + compatible = "mediatek,mt7622-ssusbsys"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/dts/Bindings/clock/mobileye,eyeq5-clk.yaml b/dts/Bindings/clock/mobileye,eyeq5-clk.yaml new file mode 100644 index 0000000000..2d4f2cde1e --- /dev/null +++ b/dts/Bindings/clock/mobileye,eyeq5-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 clock controller + +description: + The EyeQ5 clock controller handles 10 read-only PLLs derived from the main + crystal clock. It also exposes one divider clock, a child of one of the PLLs. + Its registers live in a shared region called OLB. + +maintainers: + - Grégory Clement <gregory.clement@bootlin.com> + - Théo Lebrun <theo.lebrun@bootlin.com> + - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> + +properties: + compatible: + const: mobileye,eyeq5-clk + + reg: + maxItems: 2 + + reg-names: + items: + - const: plls + - const: ospi + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + description: + Input parent clock to all PLLs. Expected to be the main crystal. + + clock-names: + items: + - const: ref + +required: + - compatible + - reg + - reg-names + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false diff --git a/dts/Bindings/clock/qcom,gcc-sc8180x.yaml b/dts/Bindings/clock/qcom,gcc-sc8180x.yaml index 6c4846b34e..a1085ef4fd 100644 --- a/dts/Bindings/clock/qcom,gcc-sc8180x.yaml +++ b/dts/Bindings/clock/qcom,gcc-sc8180x.yaml @@ -31,10 +31,15 @@ properties: - const: bi_tcxo_ao - const: sleep_clk + power-domains: + items: + - description: CX domain + required: - compatible - clocks - clock-names + - power-domains allOf: - $ref: qcom,gcc.yaml# @@ -44,6 +49,7 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> clock-controller@100000 { compatible = "qcom,gcc-sc8180x"; reg = <0x00100000 0x1f0000>; @@ -51,6 +57,7 @@ examples: <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + power-domains = <&rpmhpd SC8180X_CX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/dts/Bindings/clock/qcom,gpucc.yaml b/dts/Bindings/clock/qcom,gpucc.yaml index f369fa34e0..f57aceddac 100644 --- a/dts/Bindings/clock/qcom,gpucc.yaml +++ b/dts/Bindings/clock/qcom,gpucc.yaml @@ -53,6 +53,9 @@ properties: power-domains: maxItems: 1 + vdd-gfx-supply: + description: Regulator supply for the VDD_GFX pads + '#clock-cells': const: 1 @@ -74,6 +77,12 @@ required: - '#reset-cells' - '#power-domain-cells' +# Require that power-domains and vdd-gfx-supply are not both present +not: + required: + - power-domains + - vdd-gfx-supply + additionalProperties: false examples: diff --git a/dts/Bindings/clock/qcom,q6sstopcc.yaml b/dts/Bindings/clock/qcom,q6sstopcc.yaml index 03fa30fe92..e0f4d69272 100644 --- a/dts/Bindings/clock/qcom,q6sstopcc.yaml +++ b/dts/Bindings/clock/qcom,q6sstopcc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Q6SSTOP clock Controller maintainers: - - Govind Singh <govinds@codeaurora.org> + - Bjorn Andersson <andersson@kernel.org> properties: compatible: diff --git a/dts/Bindings/clock/qcom,sc7180-mss.yaml b/dts/Bindings/clock/qcom,sc7180-mss.yaml deleted file mode 100644 index 873a2f918b..0000000000 --- a/dts/Bindings/clock/qcom,sc7180-mss.yaml +++ /dev/null @@ -1,61 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Modem Clock Controller on SC7180 - -maintainers: - - Taniya Das <quic_tdas@quicinc.com> - -description: | - Qualcomm modem clock control module provides the clocks on SC7180. - - See also:: include/dt-bindings/clock/qcom,mss-sc7180.h - -properties: - compatible: - const: qcom,sc7180-mss - - clocks: - items: - - description: gcc_mss_mfab_axi clock from GCC - - description: gcc_mss_nav_axi clock from GCC - - description: gcc_mss_cfg_ahb clock from GCC - - clock-names: - items: - - const: gcc_mss_mfab_axis - - const: gcc_mss_nav_axi - - const: cfg_ahb - - '#clock-cells': - const: 1 - - reg: - maxItems: 1 - -required: - - compatible - - reg - - clocks - - '#clock-cells' - -additionalProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,gcc-sc7180.h> - clock-controller@41a8000 { - compatible = "qcom,sc7180-mss"; - reg = <0x041a8000 0x8000>; - clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>, - <&gcc GCC_MSS_NAV_AXI_CLK>, - <&gcc GCC_MSS_CFG_AHB_CLK>; - clock-names = "gcc_mss_mfab_axis", - "gcc_mss_nav_axi", - "cfg_ahb"; - #clock-cells = <1>; - }; -... diff --git a/dts/Bindings/clock/qcom,sm8450-camcc.yaml b/dts/Bindings/clock/qcom,sm8450-camcc.yaml index 48986460f9..fa0e5b6b02 100644 --- a/dts/Bindings/clock/qcom,sm8450-camcc.yaml +++ b/dts/Bindings/clock/qcom,sm8450-camcc.yaml @@ -17,6 +17,7 @@ description: | include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sc8280xp-camcc.h + include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: - $ref: qcom,gcc.yaml# @@ -27,6 +28,7 @@ properties: - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc + - qcom,x1e80100-camcc clocks: items: diff --git a/dts/Bindings/clock/qcom,sm8450-gpucc.yaml b/dts/Bindings/clock/qcom,sm8450-gpucc.yaml index 1a384e8532..36974309cf 100644 --- a/dts/Bindings/clock/qcom,sm8450-gpucc.yaml +++ b/dts/Bindings/clock/qcom,sm8450-gpucc.yaml @@ -18,6 +18,7 @@ description: | include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h include/dt-bindings/reset/qcom,sm8650-gpucc.h + include/dt-bindings/reset/qcom,x1e80100-gpucc.h properties: compatible: @@ -25,6 +26,7 @@ properties: - qcom,sm8450-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc + - qcom,x1e80100-gpucc clocks: items: diff --git a/dts/Bindings/clock/qcom,sm8550-dispcc.yaml b/dts/Bindings/clock/qcom,sm8550-dispcc.yaml index c129f8c16b..bad0260764 100644 --- a/dts/Bindings/clock/qcom,sm8550-dispcc.yaml +++ b/dts/Bindings/clock/qcom,sm8550-dispcc.yaml @@ -14,12 +14,17 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SM8550. - See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h + See also: + - include/dt-bindings/clock/qcom,sm8550-dispcc.h + - include/dt-bindings/clock/qcom,sm8650-dispcc.h + - include/dt-bindings/clock/qcom,x1e80100-dispcc.h properties: compatible: enum: - qcom,sm8550-dispcc + - qcom,sm8650-dispcc + - qcom,x1e80100-dispcc clocks: items: diff --git a/dts/Bindings/clock/qcom,sm8550-tcsr.yaml b/dts/Bindings/clock/qcom,sm8550-tcsr.yaml index af16b05eac..48fdd562d7 100644 --- a/dts/Bindings/clock/qcom,sm8550-tcsr.yaml +++ b/dts/Bindings/clock/qcom,sm8550-tcsr.yaml @@ -23,6 +23,7 @@ properties: - enum: - qcom,sm8550-tcsr - qcom,sm8650-tcsr + - qcom,x1e80100-tcsr - const: syscon clocks: diff --git a/dts/Bindings/clock/qcom,sm8650-dispcc.yaml b/dts/Bindings/clock/qcom,sm8650-dispcc.yaml deleted file mode 100644 index 5e0c45c380..0000000000 --- a/dts/Bindings/clock/qcom,sm8650-dispcc.yaml +++ /dev/null @@ -1,106 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Display Clock & Reset Controller for SM8650 - -maintainers: - - Bjorn Andersson <andersson@kernel.org> - - Neil Armstrong <neil.armstrong@linaro.org> - -description: | - Qualcomm display clock control module provides the clocks, resets and power - domains on SM8650. - - See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h - -properties: - compatible: - enum: - - qcom,sm8650-dispcc - - clocks: - items: - - description: Board XO source - - description: Board Always On XO source - - description: Display's AHB clock - - description: sleep clock - - description: Byte clock from DSI PHY0 - - description: Pixel clock from DSI PHY0 - - description: Byte clock from DSI PHY1 - - description: Pixel clock from DSI PHY1 - - description: Link clock from DP PHY0 - - description: VCO DIV clock from DP PHY0 - - description: Link clock from DP PHY1 - - description: VCO DIV clock from DP PHY1 - - description: Link clock from DP PHY2 - - description: VCO DIV clock from DP PHY2 - - description: Link clock from DP PHY3 - - description: VCO DIV clock from DP PHY3 - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - power-domains: - description: - A phandle and PM domain specifier for the MMCX power domain. - maxItems: 1 - - required-opps: - description: - A phandle to an OPP node describing required MMCX performance point. - maxItems: 1 - -required: - - compatible - - reg - - clocks - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - -additionalProperties: false - -examples: - - | - #include <dt-bindings/clock/qcom,sm8650-gcc.h> - #include <dt-bindings/clock/qcom,rpmh.h> - #include <dt-bindings/power/qcom-rpmpd.h> - #include <dt-bindings/power/qcom,rpmhpd.h> - clock-controller@af00000 { - compatible = "qcom,sm8650-dispcc"; - reg = <0x0af00000 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&gcc GCC_DISP_AHB_CLK>, - <&sleep_clk>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi1_phy 0>, - <&dsi1_phy 1>, - <&dp0_phy 0>, - <&dp0_phy 1>, - <&dp1_phy 0>, - <&dp1_phy 1>, - <&dp2_phy 0>, - <&dp2_phy 1>, - <&dp3_phy 0>, - <&dp3_phy 1>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - }; -... diff --git a/dts/Bindings/clock/renesas,cpg-mssr.yaml b/dts/Bindings/clock/renesas,cpg-mssr.yaml index 9c3dc6c4fa..084259d302 100644 --- a/dts/Bindings/clock/renesas,cpg-mssr.yaml +++ b/dts/Bindings/clock/renesas,cpg-mssr.yaml @@ -50,6 +50,7 @@ properties: - renesas,r8a779a0-cpg-mssr # R-Car V3U - renesas,r8a779f0-cpg-mssr # R-Car S4-8 - renesas,r8a779g0-cpg-mssr # R-Car V4H + - renesas,r8a779h0-cpg-mssr # R-Car V4M reg: maxItems: 1 diff --git a/dts/Bindings/clock/samsung,exynos850-clock.yaml b/dts/Bindings/clock/samsung,exynos850-clock.yaml index c752c8985a..cdc5ded59f 100644 --- a/dts/Bindings/clock/samsung,exynos850-clock.yaml +++ b/dts/Bindings/clock/samsung,exynos850-clock.yaml @@ -36,6 +36,8 @@ properties: - samsung,exynos850-cmu-aud - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-cpucl0 + - samsung,exynos850-cmu-cpucl1 - samsung,exynos850-cmu-dpu - samsung,exynos850-cmu-g3d - samsung,exynos850-cmu-hsi @@ -156,6 +158,46 @@ allOf: properties: compatible: contains: + const: samsung,exynos850-cmu-cpucl0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CPUCL0 switch clock (from CMU_TOP) + - description: CPUCL0 debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cpucl0_switch + - const: dout_cpucl0_dbg + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CPUCL1 switch clock (from CMU_TOP) + - description: CPUCL1 debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cpucl1_switch + - const: dout_cpucl1_dbg + + - if: + properties: + compatible: + contains: const: samsung,exynos850-cmu-dpu then: diff --git a/dts/Bindings/clock/tesla,fsd-clock.yaml b/dts/Bindings/clock/tesla,fsd-clock.yaml index dc808e2f83..b370a10a23 100644 --- a/dts/Bindings/clock/tesla,fsd-clock.yaml +++ b/dts/Bindings/clock/tesla,fsd-clock.yaml @@ -12,7 +12,7 @@ maintainers: description: | FSD clock controller consist of several clock management unit - (CMU), which generates clocks for various inteernal SoC blocks. + (CMU), which generates clocks for various internal SoC blocks. The root clock comes from external OSC clock (24 MHz). All available clocks are defined as preprocessor macros in diff --git a/dts/Bindings/clock/ti/adpll.txt b/dts/Bindings/clock/ti/adpll.txt index 4c8a2ce2cd..3122360adc 100644 --- a/dts/Bindings/clock/ti/adpll.txt +++ b/dts/Bindings/clock/ti/adpll.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments ADPLL clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped ADPLL with two to three selectable input clocks and three to four children. diff --git a/dts/Bindings/clock/ti/apll.txt b/dts/Bindings/clock/ti/apll.txt index ade4dd4c30..bbd505c119 100644 --- a/dts/Bindings/clock/ti/apll.txt +++ b/dts/Bindings/clock/ti/apll.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments APLL clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped APLL with usually two selectable input clocks (reference clock and bypass clock), with analog phase locked diff --git a/dts/Bindings/clock/ti/autoidle.txt b/dts/Bindings/clock/ti/autoidle.txt index 7c735dde9f..05645a10a9 100644 --- a/dts/Bindings/clock/ti/autoidle.txt +++ b/dts/Bindings/clock/ti/autoidle.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments autoidle clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register mapped clock which can be put to idle automatically by hardware based on the usage and a configuration bit setting. Autoidle clock is never an individual diff --git a/dts/Bindings/clock/ti/clockdomain.txt b/dts/Bindings/clock/ti/clockdomain.txt index 9c6199249c..edf0b5d427 100644 --- a/dts/Bindings/clock/ti/clockdomain.txt +++ b/dts/Bindings/clock/ti/clockdomain.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments clockdomain. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1] in consumer role. Every clock on TI SoC belongs to one clockdomain, but software only needs this information for specific clocks which require diff --git a/dts/Bindings/clock/ti/composite.txt b/dts/Bindings/clock/ti/composite.txt index 33ac7c9ad0..6f7e1331b5 100644 --- a/dts/Bindings/clock/ti/composite.txt +++ b/dts/Bindings/clock/ti/composite.txt @@ -1,7 +1,5 @@ Binding for TI composite clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped composite clock with multiple different sub-types; diff --git a/dts/Bindings/clock/ti/divider.txt b/dts/Bindings/clock/ti/divider.txt index 9b13b32974..4d7c76f0b3 100644 --- a/dts/Bindings/clock/ti/divider.txt +++ b/dts/Bindings/clock/ti/divider.txt @@ -1,7 +1,5 @@ Binding for TI divider clock -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped adjustable clock rate divider that does not gate and has only one input clock or parent. By default the value programmed into diff --git a/dts/Bindings/clock/ti/dpll.txt b/dts/Bindings/clock/ti/dpll.txt index 37a7cb6ad0..14a1b72c2e 100644 --- a/dts/Bindings/clock/ti/dpll.txt +++ b/dts/Bindings/clock/ti/dpll.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments DPLL clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped DPLL with usually two selectable input clocks (reference clock and bypass clock), with digital phase locked diff --git a/dts/Bindings/clock/ti/fapll.txt b/dts/Bindings/clock/ti/fapll.txt index c19b3f253b..88986ef39d 100644 --- a/dts/Bindings/clock/ti/fapll.txt +++ b/dts/Bindings/clock/ti/fapll.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments FAPLL clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped FAPLL with usually two selectable input clocks (reference clock and bypass clock), and one or more child diff --git a/dts/Bindings/clock/ti/fixed-factor-clock.txt b/dts/Bindings/clock/ti/fixed-factor-clock.txt index 518e3c1422..dc69477b6e 100644 --- a/dts/Bindings/clock/ti/fixed-factor-clock.txt +++ b/dts/Bindings/clock/ti/fixed-factor-clock.txt @@ -1,7 +1,5 @@ Binding for TI fixed factor rate clock sources. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1], and also uses the autoidle support from TI autoidle clock [2]. diff --git a/dts/Bindings/clock/ti/gate.txt b/dts/Bindings/clock/ti/gate.txt index 4982615c01..a8e0335b00 100644 --- a/dts/Bindings/clock/ti/gate.txt +++ b/dts/Bindings/clock/ti/gate.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments gate clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. This clock is quite much similar to the basic gate-clock [2], however, it supports a number of additional features. If no register diff --git a/dts/Bindings/clock/ti/interface.txt b/dts/Bindings/clock/ti/interface.txt index d3eb5ca92a..85fb1f2d2d 100644 --- a/dts/Bindings/clock/ti/interface.txt +++ b/dts/Bindings/clock/ti/interface.txt @@ -1,7 +1,5 @@ Binding for Texas Instruments interface clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. This clock is quite much similar to the basic gate-clock [2], however, it supports a number of additional features, including diff --git a/dts/Bindings/clock/ti/mux.txt b/dts/Bindings/clock/ti/mux.txt index b33f641f10..cd56d3c1c0 100644 --- a/dts/Bindings/clock/ti/mux.txt +++ b/dts/Bindings/clock/ti/mux.txt @@ -1,7 +1,5 @@ Binding for TI mux clock. -Binding status: Unstable - ABI compatibility may be broken in the future - This binding uses the common clock binding[1]. It assumes a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. This clock does not diff --git a/dts/Bindings/crypto/atmel,at91sam9g46-aes.yaml b/dts/Bindings/crypto/atmel,at91sam9g46-aes.yaml index 0b7383b310..7dc0748444 100644 --- a/dts/Bindings/crypto/atmel,at91sam9g46-aes.yaml +++ b/dts/Bindings/crypto/atmel,at91sam9g46-aes.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-aes + oneOf: + - const: atmel,at91sam9g46-aes + - items: + - const: microchip,sam9x7-aes + - const: atmel,at91sam9g46-aes reg: maxItems: 1 diff --git a/dts/Bindings/crypto/atmel,at91sam9g46-sha.yaml b/dts/Bindings/crypto/atmel,at91sam9g46-sha.yaml index ee2ffb0343..d378c53314 100644 --- a/dts/Bindings/crypto/atmel,at91sam9g46-sha.yaml +++ b/dts/Bindings/crypto/atmel,at91sam9g46-sha.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-sha + oneOf: + - const: atmel,at91sam9g46-sha + - items: + - const: microchip,sam9x7-sha + - const: atmel,at91sam9g46-sha reg: maxItems: 1 diff --git a/dts/Bindings/crypto/atmel,at91sam9g46-tdes.yaml b/dts/Bindings/crypto/atmel,at91sam9g46-tdes.yaml index 3d6ed24b1b..6a441f79ef 100644 --- a/dts/Bindings/crypto/atmel,at91sam9g46-tdes.yaml +++ b/dts/Bindings/crypto/atmel,at91sam9g46-tdes.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-tdes + oneOf: + - const: atmel,at91sam9g46-tdes + - items: + - const: microchip,sam9x7-tdes + - const: atmel,at91sam9g46-tdes reg: maxItems: 1 diff --git a/dts/Bindings/crypto/qcom,inline-crypto-engine.yaml b/dts/Bindings/crypto/qcom,inline-crypto-engine.yaml index 09e43157cc..e91bc7dc6a 100644 --- a/dts/Bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/dts/Bindings/crypto/qcom,inline-crypto-engine.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - qcom,sa8775p-inline-crypto-engine + - qcom,sc7180-inline-crypto-engine - qcom,sm8450-inline-crypto-engine - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine diff --git a/dts/Bindings/crypto/qcom-qce.yaml b/dts/Bindings/crypto/qcom-qce.yaml index a48bd38106..e285e382d4 100644 --- a/dts/Bindings/crypto/qcom-qce.yaml +++ b/dts/Bindings/crypto/qcom-qce.yaml @@ -45,6 +45,7 @@ properties: - items: - enum: - qcom,sc7280-qce + - qcom,sm6350-qce - qcom,sm8250-qce - qcom,sm8350-qce - qcom,sm8450-qce diff --git a/dts/Bindings/display/atmel/atmel,hlcdc-display-controller.yaml b/dts/Bindings/display/atmel/atmel,hlcdc-display-controller.yaml new file mode 100644 index 0000000000..29ed42485d --- /dev/null +++ b/dts/Bindings/display/atmel/atmel,hlcdc-display-controller.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-display-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's High LCD Controller (HLCDC) + +maintainers: + - Nicolas Ferre <nicolas.ferre@microchip.com> + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - Claudiu Beznea <claudiu.beznea@tuxon.dev> + +description: + The LCD Controller (LCDC) consists of logic for transferring LCD image + data from an external display buffer to a TFT LCD panel. The LCDC has one + display input buffer per layer that fetches pixels through the single bus + host interface and a look-up table to allow palletized display + configurations. + +properties: + compatible: + const: atmel,hlcdc-display-controller + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Output endpoint of the controller, connecting the LCD panel signals. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + description: + Endpoint connecting the LCD panel signals. + + properties: + bus-width: + enum: [ 12, 16, 18, 24 ] + +required: + - '#address-cells' + - '#size-cells' + - compatible + - port@0 + +additionalProperties: false diff --git a/dts/Bindings/display/atmel/hlcdc-dc.txt b/dts/Bindings/display/atmel/hlcdc-dc.txt deleted file mode 100644 index 923aea2534..0000000000 --- a/dts/Bindings/display/atmel/hlcdc-dc.txt +++ /dev/null @@ -1,75 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver - -The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device. -See ../../mfd/atmel-hlcdc.txt for more details. - -Required properties: - - compatible: value should be "atmel,hlcdc-display-controller" - - pinctrl-names: the pin control state names. Should contain "default". - - pinctrl-0: should contain the default pinctrl states. - - #address-cells: should be set to 1. - - #size-cells: should be set to 0. - -Required children nodes: - Children nodes are encoding available output ports and their connections - to external devices using the OF graph representation (see ../graph.txt). - At least one port node is required. - -Optional properties in grandchild nodes: - Any endpoint grandchild node may specify a desired video interface - according to ../../media/video-interfaces.txt, specifically - - bus-width: recognized values are <12>, <16>, <18> and <24>, and - override any output mode selection heuristic, forcing "rgb444", - "rgb565", "rgb666" and "rgb888" respectively. - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; - -Example 2: With a video interface override to force rgb565; as above -but with these changes/additions: - - &hlcdc { - hlcdc-display-controller { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; - - port@0 { - hlcdc_panel_output: endpoint@0 { - bus-width = <16>; - }; - }; - }; - }; diff --git a/dts/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml b/dts/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml new file mode 100644 index 0000000000..3791c9f4eb --- /dev/null +++ b/dts/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP DWC HDMI TX Encoder + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +description: + The i.MX8MP HDMI transmitter is a Synopsys DesignWare + HDMI 2.0a TX controller IP. + +allOf: + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - fsl,imx8mp-hdmi-tx + + reg-io-width: + const: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: iahb + - const: isfr + - const: cec + - const: pix + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel RGB input port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/imx8mp-power.h> + + hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi-tx"; + reg = <0x32fd8000 0x7eff>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "cec", "pix"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint = <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg = <1>; + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/ti,sn65dsi86.yaml b/dts/Bindings/display/bridge/ti,sn65dsi86.yaml index 6ec6d287bf..c93878b6d7 100644 --- a/dts/Bindings/display/bridge/ti,sn65dsi86.yaml +++ b/dts/Bindings/display/bridge/ti,sn65dsi86.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SN65DSI86 DSI to eDP bridge chip maintainers: - - Sandeep Panda <spanda@codeaurora.org> + - Douglas Anderson <dianders@chromium.org> description: | The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP. diff --git a/dts/Bindings/display/fsl,lcdif.yaml b/dts/Bindings/display/fsl,lcdif.yaml index 1c2be8d6f6..0681fc49aa 100644 --- a/dts/Bindings/display/fsl,lcdif.yaml +++ b/dts/Bindings/display/fsl,lcdif.yaml @@ -123,10 +123,16 @@ allOf: - if: properties: compatible: + const: fsl,imx6sx-lcdif + then: + required: + - power-domains + - if: + properties: + compatible: contains: enum: - fsl,imx6sl-lcdif - - fsl,imx6sx-lcdif - fsl,imx8mm-lcdif - fsl,imx8mn-lcdif - fsl,imx8mp-lcdif diff --git a/dts/Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml b/dts/Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml new file mode 100644 index 0000000000..56da163601 --- /dev/null +++ b/dts/Bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP HDMI Parallel Video Interface + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +description: + The HDMI parallel video interface is a timing and sync generator block in the + i.MX8MP SoC, that sits between the video source and the HDMI TX controller. + +properties: + compatible: + const: fsl,imx8mp-hdmi-pvi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input from the LCDIF controller. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output to the HDMI TX controller. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/imx8mp-power.h> + + display-bridge@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pvi"; + reg = <0x32fc4000 0x44>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg = <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pvi>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/msm/dsi-controller-main.yaml b/dts/Bindings/display/msm/dsi-controller-main.yaml index 4219936eda..1fa28e9765 100644 --- a/dts/Bindings/display/msm/dsi-controller-main.yaml +++ b/dts/Bindings/display/msm/dsi-controller-main.yaml @@ -19,6 +19,7 @@ properties: - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl + - qcom,msm8976-dsi-ctrl - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,qcm2290-dsi-ctrl @@ -248,6 +249,7 @@ allOf: contains: enum: - qcom,msm8953-dsi-ctrl + - qcom,msm8976-dsi-ctrl then: properties: clocks: diff --git a/dts/Bindings/display/msm/gmu.yaml b/dts/Bindings/display/msm/gmu.yaml index 4e1c25b429..b3837368a2 100644 --- a/dts/Bindings/display/msm/gmu.yaml +++ b/dts/Bindings/display/msm/gmu.yaml @@ -224,6 +224,7 @@ allOf: enum: - qcom,adreno-gmu-730.1 - qcom,adreno-gmu-740.1 + - qcom,adreno-gmu-750.1 then: properties: reg: diff --git a/dts/Bindings/display/msm/gpu.yaml b/dts/Bindings/display/msm/gpu.yaml index b019db9547..40b5c6bd11 100644 --- a/dts/Bindings/display/msm/gpu.yaml +++ b/dts/Bindings/display/msm/gpu.yaml @@ -23,7 +23,7 @@ properties: The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. items: - - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$' - const: qcom,adreno - description: | The driver is parsing the compat string for Imageon to @@ -127,7 +127,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$' then: properties: @@ -203,7 +203,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: diff --git a/dts/Bindings/display/msm/qcom,mdss.yaml b/dts/Bindings/display/msm/qcom,mdss.yaml index 0999ea07f4..e4576546bf 100644 --- a/dts/Bindings/display/msm/qcom,mdss.yaml +++ b/dts/Bindings/display/msm/qcom,mdss.yaml @@ -127,6 +127,7 @@ patternProperties: - qcom,dsi-phy-20nm - qcom,dsi-phy-28nm-8226 - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-hpm-fam-b - qcom,dsi-phy-28nm-lp - qcom,hdmi-phy-8084 - qcom,hdmi-phy-8660 diff --git a/dts/Bindings/display/msm/qcom,sm8150-mdss.yaml b/dts/Bindings/display/msm/qcom,sm8150-mdss.yaml index c0d6a4fdff..e6dc5494ba 100644 --- a/dts/Bindings/display/msm/qcom,sm8150-mdss.yaml +++ b/dts/Bindings/display/msm/qcom,sm8150-mdss.yaml @@ -53,6 +53,15 @@ patternProperties: compatible: const: qcom,sm8150-dpu + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,sm8150-dp + "^dsi@[0-9a-f]+$": type: object additionalProperties: true diff --git a/dts/Bindings/display/msm/qcom,sm8650-dpu.yaml b/dts/Bindings/display/msm/qcom,sm8650-dpu.yaml index a01d15a033..c4087cc5ab 100644 --- a/dts/Bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/dts/Bindings/display/msm/qcom,sm8650-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sm8650-dpu + enum: + - qcom,sm8650-dpu + - qcom,x1e80100-dpu reg: items: diff --git a/dts/Bindings/display/msm/qcom,sm8650-mdss.yaml b/dts/Bindings/display/msm/qcom,sm8650-mdss.yaml index bd11119dc9..24cece1e88 100644 --- a/dts/Bindings/display/msm/qcom,sm8650-mdss.yaml +++ b/dts/Bindings/display/msm/qcom,sm8650-mdss.yaml @@ -37,18 +37,21 @@ properties: patternProperties: "^display-controller@[0-9a-f]+$": type: object + additionalProperties: true properties: compatible: const: qcom,sm8650-dpu "^displayport-controller@[0-9a-f]+$": type: object + additionalProperties: true properties: compatible: const: qcom,sm8650-dp "^dsi@[0-9a-f]+$": type: object + additionalProperties: true properties: compatible: items: @@ -57,6 +60,7 @@ patternProperties: "^phy@[0-9a-f]+$": type: object + additionalProperties: true properties: compatible: const: qcom,sm8650-dsi-phy-4nm diff --git a/dts/Bindings/display/msm/qcom,x1e80100-mdss.yaml b/dts/Bindings/display/msm/qcom,x1e80100-mdss.yaml new file mode 100644 index 0000000000..3b01a0e473 --- /dev/null +++ b/dts/Bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -0,0 +1,251 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 Display MDSS + +maintainers: + - Abel Vesa <abel.vesa@linaro.org> + +description: + X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DP interfaces, etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,x1e80100-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,x1e80100-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,x1e80100-dp + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,x1e80100-dp-phy + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> + #include <dt-bindings/phy/phy-qcom-qmp.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,x1e80100-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>; + interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg"; + + resets = <&dispcc_core_bcr>; + + power-domains = <&dispcc_gdsc>; + + clocks = <&dispcc_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&dispcc_mdp_clk>; + clock-names = "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,x1e80100-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc_axi_clk>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_mdp_vsync_clk>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc_mdp_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + displayport-controller@ae90000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc_mdss_ahb_clk>, + <&dispcc_dptx0_aux_clk>, + <&dispcc_dptx0_link_clk>, + <&dispcc_dptx0_link_intf_clk>, + <&dispcc_dptx0_pixel0_clk>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&mdss_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/panel/boe,th101mb31ig002-28a.yaml b/dts/Bindings/display/panel/boe,th101mb31ig002-28a.yaml new file mode 100644 index 0000000000..32df26cbfe --- /dev/null +++ b/dts/Bindings/display/panel/boe,th101mb31ig002-28a.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/boe,th101mb31ig002-28a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BOE TH101MB31IG002-28A WXGA DSI Display Panel + +maintainers: + - Manuel Traut <manut@mecka.net> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + enum: + # BOE TH101MB31IG002-28A 10.1" WXGA TFT LCD panel + - boe,th101mb31ig002-28a + + reg: true + backlight: true + enable-gpios: true + power-supply: true + port: true + rotation: true + +required: + - compatible + - reg + - enable-gpios + - power-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "boe,th101mb31ig002-28a"; + reg = <0>; + backlight = <&backlight_lcd0>; + enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; + rotation = <90>; + power-supply = <&vcc_3v3>; + port { + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_con>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/himax,hx83112a.yaml b/dts/Bindings/display/panel/himax,hx83112a.yaml new file mode 100644 index 0000000000..174661d138 --- /dev/null +++ b/dts/Bindings/display/panel/himax,hx83112a.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/himax,hx83112a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Himax HX83112A-based DSI display panels + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: + The Himax HX83112A is a generic DSI Panel IC used to control + LCD panels. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + contains: + const: djn,9a-3r063-1102b + + vdd1-supply: + description: Digital voltage rail + + vsn-supply: + description: Positive source voltage rail + + vsp-supply: + description: Negative source voltage rail + + reg: true + port: true + +required: + - compatible + - reg + - reset-gpios + - vdd1-supply + - vsn-supply + - vsp-supply + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "djn,9a-3r063-1102b"; + reg = <0>; + + backlight = <&pm6150l_wled>; + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + vdd1-supply = <&vreg_l1e>; + vsn-supply = <&pm6150l_lcdb_ncp>; + vsp-supply = <&pm6150l_lcdb_ldo>; + + port { + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + +... diff --git a/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml b/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml index c5944b4d63..d589f16772 100644 --- a/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml +++ b/dts/Bindings/display/panel/leadtek,ltk500hd1829.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: leadtek,ltk500hd1829 + enum: + - leadtek,ltk101b4029w + - leadtek,ltk500hd1829 reg: true backlight: true reset-gpios: true diff --git a/dts/Bindings/display/panel/novatek,nt35510.yaml b/dts/Bindings/display/panel/novatek,nt35510.yaml index bc92928c80..91921f4b0e 100644 --- a/dts/Bindings/display/panel/novatek,nt35510.yaml +++ b/dts/Bindings/display/panel/novatek,nt35510.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: items: - - const: hydis,hva40wv1 + - enum: + - frida,frd400b25025 + - hydis,hva40wv1 - const: novatek,nt35510 description: This indicates the panel manufacturer of the panel that is in turn using the NT35510 panel driver. The compatible @@ -29,6 +31,7 @@ properties: vddi-supply: description: regulator that supplies the vddi voltage backlight: true + port: true required: - compatible diff --git a/dts/Bindings/display/panel/novatek,nt36672e.yaml b/dts/Bindings/display/panel/novatek,nt36672e.yaml new file mode 100644 index 0000000000..dc4672f3d0 --- /dev/null +++ b/dts/Bindings/display/panel/novatek,nt36672e.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt36672e.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT36672E LCD DSI Panel + +maintainers: + - Ritesh Kumar <quic_riteshk@quicinc.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: novatek,nt36672e + + reg: + maxItems: 1 + description: DSI virtual channel + + vddi-supply: true + avdd-supply: true + avee-supply: true + port: true + reset-gpios: true + backlight: true + +required: + - compatible + - reg + - vddi-supply + - avdd-supply + - avee-supply + - reset-gpios + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "novatek,nt36672e"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>; + + vddi-supply = <&vreg_l8c_1p8>; + avdd-supply = <&disp_avdd>; + avee-supply = <&disp_avee>; + + backlight = <&pwm_backlight>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/display/panel/panel-lvds.yaml b/dts/Bindings/display/panel/panel-lvds.yaml index 9f1016551e..155d8ffa8f 100644 --- a/dts/Bindings/display/panel/panel-lvds.yaml +++ b/dts/Bindings/display/panel/panel-lvds.yaml @@ -39,9 +39,13 @@ properties: compatible: items: - enum: + # Admatec 9904379 10.1" 1024x600 LVDS panel + - admatec,9904379 - auo,b101ew05 # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel - chunghwa,claa070wp03xg + # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel + - edt,etml0700z9ndha # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel - hannstar,hsd101pww2 # Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml index 634a10c6f2..a95445f408 100644 --- a/dts/Bindings/display/panel/panel-simple.yaml +++ b/dts/Bindings/display/panel/panel-simple.yaml @@ -73,6 +73,8 @@ properties: - auo,t215hvn01 # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel - avic,tm070ddh03 + # BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel + - boe,bp082wx1-100 # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel - boe,bp101wx1-100 # BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel @@ -141,6 +143,8 @@ properties: - edt,etm0700g0edh6 # Emerging Display Technology Corp. LVDS WSVGA TFT Display with capacitive touch - edt,etml0700y5dha + # Emerging Display Technology Corp. 10.1" LVDS WXGA TFT Display with capacitive touch + - edt,etml1010g3dra # Emerging Display Technology Corp. 5.7" VGA TFT LCD panel with # capacitive touch - edt,etmv570g2dhu diff --git a/dts/Bindings/display/panel/rocktech,jh057n00900.yaml b/dts/Bindings/display/panel/rocktech,jh057n00900.yaml index 97cccd8a84..6ec471284f 100644 --- a/dts/Bindings/display/panel/rocktech,jh057n00900.yaml +++ b/dts/Bindings/display/panel/rocktech,jh057n00900.yaml @@ -22,6 +22,8 @@ properties: enum: # Anberic RG353V-V2 5.0" 640x480 TFT LCD panel - anbernic,rg353v-panel-v2 + # Powkiddy RGB10MAX3 5.0" 720x1280 TFT LCD panel + - powkiddy,rgb10max3-panel # Powkiddy RGB30 3.0" 720x720 TFT LCD panel - powkiddy,rgb30-panel # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel @@ -43,6 +45,7 @@ properties: reset-gpios: true backlight: true + rotation: true required: - compatible diff --git a/dts/Bindings/display/panel/visionox,r66451.yaml b/dts/Bindings/display/panel/visionox,r66451.yaml index 6ba3236839..187840bb76 100644 --- a/dts/Bindings/display/panel/visionox,r66451.yaml +++ b/dts/Bindings/display/panel/visionox,r66451.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/panel/visionox,r66451.yaml# diff --git a/dts/Bindings/display/panel/visionox,rm69299.yaml b/dts/Bindings/display/panel/visionox,rm69299.yaml index fa745a6f44..7723990675 100644 --- a/dts/Bindings/display/panel/visionox,rm69299.yaml +++ b/dts/Bindings/display/panel/visionox,rm69299.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Visionox model RM69299 Panels maintainers: - - Harigovindan P <harigovi@codeaurora.org> + - Abhinav Kumar <quic_abhinavk@quicinc.com> + - Jessica Zhang <quic_jesszhan@quicinc.com> description: | This binding is for display panels using a Visionox RM692999 panel. diff --git a/dts/Bindings/display/renesas,rzg2l-du.yaml b/dts/Bindings/display/renesas,rzg2l-du.yaml new file mode 100644 index 0000000000..08e5b94780 --- /dev/null +++ b/dts/Bindings/display/renesas,rzg2l-du.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Display Unit (DU) + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + +description: | + These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L + and RZ/V2L SoCs. + +properties: + compatible: + oneOf: + - enum: + - renesas,r9a07g044-du # RZ/G2{L,LC} + - items: + - enum: + - renesas,r9a07g054-du # RZ/V2L + - const: renesas,r9a07g044-du # RZ/G2L fallback + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Main clock + - description: Register access clock + - description: Video clock + + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + The connections to the DU output video ports are modeled using the OF + graph bindings. The number of ports and their assignment are + model-dependent. Each port shall have a single endpoint. + + patternProperties: + "^port@[0-1]$": + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + + required: + - port@0 + + unevaluatedProperties: false + + renesas,vsps: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to VSP instance that serves the DU channel + - description: Channel index identifying the LIF instance in that VSP + description: + A list of phandle and channel index tuples to the VSPs that handle the + memory interfaces for the DU channels. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - power-domains + - ports + - renesas,vsps + +additionalProperties: false + +examples: + # RZ/G2L DU + - | + #include <dt-bindings/clock/r9a07g044-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + display@10890000 { + compatible = "renesas,r9a07g044-du"; + reg = <0x10890000 0x10000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + power-domains = <&cpg>; + + renesas,vsps = <&vspd0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + port@1 { + reg = <1>; + }; + }; + }; + +... diff --git a/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml b/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml index 7e59dee15a..af638b6c0d 100644 --- a/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml +++ b/dts/Bindings/display/rockchip/rockchip,dw-hdmi.yaml @@ -94,11 +94,14 @@ properties: - const: default - const: unwedge + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports - patternProperties: - "^port(@0)?$": + properties: + port@0: $ref: /schemas/graph.yaml#/properties/port description: Input of the DWC HDMI TX properties: @@ -108,11 +111,14 @@ properties: description: Connection to the VOPB endpoint@1: description: Connection to the VOPL - properties: port@1: $ref: /schemas/graph.yaml#/properties/port description: Output of the DWC HDMI TX + required: + - port@0 + - port@1 + rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -135,19 +141,25 @@ examples: #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/rk3288-power.h> hdmi: hdmi@ff980000 { compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; reg-io-width = <4>; - ddc-i2c-bus = <&i2c5>; - rockchip,grf = <&grf>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; clock-names = "iahb", "isfr"; + ddc-i2c-bus = <&i2c5>; + power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -155,11 +167,20 @@ examples: reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; + hdmi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_hdmi>; }; }; + + port@1 { + reg = <1>; + + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; }; }; diff --git a/dts/Bindings/display/solomon,ssd1307fb.yaml b/dts/Bindings/display/solomon,ssd1307fb.yaml index 3afbb52d1b..153ff86fb4 100644 --- a/dts/Bindings/display/solomon,ssd1307fb.yaml +++ b/dts/Bindings/display/solomon,ssd1307fb.yaml @@ -131,9 +131,9 @@ allOf: const: sinowealth,sh1106 then: properties: - width: + solomon,width: default: 132 - height: + solomon,height: default: 64 solomon,dclk-div: default: 1 @@ -149,9 +149,9 @@ allOf: - solomon,ssd1305 then: properties: - width: + solomon,width: default: 132 - height: + solomon,height: default: 64 solomon,dclk-div: default: 1 @@ -167,9 +167,9 @@ allOf: - solomon,ssd1306 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 64 solomon,dclk-div: default: 1 @@ -185,9 +185,9 @@ allOf: - solomon,ssd1307 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 39 solomon,dclk-div: default: 2 @@ -205,9 +205,9 @@ allOf: - solomon,ssd1309 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 64 solomon,dclk-div: default: 1 diff --git a/dts/Bindings/display/solomon,ssd132x.yaml b/dts/Bindings/display/solomon,ssd132x.yaml index 37975ee61c..dd7939989c 100644 --- a/dts/Bindings/display/solomon,ssd132x.yaml +++ b/dts/Bindings/display/solomon,ssd132x.yaml @@ -30,9 +30,9 @@ allOf: const: solomon,ssd1322 then: properties: - width: + solomon,width: default: 480 - height: + solomon,height: default: 128 - if: @@ -42,9 +42,9 @@ allOf: const: solomon,ssd1325 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 80 - if: @@ -54,9 +54,9 @@ allOf: const: solomon,ssd1327 then: properties: - width: + solomon,width: default: 128 - height: + solomon,height: default: 128 unevaluatedProperties: false diff --git a/dts/Bindings/display/solomon,ssd133x.yaml b/dts/Bindings/display/solomon,ssd133x.yaml new file mode 100644 index 0000000000..b7780038a3 --- /dev/null +++ b/dts/Bindings/display/solomon,ssd133x.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/solomon,ssd133x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Solomon SSD133x OLED Display Controllers + +maintainers: + - Javier Martinez Canillas <javierm@redhat.com> + +allOf: + - $ref: solomon,ssd-common.yaml# + +properties: + compatible: + enum: + - solomon,ssd1331 + + solomon,width: + default: 96 + + solomon,height: + default: 64 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + oled@0 { + compatible = "solomon,ssd1331"; + reg = <0x0>; + reset-gpios = <&gpio2 7>; + dc-gpios = <&gpio2 8>; + spi-max-frequency = <10000000>; + }; + }; diff --git a/dts/Bindings/display/ti/ti,am65x-dss.yaml b/dts/Bindings/display/ti/ti,am65x-dss.yaml index b6767ef0d2..55e3e490d0 100644 --- a/dts/Bindings/display/ti/ti,am65x-dss.yaml +++ b/dts/Bindings/display/ti/ti,am65x-dss.yaml @@ -37,6 +37,7 @@ properties: - description: OVR2 overlay manager for vp2 - description: VP1 video port 1 - description: VP2 video port 2 + - description: common1 DSS register area reg-names: items: @@ -47,6 +48,7 @@ properties: - const: ovr2 - const: vp1 - const: vp2 + - const: common1 clocks: items: @@ -147,9 +149,10 @@ examples: <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ - <0x04a0b000 0x1000>; /* vp2 */ + <0x04a0b000 0x1000>, /* vp2 */ + <0x04a01000 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 67 1>, diff --git a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml index ec2d7a789f..0f2501f72c 100644 --- a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -28,6 +28,9 @@ properties: - items: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma + - items: + - const: allwinner,sun50i-h616-dma + - const: allwinner,sun50i-a100-dma reg: maxItems: 1 @@ -59,10 +62,11 @@ required: if: properties: compatible: - enum: - - allwinner,sun20i-d1-dma - - allwinner,sun50i-a100-dma - - allwinner,sun50i-h6-dma + contains: + enum: + - allwinner,sun20i-d1-dma + - allwinner,sun50i-a100-dma + - allwinner,sun50i-h6-dma then: properties: diff --git a/dts/Bindings/dma/fsl,edma.yaml b/dts/Bindings/dma/fsl,edma.yaml index 437db0c623..aa51d278cb 100644 --- a/dts/Bindings/dma/fsl,edma.yaml +++ b/dts/Bindings/dma/fsl,edma.yaml @@ -25,6 +25,7 @@ properties: - fsl,imx8qm-edma - fsl,imx93-edma3 - fsl,imx93-edma4 + - fsl,imx95-edma5 - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma @@ -83,6 +84,7 @@ allOf: - fsl,imx8qm-edma - fsl,imx93-edma3 - fsl,imx93-edma4 + - fsl,imx95-edma5 then: properties: "#dma-cells": diff --git a/dts/Bindings/dma/fsl,imx-sdma.yaml b/dts/Bindings/dma/fsl,imx-sdma.yaml index b95dd8db5a..37135fa024 100644 --- a/dts/Bindings/dma/fsl,imx-sdma.yaml +++ b/dts/Bindings/dma/fsl,imx-sdma.yaml @@ -92,7 +92,8 @@ properties: description: needs firmware more than ver 2 - Shared ASRC: 23 - SAI: 24 - - HDMI Audio: 25 + - Multi SAI: 25 + - HDMI Audio: 26 The third cell: transfer priority ID enum: diff --git a/dts/Bindings/dma/marvell,mmp-dma.yaml b/dts/Bindings/dma/marvell,mmp-dma.yaml new file mode 100644 index 0000000000..d447d5207b --- /dev/null +++ b/dts/Bindings/dma/marvell,mmp-dma.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP DMA controller + +maintainers: + - Duje Mihanović <duje.mihanovic@skole.hr> + +description: + Marvell MMP SoCs may have two types of DMA controllers, peripheral and audio. + +properties: + compatible: + enum: + - marvell,pdma-1.0 + - marvell,adma-1.0 + - marvell,pxa910-squ + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt lines for the controller, may be shared or one per DMA channel + minItems: 1 + + asram: + description: + A phandle to the SRAM pool + $ref: /schemas/types.yaml#/definitions/phandle + + '#dma-channels': + deprecated: true + + '#dma-requests': + deprecated: true + +required: + - compatible + - reg + - interrupts + - '#dma-cells' + +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - marvell,pdma-1.0 + then: + properties: + asram: false + else: + required: + - asram + +unevaluatedProperties: false + +examples: + - | + dma-controller@d4000000 { + compatible = "marvell,pdma-1.0"; + reg = <0xd4000000 0x10000>; + interrupts = <47>; + #dma-cells = <2>; + dma-channels = <16>; + }; diff --git a/dts/Bindings/dma/mediatek,mt7622-hsdma.yaml b/dts/Bindings/dma/mediatek,mt7622-hsdma.yaml new file mode 100644 index 0000000000..3f1e120e40 --- /dev/null +++ b/dts/Bindings/dma/mediatek,mt7622-hsdma.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mediatek,mt7622-hsdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek High-Speed DMA Controller + +maintainers: + - Sean Wang <sean.wang@mediatek.com> + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + enum: + - mediatek,mt7622-hsdma + - mediatek,mt7623-hsdma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: hsdma + + power-domains: + maxItems: 1 + + "#dma-cells": + description: Channel number + const: 1 + +required: + - reg + - interrupts + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt2701-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/mt2701-power.h> + + dma-controller@1b007000 { + compatible = "mediatek,mt7623-hsdma"; + reg = <0x1b007000 0x1000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>; + clocks = <ðsys CLK_ETHSYS_HSDMA>; + clock-names = "hsdma"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + #dma-cells = <1>; + }; diff --git a/dts/Bindings/dma/mmp-dma.txt b/dts/Bindings/dma/mmp-dma.txt deleted file mode 100644 index ec18bf0a80..0000000000 --- a/dts/Bindings/dma/mmp-dma.txt +++ /dev/null @@ -1,81 +0,0 @@ -* MARVELL MMP DMA controller - -Marvell Peripheral DMA Controller -Used platforms: pxa688, pxa910, pxa3xx, etc - -Required properties: -- compatible: Should be "marvell,pdma-1.0" -- reg: Should contain DMA registers location and length. -- interrupts: Either contain all of the per-channel DMA interrupts - or one irq for pdma device - -Optional properties: -- dma-channels: Number of DMA channels supported by the controller (defaults - to 32 when not specified) -- #dma-channels: deprecated -- dma-requests: Number of DMA requestor lines supported by the controller - (defaults to 32 when not specified) -- #dma-requests: deprecated - -"marvell,pdma-1.0" -Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688. - -Examples: - -/* - * Each channel has specific irq - * ICU parse out irq channel from ICU register, - * while DMA controller may not able to distinguish the irq channel - * Using this method, interrupt-parent is required as demuxer - * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq, - * 18~21 is ADMA irq - */ -pdma: dma-controller@d4000000 { - compatible = "marvell,pdma-1.0"; - reg = <0xd4000000 0x10000>; - interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; - interrupt-parent = <&intcmux32>; - dma-channels = <16>; - }; - -/* - * One irq for all channels - * Dmaengine driver (DMA controller) distinguish irq channel via - * parsing internal register - */ -pdma: dma-controller@d4000000 { - compatible = "marvell,pdma-1.0"; - reg = <0xd4000000 0x10000>; - interrupts = <47>; - dma-channels = <16>; - }; - - -Marvell Two Channel DMA Controller used specifically for audio -Used platforms: pxa688, pxa910 - -Required properties: -- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ" -- reg: Should contain DMA registers location and length. -- interrupts: Either contain all of the per-channel DMA interrupts - or one irq for dma device - -"marvell,adma-1.0" used on pxa688 -"marvell,pxa910-squ" used on pxa910 - -Examples: - -/* each channel has specific irq */ -adma0: dma-controller@d42a0800 { - compatible = "marvell,adma-1.0"; - reg = <0xd42a0800 0x100>; - interrupts = <18 19>; - interrupt-parent = <&intcmux32>; - }; - -/* One irq for all channels */ -squ: dma-controller@d42a0800 { - compatible = "marvell,pxa910-squ"; - reg = <0xd42a0800 0x100>; - interrupts = <46>; - }; diff --git a/dts/Bindings/dma/mtk-hsdma.txt b/dts/Bindings/dma/mtk-hsdma.txt deleted file mode 100644 index 4bb317359d..0000000000 --- a/dts/Bindings/dma/mtk-hsdma.txt +++ /dev/null @@ -1,33 +0,0 @@ -MediaTek High-Speed DMA Controller -================================== - -This device follows the generic DMA bindings defined in dma/dma.txt. - -Required properties: - -- compatible: Must be one of - "mediatek,mt7622-hsdma": for MT7622 SoC - "mediatek,mt7623-hsdma": for MT7623 SoC -- reg: Should contain the register's base address and length. -- interrupts: Should contain a reference to the interrupt used by this - device. -- clocks: Should be the clock specifiers corresponding to the entry in - clock-names property. -- clock-names: Should contain "hsdma" entries. -- power-domains: Phandle to the power domain that the device is part of -- #dma-cells: The length of the DMA specifier, must be <1>. This one cell - in dmas property of a client device represents the channel - number. -Example: - - hsdma: dma-controller@1b007000 { - compatible = "mediatek,mt7623-hsdma"; - reg = <0 0x1b007000 0 0x1000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>; - clocks = <ðsys CLK_ETHSYS_HSDMA>; - clock-names = "hsdma"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; - #dma-cells = <1>; - }; - -DMA clients must use the format described in dma/dma.txt file. diff --git a/dts/Bindings/dma/renesas,rcar-dmac.yaml b/dts/Bindings/dma/renesas,rcar-dmac.yaml index 03aa067b12..04fc4a99a7 100644 --- a/dts/Bindings/dma/renesas,rcar-dmac.yaml +++ b/dts/Bindings/dma/renesas,rcar-dmac.yaml @@ -46,6 +46,7 @@ properties: - renesas,dmac-r8a779a0 # R-Car V3U - renesas,dmac-r8a779f0 # R-Car S4-8 - renesas,dmac-r8a779g0 # R-Car V4H + - renesas,dmac-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-dmac # R-Car Gen4 reg: true diff --git a/dts/Bindings/dts-coding-style.rst b/dts/Bindings/dts-coding-style.rst index a9bdd2b59d..8a68331075 100644 --- a/dts/Bindings/dts-coding-style.rst +++ b/dts/Bindings/dts-coding-style.rst @@ -144,6 +144,8 @@ Example:: #dma-cells = <1>; clocks = <&clock_controller 0>, <&clock_controller 1>; clock-names = "bus", "host"; + #address-cells = <1>; + #size-cells = <1>; vendor,custom-property = <2>; status = "disabled"; diff --git a/dts/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/dts/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index 8e584857dd..ab8f32c440 100644 --- a/dts/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/dts/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -26,6 +26,12 @@ properties: - description: For implementations complying for Versal. const: xlnx,versal-firmware + - description: For implementations complying for Versal NET. + items: + - enum: + - xlnx,versal-net-firmware + - const: xlnx,versal-firmware + method: description: | The method of calling the PM-API firmware layer. @@ -41,7 +47,53 @@ properties: "#power-domain-cells": const: 1 - versal_fpga: + clock-controller: + $ref: /schemas/clock/xlnx,versal-clk.yaml# + description: The clock controller is a hardware block of Xilinx versal + clock tree. It reads required input clock frequencies from the devicetree + and acts as clock provider for all clock consumers of PS clocks.list of + clock specifiers which are external input clocks to the given clock + controller. + type: object + + gpio: + $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml# + description: The gpio node describes connect to PS_MODE pins via firmware + interface. + type: object + + soc-nvmem: + $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml# + description: The ZynqMP MPSoC provides access to the hardware related data + like SOC revision, IDCODE and specific purpose efuses. + type: object + + pcap: + $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml + description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to + configure the Programmable Logic (PL). The configuration uses the + firmware interface. + type: object + + pinctrl: + $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# + description: The pinctrl node provides access to pinconfig and pincontrol + functionality available in firmware. + type: object + + power-management: + $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml# + description: The zynqmp-power node describes the power management + configurations. It will control remote suspend/shutdown interfaces. + type: object + + reset-controller: + $ref: /schemas/reset/xlnx,zynqmp-reset.yaml# + description: The reset-controller node describes connection to the reset + functionality via firmware interface. + type: object + + versal-fpga: $ref: /schemas/fpga/xlnx,versal-fpga.yaml# description: Compatible of the FPGA device. type: object @@ -53,15 +105,6 @@ properties: vector. type: object - clock-controller: - $ref: /schemas/clock/xlnx,versal-clk.yaml# - description: The clock controller is a hardware block of Xilinx versal - clock tree. It reads required input clock frequencies from the devicetree - and acts as clock provider for all clock consumers of PS clocks.list of - clock specifiers which are external input clocks to the given clock - controller. - type: object - required: - compatible @@ -73,7 +116,38 @@ examples: firmware { zynqmp_firmware: zynqmp-firmware { #power-domain-cells = <1>; + soc-nvmem { + compatible = "xlnx,zynqmp-nvmem-fw"; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc-revision@0 { + reg = <0x0 0x4>; + }; + }; + }; + gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; + pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; }; + pinctrl { + compatible = "xlnx,zynqmp-pinctrl"; + }; + power-management { + compatible = "xlnx,zynqmp-power"; + interrupts = <0 35 4>; + }; + reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; + }; }; sata { @@ -84,7 +158,7 @@ examples: compatible = "xlnx,versal-firmware"; method = "smc"; - versal_fpga: versal_fpga { + versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; diff --git a/dts/Bindings/fpga/fpga-region.txt b/dts/Bindings/fpga/fpga-region.txt deleted file mode 100644 index 528df8a0e6..0000000000 --- a/dts/Bindings/fpga/fpga-region.txt +++ /dev/null @@ -1,479 +0,0 @@ -FPGA Region Device Tree Binding - -Alan Tull 2016 - - CONTENTS - - Introduction - - Terminology - - Sequence - - FPGA Region - - Supported Use Models - - Device Tree Examples - - Constraints - - -Introduction -============ - -FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in -the Device Tree. FPGA Regions provide a way to program FPGAs under device tree -control. - -This device tree binding document hits some of the high points of FPGA usage and -attempts to include terminology used by both major FPGA manufacturers. This -document isn't a replacement for any manufacturers specifications for FPGA -usage. - - -Terminology -=========== - -Full Reconfiguration - * The entire FPGA is programmed. - -Partial Reconfiguration (PR) - * A section of an FPGA is reprogrammed while the rest of the FPGA is not - affected. - * Not all FPGA's support PR. - -Partial Reconfiguration Region (PRR) - * Also called a "reconfigurable partition" - * A PRR is a specific section of an FPGA reserved for reconfiguration. - * A base (or static) FPGA image may create a set of PRR's that later may - be independently reprogrammed many times. - * The size and specific location of each PRR is fixed. - * The connections at the edge of each PRR are fixed. The image that is loaded - into a PRR must fit and must use a subset of the region's connections. - * The busses within the FPGA are split such that each region gets its own - branch that may be gated independently. - -Persona - * Also called a "partial bit stream" - * An FPGA image that is designed to be loaded into a PRR. There may be - any number of personas designed to fit into a PRR, but only one at at time - may be loaded. - * A persona may create more regions. - -FPGA Bridge - * FPGA Bridges gate bus signals between a host and FPGA. - * FPGA Bridges should be disabled while the FPGA is being programmed to - prevent spurious signals on the cpu bus and to the soft logic. - * FPGA bridges may be actual hardware or soft logic on an FPGA. - * During Full Reconfiguration, hardware bridges between the host and FPGA - will be disabled. - * During Partial Reconfiguration of a specific region, that region's bridge - will be used to gate the busses. Traffic to other regions is not affected. - * In some implementations, the FPGA Manager transparently handles gating the - buses, eliminating the need to show the hardware FPGA bridges in the - device tree. - * An FPGA image may create a set of reprogrammable regions, each having its - own bridge and its own split of the busses in the FPGA. - -FPGA Manager - * An FPGA Manager is a hardware block that programs an FPGA under the control - of a host processor. - -Base Image - * Also called the "static image" - * An FPGA image that is designed to do full reconfiguration of the FPGA. - * A base image may set up a set of partial reconfiguration regions that may - later be reprogrammed. - - ---------------- ---------------------------------- - | Host CPU | | FPGA | - | | | | - | ----| | ----------- -------- | - | | H | | |==>| Bridge0 |<==>| PRR0 | | - | | W | | | ----------- -------- | - | | | | | | - | | B |<=====>|<==| ----------- -------- | - | | R | | |==>| Bridge1 |<==>| PRR1 | | - | | I | | | ----------- -------- | - | | D | | | | - | | G | | | ----------- -------- | - | | E | | |==>| Bridge2 |<==>| PRR2 | | - | ----| | ----------- -------- | - | | | | - ---------------- ---------------------------------- - -Figure 1: An FPGA set up with a base image that created three regions. Each -region (PRR0-2) gets its own split of the busses that is independently gated by -a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be -reprogrammed independently while the rest of the system continues to function. - - -Sequence -======== - -When a DT overlay that targets an FPGA Region is applied, the FPGA Region will -do the following: - - 1. Disable appropriate FPGA bridges. - 2. Program the FPGA using the FPGA manager. - 3. Enable the FPGA bridges. - 4. The Device Tree overlay is accepted into the live tree. - 5. Child devices are populated. - -When the overlay is removed, the child nodes will be removed and the FPGA Region -will disable the bridges. - - -FPGA Region -=========== - -FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA -Region brings together the elements needed to program on a running system and -add the child devices: - - * FPGA Manager - * FPGA Bridges - * image-specific information needed to to the programming. - * child nodes - -The intended use is that a Device Tree overlay (DTO) can be used to reprogram an -FPGA while an operating system is running. - -An FPGA Region that exists in the live Device Tree reflects the current state. -If the live tree shows a "firmware-name" property or child nodes under an FPGA -Region, the FPGA already has been programmed. A DTO that targets an FPGA Region -and adds the "firmware-name" property is taken as a request to reprogram the -FPGA. After reprogramming is successful, the overlay is accepted into the live -tree. - -The base FPGA Region in the device tree represents the FPGA and supports full -reconfiguration. It must include a phandle to an FPGA Manager. The base -FPGA region will be the child of one of the hardware bridges (the bridge that -allows register access) between the cpu and the FPGA. If there are more than -one bridge to control during FPGA programming, the region will also contain a -list of phandles to the additional hardware FPGA Bridges. - -For partial reconfiguration (PR), each PR region will have an FPGA Region. -These FPGA regions are children of FPGA bridges which are then children of the -base FPGA region. The "Full Reconfiguration to add PRR's" example below shows -this. - -If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA -Manager specified by its ancestor FPGA Region. This supports both the case -where the same FPGA Manager is used for all of an FPGA as well the case where -a different FPGA Manager is used for each region. - -FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents -shutting down bridges that are upstream from the other active regions while one -region is getting reconfigured (see Figure 1 above). During PR, the FPGA's -hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges -within the static image of the FPGA. - -Required properties: -- compatible : should contain "fpga-region" -- fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions - inherit this property from their ancestor regions. An fpga-mgr property - in a region will override any inherited FPGA manager. -- #address-cells, #size-cells, ranges : must be present to handle address space - mapping for child nodes. - -Optional properties: -- firmware-name : should contain the name of an FPGA image file located on the - firmware search path. If this property shows up in a live device tree - it indicates that the FPGA has already been programmed with this image. - If this property is in an overlay targeting an FPGA region, it is a - request to program the FPGA with that image. -- fpga-bridges : should contain a list of phandles to FPGA Bridges that must be - controlled during FPGA programming along with the parent FPGA bridge. - This property is optional if the FPGA Manager handles the bridges. - If the fpga-region is the child of an fpga-bridge, the list should not - contain the parent bridge. -- partial-fpga-config : boolean, set if partial reconfiguration is to be done, - otherwise full reconfiguration is done. -- external-fpga-config : boolean, set if the FPGA has already been configured - prior to OS boot up. -- encrypted-fpga-config : boolean, set if the bitstream is encrypted -- region-unfreeze-timeout-us : The maximum time in microseconds to wait for - bridges to successfully become enabled after the region has been - programmed. -- region-freeze-timeout-us : The maximum time in microseconds to wait for - bridges to successfully become disabled before the region has been - programmed. -- config-complete-timeout-us : The maximum time in microseconds time for the - FPGA to go to operating mode after the region has been programmed. -- child nodes : devices in the FPGA after programming. - -In the example below, when an overlay is applied targeting fpga-region0, -fpga_mgr is used to program the FPGA. Two bridges are controlled during -programming: the parent fpga_bridge0 and fpga_bridge1. Because the region is -the child of fpga_bridge0, only fpga_bridge1 needs to be specified in the -fpga-bridges property. During programming, these bridges are disabled, the -firmware specified in the overlay is loaded to the FPGA using the FPGA manager -specified in the region. If FPGA programming succeeds, the bridges are -reenabled and the overlay makes it into the live device tree. The child devices -are then populated. If FPGA programming fails, the bridges are left disabled -and the overlay is rejected. The overlay's ranges property maps the lwhps -bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by -the two child devices. - -Example: -Base tree contains: - - fpga_mgr: fpga-mgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xff706000 0x1000 - 0xffb90000 0x20>; - interrupts = <0 175 4>; - }; - - fpga_bridge0: fpga-bridge@ff400000 { - compatible = "altr,socfpga-lwhps2fpga-bridge"; - reg = <0xff400000 0x100000>; - resets = <&rst LWHPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - fpga_region0: fpga-region0 { - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - }; - - fpga_bridge1: fpga-bridge@ff500000 { - compatible = "altr,socfpga-hps2fpga-bridge"; - reg = <0xff500000 0x10000>; - resets = <&rst HPS2FPGA_RESET>; - clocks = <&l4_main_clk>; - }; - -Overlay contains: - -/dts-v1/; -/plugin/; - -&fpga_region0 { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "soc_system.rbf"; - fpga-bridges = <&fpga_bridge1>; - ranges = <0x20000 0xff200000 0x100000>, - <0x0 0xc0000000 0x20000000>; - - gpio@10040 { - compatible = "altr,pio-1.0"; - reg = <0x10040 0x20>; - altr,ngpio = <4>; - #gpio-cells = <2>; - clocks = <2>; - gpio-controller; - }; - - onchip-memory { - device_type = "memory"; - compatible = "altr,onchipmem-15.1"; - reg = <0x0 0x10000>; - }; -}; - - -Supported Use Models -==================== - -In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and -a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some -uses are specific to an FPGA device. - - * No FPGA Bridges - In this case, the FPGA Manager which programs the FPGA also handles the - bridges behind the scenes. No FPGA Bridge devices are needed for full - reconfiguration. - - * Full reconfiguration with hardware bridges - In this case, there are hardware bridges between the processor and FPGA that - need to be controlled during full reconfiguration. Before the overlay is - applied, the live DT must include the FPGA Manager, FPGA Bridges, and a - FPGA Region. The FPGA Region is the child of the bridge that allows - register access to the FPGA. Additional bridges may be listed in a - fpga-bridges property in the FPGA region or in the device tree overlay. - - * Partial reconfiguration with bridges in the FPGA - In this case, the FPGA will have one or more PRR's that may be programmed - separately while the rest of the FPGA can remain active. To manage this, - bridges need to exist in the FPGA that can gate the buses going to each FPGA - region while the buses are enabled for other sections. Before any partial - reconfiguration can be done, a base FPGA image must be loaded which includes - PRR's with FPGA bridges. The device tree should have an FPGA region for each - PRR. - -Device Tree Examples -==================== - -The intention of this section is to give some simple examples, focusing on -the placement of the elements detailed above, especially: - * FPGA Manager - * FPGA Bridges - * FPGA Region - * ranges - * target-path or target - -For the purposes of this section, I'm dividing the Device Tree into two parts, -each with its own requirements. The two parts are: - * The live DT prior to the overlay being added - * The DT overlay - -The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA -Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle -to handle programming the FPGA. If the FPGA Region is the child of another FPGA -Region, the parent's FPGA Manager is used. If FPGA Bridges need to be involved, -they are specified in the FPGA Region by the "fpga-bridges" property. During -FPGA programming, the FPGA Region will disable the bridges that are in its -"fpga-bridges" list and will re-enable them after FPGA programming has -succeeded. - -The Device Tree Overlay will contain: - * "target-path" or "target" - The insertion point where the contents of the overlay will go into the - live tree. target-path is a full path, while target is a phandle. - * "ranges" - The address space mapping from processor to FPGA bus(ses). - * "firmware-name" - Specifies the name of the FPGA image file on the firmware search - path. The search path is described in the firmware class documentation. - * "partial-fpga-config" - This binding is a boolean and should be present if partial reconfiguration - is to be done. - * child nodes corresponding to hardware that will be loaded in this region of - the FPGA. - -Device Tree Example: Full Reconfiguration without Bridges -========================================================= - -Live Device Tree contains: - fpga_mgr0: fpga-mgr@f8007000 { - compatible = "xlnx,zynq-devcfg-1.0"; - reg = <0xf8007000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 8 4>; - clocks = <&clkc 12>; - clock-names = "ref_clk"; - syscon = <&slcr>; - }; - - fpga_region0: fpga-region0 { - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr0>; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - }; - -DT Overlay contains: - -/dts-v1/; -/plugin/; - -&fpga_region0 { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "zynq-gpio.bin"; - - gpio1: gpio@40000000 { - compatible = "xlnx,xps-gpio-1.00.a"; - reg = <0x40000000 0x10000>; - gpio-controller; - #gpio-cells = <0x2>; - xlnx,gpio-width= <0x6>; - }; -}; - -Device Tree Example: Full Reconfiguration to add PRR's -====================================================== - -The base FPGA Region is specified similar to the first example above. - -This example programs the FPGA to have two regions that can later be partially -configured. Each region has its own bridge in the FPGA fabric. - -DT Overlay contains: - -/dts-v1/; -/plugin/; - -&fpga_region0 { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "base.rbf"; - - fpga-bridge@4400 { - compatible = "altr,freeze-bridge-controller"; - reg = <0x4400 0x10>; - - fpga_region1: fpga-region1 { - compatible = "fpga-region"; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - }; - }; - - fpga-bridge@4420 { - compatible = "altr,freeze-bridge-controller"; - reg = <0x4420 0x10>; - - fpga_region2: fpga-region2 { - compatible = "fpga-region"; - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges; - }; - }; -}; - -Device Tree Example: Partial Reconfiguration -============================================ - -This example reprograms one of the PRR's set up in the previous example. - -The sequence that occurs when this overlay is similar to the above, the only -differences are that the FPGA is partially reconfigured due to the -"partial-fpga-config" boolean and the only bridge that is controlled during -programming is the FPGA based bridge of fpga_region1. - -/dts-v1/; -/plugin/; - -&fpga_region1 { - #address-cells = <1>; - #size-cells = <1>; - - firmware-name = "soc_image2.rbf"; - partial-fpga-config; - - gpio@10040 { - compatible = "altr,pio-1.0"; - reg = <0x10040 0x20>; - clocks = <0x2>; - altr,ngpio = <0x4>; - #gpio-cells = <0x2>; - gpio-controller; - }; -}; - -Constraints -=========== - -It is beyond the scope of this document to fully describe all the FPGA design -constraints required to make partial reconfiguration work[1] [2] [3], but a few -deserve quick mention. - -A persona must have boundary connections that line up with those of the partition -or region it is designed to go into. - -During programming, transactions through those connections must be stopped and -the connections must be held at a fixed logic level. This can be achieved by -FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. - --- -[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf -[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf -[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf diff --git a/dts/Bindings/fpga/fpga-region.yaml b/dts/Bindings/fpga/fpga-region.yaml new file mode 100644 index 0000000000..77554885a6 --- /dev/null +++ b/dts/Bindings/fpga/fpga-region.yaml @@ -0,0 +1,358 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/fpga-region.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FPGA Region + +maintainers: + - Michal Simek <michal.simek@amd.com> + +description: | + CONTENTS + - Introduction + - Terminology + - Sequence + - FPGA Region + - Supported Use Models + - Constraints + + + Introduction + ============ + + FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in + the Device Tree. FPGA Regions provide a way to program FPGAs under device tree + control. + + The documentation hits some of the high points of FPGA usage and + attempts to include terminology used by both major FPGA manufacturers. This + document isn't a replacement for any manufacturers specifications for FPGA + usage. + + + Terminology + =========== + + Full Reconfiguration + * The entire FPGA is programmed. + + Partial Reconfiguration (PR) + * A section of an FPGA is reprogrammed while the rest of the FPGA is not + affected. + * Not all FPGA's support PR. + + Partial Reconfiguration Region (PRR) + * Also called a "reconfigurable partition" + * A PRR is a specific section of an FPGA reserved for reconfiguration. + * A base (or static) FPGA image may create a set of PRR's that later may + be independently reprogrammed many times. + * The size and specific location of each PRR is fixed. + * The connections at the edge of each PRR are fixed. The image that is loaded + into a PRR must fit and must use a subset of the region's connections. + * The busses within the FPGA are split such that each region gets its own + branch that may be gated independently. + + Persona + * Also called a "partial bit stream" + * An FPGA image that is designed to be loaded into a PRR. There may be + any number of personas designed to fit into a PRR, but only one at a time + may be loaded. + * A persona may create more regions. + + FPGA Bridge + * FPGA Bridges gate bus signals between a host and FPGA. + * FPGA Bridges should be disabled while the FPGA is being programmed to + prevent spurious signals on the cpu bus and to the soft logic. + * FPGA bridges may be actual hardware or soft logic on an FPGA. + * During Full Reconfiguration, hardware bridges between the host and FPGA + will be disabled. + * During Partial Reconfiguration of a specific region, that region's bridge + will be used to gate the busses. Traffic to other regions is not affected. + * In some implementations, the FPGA Manager transparently handles gating the + buses, eliminating the need to show the hardware FPGA bridges in the + device tree. + * An FPGA image may create a set of reprogrammable regions, each having its + own bridge and its own split of the busses in the FPGA. + + FPGA Manager + * An FPGA Manager is a hardware block that programs an FPGA under the control + of a host processor. + + Base Image + * Also called the "static image" + * An FPGA image that is designed to do full reconfiguration of the FPGA. + * A base image may set up a set of partial reconfiguration regions that may + later be reprogrammed. + + ---------------- ---------------------------------- + | Host CPU | | FPGA | + | | | | + | ----| | ----------- -------- | + | | H | | |==>| Bridge0 |<==>| PRR0 | | + | | W | | | ----------- -------- | + | | | | | | + | | B |<=====>|<==| ----------- -------- | + | | R | | |==>| Bridge1 |<==>| PRR1 | | + | | I | | | ----------- -------- | + | | D | | | | + | | G | | | ----------- -------- | + | | E | | |==>| Bridge2 |<==>| PRR2 | | + | ----| | ----------- -------- | + | | | | + ---------------- ---------------------------------- + + Figure 1: An FPGA set up with a base image that created three regions. Each + region (PRR0-2) gets its own split of the busses that is independently gated by + a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be + reprogrammed independently while the rest of the system continues to function. + + + Sequence + ======== + + When a DT overlay that targets an FPGA Region is applied, the FPGA Region will + do the following: + + 1. Disable appropriate FPGA bridges. + 2. Program the FPGA using the FPGA manager. + 3. Enable the FPGA bridges. + 4. The Device Tree overlay is accepted into the live tree. + 5. Child devices are populated. + + When the overlay is removed, the child nodes will be removed and the FPGA Region + will disable the bridges. + + + FPGA Region + =========== + + FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA + Region brings together the elements needed to program on a running system and + add the child devices: + + * FPGA Manager + * FPGA Bridges + * image-specific information needed to the programming. + * child nodes + + The intended use is that a Device Tree overlay (DTO) can be used to reprogram an + FPGA while an operating system is running. + + An FPGA Region that exists in the live Device Tree reflects the current state. + If the live tree shows a "firmware-name" property or child nodes under an FPGA + Region, the FPGA already has been programmed. A DTO that targets an FPGA Region + and adds the "firmware-name" property is taken as a request to reprogram the + FPGA. After reprogramming is successful, the overlay is accepted into the live + tree. + + The base FPGA Region in the device tree represents the FPGA and supports full + reconfiguration. It must include a phandle to an FPGA Manager. The base + FPGA region will be the child of one of the hardware bridges (the bridge that + allows register access) between the cpu and the FPGA. If there are more than + one bridge to control during FPGA programming, the region will also contain a + list of phandles to the additional hardware FPGA Bridges. + + For partial reconfiguration (PR), each PR region will have an FPGA Region. + These FPGA regions are children of FPGA bridges which are then children of the + base FPGA region. The "Full Reconfiguration to add PRR's" example below shows + this. + + If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA + Manager specified by its ancestor FPGA Region. This supports both the case + where the same FPGA Manager is used for all of an FPGA as well the case where + a different FPGA Manager is used for each region. + + FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents + shutting down bridges that are upstream from the other active regions while one + region is getting reconfigured (see Figure 1 above). During PR, the FPGA's + hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges + within the static image of the FPGA. + + + Supported Use Models + ==================== + + In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and + a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some + uses are specific to an FPGA device. + + * No FPGA Bridges + In this case, the FPGA Manager which programs the FPGA also handles the + bridges behind the scenes. No FPGA Bridge devices are needed for full + reconfiguration. + + * Full reconfiguration with hardware bridges + In this case, there are hardware bridges between the processor and FPGA that + need to be controlled during full reconfiguration. Before the overlay is + applied, the live DT must include the FPGA Manager, FPGA Bridges, and a + FPGA Region. The FPGA Region is the child of the bridge that allows + register access to the FPGA. Additional bridges may be listed in a + fpga-bridges property in the FPGA region or in the device tree overlay. + + * Partial reconfiguration with bridges in the FPGA + In this case, the FPGA will have one or more PRR's that may be programmed + separately while the rest of the FPGA can remain active. To manage this, + bridges need to exist in the FPGA that can gate the buses going to each FPGA + region while the buses are enabled for other sections. Before any partial + reconfiguration can be done, a base FPGA image must be loaded which includes + PRR's with FPGA bridges. The device tree should have an FPGA region for each + PRR. + + Constraints + =========== + + It is beyond the scope of this document to fully describe all the FPGA design + constraints required to make partial reconfiguration work[1] [2] [3], but a few + deserve quick mention. + + A persona must have boundary connections that line up with those of the partition + or region it is designed to go into. + + During programming, transactions through those connections must be stopped and + the connections must be held at a fixed logic level. This can be achieved by + FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. + + -- + [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf + [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf + [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf + +properties: + $nodename: + pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$" + + compatible: + const: fpga-region + + reg: + maxItems: 1 + + ranges: true + "#address-cells": true + "#size-cells": true + + config-complete-timeout-us: + description: + The maximum time in microseconds time for the FPGA to go to operating + mode after the region has been programmed. + + encrypted-fpga-config: + type: boolean + description: + Set if the bitstream is encrypted. + + external-fpga-config: + type: boolean + description: + Set if the FPGA has already been configured prior to OS boot up. + + firmware-name: + maxItems: 1 + description: + Should contain the name of an FPGA image file located on the firmware + search path. If this property shows up in a live device tree it indicates + that the FPGA has already been programmed with this image. + If this property is in an overlay targeting an FPGA region, it is + a request to program the FPGA with that image. + + fpga-bridges: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should contain a list of phandles to FPGA Bridges that must be + controlled during FPGA programming along with the parent FPGA bridge. + This property is optional if the FPGA Manager handles the bridges. + If the fpga-region is the child of an fpga-bridge, the list should not + contain the parent bridge. + + fpga-mgr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Should contain a phandle to an FPGA Manager. Child FPGA Regions + inherit this property from their ancestor regions. An fpga-mgr property + in a region will override any inherited FPGA manager. + + partial-fpga-config: + type: boolean + description: + Set if partial reconfiguration is to be done, otherwise full + reconfiguration is done. + + region-freeze-timeout-us: + description: + The maximum time in microseconds to wait for bridges to successfully + become disabled before the region has been programmed. + + region-unfreeze-timeout-us: + description: + The maximum time in microseconds to wait for bridges to successfully + become enabled after the region has been programmed. + +required: + - compatible + - fpga-mgr + +additionalProperties: + type: object + +examples: + - | + /* + * Full Reconfiguration without Bridges with DT overlay + */ + fpga_region0: fpga-region@0 { + compatible = "fpga-region"; + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + fpga-mgr = <&fpga_mgr0>; + ranges = <0x10000000 0x20000000 0x10000000>; + + /* DT Overlay contains: &fpga_region0 */ + firmware-name = "zynq-gpio.bin"; + gpio@40000000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0x40000000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + - | + /* + * Partial reconfiguration with bridge + */ + fpga_region1: fpga-region@0 { + compatible = "fpga-region"; + reg = <0 0>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + fpga-mgr = <&fpga_mgr1>; + fpga-bridges = <&fpga_bridge1>; + partial-fpga-config; + + /* DT Overlay contains: &fpga_region1 */ + firmware-name = "zynq-gpio-partial.bin"; + clk: clock { + compatible = "fixed-factor-clock"; + clocks = <&parentclk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + gpio@40000000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0x40000000 0x10000>; + #gpio-cells = <2>; + gpio-controller; + clocks = <&clk>; + }; + }; + }; diff --git a/dts/Bindings/fpga/xlnx,versal-fpga.yaml b/dts/Bindings/fpga/xlnx,versal-fpga.yaml index 26f18834ca..80833462f6 100644 --- a/dts/Bindings/fpga/xlnx,versal-fpga.yaml +++ b/dts/Bindings/fpga/xlnx,versal-fpga.yaml @@ -26,7 +26,7 @@ additionalProperties: false examples: - | - versal_fpga: versal_fpga { + versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; diff --git a/dts/Bindings/gpio/aspeed,ast2400-gpio.yaml b/dts/Bindings/gpio/aspeed,ast2400-gpio.yaml new file mode 100644 index 0000000000..cf11aa7ec8 --- /dev/null +++ b/dts/Bindings/gpio/aspeed,ast2400-gpio.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/aspeed,ast2400-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed GPIO controller + +maintainers: + - Andrew Jeffery <andrew@codeconstruct.com.au> + +properties: + compatible: + enum: + - aspeed,ast2400-gpio + - aspeed,ast2500-gpio + - aspeed,ast2600-gpio + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: The clock to use for debounce timings + + gpio-controller: true + gpio-line-names: + minItems: 36 + maxItems: 232 + + gpio-ranges: true + + "#gpio-cells": + const: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + ngpios: + minimum: 36 + maximum: 232 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - gpio-controller + - "#gpio-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: aspeed,ast2400-gpio + then: + properties: + gpio-line-names: + minItems: 220 + maxItems: 220 + ngpios: + const: 220 + - if: + properties: + compatible: + contains: + const: aspeed,ast2500-gpio + then: + properties: + gpio-line-names: + minItems: 232 + maxItems: 232 + ngpios: + const: 232 + - if: + properties: + compatible: + contains: + const: aspeed,ast2600-gpio + then: + properties: + gpio-line-names: + minItems: 36 + maxItems: 208 + ngpios: + enum: [ 36, 208 ] + required: + - ngpios + +additionalProperties: false + +examples: + - | + gpio@1e780000 { + compatible = "aspeed,ast2400-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + - | + gpio: gpio@1e780000 { + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x200>; + interrupts = <20>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 232>; + }; + - | + #include <dt-bindings/clock/ast2600-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + gpio0: gpio@1e780000 { + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780000 0x400>; + clocks = <&syscon ASPEED_CLK_APB2>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 208>; + ngpios = <208>; + }; + gpio1: gpio@1e780800 { + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780800 0x800>; + clocks = <&syscon ASPEED_CLK_APB1>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 208 36>; + ngpios = <36>; + }; diff --git a/dts/Bindings/gpio/gateworks,pld-gpio.txt b/dts/Bindings/gpio/gateworks,pld-gpio.txt index 6e81f8b755..d543fd1b8b 100644 --- a/dts/Bindings/gpio/gateworks,pld-gpio.txt +++ b/dts/Bindings/gpio/gateworks,pld-gpio.txt @@ -1,7 +1,6 @@ Gateworks PLD GPIO controller bindings -The GPIO controller should be a child node on an I2C bus, -see: i2c/i2c.txt for details. +The GPIO controller should be a child node on an I2C bus. Required properties: - compatible: Should be "gateworks,pld-gpio" diff --git a/dts/Bindings/gpio/gpio-aspeed.txt b/dts/Bindings/gpio/gpio-aspeed.txt deleted file mode 100644 index b2033fc3a7..0000000000 --- a/dts/Bindings/gpio/gpio-aspeed.txt +++ /dev/null @@ -1,39 +0,0 @@ -Aspeed GPIO controller Device Tree Bindings -------------------------------------------- - -Required properties: -- compatible : Either "aspeed,ast2400-gpio", "aspeed,ast2500-gpio", - or "aspeed,ast2600-gpio". - -- #gpio-cells : Should be two - - First cell is the GPIO line number - - Second cell is used to specify optional - parameters (unused) - -- reg : Address and length of the register set for the device -- gpio-controller : Marks the device node as a GPIO controller. -- interrupts : Interrupt specifier (see interrupt bindings for - details) -- interrupt-controller : Mark the GPIO controller as an interrupt-controller - -Optional properties: - -- clocks : A phandle to the clock to use for debounce timings -- ngpios : Number of GPIOs controlled by this controller. Should be set - when there are multiple GPIO controllers on a SoC (ast2600). - -The gpio and interrupt properties are further described in their respective -bindings documentation: - -- Documentation/devicetree/bindings/gpio/gpio.txt -- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - - Example: - gpio@1e780000 { - #gpio-cells = <2>; - compatible = "aspeed,ast2400-gpio"; - gpio-controller; - interrupts = <20>; - reg = <0x1e780000 0x1000>; - interrupt-controller; - }; diff --git a/dts/Bindings/gpio/gpio-mvebu.yaml b/dts/Bindings/gpio/gpio-mvebu.yaml index f1bd1e6b2e..33d4e47165 100644 --- a/dts/Bindings/gpio/gpio-mvebu.yaml +++ b/dts/Bindings/gpio/gpio-mvebu.yaml @@ -115,7 +115,7 @@ allOf: required: - reg -unevaluatedProperties: true +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/gpio/gpio-nmk.txt b/dts/Bindings/gpio/gpio-nmk.txt deleted file mode 100644 index 8315ac7780..0000000000 --- a/dts/Bindings/gpio/gpio-nmk.txt +++ /dev/null @@ -1,31 +0,0 @@ -Nomadik GPIO controller - -Required properties: -- compatible : Should be "st,nomadik-gpio". -- reg : Physical base address and length of the controller's registers. -- interrupts : The interrupt outputs from the controller. -- #gpio-cells : Should be two: - The first cell is the pin number. - The second cell is used to specify optional parameters: - - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. -- gpio-controller : Marks the device node as a GPIO controller. -- interrupt-controller : Marks the device node as an interrupt controller. -- gpio-bank : Specifies which bank a controller owns. -- st,supports-sleepmode : Specifies whether controller can sleep or not - -Example: - - gpio1: gpio@8012e080 { - compatible = "st,nomadik-gpio"; - reg = <0x8012e080 0x80>; - interrupts = <0 120 0x4>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - st,supports-sleepmode; - gpio-bank = <1>; - }; diff --git a/dts/Bindings/gpio/gpio-pca9570.yaml b/dts/Bindings/gpio/gpio-pca9570.yaml index 452f8972a9..6f73961001 100644 --- a/dts/Bindings/gpio/gpio-pca9570.yaml +++ b/dts/Bindings/gpio/gpio-pca9570.yaml @@ -28,6 +28,9 @@ properties: minItems: 4 maxItems: 8 + label: + description: A descriptive name for this device. + required: - compatible - reg diff --git a/dts/Bindings/gpio/mrvl-gpio.yaml b/dts/Bindings/gpio/mrvl-gpio.yaml index 9cf6137dd5..65155bb701 100644 --- a/dts/Bindings/gpio/mrvl-gpio.yaml +++ b/dts/Bindings/gpio/mrvl-gpio.yaml @@ -9,7 +9,7 @@ title: Marvell PXA GPIO controller maintainers: - Linus Walleij <linus.walleij@linaro.org> - Bartosz Golaszewski <bgolaszewski@baylibre.com> - - Rob Herring <robh+dt@kernel.org> + - Rob Herring <robh@kernel.org> allOf: - if: diff --git a/dts/Bindings/gpio/renesas,rcar-gpio.yaml b/dts/Bindings/gpio/renesas,rcar-gpio.yaml index aa424e2b95..cc7a950a60 100644 --- a/dts/Bindings/gpio/renesas,rcar-gpio.yaml +++ b/dts/Bindings/gpio/renesas,rcar-gpio.yaml @@ -53,6 +53,7 @@ properties: - renesas,gpio-r8a779a0 # R-Car V3U - renesas,gpio-r8a779f0 # R-Car S4-8 - renesas,gpio-r8a779g0 # R-Car V4H + - renesas,gpio-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-gpio # R-Car Gen4 reg: diff --git a/dts/Bindings/gpio/st,nomadik-gpio.yaml b/dts/Bindings/gpio/st,nomadik-gpio.yaml new file mode 100644 index 0000000000..38d37d8f72 --- /dev/null +++ b/dts/Bindings/gpio/st,nomadik-gpio.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/st,nomadik-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nomadik GPIO controller + +description: + The Nomadik GPIO driver handles Nomadik SoC GPIO blocks. This block has also + been called ST STA2X11. On the Nomadik platform, this driver is intertwined + with pinctrl-nomadik. + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + enum: + - st,nomadik-gpio + - mobileye,eyeq5-gpio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + gpio-bank: + description: System-wide GPIO bank index. + $ref: /schemas/types.yaml#/definitions/uint32 + + st,supports-sleepmode: + description: Whether the controller can sleep or not. + $ref: /schemas/types.yaml#/definitions/flag + + clocks: + maxItems: 1 + + gpio-ranges: + maxItems: 1 + + ngpios: + minimum: 0 + maximum: 32 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - "#gpio-cells" + - gpio-controller + - interrupt-controller + - gpio-bank + +unevaluatedProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: mobileye,eyeq5-gpio + then: + properties: + st,supports-sleepmode: false + +examples: + - | + gpio@8012e080 { + compatible = "st,nomadik-gpio"; + reg = <0x8012e080 0x80>; + interrupts = <0 120 0x4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + st,supports-sleepmode; + gpio-bank = <1>; + }; diff --git a/dts/Bindings/gpu/img,powervr.yaml b/dts/Bindings/gpu/img,powervr-rogue.yaml index a13298f1a1..256e252f80 100644 --- a/dts/Bindings/gpu/img,powervr.yaml +++ b/dts/Bindings/gpu/img,powervr-rogue.yaml @@ -2,10 +2,10 @@ # Copyright (c) 2023 Imagination Technologies Ltd. %YAML 1.2 --- -$id: http://devicetree.org/schemas/gpu/img,powervr.yaml# +$id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Imagination Technologies PowerVR and IMG GPU +title: Imagination Technologies PowerVR and IMG Rogue GPUs maintainers: - Frank Binns <frank.binns@imgtec.com> diff --git a/dts/Bindings/gpu/img,powervr-sgx.yaml b/dts/Bindings/gpu/img,powervr-sgx.yaml new file mode 100644 index 0000000000..f5898b0438 --- /dev/null +++ b/dts/Bindings/gpu/img,powervr-sgx.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 Imagination Technologies Ltd. +# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination Technologies PowerVR SGX GPUs + +maintainers: + - Frank Binns <frank.binns@imgtec.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,omap3430-gpu # Rev 121 + - ti,omap3630-gpu # Rev 125 + - const: img,powervr-sgx530 + - items: + - enum: + - ingenic,jz4780-gpu # Rev 130 + - ti,omap4430-gpu # Rev 120 + - const: img,powervr-sgx540 + - items: + - enum: + - allwinner,sun6i-a31-gpu # MP2 Rev 115 + - ti,omap4470-gpu # MP1 Rev 112 + - ti,omap5432-gpu # MP2 Rev 105 + - ti,am5728-gpu # MP2 Rev 116 + - ti,am6548-gpu # MP1 Rev 117 + - const: img,powervr-sgx544 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + items: + - const: core + - const: mem + - const: sys + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: ti,am6548-gpu + then: + required: + - power-domains + else: + properties: + power-domains: false + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun6i-a31-gpu + - ingenic,jz4780-gpu + then: + required: + - clocks + - clock-names + else: + properties: + clocks: false + clock-names: false + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-gpu + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + const: ingenic,jz4780-gpu + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + gpu@7000000 { + compatible = "ti,am6548-gpu", "img,powervr-sgx544"; + reg = <0x7000000 0x10000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + }; + + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpu: gpu@1c40000 { + compatible = "allwinner,sun6i-a31-gpu", "img,powervr-sgx544"; + reg = <0x01c40000 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu 1>, <&ccu 2>; + clock-names = "core", "mem"; + }; diff --git a/dts/Bindings/hwmon/adi,adm1177.yaml b/dts/Bindings/hwmon/adi,adm1177.yaml index 2e45364d05..be7e9e91a3 100644 --- a/dts/Bindings/hwmon/adi,adm1177.yaml +++ b/dts/Bindings/hwmon/adi,adm1177.yaml @@ -46,7 +46,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/hwmon/adi,adm1275.yaml b/dts/Bindings/hwmon/adi,adm1275.yaml index ab87f51c5a..b680612949 100644 --- a/dts/Bindings/hwmon/adi,adm1275.yaml +++ b/dts/Bindings/hwmon/adi,adm1275.yaml @@ -33,10 +33,6 @@ properties: reg: maxItems: 1 - shunt-resistor-micro-ohms: - description: - Shunt resistor value in micro-Ohm. - adi,volt-curr-sample-average: description: | Number of samples to be used to report voltage and current values. @@ -50,6 +46,7 @@ properties: enum: [1, 2, 4, 8, 16, 32, 64, 128] allOf: + - $ref: hwmon-common.yaml# - if: properties: compatible: @@ -107,7 +104,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/hwmon/adi,ltc2945.yaml b/dts/Bindings/hwmon/adi,ltc2945.yaml index 5cb66e97e8..6401b0a9af 100644 --- a/dts/Bindings/hwmon/adi,ltc2945.yaml +++ b/dts/Bindings/hwmon/adi,ltc2945.yaml @@ -31,7 +31,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/hwmon/adi,ltc4282.yaml b/dts/Bindings/hwmon/adi,ltc4282.yaml new file mode 100644 index 0000000000..4854b95a93 --- /dev/null +++ b/dts/Bindings/hwmon/adi,ltc4282.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,ltc4282.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C + +maintainers: + - Nuno Sa <nuno.sa@analog.com> + +description: | + Analog Devices LTC4282 I2C High Current Hot Swap Controller over I2C. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4282.pdf + +properties: + compatible: + enum: + - adi,ltc4282 + + reg: + maxItems: 1 + + vdd-supply: true + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + adi,rsense-nano-ohms: + description: Value of the sense resistor. + + adi,vin-mode-microvolt: + description: + Selects operating range for the Undervoltage, Overvoltage and Foldback + pins. Also for the ADC. Should be set to the nominal input voltage. + enum: [3300000, 5000000, 12000000, 24000000] + default: 12000000 + + adi,fet-bad-timeout-ms: + description: + From the moment a FET bad conditions is present, this property selects the + wait time/timeout for a FET-bad fault to be signaled. Setting this to 0, + disables FET bad faults to be reported. + default: 255 + maximum: 255 + + adi,overvoltage-dividers: + description: | + Select which dividers to use for VDD Overvoltage detection. Note that + when the internal dividers are used the threshold is referenced to VDD. + The percentages in the datasheet are misleading since the actual values + to look for are in the "Absolute Maximum Ratings" table in the + "Comparator Inputs" section. In there there's a line for each of the 5%, + 10% and 15% settings with the actual min, typical and max tolerances. + $ref: /schemas/types.yaml#/definitions/string + enum: [external, vdd_5_percent, vdd_10_percent, vdd_15_percent] + default: external + + adi,undervoltage-dividers: + description: | + Select which dividers to use for VDD Overvoltage detection. Note that + when the internal dividers are used the threshold is referenced to VDD. + The percentages in the datasheet are misleading since the actual values + to look for are in the "Absolute Maximum Ratings" table in the + "Comparator Inputs" section. In there there's a line for each of the 5%, + 10% and 15% settings with the actual min, typical and max tolerances. + $ref: /schemas/types.yaml#/definitions/string + enum: [external, vdd_5_percent, vdd_10_percent, vdd_15_percent] + default: external + + adi,current-limit-sense-microvolt: + description: + The current limit sense voltage of the chip is adjustable between + 12.5mV and 34.4mV in 3.1mV steps. This effectively limits the current + on the load. + enum: [12500, 15625, 18750, 21875, 25000, 28125, 31250, 34375] + default: 25000 + + adi,overcurrent-retry: + description: + If set, enables the chip to auto-retry 256 timer cycles after an + Overcurrent fault. + type: boolean + + adi,overvoltage-retry-disable: + description: + If set, disables the chip to auto-retry 50ms after an Overvoltage fault. + It's enabled by default. + type: boolean + + adi,undervoltage-retry-disable: + description: + If set, disables the chip to auto-retry 50ms after an Undervoltage fault. + It's enabled by default. + type: boolean + + adi,fault-log-enable: + description: + If set, enables the FAULT_LOG and ADC_ALERT_LOG registers to be written + to the EEPROM when a fault bit transitions high and hence, will be + available after a power cycle (the chip loads the contents of + the EE_FAULT_LOG register - the one in EEPROM - into FAULT_LOG at boot). + type: boolean + + adi,gpio1-mode: + description: Defines the function of the Pin. It can indicate that power is + good (PULL the pin low when power is not good) or that power is bad (Go + into high-z when power is not good). + $ref: /schemas/types.yaml#/definitions/string + enum: [power_bad, power_good] + default: power_good + + adi,gpio2-mode: + description: Defines the function of the Pin. It can be set as the input for + the ADC or indicating that the MOSFET is in stress (dissipating power). + $ref: /schemas/types.yaml#/definitions/string + enum: [adc_input, stress_fet] + default: adc_input + + adi,gpio3-monitor-enable: + description: If set, gpio3 is set as input for the ADC instead of gpio2. + type: boolean + +allOf: + - if: + required: + - adi,gpio3-monitor-enable + then: + properties: + adi,gpio2-mode: + const: stress_fet + +required: + - compatible + - reg + - adi,rsense-nano-ohms + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hwmon@50 { + compatible = "adi,ltc4282"; + reg = <0x50>; + adi,rsense-nano-ohms = <500>; + + adi,gpio1-mode = "power_good"; + adi,gpio2-mode = "adc_input"; + }; + }; +... diff --git a/dts/Bindings/hwmon/amphenol,chipcap2.yaml b/dts/Bindings/hwmon/amphenol,chipcap2.yaml new file mode 100644 index 0000000000..17351fdbef --- /dev/null +++ b/dts/Bindings/hwmon/amphenol,chipcap2.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/amphenol,chipcap2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ChipCap 2 humidity and temperature iio sensor + +maintainers: + - Javier Carrasco <javier.carrasco.cruz@gmail.com> + +description: | + Relative humidity and temperature sensor on I2C bus. + + Datasheets: + https://www.amphenol-sensors.com/en/telaire/humidity/527-humidity-sensors/3095-chipcap-2 + +properties: + compatible: + oneOf: + - const: amphenol,cc2d23 + - items: + - enum: + - amphenol,cc2d23s + - amphenol,cc2d25 + - amphenol,cc2d25s + - amphenol,cc2d33 + - amphenol,cc2d33s + - amphenol,cc2d35 + - amphenol,cc2d35s + - const: amphenol,cc2d23 + + reg: + maxItems: 1 + + interrupts: + items: + - description: measurement ready indicator + - description: low humidity alarm + - description: high humidity alarm + + interrupt-names: + items: + - const: ready + - const: low + - const: high + + vdd-supply: + description: + Dedicated, controllable supply-regulator to reset the device and + enter in command mode. + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + humidity@28 { + compatible = "amphenol,cc2d23s", "amphenol,cc2d23"; + reg = <0x28>; + interrupt-parent = <&gpio>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>, + <5 IRQ_TYPE_EDGE_RISING>, + <6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ready", "low", "high"; + vdd-supply = <®_vdd>; + }; + }; diff --git a/dts/Bindings/hwmon/aspeed,g6-pwm-tach.yaml b/dts/Bindings/hwmon/aspeed,g6-pwm-tach.yaml new file mode 100644 index 0000000000..9e5ed901ae --- /dev/null +++ b/dts/Bindings/hwmon/aspeed,g6-pwm-tach.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2023 Aspeed, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/aspeed,g6-pwm-tach.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED G6 PWM and Fan Tach controller + +maintainers: + - Billy Tsai <billy_tsai@aspeedtech.com> + +description: | + The ASPEED PWM controller can support up to 16 PWM outputs. + The ASPEED Fan Tacho controller can support up to 16 fan tach input. + They are independent hardware blocks, which are different from the + previous version of the ASPEED chip. + +properties: + compatible: + enum: + - aspeed,ast2600-pwm-tach + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +patternProperties: + "^fan-[0-9]+$": + $ref: fan-common.yaml# + unevaluatedProperties: false + required: + - tach-ch + +required: + - reg + - clocks + - resets + - "#pwm-cells" + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/aspeed-clock.h> + pwm_tach: pwm-tach-controller@1e610000 { + compatible = "aspeed,ast2600-pwm-tach"; + reg = <0x1e610000 0x100>; + clocks = <&syscon ASPEED_CLK_AHB>; + resets = <&syscon ASPEED_RESET_PWM>; + #pwm-cells = <3>; + + fan-0 { + tach-ch = /bits/ 8 <0x0>; + pwms = <&pwm_tach 0 40000 0>; + }; + + fan-1 { + tach-ch = /bits/ 8 <0x1 0x2>; + pwms = <&pwm_tach 1 40000 0>; + }; + }; diff --git a/dts/Bindings/hwmon/fan-common.yaml b/dts/Bindings/hwmon/fan-common.yaml new file mode 100644 index 0000000000..0fb7380816 --- /dev/null +++ b/dts/Bindings/hwmon/fan-common.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/fan-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Fan Properties + +maintainers: + - Naresh Solanki <naresh.solanki@9elements.com> + - Billy Tsai <billy_tsai@aspeedtech.com> + +properties: + max-rpm: + description: + Max RPM supported by fan. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 100000 + + min-rpm: + description: + Min RPM supported by fan. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 1000 + + pulses-per-revolution: + description: + The number of pulse from fan sensor per revolution. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 4 + + tach-div: + description: + Divisor for the tach sampling clock, which determines the sensitivity of the tach pin. + $ref: /schemas/types.yaml#/definitions/uint32 + + target-rpm: + description: + The default desired fan speed in RPM. + $ref: /schemas/types.yaml#/definitions/uint32 + + fan-driving-mode: + description: + Select the driving mode of the fan.(DC, PWM and so on) + $ref: /schemas/types.yaml#/definitions/string + enum: [ dc, pwm ] + + pwms: + description: + PWM provider. + maxItems: 1 + + "#cooling-cells": + const: 2 + + cooling-levels: + description: + The control value which correspond to thermal cooling states. + $ref: /schemas/types.yaml#/definitions/uint32-array + + tach-ch: + description: + The tach channel used for the fan. + $ref: /schemas/types.yaml#/definitions/uint8-array + + label: + description: + Optional fan label + + fan-supply: + description: + Power supply for fan. + + reg: + maxItems: 1 + +additionalProperties: true + +... diff --git a/dts/Bindings/hwmon/hwmon-common.yaml b/dts/Bindings/hwmon/hwmon-common.yaml new file mode 100644 index 0000000000..dc86b5c72c --- /dev/null +++ b/dts/Bindings/hwmon/hwmon-common.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/hwmon-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hardware Monitoring Devices Common Properties + +maintainers: + - Guenter Roeck <linux@roeck-us.net> + +properties: + label: + description: A descriptive name for this device. + + shunt-resistor-micro-ohms: + description: The value of current sense resistor. + +additionalProperties: true diff --git a/dts/Bindings/hwmon/lltc,ltc4151.yaml b/dts/Bindings/hwmon/lltc,ltc4151.yaml index e62aff6704..8f0095bb7f 100644 --- a/dts/Bindings/hwmon/lltc,ltc4151.yaml +++ b/dts/Bindings/hwmon/lltc,ltc4151.yaml @@ -25,7 +25,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/hwmon/lltc,ltc4286.yaml b/dts/Bindings/hwmon/lltc,ltc4286.yaml index 98ca163d34..853df9fef6 100644 --- a/dts/Bindings/hwmon/lltc,ltc4286.yaml +++ b/dts/Bindings/hwmon/lltc,ltc4286.yaml @@ -25,15 +25,14 @@ properties: The default is 102.4 volts. type: boolean - shunt-resistor-micro-ohms: - description: - Resistor value micro-ohms. - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/hwmon/lm75.yaml b/dts/Bindings/hwmon/lm75.yaml index ed269e428a..29bd7460cc 100644 --- a/dts/Bindings/hwmon/lm75.yaml +++ b/dts/Bindings/hwmon/lm75.yaml @@ -57,6 +57,7 @@ required: - reg allOf: + - $ref: hwmon-common.yaml# - if: not: properties: @@ -71,7 +72,7 @@ allOf: properties: interrupts: false -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/hwmon/nuvoton,nct6775.yaml b/dts/Bindings/hwmon/nuvoton,nct6775.yaml index 358b262431..e3db642878 100644 --- a/dts/Bindings/hwmon/nuvoton,nct6775.yaml +++ b/dts/Bindings/hwmon/nuvoton,nct6775.yaml @@ -25,6 +25,7 @@ properties: - nuvoton,nct6796 - nuvoton,nct6797 - nuvoton,nct6798 + - nuvoton,nct6799 reg: maxItems: 1 diff --git a/dts/Bindings/hwmon/pmbus/infineon,tda38640.yaml b/dts/Bindings/hwmon/pmbus/infineon,tda38640.yaml index ded1c11576..5c4e52b472 100644 --- a/dts/Bindings/hwmon/pmbus/infineon,tda38640.yaml +++ b/dts/Bindings/hwmon/pmbus/infineon,tda38640.yaml @@ -30,6 +30,23 @@ properties: unconnected(has internal pull-down). type: boolean + interrupts: + maxItems: 1 + + regulators: + type: object + description: + list of regulators provided by this controller. + + properties: + vout: + $ref: /schemas/regulator/regulator.yaml# + type: object + + unevaluatedProperties: false + + additionalProperties: false + required: - compatible - reg @@ -38,6 +55,7 @@ additionalProperties: false examples: - | + #include <dt-bindings/interrupt-controller/irq.h> i2c { #address-cells = <1>; #size-cells = <0>; @@ -45,5 +63,15 @@ examples: tda38640@40 { compatible = "infineon,tda38640"; reg = <0x40>; + + interrupt-parent = <&smb_pex_cpu0_event>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvnn_main_cpu0: vout { + regulator-name = "pvnn_main_cpu0"; + regulator-enable-ramp-delay = <200>; + }; + }; }; }; diff --git a/dts/Bindings/hwmon/pmbus/ti,lm25066.yaml b/dts/Bindings/hwmon/pmbus/ti,lm25066.yaml index da8292bc32..a20f140dc7 100644 --- a/dts/Bindings/hwmon/pmbus/ti,lm25066.yaml +++ b/dts/Bindings/hwmon/pmbus/ti,lm25066.yaml @@ -34,11 +34,26 @@ properties: Shunt (sense) resistor value in micro-Ohms default: 1000 + regulators: + type: object + + properties: + vout: + $ref: /schemas/regulator/regulator.yaml# + type: object + + unevaluatedProperties: false + + additionalProperties: false + required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/hwmon/hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/hwmon/ti,ina2xx.yaml b/dts/Bindings/hwmon/ti,ina2xx.yaml index 378d1f6aee..df86c2c920 100644 --- a/dts/Bindings/hwmon/ti,ina2xx.yaml +++ b/dts/Bindings/hwmon/ti,ina2xx.yaml @@ -28,10 +28,14 @@ properties: - ti,ina231 - ti,ina237 - ti,ina238 + - ti,ina260 reg: maxItems: 1 + "#io-channel-cells": + const: 1 + shunt-resistor: description: Shunt resistor value in micro-Ohm. @@ -66,7 +70,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | @@ -77,6 +84,8 @@ examples: power-sensor@44 { compatible = "ti,ina220"; reg = <0x44>; + #io-channel-cells = <1>; + label = "vdd_3v0"; shunt-resistor = <1000>; vs-supply = <&vdd_3v0>; }; diff --git a/dts/Bindings/hwmon/ti,tmp513.yaml b/dts/Bindings/hwmon/ti,tmp513.yaml index cdd1489e0c..227858e760 100644 --- a/dts/Bindings/hwmon/ti,tmp513.yaml +++ b/dts/Bindings/hwmon/ti,tmp513.yaml @@ -72,7 +72,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/hwmon/ti,tps23861.yaml b/dts/Bindings/hwmon/ti,tps23861.yaml index ebc8d466c1..f58248c29e 100644 --- a/dts/Bindings/hwmon/ti,tps23861.yaml +++ b/dts/Bindings/hwmon/ti,tps23861.yaml @@ -35,7 +35,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: hwmon-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/i2c/atmel,at91sam-i2c.yaml b/dts/Bindings/i2c/atmel,at91sam-i2c.yaml index 6adedd3ec3..b1c13bab24 100644 --- a/dts/Bindings/i2c/atmel,at91sam-i2c.yaml +++ b/dts/Bindings/i2c/atmel,at91sam-i2c.yaml @@ -25,7 +25,9 @@ properties: - atmel,sama5d2-i2c - microchip,sam9x60-i2c - items: - - const: microchip,sama7g5-i2c + - enum: + - microchip,sama7g5-i2c + - microchip,sam9x7-i2c - const: microchip,sam9x60-i2c reg: diff --git a/dts/Bindings/i2c/i2c-demux-pinctrl.yaml b/dts/Bindings/i2c/i2c-demux-pinctrl.yaml index 2c08f2a7cf..b813f6d481 100644 --- a/dts/Bindings/i2c/i2c-demux-pinctrl.yaml +++ b/dts/Bindings/i2c/i2c-demux-pinctrl.yaml @@ -32,7 +32,6 @@ description: | +-------------------------------+ allOf: - - $ref: i2c-mux.yaml - $ref: /schemas/i2c/i2c-controller.yaml# properties: @@ -41,6 +40,8 @@ properties: i2c-parent: $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 description: List of phandles of I2C masters available for selection. The first one will be used as default. diff --git a/dts/Bindings/i2c/i2c-exynos5.yaml b/dts/Bindings/i2c/i2c-exynos5.yaml index df9c57bca2..cc8bba5537 100644 --- a/dts/Bindings/i2c/i2c-exynos5.yaml +++ b/dts/Bindings/i2c/i2c-exynos5.yaml @@ -33,6 +33,7 @@ properties: - const: samsung,exynos7-hsi2c - items: - enum: + - google,gs101-hsi2c - samsung,exynos850-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 diff --git a/dts/Bindings/i2c/i2c-imx-lpi2c.yaml b/dts/Bindings/i2c/i2c-imx-lpi2c.yaml index 4656f5112b..54d500be6a 100644 --- a/dts/Bindings/i2c/i2c-imx-lpi2c.yaml +++ b/dts/Bindings/i2c/i2c-imx-lpi2c.yaml @@ -24,6 +24,7 @@ properties: - fsl,imx8qm-lpi2c - fsl,imx8ulp-lpi2c - fsl,imx93-lpi2c + - fsl,imx95-lpi2c - const: fsl,imx7ulp-lpi2c reg: diff --git a/dts/Bindings/i2c/i2c-mpc.yaml b/dts/Bindings/i2c/i2c-mpc.yaml index 70fb69b923..b1d7d14c0b 100644 --- a/dts/Bindings/i2c/i2c-mpc.yaml +++ b/dts/Bindings/i2c/i2c-mpc.yaml @@ -96,6 +96,6 @@ examples: interrupts = <43 2>; interrupt-parent = <&mpic>; clock-frequency = <400000>; - i2c-scl-clk-low-timeout-us = <10000>; + i2c-transfer-timeout-us = <10000>; }; ... diff --git a/dts/Bindings/i2c/i2c-mux-pca954x.yaml b/dts/Bindings/i2c/i2c-mux-pca954x.yaml index 2d7bb998b0..9aa0585200 100644 --- a/dts/Bindings/i2c/i2c-mux-pca954x.yaml +++ b/dts/Bindings/i2c/i2c-mux-pca954x.yaml @@ -71,6 +71,23 @@ properties: description: A voltage regulator supplying power to the chip. On PCA9846 the regulator supplies power to VDD2 (core logic) and optionally to VDD1. + maxim,isolate-stuck-channel: + type: boolean + description: Allows to use non faulty channels while a stuck channel is + isolated from the upstream bus. If not set all channels are isolated from + the upstream bus until the fault is cleared. + + maxim,send-flush-out-sequence: + type: boolean + description: Send a flush-out sequence to stuck auxiliary buses + automatically after a stuck channel is being detected. + + maxim,preconnection-wiggle-test-enable: + type: boolean + description: Send a STOP condition to the auxiliary buses when the switch + register activates a channel to detect a stuck high fault. On fault the + channel is isolated from the upstream bus. + required: - compatible - reg @@ -95,6 +112,19 @@ allOf: "#interrupt-cells": false interrupt-controller: false + - if: + not: + properties: + compatible: + contains: + enum: + - maxim,max7357 + then: + properties: + maxim,isolate-stuck-channel: false + maxim,send-flush-out-sequence: false + maxim,preconnection-wiggle-test-enable: false + unevaluatedProperties: false examples: diff --git a/dts/Bindings/i2c/i2c-pxa.yaml b/dts/Bindings/i2c/i2c-pxa.yaml index 31386a8d76..e89ee36174 100644 --- a/dts/Bindings/i2c/i2c-pxa.yaml +++ b/dts/Bindings/i2c/i2c-pxa.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Marvell MMP I2C controller maintainers: - - Rob Herring <robh+dt@kernel.org> + - Rob Herring <robh@kernel.org> allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/dts/Bindings/i2c/i2c.txt b/dts/Bindings/i2c/i2c.txt deleted file mode 100644 index fc3dd7ec04..0000000000 --- a/dts/Bindings/i2c/i2c.txt +++ /dev/null @@ -1,151 +0,0 @@ -Generic device tree bindings for I2C busses -=========================================== - -This document describes generic bindings which can be used to describe I2C -busses and their child devices in a device tree. - -Required properties (per bus) ------------------------------ - -- #address-cells - should be <1>. Read more about addresses below. -- #size-cells - should be <0>. -- compatible - name of I2C bus controller - -For other required properties e.g. to describe register sets, -clocks, etc. check the binding documentation of the specific driver. - -The cells properties above define that an address of children of an I2C bus -are described by a single value. - -Optional properties (per bus) ------------------------------ - -These properties may not be supported by all drivers. However, if a driver -wants to support one of the below features, it should adapt these bindings. - -- clock-frequency - frequency of bus clock in Hz. - -- i2c-bus - For I2C adapters that have child nodes that are a mixture of both I2C - devices and non-I2C devices, the 'i2c-bus' subnode can be used for - populating I2C devices. If the 'i2c-bus' subnode is present, only - subnodes of this will be considered as I2C slaves. The properties, - '#address-cells' and '#size-cells' must be defined under this subnode - if present. - -- i2c-scl-falling-time-ns - Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C - specification. - -- i2c-scl-internal-delay-ns - Number of nanoseconds the IP core additionally needs to setup SCL. - -- i2c-scl-rising-time-ns - Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C - specification. - -- i2c-sda-falling-time-ns - Number of nanoseconds the SDA signal takes to fall; t(f) in the I2C - specification. - -- i2c-analog-filter - Enable analog filter for i2c lines. - -- i2c-digital-filter - Enable digital filter for i2c lines. - -- i2c-digital-filter-width-ns - Width of spikes which can be filtered by digital filter - (i2c-digital-filter). This width is specified in nanoseconds. - -- i2c-analog-filter-cutoff-frequency - Frequency that the analog filter (i2c-analog-filter) uses to distinguish - which signal to filter. Signal with higher frequency than specified will - be filtered out. Only lower frequency will pass (this is applicable to - a low-pass analog filter). Typical value should be above the normal - i2c bus clock frequency (clock-frequency). - Specified in Hz. - -- multi-master - states that there is another master active on this bus. The OS can use - this information to adapt power management to keep the arbitration awake - all the time, for example. Can not be combined with 'single-master'. - -- pinctrl - add extra pinctrl to configure SCL/SDA pins to GPIO function for bus - recovery, call it "gpio" or "recovery" (deprecated) state - -- scl-gpios - specify the gpio related to SCL pin. Used for GPIO bus recovery. - -- sda-gpios - specify the gpio related to SDA pin. Optional for GPIO bus recovery. - -- single-master - states that there is no other master active on this bus. The OS can use - this information to detect a stalled bus more reliably, for example. - Can not be combined with 'multi-master'. - -- smbus - states that additional SMBus restrictions and features apply to this bus. - An example of feature is SMBusHostNotify. Examples of restrictions are - more reserved addresses and timeout definitions. - -- smbus-alert - states that the optional SMBus-Alert feature apply to this bus. - -- mctp-controller - indicates that the system is accessible via this bus as an endpoint for - MCTP over I2C transport. - -Required properties (per child device) --------------------------------------- - -- compatible - name of I2C slave device - -- reg - One or many I2C slave addresses. These are usually a 7 bit addresses. - However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is - used to mark a 10 bit address. It is needed to avoid the ambiguity - between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050 - which, in theory, can be on the same bus. - Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we - listen to be devices ourselves. - -Optional properties (per child device) --------------------------------------- - -These properties may not be supported by all drivers. However, if a driver -wants to support one of the below features, it should adapt these bindings. - -- host-notify - device uses SMBus host notify protocol instead of interrupt line. - -- interrupts - interrupts used by the device. - -- interrupt-names - "irq", "wakeup" and "smbus_alert" names are recognized by I2C core, - other names are left to individual drivers. - -- reg-names - Names of map programmable addresses. - It can contain any map needing another address than default one. - -- wakeup-source - device can be used as a wakeup source. - -Binding may contain optional "interrupts" property, describing interrupts -used by the device. I2C core will assign "irq" interrupt (or the very first -interrupt if not using interrupt names) as primary interrupt for the slave. - -Alternatively, devices supporting SMBus Host Notify, and connected to -adapters that support this feature, may use "host-notify" property. I2C -core will create a virtual interrupt for Host Notify and assign it as -primary interrupt for the slave. - -Also, if device is marked as a wakeup source, I2C core will set up "wakeup" -interrupt for the device. If "wakeup" interrupt name is not present in the -binding, then primary interrupt will be used as wakeup interrupt. diff --git a/dts/Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml b/dts/Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml index b8319dcf3d..8676335e9e 100644 --- a/dts/Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml +++ b/dts/Bindings/i2c/nvidia,tegra186-bpmp-i2c.yaml @@ -21,8 +21,7 @@ description: | See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP binding. - This node represents an I2C controller. See ../i2c/i2c.txt for details - of the core I2C binding. + This node represents an I2C controller. properties: compatible: diff --git a/dts/Bindings/i2c/qcom,i2c-cci.yaml b/dts/Bindings/i2c/qcom,i2c-cci.yaml index 8386cfe215..f0eabff863 100644 --- a/dts/Bindings/i2c/qcom,i2c-cci.yaml +++ b/dts/Bindings/i2c/qcom,i2c-cci.yaml @@ -270,7 +270,7 @@ examples: port { ov7251_ep: endpoint { - data-lanes = <0 1>; + data-lanes = <0>; link-frequencies = /bits/ 64 <240000000 319200000>; remote-endpoint = <&csiphy3_ep>; }; diff --git a/dts/Bindings/i2c/renesas,rcar-i2c.yaml b/dts/Bindings/i2c/renesas,rcar-i2c.yaml index c4ace5585e..51b220da46 100644 --- a/dts/Bindings/i2c/renesas,rcar-i2c.yaml +++ b/dts/Bindings/i2c/renesas,rcar-i2c.yaml @@ -53,6 +53,7 @@ properties: - renesas,i2c-r8a779a0 # R-Car V3U - renesas,i2c-r8a779f0 # R-Car S4-8 - renesas,i2c-r8a779g0 # R-Car V4H + - renesas,i2c-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-i2c # R-Car Gen4 reg: diff --git a/dts/Bindings/i2c/st,nomadik-i2c.yaml b/dts/Bindings/i2c/st,nomadik-i2c.yaml index 16024415a4..44c54b162b 100644 --- a/dts/Bindings/i2c/st,nomadik-i2c.yaml +++ b/dts/Bindings/i2c/st,nomadik-i2c.yaml @@ -14,9 +14,6 @@ description: The Nomadik I2C host controller began its life in the ST maintainers: - Linus Walleij <linus.walleij@linaro.org> -allOf: - - $ref: /schemas/i2c/i2c-controller.yaml# - # Need a custom select here or 'arm,primecell' will match on lots of nodes select: properties: @@ -24,21 +21,23 @@ select: contains: enum: - st,nomadik-i2c + - mobileye,eyeq5-i2c required: - compatible properties: compatible: oneOf: - # The variant found in STn8815 - items: - const: st,nomadik-i2c - const: arm,primecell - # The variant found in DB8500 - items: - const: stericsson,db8500-i2c - const: st,nomadik-i2c - const: arm,primecell + - items: + - const: mobileye,eyeq5-i2c + - const: arm,primecell reg: maxItems: 1 @@ -55,7 +54,7 @@ properties: - items: - const: mclk - const: apb_pclk - # Clock name in DB8500 + # Clock name in DB8500 or EyeQ5 - items: - const: i2cclk - const: apb_pclk @@ -70,6 +69,16 @@ properties: minimum: 1 maximum: 400000 + mobileye,olb: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to OLB system controller node. + - description: Platform-wide controller ID (integer starting from zero). + description: + The phandle pointing to OLB system controller node, with the I2C + controller index. + required: - compatible - reg @@ -79,6 +88,20 @@ required: unevaluatedProperties: false +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + const: mobileye,eyeq5-i2c + then: + required: + - mobileye,olb + else: + properties: + mobileye,olb: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> @@ -111,5 +134,19 @@ examples: clocks = <&i2c0clk>, <&pclki2c0>; clock-names = "mclk", "apb_pclk"; }; + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + i2c@300000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0x300000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c_ser_clk>, <&i2c_clk>; + clock-names = "i2cclk", "apb_pclk"; + mobileye,olb = <&olb 0>; + }; ... diff --git a/dts/Bindings/i3c/aspeed,ast2600-i3c.yaml b/dts/Bindings/i3c/aspeed,ast2600-i3c.yaml index fcc3dbff9c..47be5d9a32 100644 --- a/dts/Bindings/i3c/aspeed,ast2600-i3c.yaml +++ b/dts/Bindings/i3c/aspeed,ast2600-i3c.yaml @@ -57,7 +57,7 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - i3c-master@2000 { + i3c@2000 { compatible = "aspeed,ast2600-i3c"; reg = <0x2000 0x1000>; #address-cells = <3>; diff --git a/dts/Bindings/i3c/cdns,i3c-master.yaml b/dts/Bindings/i3c/cdns,i3c-master.yaml index cc40d25358..cad6d53d0e 100644 --- a/dts/Bindings/i3c/cdns,i3c-master.yaml +++ b/dts/Bindings/i3c/cdns,i3c-master.yaml @@ -41,7 +41,7 @@ unevaluatedProperties: false examples: - | - i3c-master@d040000 { + i3c@d040000 { compatible = "cdns,i3c-master"; clocks = <&coreclock>, <&i3csysclock>; clock-names = "pclk", "sysclk"; diff --git a/dts/Bindings/i3c/i3c.yaml b/dts/Bindings/i3c/i3c.yaml index c816e295d5..113957ebe9 100644 --- a/dts/Bindings/i3c/i3c.yaml +++ b/dts/Bindings/i3c/i3c.yaml @@ -17,7 +17,7 @@ description: | properties: $nodename: - pattern: "^i3c-master@[0-9a-f]+$" + pattern: "^i3c@[0-9a-f]+$" "#address-cells": const: 3 @@ -71,7 +71,7 @@ patternProperties: description: | I2C child, should be named: <device-type>@<i2c-address> - All properties described in Documentation/devicetree/bindings/i2c/i2c.txt + All properties described in dtschema schemas/i2c/i2c-controller.yaml are valid here, except the reg property whose content is changed. properties: @@ -153,7 +153,7 @@ additionalProperties: true examples: - | - i3c-master@d040000 { + i3c@d040000 { compatible = "cdns,i3c-master"; clocks = <&coreclock>, <&i3csysclock>; clock-names = "pclk", "sysclk"; diff --git a/dts/Bindings/i3c/mipi-i3c-hci.yaml b/dts/Bindings/i3c/mipi-i3c-hci.yaml index 5dda8cb44c..39bb1a1784 100644 --- a/dts/Bindings/i3c/mipi-i3c-hci.yaml +++ b/dts/Bindings/i3c/mipi-i3c-hci.yaml @@ -43,7 +43,7 @@ unevaluatedProperties: false examples: - | - i3c-master@a0000000 { + i3c@a0000000 { compatible = "mipi-i3c-hci"; reg = <0xa0000000 0x2000>; interrupts = <89>; diff --git a/dts/Bindings/i3c/silvaco,i3c-master.yaml b/dts/Bindings/i3c/silvaco,i3c-master.yaml index 133855f11b..c56ff77677 100644 --- a/dts/Bindings/i3c/silvaco,i3c-master.yaml +++ b/dts/Bindings/i3c/silvaco,i3c-master.yaml @@ -48,7 +48,7 @@ unevaluatedProperties: false examples: - | - i3c-master@a0000000 { + i3c@a0000000 { compatible = "silvaco,i3c-master-v1"; clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>; clock-names = "pclk", "fast_clk", "slow_clk"; diff --git a/dts/Bindings/i3c/snps,dw-i3c-master.yaml b/dts/Bindings/i3c/snps,dw-i3c-master.yaml index 7a76fd3296..c0e805e531 100644 --- a/dts/Bindings/i3c/snps,dw-i3c-master.yaml +++ b/dts/Bindings/i3c/snps,dw-i3c-master.yaml @@ -35,7 +35,7 @@ unevaluatedProperties: false examples: - | - i3c-master@2000 { + i3c@2000 { compatible = "snps,dw-i3c-master-1.00a"; #address-cells = <3>; #size-cells = <0>; diff --git a/dts/Bindings/iio/adc/adc.yaml b/dts/Bindings/iio/adc/adc.yaml index 2616017297..36775f8f71 100644 --- a/dts/Bindings/iio/adc/adc.yaml +++ b/dts/Bindings/iio/adc/adc.yaml @@ -22,7 +22,6 @@ properties: maxItems: 1 label: - $ref: /schemas/types.yaml#/definitions/string description: Unique name to identify which channel this is. bipolar: diff --git a/dts/Bindings/iio/adc/adi,ad9467.yaml b/dts/Bindings/iio/adc/adi,ad9467.yaml index 7aa748d6b7..eecd5fbab6 100644 --- a/dts/Bindings/iio/adc/adi,ad9467.yaml +++ b/dts/Bindings/iio/adc/adi,ad9467.yaml @@ -44,6 +44,9 @@ properties: Pin that controls the powerdown mode of the device. maxItems: 1 + io-backends: + maxItems: 1 + reset-gpios: description: Reset pin for the device. @@ -68,6 +71,7 @@ examples: reg = <0>; clocks = <&adc_clk>; clock-names = "adc-clk"; + io-backends = <&iio_backend>; }; }; ... diff --git a/dts/Bindings/iio/adc/adi,axi-adc.yaml b/dts/Bindings/iio/adc/adi,axi-adc.yaml index 9996dd93f8..3d49d21ad3 100644 --- a/dts/Bindings/iio/adc/adi,axi-adc.yaml +++ b/dts/Bindings/iio/adc/adi,axi-adc.yaml @@ -39,12 +39,15 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: A reference to a the actual ADC to which this FPGA ADC interfaces to. + deprecated: true + + '#io-backend-cells': + const: 0 required: - compatible - dmas - reg - - adi,adc-dev additionalProperties: false @@ -55,7 +58,6 @@ examples: reg = <0x44a00000 0x10000>; dmas = <&rx_dma 0>; dma-names = "rx"; - - adi,adc-dev = <&spi_adc>; + #io-backend-cells = <0>; }; ... diff --git a/dts/Bindings/iio/adc/microchip,pac1934.yaml b/dts/Bindings/iio/adc/microchip,pac1934.yaml new file mode 100644 index 0000000000..47a11a9ac9 --- /dev/null +++ b/dts/Bindings/iio/adc/microchip,pac1934.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/microchip,pac1934.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PAC1934 Power Monitors with Accumulator + +maintainers: + - Marius Cristea <marius.cristea@microchip.com> + +description: | + This device is part of the Microchip family of Power Monitors with + Accumulator. + The datasheet for PAC1931, PAC1932, PAC1933 and PAC1934 can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/PAC1931-Family-Data-Sheet-DS20005850E.pdf + +properties: + compatible: + enum: + - microchip,pac1931 + - microchip,pac1932 + - microchip,pac1933 + - microchip,pac1934 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + interrupts: + maxItems: 1 + + slow-io-gpios: + description: + A GPIO used to trigger a change is sampling rate (lowering the chip power + consumption). If configured in SLOW mode, if this pin is forced high, + sampling rate is forced to eight samples/second. When it is forced low, + the sampling rate is 1024 samples/second unless a different sample rate + has been programmed. + +patternProperties: + "^channel@[1-4]+$": + type: object + $ref: adc.yaml + description: + Represents the external channels which are connected to the ADC. + + properties: + reg: + items: + minimum: 1 + maximum: 4 + + shunt-resistor-micro-ohms: + description: + Value in micro Ohms of the shunt resistor connected between + the SENSE+ and SENSE- inputs, across which the current is measured. + Value is needed to compute the scaling of the measured current. + + required: + - reg + - shunt-resistor-micro-ohms + + unevaluatedProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + power-monitor@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <24900000>; + label = "CPU"; + }; + + channel@2 { + reg = <0x2>; + shunt-resistor-micro-ohms = <49900000>; + label = "GPU"; + }; + + channel@3 { + reg = <0x3>; + shunt-resistor-micro-ohms = <75000000>; + label = "MEM"; + bipolar; + }; + + channel@4 { + reg = <0x4>; + shunt-resistor-micro-ohms = <100000000>; + label = "NET"; + bipolar; + }; + }; + }; + +... diff --git a/dts/Bindings/iio/adc/nxp,imx93-adc.yaml b/dts/Bindings/iio/adc/nxp,imx93-adc.yaml index dacc526dc6..dfc3f51291 100644 --- a/dts/Bindings/iio/adc/nxp,imx93-adc.yaml +++ b/dts/Bindings/iio/adc/nxp,imx93-adc.yaml @@ -31,7 +31,6 @@ properties: - description: normal conversion, include EOC (End of Conversion), ECH (End of Chain), JEOC (End of Injected Conversion) and JECH (End of injected Chain). - - description: Self-testing Interrupts. clocks: maxItems: 1 @@ -70,8 +69,7 @@ examples: reg = <0x44530000 0x10000>; interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_ADC1_GATE>; clock-names = "ipg"; vref-supply = <®_vref_1v8>; diff --git a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml index 40fa0710f1..c28db0d635 100644 --- a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml @@ -75,7 +75,6 @@ patternProperties: in the PMIC-specific files in include/dt-bindings/iio/. label: - $ref: /schemas/types.yaml#/definitions/string description: | ADC input of the platform as seen in the schematics. For thermistor inputs connected to generic AMUX or GPIO inputs diff --git a/dts/Bindings/iio/adc/richtek,rtq6056.yaml b/dts/Bindings/iio/adc/richtek,rtq6056.yaml index 88e008629e..af2c3a67f8 100644 --- a/dts/Bindings/iio/adc/richtek,rtq6056.yaml +++ b/dts/Bindings/iio/adc/richtek,rtq6056.yaml @@ -25,7 +25,14 @@ description: | properties: compatible: - const: richtek,rtq6056 + oneOf: + - enum: + - richtek,rtq6056 + - richtek,rtq6059 + - items: + - enum: + - richtek,rtq6053 + - const: richtek,rtq6056 reg: maxItems: 1 diff --git a/dts/Bindings/iio/adc/ti,ads1298.yaml b/dts/Bindings/iio/adc/ti,ads1298.yaml new file mode 100644 index 0000000000..bf5a43a81d --- /dev/null +++ b/dts/Bindings/iio/adc/ti,ads1298.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,ads1298.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments' ads1298 medical ADC chips + +description: | + Datasheet at: https://www.ti.com/product/ADS1298 + Bindings for this chip aren't complete. + +maintainers: + - Mike Looijmans <mike.looijmans@topic.nl> + +properties: + compatible: + enum: + - ti,ads1298 + + reg: + maxItems: 1 + + spi-cpha: true + + reset-gpios: + maxItems: 1 + + avdd-supply: + description: + Analog power supply, voltage between AVDD and AVSS. When providing a + symmetric +/- 2.5V, the regulator should report 5V. + + vref-supply: + description: + Optional reference voltage. If omitted, internal reference is used, + which is 2.4V when analog supply is below 4.4V, 4V otherwise. + + clocks: + description: Optional 2.048 MHz external source clock on CLK pin + maxItems: 1 + + interrupts: + description: Interrupt on DRDY pin, triggers on falling edge + maxItems: 1 + + label: true + +required: + - compatible + - reg + - avdd-supply + - interrupts + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@1 { + reg = <1>; + compatible = "ti,ads1298"; + label = "ads1298-1-ecg"; + avdd-supply = <®_iso_5v_a>; + clocks = <&clk_ads1298>; + interrupt-parent = <&gpio0>; + interrupts = <78 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <20000000>; + spi-cpha; + }; + }; +... diff --git a/dts/Bindings/iio/afe/voltage-divider.yaml b/dts/Bindings/iio/afe/voltage-divider.yaml index dddf97b505..4151f99b42 100644 --- a/dts/Bindings/iio/afe/voltage-divider.yaml +++ b/dts/Bindings/iio/afe/voltage-divider.yaml @@ -39,6 +39,17 @@ properties: description: | Channel node of a voltage io-channel. + '#io-channel-cells': + description: + In addition to consuming the measurement services of a voltage + output channel, the voltage divider can act as a provider of + measurement services to other devices. This is particularly + useful in scenarios wherein an ADC has an analog frontend, + such as a voltage divider, and then consuming its raw value + isn't interesting. In this case, the voltage before the divider + is desired. + const: 1 + output-ohms: description: Resistance Rout over which the output voltage is measured. See full-ohms. diff --git a/dts/Bindings/iio/amplifiers/adi,hmc425a.yaml b/dts/Bindings/iio/amplifiers/adi,hmc425a.yaml index 67de9d4e3a..3a470459b9 100644 --- a/dts/Bindings/iio/amplifiers/adi,hmc425a.yaml +++ b/dts/Bindings/iio/amplifiers/adi,hmc425a.yaml @@ -21,6 +21,8 @@ description: | HMC540S 1 dB LSB Silicon MMIC 4-Bit Digital Positive Control Attenuator, 0.1 - 8 GHz https://www.analog.com/media/en/technical-documentation/data-sheets/hmc540s.pdf + LTC6373 is a 3-Bit precision instrumentation amplifier with fully differential outputs + https://www.analog.com/media/en/technical-documentation/data-sheets/ltc6373.pdf properties: compatible: @@ -28,16 +30,55 @@ properties: - adi,adrf5740 - adi,hmc425a - adi,hmc540s + - adi,ltc6373 vcc-supply: true ctrl-gpios: description: - Must contain an array of 6 GPIO specifiers, referring to the GPIO pins - connected to the control pins V1-V6. - minItems: 6 + Must contain an array of GPIO specifiers, referring to the GPIO pins + connected to the control pins. + ADRF5740 - 4 GPIO connected to D2-D5 + HMC540S - 4 GPIO connected to V1-V4 + HMC425A - 6 GPIO connected to V1-V6 + LTC6373 - 3 GPIO connected to A0-A2 + minItems: 1 maxItems: 6 +allOf: + - if: + properties: + compatible: + contains: + const: adi,hmc425a + then: + properties: + ctrl-gpios: + minItems: 6 + maxItems: 6 + - if: + properties: + compatible: + contains: + anyOf: + - const: adi,adrf5740 + - const: adi,hmc540s + then: + properties: + ctrl-gpios: + minItems: 4 + maxItems: 4 + - if: + properties: + compatible: + contains: + const: adi,ltc6373 + then: + properties: + ctrl-gpios: + minItems: 3 + maxItems: 3 + required: - compatible - ctrl-gpios diff --git a/dts/Bindings/iio/frequency/adi,admfm2000.yaml b/dts/Bindings/iio/frequency/adi,admfm2000.yaml new file mode 100644 index 0000000000..2bcf4bbc12 --- /dev/null +++ b/dts/Bindings/iio/frequency/adi,admfm2000.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,admfm2000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADMFM2000 Dual Microwave Down Converter + +maintainers: + - Kim Seer Paller <kimseer.paller@analog.com> + +description: + Dual microwave down converter module with input RF and LO frequency ranges + from 0.5 to 32 GHz and an output IF frequency range from 0.1 to 8 GHz. + It consists of a LNA, mixer, IF filter, DSA, and IF amplifier for each down + conversion path. + +properties: + compatible: + enum: + - adi,admfm2000 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^channel@[0-1]$": + type: object + description: Represents a channel of the device. + + additionalProperties: false + + properties: + reg: + description: + The channel number. + minimum: 0 + maximum: 1 + + adi,mixer-mode: + description: + Enable mixer mode for the channel. It downconverts RF between 5 GHz + and 32 GHz to IF between 0.5 GHz and 8 GHz. If not present, the channel + is in direct IF mode which bypasses the mixer and downconverts RF + between 2 GHz and 8 GHz to IF between 0.5 GHz and 8 GHz. + type: boolean + + switch-gpios: + description: | + GPIOs to select the RF path for the channel. The same state of CTRL-A + and CTRL-B GPIOs is not permitted. + CTRL-A CTRL-B CH1 Status CH2 Status + 1 0 Direct IF mode Mixer mode + 0 1 Mixer mode Direct IF mode + + items: + - description: CTRL-A GPIO + - description: CTRL-B GPIO + + attenuation-gpios: + description: | + Choice of attenuation: + DSA-V4 DSA-V3 DSA-V2 DSA-V1 DSA-V0 + 1 1 1 1 1 0 dB + 1 1 1 1 0 -1 dB + 1 1 1 0 1 -2 dB + 1 1 0 1 1 -4 dB + 1 0 1 1 1 -8 dB + 0 1 1 1 1 -16 dB + 0 0 0 0 0 -31 dB + + items: + - description: DSA-V0 GPIO + - description: DSA-V1 GPIO + - description: DSA-V2 GPIO + - description: DSA-V3 GPIO + - description: DSA-V4 GPIO + + required: + - reg + - switch-gpios + - attenuation-gpios + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + converter { + compatible = "adi,admfm2000"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + switch-gpios = <&gpio 1 GPIO_ACTIVE_LOW>, + <&gpio 2 GPIO_ACTIVE_HIGH>; + + attenuation-gpios = <&gpio 17 GPIO_ACTIVE_LOW>, + <&gpio 22 GPIO_ACTIVE_LOW>, + <&gpio 23 GPIO_ACTIVE_LOW>, + <&gpio 24 GPIO_ACTIVE_LOW>, + <&gpio 25 GPIO_ACTIVE_LOW>; + }; + + channel@1 { + reg = <1>; + adi,mixer-mode; + switch-gpios = <&gpio 3 GPIO_ACTIVE_LOW>, + <&gpio 4 GPIO_ACTIVE_HIGH>; + + attenuation-gpios = <&gpio 0 GPIO_ACTIVE_LOW>, + <&gpio 5 GPIO_ACTIVE_LOW>, + <&gpio 6 GPIO_ACTIVE_LOW>, + <&gpio 16 GPIO_ACTIVE_LOW>, + <&gpio 26 GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/dts/Bindings/iio/gyroscope/bosch,bmg160.yaml b/dts/Bindings/iio/gyroscope/bosch,bmg160.yaml index 1414ba9977..3c6fe74af0 100644 --- a/dts/Bindings/iio/gyroscope/bosch,bmg160.yaml +++ b/dts/Bindings/iio/gyroscope/bosch,bmg160.yaml @@ -22,6 +22,9 @@ properties: vdd-supply: true vddio-supply: true + spi-max-frequency: + maximum: 10000000 + interrupts: minItems: 1 maxItems: 2 @@ -33,7 +36,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/humidity/ti,hdc2010.yaml b/dts/Bindings/iio/humidity/ti,hdc2010.yaml index 79e75a8675..e3eca89175 100644 --- a/dts/Bindings/iio/humidity/ti,hdc2010.yaml +++ b/dts/Bindings/iio/humidity/ti,hdc2010.yaml @@ -27,6 +27,9 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/iio/humidity/ti,hdc3020.yaml b/dts/Bindings/iio/humidity/ti,hdc3020.yaml index 7f6d0f9edc..8b5dedd1a5 100644 --- a/dts/Bindings/iio/humidity/ti,hdc3020.yaml +++ b/dts/Bindings/iio/humidity/ti,hdc3020.yaml @@ -43,6 +43,7 @@ additionalProperties: false examples: - | + #include <dt-bindings/interrupt-controller/irq.h> i2c { #address-cells = <1>; #size-cells = <0>; @@ -51,5 +52,7 @@ examples: compatible = "ti,hdc3021", "ti,hdc3020"; reg = <0x47>; vdd-supply = <&vcc_3v3>; + interrupt-parent = <&gpio3>; + interrupts = <23 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/dts/Bindings/iio/imu/st,lsm6dsx.yaml b/dts/Bindings/iio/imu/st,lsm6dsx.yaml index 28b667a9cb..c48a96d17f 100644 --- a/dts/Bindings/iio/imu/st,lsm6dsx.yaml +++ b/dts/Bindings/iio/imu/st,lsm6dsx.yaml @@ -35,7 +35,9 @@ properties: - st,lsm6dsv - st,lsm6dso16is - items: - - const: st,asm330lhhx + - enum: + - st,asm330lhhx + - st,asm330lhhxg1 - const: st,lsm6dsr - items: - const: st,lsm6dstx diff --git a/dts/Bindings/iio/light/ams,as73211.yaml b/dts/Bindings/iio/light/ams,as73211.yaml index 0e8cd02759..062a038aa0 100644 --- a/dts/Bindings/iio/light/ams,as73211.yaml +++ b/dts/Bindings/iio/light/ams,as73211.yaml @@ -4,19 +4,22 @@ $id: http://devicetree.org/schemas/iio/light/ams,as73211.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: AMS AS73211 JENCOLOR(R) Digital XYZ Sensor +title: AMS AS73211 JENCOLOR(R) Digital XYZ Sensor and AMS AS7331 UV Sensor maintainers: - Christian Eggers <ceggers@arri.de> description: | - XYZ True Color Sensor with I2C Interface + AMS AS73211 XYZ True Color Sensor with I2C Interface https://ams.com/documents/20143/36005/AS73211_DS000556_3-01.pdf/a65474c0-b302-c2fd-e30a-c98df87616df + AMS AS7331 UVA, UVB and UVC Sensor with I2C Interface + https://ams.com/documents/20143/9106314/AS7331_DS001047_4-00.pdf properties: compatible: enum: - ams,as73211 + - ams,as7331 reg: description: diff --git a/dts/Bindings/iio/light/vishay,veml6075.yaml b/dts/Bindings/iio/light/vishay,veml6075.yaml index abee04cd12..91c318746b 100644 --- a/dts/Bindings/iio/light/vishay,veml6075.yaml +++ b/dts/Bindings/iio/light/vishay,veml6075.yaml @@ -21,6 +21,7 @@ properties: required: - compatible - reg + - vdd-supply additionalProperties: false diff --git a/dts/Bindings/iio/magnetometer/voltafield,af8133j.yaml b/dts/Bindings/iio/magnetometer/voltafield,af8133j.yaml new file mode 100644 index 0000000000..b6ab01a691 --- /dev/null +++ b/dts/Bindings/iio/magnetometer/voltafield,af8133j.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/voltafield,af8133j.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Voltafield AF8133J magnetometer sensor + +maintainers: + - OndÅ™ej Jirman <megi@xff.cz> + +properties: + compatible: + const: voltafield,af8133j + + reg: + maxItems: 1 + + reset-gpios: + description: + A signal for active low reset input of the sensor. (optional; if not + used, software reset over I2C will be used instead) + + avdd-supply: + description: + A regulator that provides AVDD power (Working power, usually 3.3V) to + the sensor. + + dvdd-supply: + description: + A regulator that provides DVDD power (Digital IO power, 1.8V - AVDD) + to the sensor. + + mount-matrix: + description: An optional 3x3 mounting rotation matrix. + +required: + - compatible + - reg + - avdd-supply + - dvdd-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@1c { + compatible = "voltafield,af8133j"; + reg = <0x1c>; + avdd-supply = <®_dldo1>; + dvdd-supply = <®_dldo1>; + reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/dts/Bindings/iio/pressure/honeywell,hsc030pa.yaml b/dts/Bindings/iio/pressure/honeywell,hsc030pa.yaml index 65a24ed67b..89977b9f01 100644 --- a/dts/Bindings/iio/pressure/honeywell,hsc030pa.yaml +++ b/dts/Bindings/iio/pressure/honeywell,hsc030pa.yaml @@ -99,6 +99,9 @@ required: - honeywell,transfer-function - honeywell,pressure-triplet +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml + additionalProperties: false dependentSchemas: diff --git a/dts/Bindings/iio/pressure/honeywell,mprls0025pa.yaml b/dts/Bindings/iio/pressure/honeywell,mprls0025pa.yaml index d9e903fbfd..6994b30015 100644 --- a/dts/Bindings/iio/pressure/honeywell,mprls0025pa.yaml +++ b/dts/Bindings/iio/pressure/honeywell,mprls0025pa.yaml @@ -8,25 +8,28 @@ title: Honeywell mprls0025pa pressure sensor maintainers: - Andreas Klinger <ak@it-klinger.de> + - Petre Rodan <petre.rodan@subdimension.ro> description: | Honeywell pressure sensor of model mprls0025pa. - This sensor has an I2C and SPI interface. Only the I2C interface is - implemented. + This sensor has an I2C and SPI interface. There are many models with different pressure ranges available. The vendor calls them "mpr series". All of them have the identical programming model and differ in the pressure range, unit and transfer function. - To support different models one need to specify the pressure range as well as - the transfer function. Pressure range needs to be converted from its unit to - pascal. + To support different models one need to specify its pressure triplet as well + as the transfer function. + + For custom silicon chips not covered by the Honeywell MPR series datasheet, + the pressure values can be specified manually via honeywell,pmin-pascal and + honeywell,pmax-pascal. + The minimal range value stands for the minimum pressure and the maximum value + also for the maximum pressure with linear relation inside the range. The transfer function defines the ranges of numerical values delivered by the - sensor. The minimal range value stands for the minimum pressure and the - maximum value also for the maximum pressure with linear relation inside the - range. + sensor. Specifications about the devices can be found at: https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/ @@ -42,6 +45,10 @@ properties: maxItems: 1 interrupts: + description: + Optional interrupt for indicating End-of-conversion. + If not present, the driver loops for a while until the received status + byte indicates correct measurement. maxItems: 1 reset-gpios: @@ -50,14 +57,6 @@ properties: If not present the device is not reset during the probe. maxItems: 1 - honeywell,pmin-pascal: - description: - Minimum pressure value the sensor can measure in pascal. - - honeywell,pmax-pascal: - description: - Maximum pressure value the sensor can measure in pascal. - honeywell,transfer-function: description: | Transfer function which defines the range of valid values delivered by the @@ -65,19 +64,57 @@ properties: 1 - A, 10% to 90% of 2^24 (1677722 .. 15099494) 2 - B, 2.5% to 22.5% of 2^24 (419430 .. 3774874) 3 - C, 20% to 80% of 2^24 (3355443 .. 13421773) + enum: [1, 2, 3] $ref: /schemas/types.yaml#/definitions/uint32 + honeywell,pressure-triplet: + description: | + Case-sensitive five character string that defines pressure range, unit + and type as part of the device nomenclature. In the unlikely case of a + custom chip, unset and provide pmin-pascal and pmax-pascal instead. + enum: [0001BA, 01.6BA, 02.5BA, 0060MG, 0100MG, 0160MG, 0250MG, 0400MG, + 0600MG, 0001BG, 01.6BG, 02.5BG, 0100KA, 0160KA, 0250KA, 0006KG, + 0010KG, 0016KG, 0025KG, 0040KG, 0060KG, 0100KG, 0160KG, 0250KG, + 0015PA, 0025PA, 0030PA, 0001PG, 0005PG, 0015PG, 0030PG, 0300YG] + $ref: /schemas/types.yaml#/definitions/string + + honeywell,pmin-pascal: + description: + Minimum pressure value the sensor can measure in pascal. + + honeywell,pmax-pascal: + description: + Maximum pressure value the sensor can measure in pascal. + + spi-max-frequency: + maximum: 800000 + vdd-supply: description: provide VDD power to the sensor. required: - compatible - reg - - honeywell,pmin-pascal - - honeywell,pmax-pascal - honeywell,transfer-function - vdd-supply +oneOf: + - required: + - honeywell,pressure-triplet + - required: + - honeywell,pmin-pascal + - honeywell,pmax-pascal + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml + - if: + required: + - honeywell,pressure-triplet + then: + properties: + honeywell,pmin-pascal: false + honeywell,pmax-pascal: false + additionalProperties: false examples: @@ -93,10 +130,29 @@ examples: reg = <0x18>; reset-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; interrupt-parent = <&gpio3>; - interrupts = <21 IRQ_TYPE_EDGE_FALLING>; - honeywell,pmin-pascal = <0>; - honeywell,pmax-pascal = <172369>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + honeywell,pressure-triplet = "0025PA"; + honeywell,transfer-function = <1>; + vdd-supply = <&vcc_3v3>; + }; + }; + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + pressure@0 { + compatible = "honeywell,mprls0025pa"; + reg = <0>; + spi-max-frequency = <800000>; + reset-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = <30 IRQ_TYPE_EDGE_RISING>; + + honeywell,pressure-triplet = "0015PA"; honeywell,transfer-function = <1>; vdd-supply = <&vcc_3v3>; }; }; +... diff --git a/dts/Bindings/iio/temperature/ti,tmp117.yaml b/dts/Bindings/iio/temperature/ti,tmp117.yaml index 8c6d7735e8..58aa154277 100644 --- a/dts/Bindings/iio/temperature/ti,tmp117.yaml +++ b/dts/Bindings/iio/temperature/ti,tmp117.yaml @@ -24,9 +24,16 @@ properties: reg: maxItems: 1 + vcc-supply: + description: provide VCC power to the sensor. + + label: + description: Unique name to identify which device this is. + required: - compatible - reg + - vcc-supply additionalProperties: false @@ -39,5 +46,6 @@ examples: tmp117@48 { compatible = "ti,tmp117"; reg = <0x48>; + vcc-supply = <&pmic_reg_3v3>; }; }; diff --git a/dts/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/dts/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index 5efceb3138..c384bf0bb2 100644 --- a/dts/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/dts/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -49,7 +49,6 @@ patternProperties: $ref: input.yaml# properties: label: - $ref: /schemas/types.yaml#/definitions/string description: Descriptive name of the key linux,code: true diff --git a/dts/Bindings/input/atmel,captouch.txt b/dts/Bindings/input/atmel,captouch.txt deleted file mode 100644 index fe9ee5c53b..0000000000 --- a/dts/Bindings/input/atmel,captouch.txt +++ /dev/null @@ -1,36 +0,0 @@ -Device tree bindings for Atmel capacitive touch device, typically -an Atmel touch sensor connected to AtmegaXX MCU running firmware -based on Qtouch library. - -The node for this device must be a child of a I2C controller node, as the -device communicates via I2C. - -Required properties: - - compatible: Must be "atmel,captouch". - reg: The I2C slave address of the device. - interrupts: Property describing the interrupt line the device - is connected to. The device only has one interrupt - source. - linux,keycodes: Specifies an array of numeric keycode values to - be used for reporting button presses. The array can - contain up to 8 entries. - -Optional properties: - - autorepeat: Enables the Linux input system's autorepeat - feature on the input device. - -Example: - - atmel-captouch@51 { - compatible = "atmel,captouch"; - reg = <0x51>; - interrupt-parent = <&tlmm>; - interrupts = <67 IRQ_TYPE_EDGE_FALLING>; - linux,keycodes = <BTN_0>, <BTN_1>, - <BTN_2>, <BTN_3>, - <BTN_4>, <BTN_5>, - <BTN_6>, <BTN_7>; - autorepeat; - }; diff --git a/dts/Bindings/input/atmel,captouch.yaml b/dts/Bindings/input/atmel,captouch.yaml new file mode 100644 index 0000000000..f7477091d5 --- /dev/null +++ b/dts/Bindings/input/atmel,captouch.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/atmel,captouch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel capacitive touch device + +maintainers: + - Dharma balasubiramani <dharma.b@microchip.com> + +description: + Atmel capacitive touch device, typically an Atmel touch sensor connected to + AtmegaXX MCU running firmware based on Qtouch library. + +allOf: + - $ref: input.yaml# + +properties: + compatible: + const: atmel,captouch + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + linux,keycodes: + minItems: 1 + maxItems: 8 + +required: + - compatible + - reg + - interrupts + - linux,keycodes + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/input/linux-event-codes.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + touch@51 { + compatible = "atmel,captouch"; + reg = <0x51>; + interrupt-parent = <&tlmm>; + interrupts = <67 IRQ_TYPE_EDGE_FALLING>; + linux,keycodes = <BTN_0>, <BTN_1>, + <BTN_2>, <BTN_3>, + <BTN_4>, <BTN_5>, + <BTN_6>, <BTN_7>; + autorepeat; + }; + }; diff --git a/dts/Bindings/input/da9062-onkey.txt b/dts/Bindings/input/da9062-onkey.txt deleted file mode 100644 index e5eef59a93..0000000000 --- a/dts/Bindings/input/da9062-onkey.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Dialog DA9061/62/63 OnKey Module - -This module is part of the DA9061/DA9062/DA9063. For more details about entire -DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt -For DA9063 see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml - -This module provides the KEY_POWER event. - -Required properties: - -- compatible: should be one of the following valid compatible string lines: - "dlg,da9061-onkey", "dlg,da9062-onkey" - "dlg,da9062-onkey" - "dlg,da9063-onkey" - -Optional properties: - -- dlg,disable-key-power : Disable power-down using a long key-press. If this - entry exists the OnKey driver will remove support for the KEY_POWER key - press when triggered using a long press of the OnKey. - -Example: DA9063 - - pmic0: da9063@58 { - onkey { - compatible = "dlg,da9063-onkey"; - dlg,disable-key-power; - }; - }; - -Example: DA9062 - - pmic0: da9062@58 { - onkey { - compatible = "dlg,da9062-onkey"; - dlg,disable-key-power; - }; - }; - -Example: DA9061 using a fall-back compatible for the DA9062 onkey driver - - pmic0: da9061@58 { - onkey { - compatible = "dlg,da9061-onkey", "dlg,da9062-onkey"; - dlg,disable-key-power; - }; - }; diff --git a/dts/Bindings/input/dlg,da9062-onkey.yaml b/dts/Bindings/input/dlg,da9062-onkey.yaml new file mode 100644 index 0000000000..1480d95421 --- /dev/null +++ b/dts/Bindings/input/dlg,da9062-onkey.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/dlg,da9062-onkey.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dialog DA9061/62/63 OnKey Module + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + This module is part of the DA9061/DA9062/DA9063. For more details about entire + DA906{1,2,3} chips see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml + + This module provides the KEY_POWER event. + +properties: + compatible: + oneOf: + - enum: + - dlg,da9062-onkey + - dlg,da9063-onkey + - items: + - const: dlg,da9061-onkey + - const: dlg,da9062-onkey + + dlg,disable-key-power: + type: boolean + description: + Disable power-down using a long key-press. If this entry exists + the OnKey driver will remove support for the KEY_POWER key press + when triggered using a long press of the OnKey. + +required: + - compatible + +additionalProperties: false diff --git a/dts/Bindings/input/samsung,s3c6410-keypad.yaml b/dts/Bindings/input/samsung,s3c6410-keypad.yaml new file mode 100644 index 0000000000..a53569aa0e --- /dev/null +++ b/dts/Bindings/input/samsung,s3c6410-keypad.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/samsung,s3c6410-keypad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series Keypad Controller + +description: + Samsung SoC Keypad controller is used to interface a SoC with a matrix-type + keypad device. The keypad controller supports multiple row and column lines. + A key can be placed at each intersection of a unique row and a unique column. + The keypad controller can sense a key-press and key-release and report the + event using a interrupt to the cpu. + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +properties: + compatible: + enum: + - samsung,s3c6410-keypad + - samsung,s5pv210-keypad + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: keypad + + interrupts: + maxItems: 1 + + wakeup-source: true + + linux,input-no-autorepeat: + type: boolean + description: + Do no enable autorepeat feature. + + linux,input-wakeup: + type: boolean + deprecated: true + + samsung,keypad-num-columns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of column lines connected to the keypad controller. + + samsung,keypad-num-rows: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of row lines connected to the keypad controller. + +patternProperties: + '^key-[0-9a-z]+$': + type: object + $ref: input.yaml# + additionalProperties: false + description: + Each key connected to the keypad controller is represented as a child + node to the keypad controller device node. + + properties: + keypad,column: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The column number to which the key is connected. + + keypad,row: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The row number to which the key is connected. + + linux,code: true + + required: + - keypad,column + - keypad,row + - linux,code + +required: + - compatible + - reg + - interrupts + - samsung,keypad-num-columns + - samsung,keypad-num-rows + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos4.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + keypad@100a0000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0x100a0000 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_KEYIF>; + clock-names = "keypad"; + + samsung,keypad-num-rows = <2>; + samsung,keypad-num-columns = <8>; + linux,input-no-autorepeat; + wakeup-source; + + key-1 { + keypad,row = <0>; + keypad,column = <3>; + linux,code = <2>; + }; + + key-2 { + keypad,row = <0>; + keypad,column = <4>; + linux,code = <3>; + }; + }; diff --git a/dts/Bindings/input/samsung-keypad.txt b/dts/Bindings/input/samsung-keypad.txt deleted file mode 100644 index 4c5c0a8258..0000000000 --- a/dts/Bindings/input/samsung-keypad.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Samsung's Keypad Controller device tree bindings - -Samsung's Keypad controller is used to interface a SoC with a matrix-type -keypad device. The keypad controller supports multiple row and column lines. -A key can be placed at each intersection of a unique row and a unique column. -The keypad controller can sense a key-press and key-release and report the -event using a interrupt to the cpu. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad - controller. - - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad - controller. - -- reg: physical base address of the controller and length of memory mapped - region. - -- interrupts: The interrupt number to the cpu. - -Required Board Specific Properties: -- samsung,keypad-num-rows: Number of row lines connected to the keypad - controller. - -- samsung,keypad-num-columns: Number of column lines connected to the - keypad controller. - -- Keys represented as child nodes: Each key connected to the keypad - controller is represented as a child node to the keypad controller - device node and should include the following properties. - - keypad,row: the row number to which the key is connected. - - keypad,column: the column number to which the key is connected. - - linux,code: the key-code to be reported when the key is pressed - and released. - -- pinctrl-0: Should specify pin control groups used for this controller. -- pinctrl-names: Should contain only one value - "default". - -Optional Properties: -- wakeup-source: use any event on keypad as wakeup event. - (Legacy property supported: "linux,input-wakeup") - -Optional Properties specific to linux: -- linux,keypad-no-autorepeat: do no enable autorepeat feature. - - -Example: - keypad@100a0000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0x100A0000 0x100>; - interrupts = <173>; - samsung,keypad-num-rows = <2>; - samsung,keypad-num-columns = <8>; - linux,input-no-autorepeat; - wakeup-source; - - pinctrl-names = "default"; - pinctrl-0 = <&keypad_rows &keypad_columns>; - - key_1 { - keypad,row = <0>; - keypad,column = <3>; - linux,code = <2>; - }; - - key_2 { - keypad,row = <0>; - keypad,column = <4>; - linux,code = <3>; - }; - - key_3 { - keypad,row = <0>; - keypad,column = <5>; - linux,code = <4>; - }; - }; diff --git a/dts/Bindings/input/touchscreen/fsl,imx6ul-tsc.yaml b/dts/Bindings/input/touchscreen/fsl,imx6ul-tsc.yaml new file mode 100644 index 0000000000..678756ad0f --- /dev/null +++ b/dts/Bindings/input/touchscreen/fsl,imx6ul-tsc.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/fsl,imx6ul-tsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6UL Touch Controller + +maintainers: + - Haibo Chen <haibo.chen@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + +properties: + compatible: + const: fsl,imx6ul-tsc + + reg: + items: + - description: touch controller address + - description: ADC2 address + + interrupts: + items: + - description: touch controller address + - description: ADC2 address + + clocks: + maxItems: 2 + + clock-names: + items: + - const: tsc + - const: adc + + xnur-gpios: + maxItems: 1 + description: + The X- gpio this controller connect to. This xnur-gpio returns to + low once the finger leave the touch screen (The last touch event + the touch controller capture). + + measure-delay-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The value of measure delay time. Before X-axis or Y-axis measurement, + the screen need some time before even potential distribution ready. + default: 0xffff + minimum: 0 + maximum: 0xffffff + + pre-charge-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The touch screen need some time to precharge. + default: 0xfff + minimum: 0 + maximum: 0xffffffff + + touchscreen-average-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of data samples which are averaged for each read. + enum: [ 1, 4, 8, 16, 32 ] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - xnur-gpios + +allOf: + - $ref: touchscreen.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/imx6ul-clock.h> + #include <dt-bindings/gpio/gpio.h> + touchscreen@2040000 { + compatible = "fsl,imx6ul-tsc"; + reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_ADC2>; + clock-names = "tsc", "adc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xfff>; + pre-charge-time = <0xffff>; + touchscreen-average-samples = <32>; + }; diff --git a/dts/Bindings/input/touchscreen/goodix,gt9916.yaml b/dts/Bindings/input/touchscreen/goodix,gt9916.yaml new file mode 100644 index 0000000000..d90f045ac0 --- /dev/null +++ b/dts/Bindings/input/touchscreen/goodix,gt9916.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/goodix,gt9916.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Goodix Berlin series touchscreen controller + +description: The Goodix Berlin series of touchscreen controllers + be connected to either I2C or SPI buses. + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: touchscreen.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - goodix,gt9916 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + avdd-supply: + description: Analog power supply regulator on AVDD pin + + vddio-supply: + description: power supply regulator on VDDIO pin + + spi-max-frequency: true + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-swapped-x-y: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - avdd-supply + - touchscreen-size-x + - touchscreen-size-y + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + touchscreen@5d { + compatible = "goodix,gt9916"; + reg = <0x5d>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + avdd-supply = <&ts_avdd>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <768>; + }; + }; + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + cs-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + avdd-supply = <&ts_avdd>; + spi-max-frequency = <1000000>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <768>; + }; + }; + +... diff --git a/dts/Bindings/input/touchscreen/goodix.yaml b/dts/Bindings/input/touchscreen/goodix.yaml index 3d016b87c8..2a2d86cfd1 100644 --- a/dts/Bindings/input/touchscreen/goodix.yaml +++ b/dts/Bindings/input/touchscreen/goodix.yaml @@ -37,8 +37,9 @@ properties: maxItems: 1 irq-gpios: - description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin - as output to reset the device. + description: GPIO pin used for IRQ input. Additionally, this line is + sampled by the device on reset deassertion to select the I2C client + address, thus it can be driven by the host during the reset sequence. maxItems: 1 reset-gpios: diff --git a/dts/Bindings/input/touchscreen/imagis,ist3038c.yaml b/dts/Bindings/input/touchscreen/imagis,ist3038c.yaml index 0d6b033fd5..77ba280b3b 100644 --- a/dts/Bindings/input/touchscreen/imagis,ist3038c.yaml +++ b/dts/Bindings/input/touchscreen/imagis,ist3038c.yaml @@ -9,15 +9,14 @@ title: Imagis IST30XXC family touchscreen controller maintainers: - Markuss Broks <markuss.broks@gmail.com> -allOf: - - $ref: touchscreen.yaml# - properties: $nodename: pattern: "^touchscreen@[0-9a-f]+$" compatible: enum: + - imagis,ist3032c + - imagis,ist3038b - imagis,ist3038c reg: @@ -32,6 +31,10 @@ properties: vddio-supply: description: Power supply regulator for the I2C bus + linux,keycodes: + description: Keycodes for the touch keys + maxItems: 5 + touchscreen-size-x: true touchscreen-size-y: true touchscreen-fuzz-x: true @@ -42,6 +45,18 @@ properties: additionalProperties: false +allOf: + - $ref: touchscreen.yaml# + - if: + not: + properties: + compatible: + contains: + const: imagis,ist3032c + then: + properties: + linux,keycodes: false + required: - compatible - reg diff --git a/dts/Bindings/input/touchscreen/imx6ul_tsc.txt b/dts/Bindings/input/touchscreen/imx6ul_tsc.txt deleted file mode 100644 index 1649150044..0000000000 --- a/dts/Bindings/input/touchscreen/imx6ul_tsc.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Freescale i.MX6UL Touch Controller - -Required properties: -- compatible: must be "fsl,imx6ul-tsc". -- reg: this touch controller address and the ADC2 address. -- interrupts: the interrupt of this touch controller and ADC2. -- clocks: the root clock of touch controller and ADC2. -- clock-names; must be "tsc" and "adc". -- xnur-gpio: the X- gpio this controller connect to. - This xnur-gpio returns to low once the finger leave the touch screen (The - last touch event the touch controller capture). - -Optional properties: -- measure-delay-time: the value of measure delay time. - Before X-axis or Y-axis measurement, the screen need some time before - even potential distribution ready. - This value depends on the touch screen. -- pre-charge-time: the touch screen need some time to precharge. - This value depends on the touch screen. -- touchscreen-average-samples: Number of data samples which are averaged for - each read. Valid values are 1, 4, 8, 16 and 32. - -Example: - tsc: tsc@2040000 { - compatible = "fsl,imx6ul-tsc"; - reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_IPG>, - <&clks IMX6UL_CLK_ADC2>; - clock-names = "tsc", "adc"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xfff>; - pre-charge-time = <0xffff>; - touchscreen-average-samples = <32>; - }; diff --git a/dts/Bindings/input/touchscreen/melfas,mms114.yaml b/dts/Bindings/input/touchscreen/melfas,mms114.yaml index 07f9dd6b1c..90ebd4f835 100644 --- a/dts/Bindings/input/touchscreen/melfas,mms114.yaml +++ b/dts/Bindings/input/touchscreen/melfas,mms114.yaml @@ -17,13 +17,17 @@ properties: pattern: "^touchscreen(@.*)?$" compatible: - items: + oneOf: - enum: - melfas,mms114 - melfas,mms134s - melfas,mms136 - melfas,mms152 - melfas,mms345l + - items: + - enum: + - melfas,mms252 + - const: melfas,mms114 reg: description: I2C address diff --git a/dts/Bindings/input/touchscreen/silead,gsl1680.yaml b/dts/Bindings/input/touchscreen/silead,gsl1680.yaml index 95b554be25..5381a96f49 100644 --- a/dts/Bindings/input/touchscreen/silead,gsl1680.yaml +++ b/dts/Bindings/input/touchscreen/silead,gsl1680.yaml @@ -31,7 +31,7 @@ properties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: > File basename for board specific firmware diff --git a/dts/Bindings/interconnect/qcom,rpm.yaml b/dts/Bindings/interconnect/qcom,rpm.yaml index 08c1c6b9d7..5aaa92a7ce 100644 --- a/dts/Bindings/interconnect/qcom,rpm.yaml +++ b/dts/Bindings/interconnect/qcom,rpm.yaml @@ -23,6 +23,9 @@ properties: compatible: enum: + - qcom,msm8909-bimc + - qcom,msm8909-pcnoc + - qcom,msm8909-snoc - qcom,msm8916-bimc - qcom,msm8916-pcnoc - qcom,msm8916-snoc diff --git a/dts/Bindings/interconnect/qcom,rpmh.yaml b/dts/Bindings/interconnect/qcom,rpmh.yaml index 74ab080249..9318b845ec 100644 --- a/dts/Bindings/interconnect/qcom,rpmh.yaml +++ b/dts/Bindings/interconnect/qcom,rpmh.yaml @@ -8,7 +8,7 @@ title: Qualcomm RPMh Network-On-Chip Interconnect maintainers: - Georgi Djakov <georgi.djakov@linaro.org> - - Odelu Kukatla <okukatla@codeaurora.org> + - Odelu Kukatla <quic_okukatla@quicinc.com> description: | RPMh interconnect providers support system bandwidth requirements through diff --git a/dts/Bindings/interconnect/qcom,sm7150-rpmh.yaml b/dts/Bindings/interconnect/qcom,sm7150-rpmh.yaml new file mode 100644 index 0000000000..b565d1a382 --- /dev/null +++ b/dts/Bindings/interconnect/qcom,sm7150-rpmh.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm7150-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SM7150 + +maintainers: + - Danila Tikhonov <danila@jiaxyga.com> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sm7150-rpmh.h + +allOf: + - $ref: qcom,rpmh-common.yaml# + +properties: + compatible: + enum: + - qcom,sm7150-aggre1-noc + - qcom,sm7150-aggre2-noc + - qcom,sm7150-compute-noc + - qcom,sm7150-config-noc + - qcom,sm7150-dc-noc + - qcom,sm7150-gem-noc + - qcom,sm7150-mc-virt + - qcom,sm7150-mmss-noc + - qcom,sm7150-system-noc + + reg: + maxItems: 1 + +# Child node's properties +patternProperties: + '^interconnect-[0-9]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + allOf: + - $ref: qcom,rpmh-common.yaml# + + properties: + compatible: + enum: + - qcom,sm7150-camnoc-virt + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mc_virt: interconnect@1380000 { + compatible = "qcom,sm7150-mc-virt"; + reg = <0x01380000 0x40000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm7150-system-noc"; + reg = <0x01620000 0x40000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + + camnoc_virt: interconnect-0 { + compatible = "qcom,sm7150-camnoc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; diff --git a/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml index 3d06db98e9..a937447637 100644 --- a/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml +++ b/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml @@ -36,6 +36,7 @@ properties: - amlogic,meson-a1-gpio-intc - amlogic,meson-s4-gpio-intc - amlogic,c3-gpio-intc + - amlogic,t7-gpio-intc - const: amlogic,meson-gpio-intc reg: diff --git a/dts/Bindings/interrupt-controller/atmel,aic.txt b/dts/Bindings/interrupt-controller/atmel,aic.txt deleted file mode 100644 index 7079d44bf3..0000000000 --- a/dts/Bindings/interrupt-controller/atmel,aic.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Advanced Interrupt Controller (AIC) - -Required properties: -- compatible: Should be: - - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2", - "sama5d3" or "sama5d4" - - "microchip,<chip>-aic" where <chip> can be "sam9x60" - -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. It should be 3. - The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet). - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - Default flag for internal sources should be set to 4 (active high). - The third cell is used to specify the irq priority from 0 (lowest) to 7 - (highest). -- reg: Should contain AIC registers location and length -- atmel,external-irqs: u32 array of external irqs. - -Examples: - /* - * AIC - */ - aic: interrupt-controller@fffff000 { - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xfffff000 0x200>; - }; - - /* - * An interrupt generating device that is wired to an AIC. - */ - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21 4 5>; - }; diff --git a/dts/Bindings/interrupt-controller/atmel,aic.yaml b/dts/Bindings/interrupt-controller/atmel,aic.yaml new file mode 100644 index 0000000000..d4658fe386 --- /dev/null +++ b/dts/Bindings/interrupt-controller/atmel,aic.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Advanced Interrupt Controller (AIC) + +maintainers: + - Nicolas Ferre <nicolas.ferre@microchip.com> + - Dharma balasubiramani <dharma.b@microchip.com> + +description: + The Advanced Interrupt Controller (AIC) is an 8-level priority, individually + maskable, vectored interrupt controller providing handling of up to one + hundred and twenty-eight interrupt sources. + +properties: + compatible: + enum: + - atmel,at91rm9200-aic + - atmel,sama5d2-aic + - atmel,sama5d3-aic + - atmel,sama5d4-aic + - microchip,sam9x60-aic + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: | + The 1st cell is the IRQ number (Peripheral IDentifier on datasheet). + The 2nd cell specifies flags: + bits[3:0] trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. + Valid combinations: 1, 2, 3, 4, 8. + Default for internal sources: 4 (active high). + The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest). + + interrupts: + maxItems: 1 + + atmel,external-irqs: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: u32 array of external irqs. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - if: + properties: + compatible: + contains: + const: atmel,at91rm9200-aic + then: + properties: + atmel,external-irqs: + minItems: 1 + maxItems: 7 + else: + properties: + atmel,external-irqs: + minItems: 1 + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - atmel,external-irqs + +unevaluatedProperties: false + +examples: + - | + interrupt-controller@fffff000 { + compatible = "atmel,at91rm9200-aic"; + reg = <0xfffff000 0x200>; + interrupt-controller; + #interrupt-cells = <3>; + atmel,external-irqs = <31>; + }; +... diff --git a/dts/Bindings/interrupt-controller/fsl,intmux.yaml b/dts/Bindings/interrupt-controller/fsl,intmux.yaml index 985bfa4f6f..78baa0a571 100644 --- a/dts/Bindings/interrupt-controller/fsl,intmux.yaml +++ b/dts/Bindings/interrupt-controller/fsl,intmux.yaml @@ -37,6 +37,9 @@ properties: clock-names: const: ipg + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml b/dts/Bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml new file mode 100644 index 0000000000..e1a379c052 --- /dev/null +++ b/dts/Bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mt6577-sysirq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek sysirq + +description: + MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI + interrupt. + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +properties: + compatible: + oneOf: + - const: mediatek,mt6577-sysirq + - items: + - enum: + - mediatek,mt2701-sysirq + - mediatek,mt2712-sysirq + - mediatek,mt6580-sysirq + - mediatek,mt6582-sysirq + - mediatek,mt6589-sysirq + - mediatek,mt6592-sysirq + - mediatek,mt6755-sysirq + - mediatek,mt6765-sysirq + - mediatek,mt6779-sysirq + - mediatek,mt6795-sysirq + - mediatek,mt6797-sysirq + - mediatek,mt7622-sysirq + - mediatek,mt7623-sysirq + - mediatek,mt7629-sysirq + - mediatek,mt8127-sysirq + - mediatek,mt8135-sysirq + - mediatek,mt8173-sysirq + - mediatek,mt8183-sysirq + - mediatek,mt8365-sysirq + - mediatek,mt8516-sysirq + - const: mediatek,mt6577-sysirq + + reg: + minItems: 1 + maxItems: 2 + + interrupt-controller: true + + "#interrupt-cells": + $ref: "arm,gic.yaml#/properties/#interrupt-cells" + +required: + - reg + - interrupt-controller + - "#interrupt-cells" + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - if: + properties: + compatible: + contains: + const: mediatek,mt6797-sysirq + then: + properties: + reg: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + interrupt-controller@10200620 { + compatible = "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq"; + reg = <0x10220620 0x20>, + <0x10220690 0x10>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + }; diff --git a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt deleted file mode 100644 index 3ffc60184e..0000000000 --- a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt +++ /dev/null @@ -1,44 +0,0 @@ -MediaTek sysirq - -MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI -interrupt. - -Required properties: -- compatible: should be - "mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516 - "mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183 - "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173 - "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135 - "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127 - "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622 - "mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623 - "mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629 - "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795 - "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797 - "mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq": for MT6779 - "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765 - "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755 - "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592 - "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589 - "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582 - "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580 - "mediatek,mt6577-sysirq": for MT6577 - "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 - "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 - "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. -- reg: Physical base address of the intpol registers and length of memory - mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others - need 1. - -Example: - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6797-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10220620 0 0x20>, - <0 0x10220690 0 0x10>; - }; diff --git a/dts/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/dts/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index d3b5aec0a3..daef4ee06f 100644 --- a/dts/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/dts/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -44,7 +44,7 @@ properties: maxItems: 1 interrupts: - minItems: 41 + minItems: 45 items: - description: NMI interrupt - description: IRQ0 interrupt @@ -88,9 +88,15 @@ properties: - description: GPIO interrupt, TINT30 - description: GPIO interrupt, TINT31 - description: Bus error interrupt + - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt + - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt + - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt + - description: ECCRAM1 1bit error interrupt + - description: ECCRAM1 2bit error interrupt + - description: ECCRAM1 error overflow interrupt interrupt-names: - minItems: 41 + minItems: 45 items: - const: nmi - const: irq0 @@ -134,6 +140,12 @@ properties: - const: tint30 - const: tint31 - const: bus-err + - const: ec7tie1-0 + - const: ec7tie2-0 + - const: ec7tiovf-0 + - const: ec7tie1-1 + - const: ec7tie2-1 + - const: ec7tiovf-1 clocks: maxItems: 2 @@ -156,6 +168,7 @@ required: - interrupt-controller - reg - interrupts + - interrupt-names - clocks - clock-names - power-domains @@ -169,16 +182,19 @@ allOf: compatible: contains: enum: - - renesas,r9a07g043u-irqc - renesas,r9a08g045-irqc then: properties: interrupts: - minItems: 42 + maxItems: 45 interrupt-names: - minItems: 42 - required: - - interrupt-names + maxItems: 45 + else: + properties: + interrupts: + minItems: 48 + interrupt-names: + minItems: 48 unevaluatedProperties: false @@ -233,7 +249,14 @@ examples: <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", "irq4", "irq5", "irq6", "irq7", @@ -244,7 +267,10 @@ examples: "tint16", "tint17", "tint18", "tint19", "tint20", "tint21", "tint22", "tint23", "tint24", "tint25", "tint26", "tint27", - "tint28", "tint29", "tint30", "tint31"; + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, <&cpg CPG_MOD R9A07G044_IA55_PCLK>; clock-names = "clk", "pclk"; diff --git a/dts/Bindings/interrupt-controller/starfive,jh8100-intc.yaml b/dts/Bindings/interrupt-controller/starfive,jh8100-intc.yaml new file mode 100644 index 0000000000..ada5788602 --- /dev/null +++ b/dts/Bindings/interrupt-controller/starfive,jh8100-intc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive External Interrupt Controller + +description: + StarFive SoC JH8100 contain a external interrupt controller. It can be used + to handle high-level input interrupt signals. It also send the output + interrupt signal to RISC-V PLIC. + +maintainers: + - Changhuang Liang <changhuang.liang@starfivetech.com> + +properties: + compatible: + const: starfive,jh8100-intc + + reg: + maxItems: 1 + + clocks: + description: APB clock for the interrupt controller + maxItems: 1 + + resets: + description: APB reset for the interrupt controller + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller@12260000 { + compatible = "starfive,jh8100-intc"; + reg = <0x12260000 0x10000>; + clocks = <&syscrg_ne 76>; + resets = <&syscrg_ne 13>; + interrupts = <45>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/dts/Bindings/iommu/arm,smmu.yaml b/dts/Bindings/iommu/arm,smmu.yaml index a4042ae247..5c130cf06a 100644 --- a/dts/Bindings/iommu/arm,smmu.yaml +++ b/dts/Bindings/iommu/arm,smmu.yaml @@ -83,6 +83,7 @@ properties: - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" items: - enum: + - qcom,qcm2290-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8280xp-smmu-500 @@ -93,6 +94,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -462,6 +464,7 @@ allOf: compatible: items: - enum: + - qcom,qcm2290-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - const: qcom,adreno-smmu @@ -484,7 +487,12 @@ allOf: - if: properties: compatible: - const: qcom,sm8450-smmu-500 + items: + - const: qcom,sm8450-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: properties: clock-names: @@ -508,7 +516,13 @@ allOf: - if: properties: compatible: - const: qcom,sm8550-smmu-500 + items: + - enum: + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 then: properties: clock-names: @@ -534,7 +548,6 @@ allOf: - cavium,smmu-v2 - marvell,ap806-smmu-500 - nvidia,smmu-500 - - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc8180x-smmu-500 @@ -544,7 +557,6 @@ allOf: - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 then: properties: diff --git a/dts/Bindings/leds/backlight/kinetic,ktd2801.yaml b/dts/Bindings/leds/backlight/kinetic,ktd2801.yaml new file mode 100644 index 0000000000..b005065e0f --- /dev/null +++ b/dts/Bindings/leds/backlight/kinetic,ktd2801.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/kinetic,ktd2801.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Kinetic Technologies KTD2801 one-wire backlight + +maintainers: + - Duje Mihanović <duje.mihanovic@skole.hr> + +description: | + The Kinetic Technologies KTD2801 is a LED backlight driver controlled + by a single GPIO line. The driver can be controlled with a PWM signal + or by pulsing the GPIO line to set the backlight level. This is called + "ExpressWire". + +allOf: + - $ref: common.yaml# + +properties: + compatible: + const: kinetic,ktd2801 + + ctrl-gpios: + maxItems: 1 + + default-brightness: true + max-brightness: true + +required: + - compatible + - ctrl-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + backlight { + compatible = "kinetic,ktd2801"; + ctrl-gpios = <&gpio 97 GPIO_ACTIVE_HIGH>; + max-brightness = <210>; + default-brightness = <100>; + }; diff --git a/dts/Bindings/leds/backlight/qcom-wled.yaml b/dts/Bindings/leds/backlight/qcom-wled.yaml index 5f1849bdab..a849078101 100644 --- a/dts/Bindings/leds/backlight/qcom-wled.yaml +++ b/dts/Bindings/leds/backlight/qcom-wled.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. WLED driver maintainers: - - Bjorn Andersson <bjorn.andersson@linaro.org> - - Kiran Gunda <kgunda@codeaurora.org> + - Bjorn Andersson <andersson@kernel.org> + - Kiran Gunda <quic_kgunda@quicinc.com> description: | WLED (White Light Emitting Diode) driver is used for controlling display diff --git a/dts/Bindings/leds/common.yaml b/dts/Bindings/leds/common.yaml index 55a8d1385e..8a3c2398b1 100644 --- a/dts/Bindings/leds/common.yaml +++ b/dts/Bindings/leds/common.yaml @@ -200,6 +200,18 @@ properties: #trigger-source-cells property in the source node. $ref: /schemas/types.yaml#/definitions/phandle-array + active-low: + type: boolean + description: + Makes LED active low. To turn the LED ON, line needs to be + set to low voltage instead of high. + + inactive-high-impedance: + type: boolean + description: + Set LED to high-impedance mode to turn the LED OFF. LED might also + describe this mode as tristate. + # Required properties for flash LED child nodes: flash-max-microamp: description: diff --git a/dts/Bindings/leds/leds-bcm63138.yaml b/dts/Bindings/leds/leds-bcm63138.yaml index 52252fb6bb..bb20394fca 100644 --- a/dts/Bindings/leds/leds-bcm63138.yaml +++ b/dts/Bindings/leds/leds-bcm63138.yaml @@ -52,10 +52,6 @@ patternProperties: maxItems: 1 description: LED pin number - active-low: - type: boolean - description: Makes LED active low - required: - reg diff --git a/dts/Bindings/leds/leds-bcm6328.yaml b/dts/Bindings/leds/leds-bcm6328.yaml index 51cc0d82c1..f3a3ef9929 100644 --- a/dts/Bindings/leds/leds-bcm6328.yaml +++ b/dts/Bindings/leds/leds-bcm6328.yaml @@ -78,10 +78,6 @@ patternProperties: - maximum: 23 description: LED pin number (only LEDs 0 to 23 are valid). - active-low: - type: boolean - description: Makes LED active low. - brcm,hardware-controlled: type: boolean description: Makes this LED hardware controlled. diff --git a/dts/Bindings/leds/leds-bcm6358.txt b/dts/Bindings/leds/leds-bcm6358.txt index 6e51c6b91e..211ffc3c4a 100644 --- a/dts/Bindings/leds/leds-bcm6358.txt +++ b/dts/Bindings/leds/leds-bcm6358.txt @@ -25,8 +25,6 @@ LED sub-node required properties: LED sub-node optional properties: - label : see Documentation/devicetree/bindings/leds/common.txt - - active-low : Boolean, makes LED active low. - Default : false - default-state : see Documentation/devicetree/bindings/leds/common.txt - linux,default-trigger : see diff --git a/dts/Bindings/leds/leds-pwm-multicolor.yaml b/dts/Bindings/leds/leds-pwm-multicolor.yaml index bd6ec04a87..a31a202afe 100644 --- a/dts/Bindings/leds/leds-pwm-multicolor.yaml +++ b/dts/Bindings/leds/leds-pwm-multicolor.yaml @@ -41,9 +41,7 @@ properties: pwm-names: true - active-low: - description: For PWMs where the LED is wired to supply rather than ground. - type: boolean + active-low: true color: true diff --git a/dts/Bindings/leds/leds-pwm.yaml b/dts/Bindings/leds/leds-pwm.yaml index 7de6da58be..113b7c2183 100644 --- a/dts/Bindings/leds/leds-pwm.yaml +++ b/dts/Bindings/leds/leds-pwm.yaml @@ -34,11 +34,6 @@ patternProperties: Maximum brightness possible for the LED $ref: /schemas/types.yaml#/definitions/uint32 - active-low: - description: - For PWMs where the LED is wired to supply rather than ground. - type: boolean - required: - pwms - max-brightness diff --git a/dts/Bindings/leds/leds-qcom-lpg.yaml b/dts/Bindings/leds/leds-qcom-lpg.yaml index ea84ad426d..54a428d3d4 100644 --- a/dts/Bindings/leds/leds-qcom-lpg.yaml +++ b/dts/Bindings/leds/leds-qcom-lpg.yaml @@ -11,7 +11,7 @@ maintainers: description: > The Qualcomm Light Pulse Generator consists of three different hardware blocks; - a ramp generator with lookup table, the light pulse generator and a three + a ramp generator with lookup table (LUT), the light pulse generator and a three channel current sink. These blocks are found in a wide range of Qualcomm PMICs. properties: @@ -63,6 +63,29 @@ properties: - description: dtest line to attach - description: flags for the attachment + nvmem: + description: > + This property is required for PMICs that supports PPG, which is when a + PMIC stores LPG per-channel data and pattern LUT in SDAM modules instead + of in a LUT peripheral. For PMICs, such as PM8350C, per-channel data + and pattern LUT is separated into 2 SDAM modules. In that case, phandles + to both SDAM modules need to be specified. + minItems: 1 + maxItems: 2 + + nvmem-names: + minItems: 1 + items: + - const: lpg_chan_sdam + - const: lut_sdam + + qcom,pbs: + $ref: /schemas/types.yaml#/definitions/phandle + description: > + Phandle of the Qualcomm Programmable Boot Sequencer node (PBS). + PBS node is used to trigger LPG pattern sequences for PMICs that support + single SDAM PPG. + multi-led: type: object $ref: leds-class-multicolor.yaml# @@ -106,6 +129,52 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pm660l-lpg + - qcom,pm8150b-lpg + - qcom,pm8150l-lpg + - qcom,pm8916-pwm + - qcom,pm8941-lpg + - qcom,pm8994-lpg + - qcom,pmc8180c-lpg + - qcom,pmi8994-lpg + - qcom,pmi8998-lpg + - qcom,pmk8550-pwm + then: + properties: + nvmem: false + nvmem-names: false + + - if: + properties: + compatible: + contains: + const: qcom,pmi632-lpg + then: + properties: + nvmem: + maxItems: 1 + nvmem-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8350c-pwm + then: + properties: + nvmem: + minItems: 2 + nvmem-names: + minItems: 2 + examples: - | #include <dt-bindings/leds/common.h> @@ -191,4 +260,35 @@ examples: compatible = "qcom,pm8916-pwm"; #pwm-cells = <2>; }; + - | + #include <dt-bindings/leds/common.h> + + led-controller { + compatible = "qcom,pmi632-lpg"; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + nvmem-names = "lpg_chan_sdam"; + nvmem = <&pmi632_sdam_7>; + qcom,pbs = <&pmi632_pbs_client3>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_RED>; + label = "red"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + label = "green"; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + label = "blue"; + }; + }; + ... diff --git a/dts/Bindings/leds/onnn,ncp5623.yaml b/dts/Bindings/leds/onnn,ncp5623.yaml new file mode 100644 index 0000000000..9c9f3a682b --- /dev/null +++ b/dts/Bindings/leds/onnn,ncp5623.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/onnn,ncp5623.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ON Semiconductor NCP5623 multi-LED Driver + +maintainers: + - Abdel Alkuor <alkuor@gmail.com> + +description: + NCP5623 Triple Output I2C Controlled LED Driver. + https://www.onsemi.com/pdf/datasheet/ncp5623-d.pdf + +properties: + compatible: + enum: + - onnn,ncp5623 + + reg: + const: 0x38 + + multi-led: + type: object + $ref: leds-class-multicolor.yaml# + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^led@[0-2]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + minimum: 0 + maximum: 2 + + required: + - reg + - color + + required: + - "#address-cells" + - "#size-cells" + +required: + - compatible + - reg + - multi-led + +additionalProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@38 { + compatible = "onnn,ncp5623"; + reg = <0x38>; + + multi-led { + color = <LED_COLOR_ID_RGB>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_RED>; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + }; + }; diff --git a/dts/Bindings/mailbox/fsl,mu.yaml b/dts/Bindings/mailbox/fsl,mu.yaml index 12e7a7d536..00631afcd5 100644 --- a/dts/Bindings/mailbox/fsl,mu.yaml +++ b/dts/Bindings/mailbox/fsl,mu.yaml @@ -29,8 +29,11 @@ properties: - const: fsl,imx8ulp-mu - const: fsl,imx8-mu-scu - const: fsl,imx8-mu-seco - - const: fsl,imx93-mu-s4 - const: fsl,imx8ulp-mu-s4 + - const: fsl,imx93-mu-s4 + - const: fsl,imx95-mu + - const: fsl,imx95-mu-ele + - const: fsl,imx95-mu-v2x - items: - const: fsl,imx93-mu - const: fsl,imx8ulp-mu @@ -95,6 +98,19 @@ properties: power-domains: maxItems: 1 + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +patternProperties: + "^sram@[a-f0-9]+": + $ref: /schemas/sram/sram.yaml# + unevaluatedProperties: false + required: - compatible - reg @@ -122,6 +138,15 @@ allOf: required: - interrupt-names + - if: + not: + properties: + compatible: + const: fsl,imx95-mu + then: + patternProperties: + "^sram@[a-f0-9]+": false + additionalProperties: false examples: @@ -134,3 +159,34 @@ examples: interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x10000>; + ranges; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + }; diff --git a/dts/Bindings/media/i2c/techwell,tw9900.yaml b/dts/Bindings/media/i2c/techwell,tw9900.yaml index e37317f810..c9673391af 100644 --- a/dts/Bindings/media/i2c/techwell,tw9900.yaml +++ b/dts/Bindings/media/i2c/techwell,tw9900.yaml @@ -36,7 +36,7 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/$defs/port-base + $ref: /schemas/graph.yaml#/properties/port description: Analog input port properties: diff --git a/dts/Bindings/media/mediatek,vcodec-encoder.yaml b/dts/Bindings/media/mediatek,vcodec-encoder.yaml index a2051b31fa..b45743d0a9 100644 --- a/dts/Bindings/media/mediatek,vcodec-encoder.yaml +++ b/dts/Bindings/media/mediatek,vcodec-encoder.yaml @@ -16,14 +16,18 @@ description: |+ properties: compatible: - enum: - - mediatek,mt8173-vcodec-enc-vp8 - - mediatek,mt8173-vcodec-enc - - mediatek,mt8183-vcodec-enc - - mediatek,mt8188-vcodec-enc - - mediatek,mt8192-vcodec-enc - - mediatek,mt8195-vcodec-enc - + oneOf: + - items: + - enum: + - mediatek,mt8173-vcodec-enc-vp8 + - mediatek,mt8173-vcodec-enc + - mediatek,mt8183-vcodec-enc + - mediatek,mt8188-vcodec-enc + - mediatek,mt8192-vcodec-enc + - mediatek,mt8195-vcodec-enc + - items: + - const: mediatek,mt8186-vcodec-enc + - const: mediatek,mt8183-vcodec-enc reg: maxItems: 1 @@ -109,10 +113,7 @@ allOf: properties: compatible: enum: - - mediatek,mt8173-vcodec-enc - - mediatek,mt8188-vcodec-enc - - mediatek,mt8192-vcodec-enc - - mediatek,mt8195-vcodec-enc + - mediatek,mt8173-vcodec-enc-vp8 then: properties: @@ -122,8 +123,8 @@ allOf: maxItems: 1 clock-names: items: - - const: venc_sel - else: # for vp8 hw encoder + - const: venc_lt_sel + else: properties: clock: items: @@ -131,7 +132,7 @@ allOf: maxItems: 1 clock-names: items: - - const: venc_lt_sel + - const: venc_sel additionalProperties: false diff --git a/dts/Bindings/media/mediatek-jpeg-encoder.yaml b/dts/Bindings/media/mediatek-jpeg-encoder.yaml index 37800e1908..83c020a673 100644 --- a/dts/Bindings/media/mediatek-jpeg-encoder.yaml +++ b/dts/Bindings/media/mediatek-jpeg-encoder.yaml @@ -38,7 +38,8 @@ properties: maxItems: 1 iommus: - maxItems: 2 + minItems: 2 + maxItems: 4 description: | Points to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. diff --git a/dts/Bindings/media/rockchip-isp1.yaml b/dts/Bindings/media/rockchip-isp1.yaml index afcaa427d4..6be00aca41 100644 --- a/dts/Bindings/media/rockchip-isp1.yaml +++ b/dts/Bindings/media/rockchip-isp1.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - fsl,imx8mp-isp - rockchip,px30-cif-isp - rockchip,rk3399-cif-isp @@ -36,9 +37,9 @@ properties: minItems: 3 items: # isp0 and isp1 - - description: ISP clock - - description: ISP AXI clock - - description: ISP AHB clock + - description: ISP clock (for imx8mp, clk) + - description: ISP AXI clock (for imx8mp, m_hclk) + - description: ISP AHB clock (for imx8mp, hclk) # only for isp1 - description: ISP Pixel clock @@ -52,6 +53,13 @@ properties: # only for isp1 - const: pclk + fsl,blk-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: + A phandle to the media block control for the ISP, followed by a cell + containing the index of the gasket. + iommus: maxItems: 1 @@ -113,9 +121,6 @@ required: - interrupts - clocks - clock-names - - iommus - - phys - - phy-names - power-domains - ports @@ -143,6 +148,26 @@ allOf: required: - interrupt-names + - if: + properties: + compatible: + contains: + const: fsl,imx8mp-isp + then: + properties: + iommus: false + phys: false + phy-names: false + required: + - fsl,blk-ctrl + else: + properties: + fsl,blk-ctrl: false + required: + - iommus + - phys + - phy-names + additionalProperties: false examples: diff --git a/dts/Bindings/media/st,stm32mp25-video-codec.yaml b/dts/Bindings/media/st,stm32mp25-video-codec.yaml new file mode 100644 index 0000000000..b8611bc875 --- /dev/null +++ b/dts/Bindings/media/st,stm32mp25-video-codec.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32mp25-video-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 VDEC video decoder & VENC video encoder + +maintainers: + - Hugues Fruchet <hugues.fruchet@foss.st.com> + +description: + The STMicroelectronics STM32MP25 SOCs embeds a VDEC video hardware + decoder peripheral based on Verisilicon VC8000NanoD IP (former Hantro G1) + and a VENC video hardware encoder peripheral based on Verisilicon + VC8000NanoE IP (former Hantro H1). + +properties: + compatible: + enum: + - st,stm32mp25-vdec + - st,stm32mp25-venc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + video-codec@580d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x580d0000 0x3c8>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_icn_p_vdec>; + }; diff --git a/dts/Bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml b/dts/Bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml new file mode 100644 index 0000000000..82fc5f4a1e --- /dev/null +++ b/dts/Bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX WEIM Bus Peripheral Nodes + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + +description: + This binding is meant for the child nodes of the WEIM node. The node + represents any device connected to the WEIM bus. It may be a Flash chip, + RAM chip or Ethernet controller, etc. These properties are meant for + configuring the WEIM settings/timings and will accompany the bindings + supported by the respective device. + +properties: + reg: true + + fsl,weim-cs-timing: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Timing values for the child node. + minItems: 2 + maxItems: 6 + +# the WEIM child will have its own native properties +additionalProperties: true diff --git a/dts/Bindings/memory-controllers/fsl/fsl,imx-weim.yaml b/dts/Bindings/memory-controllers/fsl/fsl,imx-weim.yaml new file mode 100644 index 0000000000..3f40ca5b13 --- /dev/null +++ b/dts/Bindings/memory-controllers/fsl/fsl,imx-weim.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX Wireless External Interface Module (WEIM) + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + +description: + The term "wireless" does not imply that the WEIM is literally an interface + without wires. It simply means that this module was originally designed for + wireless and mobile applications that use low-power technology. The actual + devices are instantiated from the child nodes of a WEIM node. + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - fsl,imx1-weim + - fsl,imx27-weim + - fsl,imx50-weim + - fsl,imx51-weim + - fsl,imx6q-weim + - items: + - enum: + - fsl,imx31-weim + - fsl,imx35-weim + - const: fsl,imx27-weim + - items: + - enum: + - fsl,imx6sx-weim + - fsl,imx6ul-weim + - const: fsl,imx6q-weim + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + ranges: true + + fsl,weim-cs-gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the system General Purpose Register controller that contains + WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] + should be set up as one of the following 4 possible values depending on + the CS space configuration. + + IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 + --------------------------------------------- + 05 128M 0M 0M 0M + 033 64M 64M 0M 0M + 0113 64M 32M 32M 0M + 01111 32M 32M 32M 32M + + In case that the property is absent, the reset value or what bootloader + sets up in IOMUXC_GPR1[11:0] will be used. + + fsl,burst-clk-enable: + type: boolean + description: + The presence of this property indicates that the weim bus should operate + in Burst Clock Mode. + + fsl,continuous-burst-clk: + type: boolean + description: + Make Burst Clock to output continuous clock. Without this option Burst + Clock will output clock only when necessary. + +patternProperties: + "^.*@[0-7],[0-9a-f]+$": + type: object + description: Devices attached to chip selects are represented as subnodes. + $ref: fsl,imx-weim-peripherals.yaml + additionalProperties: true + required: + - fsl,weim-cs-timing + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + +allOf: + - if: + properties: + compatible: + not: + contains: + enum: + - fsl,imx50-weim + - fsl,imx6q-weim + then: + properties: + fsl,weim-cs-gpr: false + fsl,burst-clk-enable: false + - if: + not: + required: + - fsl,burst-clk-enable + then: + properties: + fsl,continuous-burst-clk: false + - if: + properties: + compatible: + contains: + const: fsl,imx1-weim + then: + patternProperties: + "^.*@[0-7],[0-9a-f]+$": + properties: + fsl,weim-cs-timing: + items: + items: + - description: CSxU + - description: CSxL + - if: + properties: + compatible: + contains: + enum: + - fsl,imx27-weim + - fsl,imx31-weim + - fsl,imx35-weim + then: + patternProperties: + "^.*@[0-7],[0-9a-f]+$": + properties: + fsl,weim-cs-timing: + items: + items: + - description: CSCRxU + - description: CSCRxL + - description: CSCRxA + - if: + properties: + compatible: + contains: + enum: + - fsl,imx50-weim + - fsl,imx51-weim + - fsl,imx6q-weim + - fsl,imx6sx-weim + - fsl,imx6ul-weim + then: + patternProperties: + "^.*@[0-7],[0-9a-f]+$": + properties: + fsl,weim-cs-timing: + items: + items: + - description: CSxGCR1 + - description: CSxGCR2 + - description: CSxRCR1 + - description: CSxRCR2 + - description: CSxWCR1 + - description: CSxWCR2 + +additionalProperties: false + +examples: + - | + memory-controller@21b8000 { + compatible = "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + clocks = <&clks 196>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x08000000>; + fsl,weim-cs-gpr = <&gpr>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; + }; diff --git a/dts/Bindings/memory-controllers/mc-peripheral-props.yaml b/dts/Bindings/memory-controllers/mc-peripheral-props.yaml index 8d9dae15ad..00deeb09f8 100644 --- a/dts/Bindings/memory-controllers/mc-peripheral-props.yaml +++ b/dts/Bindings/memory-controllers/mc-peripheral-props.yaml @@ -37,5 +37,6 @@ allOf: - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# - $ref: ti,gpmc-child.yaml# + - $ref: fsl/fsl,imx-weim-peripherals.yaml additionalProperties: true diff --git a/dts/Bindings/memory-controllers/nvidia,tegra20-emc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra20-emc.yaml index f54e553e6c..71896cb106 100644 --- a/dts/Bindings/memory-controllers/nvidia,tegra20-emc.yaml +++ b/dts/Bindings/memory-controllers/nvidia,tegra20-emc.yaml @@ -145,7 +145,7 @@ patternProperties: "^emc-table@[0-9]+$": $ref: "#/$defs/emc-table" - "^emc-tables@[a-z0-9-]+$": + "^emc-tables@[a-f0-9-]+$": type: object properties: reg: diff --git a/dts/Bindings/memory-controllers/renesas,rpc-if.yaml b/dts/Bindings/memory-controllers/renesas,rpc-if.yaml index 25f3bb9890..d7745dd53b 100644 --- a/dts/Bindings/memory-controllers/renesas,rpc-if.yaml +++ b/dts/Bindings/memory-controllers/renesas,rpc-if.yaml @@ -45,6 +45,7 @@ properties: - items: - enum: - renesas,r8a779g0-rpc-if # R-Car V4H + - renesas,r8a779h0-rpc-if # R-Car V4M - const: renesas,rcar-gen4-rpc-if # a generic R-Car gen4 device - items: diff --git a/dts/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/dts/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 14f1833d37..84ac6f50a6 100644 --- a/dts/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/dts/Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -23,7 +23,9 @@ maintainers: properties: compatible: - const: st,stm32mp1-fmc2-ebi + enum: + - st,stm32mp1-fmc2-ebi + - st,stm32mp25-fmc2-ebi reg: maxItems: 1 @@ -34,6 +36,9 @@ properties: resets: maxItems: 1 + power-domains: + maxItems: 1 + "#address-cells": const: 2 diff --git a/dts/Bindings/mfd/atmel,hlcdc.yaml b/dts/Bindings/mfd/atmel,hlcdc.yaml new file mode 100644 index 0000000000..4aa36903e7 --- /dev/null +++ b/dts/Bindings/mfd/atmel,hlcdc.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,hlcdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's HLCD Controller + +maintainers: + - Nicolas Ferre <nicolas.ferre@microchip.com> + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - Claudiu Beznea <claudiu.beznea@tuxon.dev> + +description: + The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two + subdevices, a PWM chip and a Display Controller. + +properties: + compatible: + enum: + - atmel,at91sam9n12-hlcdc + - atmel,at91sam9x5-hlcdc + - atmel,sama5d2-hlcdc + - atmel,sama5d3-hlcdc + - atmel,sama5d4-hlcdc + - microchip,sam9x60-hlcdc + - microchip,sam9x75-xlcdc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + + clock-names: + items: + - const: periph_clk + - const: sys_clk + - const: slow_clk + - const: lvds_pll_clk + minItems: 3 + + display-controller: + $ref: /schemas/display/atmel/atmel,hlcdc-display-controller.yaml + + pwm: + $ref: /schemas/pwm/atmel,hlcdc-pwm.yaml + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/at91.h> + #include <dt-bindings/dma/at91.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + lcd_controller: lcd-controller@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + + display-controller { + compatible = "atmel,hlcdc-display-controller"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + + pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; diff --git a/dts/Bindings/mfd/atmel,sama5d2-flexcom.yaml b/dts/Bindings/mfd/atmel,sama5d2-flexcom.yaml new file mode 100644 index 0000000000..0dc6a40b63 --- /dev/null +++ b/dts/Bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,sama5d2-flexcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Flexcom (Flexible Serial Communication Unit) + +maintainers: + - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> + +description: + The Microchip Flexcom is just a wrapper which embeds a SPI controller, + an I2C controller and an USART. Only one function can be used at a + time and is chosen at boot time according to the device tree. + +properties: + compatible: + oneOf: + - const: atmel,sama5d2-flexcom + - items: + - const: microchip,sam9x7-flexcom + - const: atmel,sama5d2-flexcom + - items: + - const: microchip,sama7g5-flexcom + - const: atmel,sama5d2-flexcom + + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + description: + One range for the full I/O register region. (including USART, + TWI and SPI registers). + items: + maxItems: 3 + + atmel,flexcom-mode: + description: | + Specifies the flexcom mode as follows: + 1: USART + 2: SPI + 3: I2C. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +patternProperties: + "^serial@[0-9a-f]+$": + type: object + description: + Child node describing USART. See atmel-usart.txt for details + of USART bindings. + + "^spi@[0-9a-f]+$": + type: object + description: + Child node describing SPI. See ../spi/spi_atmel.txt for details + of SPI bindings. + + "^i2c@[0-9a-f]+$": + $ref: /schemas/i2c/atmel,at91sam-i2c.yaml + description: + Child node describing I2C. + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + - atmel,flexcom-mode + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + flx0: flexcom@f8034000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8034000 0x200>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8034000 0x800>; + atmel,flexcom-mode = <2>; + }; +... diff --git a/dts/Bindings/mfd/atmel-flexcom.txt b/dts/Bindings/mfd/atmel-flexcom.txt deleted file mode 100644 index af692e8833..0000000000 --- a/dts/Bindings/mfd/atmel-flexcom.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) - -The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C -controller and an USART. Only one function can be used at a time and is chosen -at boot time according to the device tree. - -Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" - or "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom" -- reg: Should be the offset/length value for Flexcom dedicated - I/O registers (without USART, TWI or SPI registers). -- clocks: Should be the Flexcom peripheral clock from PMC. -- #address-cells: Should be <1> -- #size-cells: Should be <1> -- ranges: Should be one range for the full I/O register region - (including USART, TWI and SPI registers). -- atmel,flexcom-mode: Should be one of the following values: - - <1> for USART - - <2> for SPI - - <3> for I2C - -Required child: -A single available child device of type matching the "atmel,flexcom-mode" -property. - -The phandle provided by the clocks property of the child is the same as one for -the Flexcom parent. - -For other properties, please refer to the documentations of the respective -device: -- ../serial/atmel-usart.txt -- ../spi/spi_atmel.txt -- ../i2c/i2c-at91.txt - -Example: - -flexcom@f8034000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8034000 0x200>; - clocks = <&flx0_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8034000 0x800>; - atmel,flexcom-mode = <2>; - - spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&flx0_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - - flash@0 { - compatible = "atmel,at25f512b"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; -}; diff --git a/dts/Bindings/mfd/atmel-hlcdc.txt b/dts/Bindings/mfd/atmel-hlcdc.txt deleted file mode 100644 index 7de696eefa..0000000000 --- a/dts/Bindings/mfd/atmel-hlcdc.txt +++ /dev/null @@ -1,56 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver - -Required properties: - - compatible: value should be one of the following: - "atmel,at91sam9n12-hlcdc" - "atmel,at91sam9x5-hlcdc" - "atmel,sama5d2-hlcdc" - "atmel,sama5d3-hlcdc" - "atmel,sama5d4-hlcdc" - "microchip,sam9x60-hlcdc" - "microchip,sam9x75-xlcdc" - - reg: base address and size of the HLCDC device registers. - - clock-names: the name of the 3 clocks requested by the HLCDC device. - Should contain "periph_clk", "sys_clk" and "slow_clk". - - clocks: should contain the 3 clocks requested by the HLCDC device. - - interrupts: should contain the description of the HLCDC interrupt line - -The HLCDC IP exposes two subdevices: - - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt - - a Display Controller: see ../display/atmel/hlcdc-dc.txt - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hlcdc_panel_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; diff --git a/dts/Bindings/mfd/da9062.txt b/dts/Bindings/mfd/da9062.txt deleted file mode 100644 index e4eedd3bd2..0000000000 --- a/dts/Bindings/mfd/da9062.txt +++ /dev/null @@ -1,124 +0,0 @@ -* Dialog DA9062 Power Management Integrated Circuit (PMIC) - -Product information for the DA9062 and DA9061 devices can be found here: -- https://www.dialog-semiconductor.com/products/da9062 -- https://www.dialog-semiconductor.com/products/da9061 - -The DA9062 PMIC consists of: - -Device Supply Names Description ------- ------------ ----------- -da9062-regulator : : LDOs & BUCKs -da9062-rtc : : Real-Time Clock -da9062-onkey : : On Key -da9062-watchdog : : Watchdog Timer -da9062-thermal : : Thermal -da9062-gpio : : GPIOs - -The DA9061 PMIC consists of: - -Device Supply Names Description ------- ------------ ----------- -da9062-regulator : : LDOs & BUCKs -da9062-onkey : : On Key -da9062-watchdog : : Watchdog Timer -da9062-thermal : : Thermal - -====== - -Required properties: - -- compatible : Should be - "dlg,da9062" for DA9062 - "dlg,da9061" for DA9061 -- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be - modified to match the chip's OTP settings). - -Optional properties: - -- gpio-controller : Marks the device as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify the gpio polarity. - -See Documentation/devicetree/bindings/gpio/gpio.txt for further information on -GPIO bindings. - -- interrupts : IRQ line information. -- interrupt-controller - -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for -further information on IRQ bindings. - -Sub-nodes: - -- regulators : This node defines the settings for the LDOs and BUCKs. - The DA9062 regulators are bound using their names listed below: - - buck1 : BUCK_1 - buck2 : BUCK_2 - buck3 : BUCK_3 - buck4 : BUCK_4 - ldo1 : LDO_1 - ldo2 : LDO_2 - ldo3 : LDO_3 - ldo4 : LDO_4 - - The DA9061 regulators are bound using their names listed below: - - buck1 : BUCK_1 - buck2 : BUCK_2 - buck3 : BUCK_3 - ldo1 : LDO_1 - ldo2 : LDO_2 - ldo3 : LDO_3 - ldo4 : LDO_4 - - The component follows the standard regulator framework and the bindings - details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - - regulator-initial-mode may be specified for buck regulators using mode values - from include/dt-bindings/regulator/dlg,da9063-regulator.h. - -- rtc : This node defines settings required for the Real-Time Clock associated - with the DA9062. There are currently no entries in this binding, however - compatible = "dlg,da9062-rtc" should be added if a node is created. - -- onkey : See ../input/da9062-onkey.txt - -- watchdog: See ../watchdog/da9062-wdt.txt - -- thermal : See ../thermal/da9062-thermal.txt - -Example: - - pmic0: da9062@58 { - compatible = "dlg,da9062"; - reg = <0x58>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9062-rtc"; - }; - - regulators { - DA9062_BUCK1: buck1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <500000>; - regulator-max-microamp = <2000000>; - regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; - regulator-boot-on; - }; - DA9062_LDO1: ldo1 { - regulator-name = "LDO_1"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - }; - }; - }; - diff --git a/dts/Bindings/mfd/dlg,da9063.yaml b/dts/Bindings/mfd/dlg,da9063.yaml index c5a7e10d7d..51612dc227 100644 --- a/dts/Bindings/mfd/dlg,da9063.yaml +++ b/dts/Bindings/mfd/dlg,da9063.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/dlg,da9063.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC) +title: Dialog DA906{3L,3,2,1} Power Management Integrated Circuit (PMIC) maintainers: - Steve Twiss <stwiss.opensource@diasemi.com> @@ -17,10 +17,17 @@ description: | moment where all voltage monitors are disabled. Next, as da9063 only supports UV *and* OV monitoring, both must be set to the same severity and value (0: disable, 1: enable). + Product information for the DA906{3L,3,2,1} devices can be found here: + - https://www.dialog-semiconductor.com/products/da9063l + - https://www.dialog-semiconductor.com/products/da9063 + - https://www.dialog-semiconductor.com/products/da9062 + - https://www.dialog-semiconductor.com/products/da9061 properties: compatible: enum: + - dlg,da9061 + - dlg,da9062 - dlg,da9063 - dlg,da9063l @@ -35,20 +42,28 @@ properties: "#interrupt-cells": const: 2 - dlg,use-sw-pm: - type: boolean - description: - Disable the watchdog during suspend. - Only use this option if you can't use the watchdog automatic suspend - function during a suspend (see register CONTROL_B). + gpio-controller: true - watchdog: + "#gpio-cells": + const: 2 + + gpio: type: object - $ref: /schemas/watchdog/watchdog.yaml# - unevaluatedProperties: false + additionalProperties: false properties: compatible: - const: dlg,da9063-watchdog + const: dlg,da9062-gpio + + onkey: + $ref: /schemas/input/dlg,da9062-onkey.yaml + + regulators: + type: object + additionalProperties: false + patternProperties: + "^(ldo([1-9]|1[01])|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged|buck[1-4])$": + $ref: /schemas/regulator/regulator.yaml + unevaluatedProperties: false rtc: type: object @@ -56,37 +71,86 @@ properties: unevaluatedProperties: false properties: compatible: - const: dlg,da9063-rtc + enum: + - dlg,da9062-rtc + - dlg,da9063-rtc - onkey: - type: object - $ref: /schemas/input/input.yaml# - unevaluatedProperties: false - properties: - compatible: - const: dlg,da9063-onkey + thermal: + $ref: /schemas/thermal/dlg,da9062-thermal.yaml - dlg,disable-key-power: - type: boolean - description: | - Disable power-down using a long key-press. - If this entry does not exist then by default the key-press triggered - power down is enabled and the OnKey will support both KEY_POWER and - KEY_SLEEP. + watchdog: + $ref: /schemas/watchdog/dlg,da9062-watchdog.yaml - regulators: +patternProperties: + "^(.+-hog(-[0-9]+)?)$": type: object - additionalProperties: false - patternProperties: - "^(ldo([1-9]|1[01])|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged)$": - $ref: /schemas/regulator/regulator.yaml - unevaluatedProperties: false + + required: + - gpio-hog required: - compatible - reg - - interrupts - - interrupt-controller + +allOf: + - if: + properties: + compatible: + contains: + enum: + - dlg,da9063 + - dlg,da9063l + then: + properties: + gpio-controller: false + "#gpio-cells": false + gpio: false + regulators: + patternProperties: + "^buck[1-4]$": false + thermal: false + required: + - interrupts + - interrupt-controller + - '#interrupt-cells' + + - if: + properties: + compatible: + contains: + enum: + - dlg,da9062 + then: + properties: + regulators: + patternProperties: + "^(ldo([5-9]|10|11)|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged)$": false + required: + - gpio + - onkey + - rtc + - thermal + - watchdog + + - if: + properties: + compatible: + contains: + enum: + - dlg,da9061 + then: + properties: + gpio-controller: false + "#gpio-cells": false + gpio: false + regulators: + patternProperties: + "^(ldo([5-9]|10|11)|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged|buck4)$": false + rtc: false + required: + - onkey + - thermal + - watchdog additionalProperties: false @@ -99,10 +163,10 @@ examples: pmic@58 { compatible = "dlg,da9063"; reg = <0x58>; - #interrupt-cells = <2>; interrupt-parent = <&gpio6>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; rtc { compatible = "dlg,da9063-rtc"; @@ -143,4 +207,121 @@ examples: }; }; }; + + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/regulator/dlg,da9063-regulator.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + pmic@58 { + compatible = "dlg,da9062"; + reg = <0x58>; + gpio-controller; + #gpio-cells = <2>; + + sd0-pwr-sel-hog { + gpio-hog; + gpios = <1 0>; + input; + line-name = "SD0_PWR_SEL"; + }; + + sd1-pwr-sel-hog { + gpio-hog; + gpios = <2 0>; + input; + line-name = "SD1_PWR_SEL"; + }; + + sw-et0-en-hog { + gpio-hog; + gpios = <3 0>; + input; + line-name = "SW_ET0_EN#"; + }; + + pmic-good-hog { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "PMIC_PGOOD"; + }; + + gpio { + compatible = "dlg,da9062-gpio"; + }; + + onkey { + compatible = "dlg,da9062-onkey"; + }; + + regulators { + buck1 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1380000>; + regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; + regulator-always-on; + }; + buck2 { + regulator-name = "vdd_soc"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1380000>; + regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; + regulator-always-on; + }; + buck3 { + regulator-name = "vdd_ddr3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; + regulator-always-on; + }; + buck4 { + regulator-name = "vdd_eth"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; + regulator-always-on; + }; + ldo1 { + regulator-name = "vdd_snvs"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + ldo2 { + regulator-name = "vdd_high"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + ldo3 { + regulator-name = "vdd_eth_io"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + ldo4 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + + rtc { + compatible = "dlg,da9062-rtc"; + }; + + thermal { + compatible = "dlg,da9062-thermal"; + }; + + watchdog { + compatible = "dlg,da9062-watchdog"; + dlg,use-sw-pm; + }; + }; + }; ... diff --git a/dts/Bindings/mfd/google,cros-ec.yaml b/dts/Bindings/mfd/google,cros-ec.yaml index e1ca4f297c..aac8819bd0 100644 --- a/dts/Bindings/mfd/google,cros-ec.yaml +++ b/dts/Bindings/mfd/google,cros-ec.yaml @@ -93,6 +93,11 @@ properties: '#size-cells': const: 0 + '#gpio-cells': + const: 2 + + gpio-controller: true + typec: $ref: /schemas/chrome/google,cros-ec-typec.yaml# @@ -275,6 +280,8 @@ examples: interrupts = <99 0>; interrupt-parent = <&gpio7>; spi-max-frequency = <5000000>; + #gpio-cells = <2>; + gpio-controller; proximity { compatible = "google,cros-ec-mkbp-proximity"; diff --git a/dts/Bindings/mfd/iqs62x.yaml b/dts/Bindings/mfd/iqs62x.yaml index 044cd7542c..f438c23749 100644 --- a/dts/Bindings/mfd/iqs62x.yaml +++ b/dts/Bindings/mfd/iqs62x.yaml @@ -31,7 +31,7 @@ properties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Specifies the name of the calibration and configuration file selected by the driver. If this property is omitted, the name is chosen based on the diff --git a/dts/Bindings/mfd/qcom,tcsr.yaml b/dts/Bindings/mfd/qcom,tcsr.yaml index 798705ab6a..b97d770153 100644 --- a/dts/Bindings/mfd/qcom,tcsr.yaml +++ b/dts/Bindings/mfd/qcom,tcsr.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,msm8976-tcsr - qcom,msm8998-tcsr + - qcom,qcm2290-tcsr - qcom,qcs404-tcsr - qcom,sc7180-tcsr - qcom,sc7280-tcsr @@ -28,6 +29,7 @@ properties: - qcom,sdx55-tcsr - qcom,sdx65-tcsr - qcom,sm4450-tcsr + - qcom,sm6115-tcsr - qcom,sm8150-tcsr - qcom,sm8250-tcsr - qcom,sm8350-tcsr diff --git a/dts/Bindings/mfd/syscon.yaml b/dts/Bindings/mfd/syscon.yaml index 084b5c2a2a..9d55bee155 100644 --- a/dts/Bindings/mfd/syscon.yaml +++ b/dts/Bindings/mfd/syscon.yaml @@ -72,7 +72,10 @@ properties: - rockchip,rk3588-qos - rockchip,rv1126-qos - starfive,jh7100-sysmain + - ti,am62-usb-phy-ctrl - ti,am654-dss-oldi-io-ctrl + - ti,am654-serdes-ctrl + - ti,j784s4-pcie-ctrl - const: syscon diff --git a/dts/Bindings/mfd/ti,twl.yaml b/dts/Bindings/mfd/ti,twl.yaml index c04d57ba22..52ed228fb1 100644 --- a/dts/Bindings/mfd/ti,twl.yaml +++ b/dts/Bindings/mfd/ti,twl.yaml @@ -34,6 +34,8 @@ properties: interrupt-controller: true + system-power-controller: true + "#interrupt-cells": const: 1 diff --git a/dts/Bindings/mips/cpus.yaml b/dts/Bindings/mips/cpus.yaml index cf382dea39..a85137add6 100644 --- a/dts/Bindings/mips/cpus.yaml +++ b/dts/Bindings/mips/cpus.yaml @@ -23,22 +23,23 @@ properties: - brcm,bmips4380 - brcm,bmips5000 - brcm,bmips5200 - - ingenic,xburst-mxu1.0 + - img,i6500 - ingenic,xburst-fpu1.0-mxu1.1 - ingenic,xburst-fpu2.0-mxu2.0 + - ingenic,xburst-mxu1.0 - ingenic,xburst2-fpu2.1-mxu2.1-smt - loongson,gs264 - mips,m14Kc - - mips,mips4Kc - - mips,mips4KEc - - mips,mips24Kc + - mips,mips1004Kc - mips,mips24KEc + - mips,mips24Kc + - mips,mips4KEc + - mips,mips4Kc - mips,mips74Kc - - mips,mips1004Kc - mti,interaptiv - - mti,mips24KEc - mti,mips14KEc - mti,mips14Kc + - mti,mips24KEc reg: maxItems: 1 diff --git a/dts/Bindings/mips/mobileye.yaml b/dts/Bindings/mips/mobileye.yaml new file mode 100644 index 0000000000..831975f6b4 --- /dev/null +++ b/dts/Bindings/mips/mobileye.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright 2023 Mobileye Vision Technologies Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mobileye.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye SoC series + +maintainers: + - Vladimir Kondratiev <vladimir.kondratiev@intel.com> + - Gregory CLEMENT <gregory.clement@bootlin.com> + - Théo Lebrun <theo.lebrun@bootlin.com> + +description: + Boards with a Mobileye SoC shall have the following properties. + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Boards with Mobileye EyeQ5 SoC + items: + - enum: + - mobileye,eyeq5-epm5 + - const: mobileye,eyeq5 + +additionalProperties: true + +... diff --git a/dts/Bindings/misc/qcom,fastrpc.yaml b/dts/Bindings/misc/qcom,fastrpc.yaml index 2dc3e245fa..c27a8f33d8 100644 --- a/dts/Bindings/misc/qcom,fastrpc.yaml +++ b/dts/Bindings/misc/qcom,fastrpc.yaml @@ -77,6 +77,8 @@ patternProperties: reg: maxItems: 1 + dma-coherent: true + iommus: minItems: 1 maxItems: 3 diff --git a/dts/Bindings/misc/xlnx,sd-fec.txt b/dts/Bindings/misc/xlnx,sd-fec.txt deleted file mode 100644 index e3289634fa..0000000000 --- a/dts/Bindings/misc/xlnx,sd-fec.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Xilinx SDFEC(16nm) IP * - -The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block -which provides high-throughput LDPC and Turbo Code implementations. -The LDPC decode & encode functionality is capable of covering a range of -customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality -principally covers codes used by LTE. The FEC Engine offers significant -power and area savings versus implementations done in the FPGA fabric. - - -Required properties: -- compatible: Must be "xlnx,sd-fec-1.1" -- clock-names : List of input clock names from the following: - - "core_clk", Main processing clock for processing core (required) - - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required) - - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional) - - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional) - - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional) - - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional) - - "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional) - - "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional) -- clocks : Clock phandles (see clock_bindings.txt for details). -- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers - location and length. -- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes - being used. -- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is - driven with a fixed value and is not present on the device, a value of 1 - configures the DIN_WORDS to be block based, while a value of 2 configures the - DIN_WORDS input to be supplied for each AXI transaction. -- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1 - configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width - of "4x128b". -- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is - driven with a fixed value and is not present on the device, a value of 1 - configures the DOUT_WORDS to be block based, while a value of 2 configures the - DOUT_WORDS input to be supplied for each AXI transaction. -- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1 - configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width - of "4x128b". -Optional properties: -- interrupts: should contain SDFEC interrupt number - -Example ---------------------------------------- - sd_fec_0: sd-fec@a0040000 { - compatible = "xlnx,sd-fec-1.1"; - clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk"; - clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>; - reg = <0x0 0xa0040000 0x0 0x40000>; - interrupt-parent = <&axi_intc>; - interrupts = <1 0>; - xlnx,sdfec-code = "ldpc"; - xlnx,sdfec-din-words = <0>; - xlnx,sdfec-din-width = <2>; - xlnx,sdfec-dout-words = <0>; - xlnx,sdfec-dout-width = <1>; - }; diff --git a/dts/Bindings/misc/xlnx,sd-fec.yaml b/dts/Bindings/misc/xlnx,sd-fec.yaml new file mode 100644 index 0000000000..9bd2103374 --- /dev/null +++ b/dts/Bindings/misc/xlnx,sd-fec.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx SDFEC(16nm) IP + +maintainers: + - Cvetic, Dragan <dragan.cvetic@amd.com> + - Erim, Salih <salih.erim@amd.com> + +description: + The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block + which provides high-throughput LDPC and Turbo Code implementations. + The LDPC decode & encode functionality is capable of covering a range of + customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality + principally covers codes used by LTE. The FEC Engine offers significant + power and area savings versus implementations done in the FPGA fabric. + +properties: + compatible: + const: xlnx,sd-fec-1.1 + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 8 + additionalItems: true + items: + - description: Main processing clock for processing core + - description: AXI4-Lite memory-mapped slave interface clock + - description: Control input AXI4-Stream Slave interface clock + - description: DIN AXI4-Stream Slave interface clock + - description: Status output AXI4-Stream Master interface clock + - description: DOUT AXI4-Stream Master interface clock + - description: DIN_WORDS AXI4-Stream Slave interface clock + - description: DOUT_WORDS AXI4-Stream Master interface clock + + clock-names: + allOf: + - minItems: 2 + maxItems: 8 + additionalItems: true + items: + - const: core_clk + - const: s_axi_aclk + - items: + enum: + - core_clk + - s_axi_aclk + - s_axis_ctrl_aclk + - s_axis_din_aclk + - m_axis_status_aclk + - m_axis_dout_aclk + - s_axis_din_words_aclk + - m_axis_dout_words_aclk + + interrupts: + maxItems: 1 + + xlnx,sdfec-code: + description: + The SD-FEC integrated block supports Low Density Parity Check (LDPC) + decoding and encoding and Turbo code decoding. The LDPC codes used are + highly configurable, and the specific code used can be specified on + a codeword-by-codeword basis. The Turbo code decoding is required by LTE + standard. + $ref: /schemas/types.yaml#/definitions/string + items: + enum: [ ldpc, turbo ] + + xlnx,sdfec-din-width: + description: + Configures the DIN AXI stream where a value of 1 + configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width + of "4x128b". + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 4 ] + + xlnx,sdfec-din-words: + description: + A value 0 indicates that the DIN_WORDS interface is + driven with a fixed value and is not present on the device, a value of 1 + configures the DIN_WORDS to be block based, while a value of 2 configures the + DIN_WORDS input to be supplied for each AXI transaction. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + + xlnx,sdfec-dout-width: + description: + Configures the DOUT AXI stream where a value of 1 configures a width of "1x128b", + 2 a width of "2x128b" and 4 configures a width of "4x128b". + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 4 ] + + xlnx,sdfec-dout-words: + description: + A value 0 indicates that the DOUT_WORDS interface is + driven with a fixed value and is not present on the device, a value of 1 + configures the DOUT_WORDS to be block based, while a value of 2 configures the + DOUT_WORDS input to be supplied for each AXI transaction. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + +required: + - compatible + - reg + - clocks + - clock-names + - xlnx,sdfec-code + - xlnx,sdfec-din-width + - xlnx,sdfec-din-words + - xlnx,sdfec-dout-width + - xlnx,sdfec-dout-words + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + sd-fec@a0040000 { + compatible = "xlnx,sd-fec-1.1"; + reg = <0xa0040000 0x40000>; + clocks = <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_1>, + <&misc_clk_1>, <&misc_clk_1>; + clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk", + "s_axis_din_aclk", "m_axis_status_aclk", + "m_axis_dout_aclk"; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + xlnx,sdfec-code = "ldpc"; + xlnx,sdfec-din-width = <2>; + xlnx,sdfec-din-words = <0>; + xlnx,sdfec-dout-width = <1>; + xlnx,sdfec-dout-words = <0>; + }; + diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.yaml b/dts/Bindings/mmc/fsl-imx-esdhc.yaml index 82eb7a24c8..82f7ee8702 100644 --- a/dts/Bindings/mmc/fsl-imx-esdhc.yaml +++ b/dts/Bindings/mmc/fsl-imx-esdhc.yaml @@ -55,8 +55,9 @@ properties: - enum: - fsl,imx8mn-usdhc - fsl,imx8mp-usdhc - - fsl,imx93-usdhc - fsl,imx8ulp-usdhc + - fsl,imx93-usdhc + - fsl,imx95-usdhc - const: fsl,imx8mm-usdhc - items: - enum: @@ -162,6 +163,9 @@ properties: - const: ahb - const: per + iommus: + maxItems: 1 + power-domains: maxItems: 1 @@ -173,6 +177,11 @@ properties: - const: state_100mhz - const: state_200mhz - const: sleep + - minItems: 2 + items: + - const: default + - const: state_100mhz + - const: sleep - minItems: 1 items: - const: default diff --git a/dts/Bindings/mmc/fsl-imx-mmc.yaml b/dts/Bindings/mmc/fsl-imx-mmc.yaml index 221f5bc047..7911316fbd 100644 --- a/dts/Bindings/mmc/fsl-imx-mmc.yaml +++ b/dts/Bindings/mmc/fsl-imx-mmc.yaml @@ -24,6 +24,14 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: per + interrupts: maxItems: 1 @@ -34,6 +42,8 @@ properties: const: rx-tx required: + - clocks + - clock-names - compatible - reg - interrupts @@ -46,6 +56,8 @@ examples: compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; reg = <0x10014000 0x1000>; interrupts = <11>; + clocks = <&clks 29>, <&clks 60>; + clock-names = "ipg", "per"; dmas = <&dma 7>; dma-names = "rx-tx"; bus-width = <4>; diff --git a/dts/Bindings/mmc/hi3798cv200-dw-mshc.txt b/dts/Bindings/mmc/hi3798cv200-dw-mshc.txt deleted file mode 100644 index a0693b7145..0000000000 --- a/dts/Bindings/mmc/hi3798cv200-dw-mshc.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile - Storage Host Controller - -Read synopsys-dw-mshc.txt for more details - -The Synopsys designware mobile storage host controller is used to interface -a SoC with storage medium such as eMMC or SD/MMC cards. This file documents -differences between the core Synopsys dw mshc controller properties described -by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200 -specific extensions to the Synopsys Designware Mobile Storage Host Controller. - -Required Properties: -- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc". -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. -- clock-names: Should contain the following: - "ciu" - The ciu clock described in synopsys-dw-mshc.txt. - "biu" - The biu clock described in synopsys-dw-mshc.txt. - "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling. - "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving. - -Example: - - emmc: mmc@9830000 { - compatible = "hisilicon,hi3798cv200-dw-mshc"; - reg = <0x9830000 0x10000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>, - <&crg HISTB_MMC_SAMPLE_CLK>, - <&crg HISTB_MMC_DRV_CLK>; - clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; - fifo-depth = <256>; - clock-frequency = <200000000>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - bus-width = <8>; - }; diff --git a/dts/Bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml b/dts/Bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml new file mode 100644 index 0000000000..41c9b22523 --- /dev/null +++ b/dts/Bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiSTB SoCs specific extensions to the Synopsys DWMMC controller + +maintainers: + - Yang Xiwen <forbidden405@outlook.com> + +properties: + compatible: + enum: + - hisilicon,hi3798cv200-dw-mshc + - hisilicon,hi3798mv200-dw-mshc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: bus interface unit clock + - description: card interface unit clock + - description: card input sample phase clock + - description: controller output drive phase clock + + clock-names: + items: + - const: ciu + - const: biu + - const: ciu-sample + - const: ciu-drive + + hisilicon,sap-dll-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path. + It is integrated into CRG core on the SoC and has to be controlled during tuning. + items: + - description: A phandle pointed to the CRG syscon node + - description: Sample DLL register offset in CRG address space + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - $ref: synopsys-dw-mshc-common.yaml# + + - if: + properties: + compatible: + contains: + const: hisilicon,hi3798mv200-dw-mshc + then: + required: + - hisilicon,sap-dll-reg + else: + properties: + hisilicon,sap-dll-reg: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/histb-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mmc@9830000 { + compatible = "hisilicon,hi3798cv200-dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>, + <&crg HISTB_MMC_DRV_CLK>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; + resets = <&crg 0xa0 4>; + reset-names = "reset"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins_1 &emmc_pins_2 + &emmc_pins_3 &emmc_pins_4>; + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + }; diff --git a/dts/Bindings/mmc/renesas,sdhi.yaml b/dts/Bindings/mmc/renesas,sdhi.yaml index f7a4c6bc70..29f2400247 100644 --- a/dts/Bindings/mmc/renesas,sdhi.yaml +++ b/dts/Bindings/mmc/renesas,sdhi.yaml @@ -67,6 +67,7 @@ properties: - renesas,sdhi-r8a779a0 # R-Car V3U - renesas,sdhi-r8a779f0 # R-Car S4-8 - renesas,sdhi-r8a779g0 # R-Car V4H + - renesas,sdhi-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-sdhi # R-Car Gen4 reg: diff --git a/dts/Bindings/mmc/snps,dwcmshc-sdhci.yaml b/dts/Bindings/mmc/snps,dwcmshc-sdhci.yaml index 42804d9552..4d3031d996 100644 --- a/dts/Bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/dts/Bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -19,6 +19,8 @@ properties: - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci + - sophgo,cv1800b-dwcmshc + - sophgo,sg2002-dwcmshc - thead,th1520-dwcmshc reg: diff --git a/dts/Bindings/mtd/atmel-nand.txt b/dts/Bindings/mtd/atmel-nand.txt index 50645828ac..4598930851 100644 --- a/dts/Bindings/mtd/atmel-nand.txt +++ b/dts/Bindings/mtd/atmel-nand.txt @@ -56,6 +56,7 @@ Required properties: "atmel,sama5d4-pmecc" "atmel,sama5d2-pmecc" "microchip,sam9x60-pmecc" + "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc" - reg: should contain 2 register ranges. The first one is pointing to the PMECC block, and the second one to the PMECC_ERRLOC block. diff --git a/dts/Bindings/mtd/brcm,brcmnand.yaml b/dts/Bindings/mtd/brcm,brcmnand.yaml index f57e96374e..064e840aea 100644 --- a/dts/Bindings/mtd/brcm,brcmnand.yaml +++ b/dts/Bindings/mtd/brcm,brcmnand.yaml @@ -9,6 +9,7 @@ title: Broadcom STB NAND Controller maintainers: - Brian Norris <computersforpeace@gmail.com> - Kamal Dasu <kdasu.kdev@gmail.com> + - William Zhang <william.zhang@broadcom.com> description: | The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND @@ -18,9 +19,10 @@ description: | supports basic PROGRAM and READ functions, among other features. This controller was originally designed for STB SoCs (BCM7xxx) but is now - available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and - iProc/Cygnus. Its history includes several similar (but not fully register - compatible) versions. + available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based + Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus. + Its history includes several similar (but not fully register compatible) + versions. -- Additional SoC-specific NAND controller properties -- @@ -53,7 +55,7 @@ properties: - brcm,brcmnand-v7.2 - brcm,brcmnand-v7.3 - const: brcm,brcmnand - - description: BCM63138 SoC-specific NAND controller + - description: BCMBCA SoC-specific NAND controller items: - const: brcm,nand-bcm63138 - enum: @@ -111,6 +113,13 @@ properties: earlier versions of this core that include WP type: boolean + brcm,wp-not-connected: + description: + Use this property when WP pin is not physically wired to the NAND chip. + Write protection feature cannot be used. By default, controller assumes + the pin is connected and feature is used. + $ref: /schemas/types.yaml#/definitions/flag + patternProperties: "^nand@[a-f0-9]$": type: object @@ -137,6 +146,15 @@ patternProperties: layout. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,nand-ecc-use-strap: + description: + This property requires the host system to get the ECC related + settings from the SoC NAND boot strap configuration instead of + the generic NAND ECC settings. This is a common hardware design + on BCMBCA based boards. This strap ECC option and generic NAND + ECC option can not be specified at the same time. + $ref: /schemas/types.yaml#/definitions/flag + unevaluatedProperties: false allOf: @@ -177,6 +195,8 @@ allOf: - const: iproc-idm - const: iproc-ext - if: + required: + - interrupts properties: interrupts: minItems: 2 @@ -184,12 +204,26 @@ allOf: required: - interrupt-names + - if: + patternProperties: + "^nand@[a-f0-9]$": + required: + - brcm,nand-ecc-use-strap + then: + patternProperties: + "^nand@[a-f0-9]$": + properties: + nand-ecc-strength: false + nand-ecc-step-size: false + nand-ecc-maximize: false + nand-ecc-algo: false + brcm,nand-oob-sector-size: false + unevaluatedProperties: false required: - reg - reg-names - - interrupts examples: - | diff --git a/dts/Bindings/mtd/davinci-nand.txt b/dts/Bindings/mtd/davinci-nand.txt index edebeae1f5..eb8e2ff4db 100644 --- a/dts/Bindings/mtd/davinci-nand.txt +++ b/dts/Bindings/mtd/davinci-nand.txt @@ -68,7 +68,7 @@ Deprecated properties: false. Nand device bindings may contain additional sub-nodes describing partitions of -the address space. See partition.txt for more detail. The NAND Flash timing +the address space. See mtd.yaml for more detail. The NAND Flash timing values must be programmed in the chip select’s node of AEMIF memory-controller (see Documentation/devicetree/bindings/memory-controllers/ davinci-aemif.txt). diff --git a/dts/Bindings/mtd/flctl-nand.txt b/dts/Bindings/mtd/flctl-nand.txt index 427f46dc60..51518399d7 100644 --- a/dts/Bindings/mtd/flctl-nand.txt +++ b/dts/Bindings/mtd/flctl-nand.txt @@ -15,7 +15,7 @@ The DMA fields are not used yet in the driver but are listed here for completing the bindings. The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. +address space. See mtd.yaml for more detail. Example: diff --git a/dts/Bindings/mtd/fsl-upm-nand.txt b/dts/Bindings/mtd/fsl-upm-nand.txt index 25f07c1f9e..530c017e01 100644 --- a/dts/Bindings/mtd/fsl-upm-nand.txt +++ b/dts/Bindings/mtd/fsl-upm-nand.txt @@ -22,7 +22,7 @@ Deprecated properties: (R/B# pins not connected). Each flash chip described may optionally contain additional sub-nodes -describing partitions of the address space. See partition.txt for more +describing partitions of the address space. See mtd.yaml for more detail. Examples: diff --git a/dts/Bindings/mtd/gpio-control-nand.txt b/dts/Bindings/mtd/gpio-control-nand.txt index 486a17d533..0edf55d47e 100644 --- a/dts/Bindings/mtd/gpio-control-nand.txt +++ b/dts/Bindings/mtd/gpio-control-nand.txt @@ -26,7 +26,7 @@ Optional properties: read to ensure that the GPIO accesses have completed. The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. +address space. See mtd.yaml for more detail. Examples: diff --git a/dts/Bindings/mtd/gpmi-nand.yaml b/dts/Bindings/mtd/gpmi-nand.yaml index ba086c3462..021c0da0b0 100644 --- a/dts/Bindings/mtd/gpmi-nand.yaml +++ b/dts/Bindings/mtd/gpmi-nand.yaml @@ -12,7 +12,7 @@ maintainers: description: | The GPMI nand controller provides an interface to control the NAND flash chips. The device tree may optionally contain sub-nodes - describing partitions of the address space. See partition.txt for + describing partitions of the address space. See mtd.yaml for more detail. properties: diff --git a/dts/Bindings/mtd/hisi504-nand.txt b/dts/Bindings/mtd/hisi504-nand.txt index 8963983ae7..362203e7d5 100644 --- a/dts/Bindings/mtd/hisi504-nand.txt +++ b/dts/Bindings/mtd/hisi504-nand.txt @@ -22,7 +22,7 @@ The following ECC strength and step size are currently supported: - nand-ecc-strength = <16>, nand-ecc-step-size = <1024> Flash chip may optionally contain additional sub-nodes describing partitions of -the address space. See partition.txt for more detail. +the address space. See mtd.yaml for more detail. Example: diff --git a/dts/Bindings/mtd/jedec,spi-nor.yaml b/dts/Bindings/mtd/jedec,spi-nor.yaml index 58f0cea160..6e3afb4292 100644 --- a/dts/Bindings/mtd/jedec,spi-nor.yaml +++ b/dts/Bindings/mtd/jedec,spi-nor.yaml @@ -52,6 +52,9 @@ properties: minItems: 1 maxItems: 2 + interrupts: + maxItems: 1 + m25p,fast-read: type: boolean description: diff --git a/dts/Bindings/mtd/mtd.yaml b/dts/Bindings/mtd/mtd.yaml index f322290ee5..ee442ecb11 100644 --- a/dts/Bindings/mtd/mtd.yaml +++ b/dts/Bindings/mtd/mtd.yaml @@ -10,6 +10,8 @@ maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> - Richard Weinberger <richard@nod.at> +select: false + properties: $nodename: pattern: "^(flash|.*sram|nand)(@.*)?$" diff --git a/dts/Bindings/mtd/nvidia-tegra20-nand.txt b/dts/Bindings/mtd/nvidia-tegra20-nand.txt index e737e5beb7..4a00ec2b25 100644 --- a/dts/Bindings/mtd/nvidia-tegra20-nand.txt +++ b/dts/Bindings/mtd/nvidia-tegra20-nand.txt @@ -39,7 +39,7 @@ Optional children node properties: - wp-gpios: GPIO specifier for the write protect pin. Optional child node of NAND chip nodes: -Partitions: see partition.txt +Partitions: see mtd.yaml Example: nand-controller@70008000 { diff --git a/dts/Bindings/mtd/orion-nand.txt b/dts/Bindings/mtd/orion-nand.txt index 2d6ab660e6..b9997b1f13 100644 --- a/dts/Bindings/mtd/orion-nand.txt +++ b/dts/Bindings/mtd/orion-nand.txt @@ -13,7 +13,7 @@ Optional properties: registers in usecs The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. +address space. See mtd.yaml for more detail. Example: diff --git a/dts/Bindings/mtd/partitions/linux,ubi.yaml b/dts/Bindings/mtd/partitions/linux,ubi.yaml new file mode 100644 index 0000000000..27e1ac1f25 --- /dev/null +++ b/dts/Bindings/mtd/partitions/linux,ubi.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/linux,ubi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unsorted Block Images + +description: | + UBI ("Unsorted Block Images") is a volume management system for raw + flash devices which manages multiple logical volumes on a single + physical flash device and spreads the I/O load (i.e wear-leveling) + across the whole flash chip. + +maintainers: + - Daniel Golle <daniel@makrotopia.org> + +allOf: + - $ref: partition.yaml# + +properties: + compatible: + const: linux,ubi + + volumes: + type: object + description: UBI Volumes + + patternProperties: + "^ubi-volume-.*$": + $ref: /schemas/mtd/partitions/ubi-volume.yaml# + + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x100000>; + label = "bootloader"; + read-only; + }; + + partition@100000 { + reg = <0x100000 0x1ff00000>; + label = "ubi"; + compatible = "linux,ubi"; + + volumes { + ubi-volume-caldata { + volid = <2>; + volname = "rf"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom@0 { + reg = <0x0 0x1000>; + }; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/mtd/partitions/ubi-volume.yaml b/dts/Bindings/mtd/partitions/ubi-volume.yaml new file mode 100644 index 0000000000..19736b2605 --- /dev/null +++ b/dts/Bindings/mtd/partitions/ubi-volume.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/ubi-volume.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UBI volume + +description: | + This binding describes a single UBI volume. Volumes can be matches either + by their ID or their name, or both. + +maintainers: + - Daniel Golle <daniel@makrotopia.org> + +properties: + volid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Match UBI volume ID + + volname: + $ref: /schemas/types.yaml#/definitions/string + description: + Match UBI volume ID + + nvmem-layout: + $ref: /schemas/nvmem/layouts/nvmem-layout.yaml# + description: + This container may reference an NVMEM layout parser. + +anyOf: + - required: + - volid + + - required: + - volname + +# This is a generic file other binding inherit from and extend +additionalProperties: true diff --git a/dts/Bindings/mtd/samsung-s3c2410.txt b/dts/Bindings/mtd/samsung-s3c2410.txt index 09815c40fc..6354553506 100644 --- a/dts/Bindings/mtd/samsung-s3c2410.txt +++ b/dts/Bindings/mtd/samsung-s3c2410.txt @@ -19,7 +19,7 @@ Optional child properties: Each child device node may optionally contain a 'partitions' sub-node, which further contains sub-nodes describing the flash partition mapping. -See partition.txt for more detail. +See mtd.yaml for more detail. Example: diff --git a/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml b/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml index e72cb5baca..b8ef9ba88e 100644 --- a/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml +++ b/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml @@ -14,10 +14,11 @@ properties: enum: - st,stm32mp15-fmc2 - st,stm32mp1-fmc2-nfc + - st,stm32mp25-fmc2-nfc reg: minItems: 6 - maxItems: 7 + maxItems: 12 interrupts: maxItems: 1 @@ -92,6 +93,28 @@ allOf: - description: Chip select 1 command - description: Chip select 1 address space + - if: + properties: + compatible: + contains: + const: st,stm32mp25-fmc2-nfc + then: + properties: + reg: + items: + - description: Chip select 0 data + - description: Chip select 0 command + - description: Chip select 0 address space + - description: Chip select 1 data + - description: Chip select 1 command + - description: Chip select 1 address space + - description: Chip select 2 data + - description: Chip select 2 command + - description: Chip select 2 address space + - description: Chip select 3 data + - description: Chip select 3 command + - description: Chip select 3 address space + required: - compatible - reg diff --git a/dts/Bindings/mux/mux-controller.yaml b/dts/Bindings/mux/mux-controller.yaml index 8b943082a2..571ad9e13e 100644 --- a/dts/Bindings/mux/mux-controller.yaml +++ b/dts/Bindings/mux/mux-controller.yaml @@ -74,7 +74,7 @@ select: properties: $nodename: - pattern: '^mux-controller(@.*|-[0-9a-f]+)?$' + pattern: '^mux-controller(@.*|-([0-9]|[1-9][0-9]+))?$' '#mux-control-cells': enum: [ 0, 1 ] diff --git a/dts/Bindings/net/bluetooth/qualcomm-bluetooth.yaml b/dts/Bindings/net/bluetooth/qualcomm-bluetooth.yaml index eba2f3026a..055a335188 100644 --- a/dts/Bindings/net/bluetooth/qualcomm-bluetooth.yaml +++ b/dts/Bindings/net/bluetooth/qualcomm-bluetooth.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Bluetooth Chips maintainers: - - Balakrishna Godavarthi <bgodavar@codeaurora.org> - - Rocky Liao <rjliao@codeaurora.org> + - Balakrishna Godavarthi <quic_bgodavar@quicinc.com> + - Rocky Liao <quic_rjliao@quicinc.com> description: This binding describes Qualcomm UART-attached bluetooth chips. @@ -94,6 +94,10 @@ properties: local-bd-address: true + qcom,local-bd-address-broken: + type: boolean + description: + boot firmware is incorrectly passing the address in big-endian order required: - compatible diff --git a/dts/Bindings/net/brcm,asp-v2.0.yaml b/dts/Bindings/net/brcm,asp-v2.0.yaml index 75d8138298..660e2ca42d 100644 --- a/dts/Bindings/net/brcm,asp-v2.0.yaml +++ b/dts/Bindings/net/brcm,asp-v2.0.yaml @@ -17,6 +17,10 @@ properties: oneOf: - items: - enum: + - brcm,bcm74165b0-asp + - const: brcm,asp-v2.2 + - items: + - enum: - brcm,bcm74165-asp - const: brcm,asp-v2.1 - items: diff --git a/dts/Bindings/net/brcm,unimac-mdio.yaml b/dts/Bindings/net/brcm,unimac-mdio.yaml index 6684810fcb..23dfe0838d 100644 --- a/dts/Bindings/net/brcm,unimac-mdio.yaml +++ b/dts/Bindings/net/brcm,unimac-mdio.yaml @@ -24,6 +24,7 @@ properties: - brcm,genet-mdio-v5 - brcm,asp-v2.0-mdio - brcm,asp-v2.1-mdio + - brcm,asp-v2.2-mdio - brcm,unimac-mdio reg: diff --git a/dts/Bindings/net/can/fsl,flexcan.yaml b/dts/Bindings/net/can/fsl,flexcan.yaml index 4162469c3c..f197d9b516 100644 --- a/dts/Bindings/net/can/fsl,flexcan.yaml +++ b/dts/Bindings/net/can/fsl,flexcan.yaml @@ -39,6 +39,9 @@ properties: - fsl,imx6sx-flexcan - const: fsl,imx6q-flexcan - items: + - const: fsl,imx95-flexcan + - const: fsl,imx93-flexcan + - items: - enum: - fsl,ls1028ar1-flexcan - const: fsl,lx2160ar1-flexcan diff --git a/dts/Bindings/net/can/microchip,mpfs-can.yaml b/dts/Bindings/net/can/microchip,mpfs-can.yaml index 45aa3de7cf..01e4d4a54d 100644 --- a/dts/Bindings/net/can/microchip,mpfs-can.yaml +++ b/dts/Bindings/net/can/microchip,mpfs-can.yaml @@ -24,7 +24,9 @@ properties: maxItems: 1 clocks: - maxItems: 1 + items: + - description: AHB peripheral clock + - description: CAN bus clock required: - compatible @@ -39,7 +41,7 @@ examples: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x2010c000 0x1000>; - clocks = <&clkcfg 17>; + clocks = <&clkcfg 17>, <&clkcfg 37>; interrupt-parent = <&plic>; interrupts = <56>; }; diff --git a/dts/Bindings/net/can/tcan4x5x.txt b/dts/Bindings/net/can/tcan4x5x.txt index 170e23f061..20c0572c98 100644 --- a/dts/Bindings/net/can/tcan4x5x.txt +++ b/dts/Bindings/net/can/tcan4x5x.txt @@ -28,6 +28,8 @@ Optional properties: available with tcan4552/4553. - device-wake-gpios: Wake up GPIO to wake up the TCAN device. Not available with tcan4552/4553. + - wakeup-source: Leave the chip running when suspended, and configure + the RX interrupt to wake up the device. Example: tcan4x5x: tcan4x5x@0 { @@ -42,4 +44,5 @@ tcan4x5x: tcan4x5x@0 { device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + wakeup-source; }; diff --git a/dts/Bindings/net/can/xilinx,can.yaml b/dts/Bindings/net/can/xilinx,can.yaml index 64d57c343e..8d4e5af6fd 100644 --- a/dts/Bindings/net/can/xilinx,can.yaml +++ b/dts/Bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc; }; - | diff --git a/dts/Bindings/net/cdns,macb.yaml b/dts/Bindings/net/cdns,macb.yaml index bf8894a025..2c71e2cf3a 100644 --- a/dts/Bindings/net/cdns,macb.yaml +++ b/dts/Bindings/net/cdns,macb.yaml @@ -59,6 +59,11 @@ properties: - cdns,gem # Generic - cdns,macb # Generic + - items: + - enum: + - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface + - const: microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface + reg: minItems: 1 items: diff --git a/dts/Bindings/net/dsa/ar9331.txt b/dts/Bindings/net/dsa/ar9331.txt deleted file mode 100644 index f824fdae0d..0000000000 --- a/dts/Bindings/net/dsa/ar9331.txt +++ /dev/null @@ -1,147 +0,0 @@ -Atheros AR9331 built-in switch -============================= - -It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal -MDIO bus. All PHYs are built-in as well. - -Required properties: - - - compatible: should be: "qca,ar9331-switch" - - reg: Address on the MII bus for the switch. - - resets : Must contain an entry for each entry in reset-names. - - reset-names : Must include the following entries: "switch" - - interrupt-parent: Phandle to the parent interrupt controller - - interrupts: IRQ line for the switch - - interrupt-controller: Indicates the switch is itself an interrupt - controller. This is used for the PHY interrupts. - - #interrupt-cells: must be 1 - - mdio: Container of PHY and devices on the switches MDIO bus. - -See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional -required and optional properties. -Examples: - -eth0: ethernet@19000000 { - compatible = "qca,ar9330-eth"; - reg = <0x19000000 0x200>; - interrupts = <4>; - - resets = <&rst 9>, <&rst 22>; - reset-names = "mac", "mdio"; - clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; - clock-names = "eth", "mdio"; - - phy-mode = "mii"; - phy-handle = <&phy_port4>; -}; - -eth1: ethernet@1a000000 { - compatible = "qca,ar9330-eth"; - reg = <0x1a000000 0x200>; - interrupts = <5>; - resets = <&rst 13>, <&rst 23>; - reset-names = "mac", "mdio"; - clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; - clock-names = "eth", "mdio"; - - phy-mode = "gmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch10: switch@10 { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "qca,ar9331-switch"; - reg = <0x10>; - resets = <&rst 8>; - reset-names = "switch"; - - interrupt-parent = <&miscintc>; - interrupts = <12>; - - interrupt-controller; - #interrupt-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - switch_port0: port@0 { - reg = <0x0>; - ethernet = <ð1>; - - phy-mode = "gmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - switch_port1: port@1 { - reg = <0x1>; - phy-handle = <&phy_port0>; - phy-mode = "internal"; - }; - - switch_port2: port@2 { - reg = <0x2>; - phy-handle = <&phy_port1>; - phy-mode = "internal"; - }; - - switch_port3: port@3 { - reg = <0x3>; - phy-handle = <&phy_port2>; - phy-mode = "internal"; - }; - - switch_port4: port@4 { - reg = <0x4>; - phy-handle = <&phy_port3>; - phy-mode = "internal"; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&switch10>; - - phy_port0: phy@0 { - reg = <0x0>; - interrupts = <0>; - }; - - phy_port1: phy@1 { - reg = <0x1>; - interrupts = <0>; - }; - - phy_port2: phy@2 { - reg = <0x2>; - interrupts = <0>; - }; - - phy_port3: phy@3 { - reg = <0x3>; - interrupts = <0>; - }; - - phy_port4: phy@4 { - reg = <0x4>; - interrupts = <0>; - }; - }; - }; - }; -}; diff --git a/dts/Bindings/net/dsa/microchip,ksz.yaml b/dts/Bindings/net/dsa/microchip,ksz.yaml index c963dc09e8..52acc15ebc 100644 --- a/dts/Bindings/net/dsa/microchip,ksz.yaml +++ b/dts/Bindings/net/dsa/microchip,ksz.yaml @@ -31,6 +31,7 @@ properties: - microchip,ksz9893 - microchip,ksz9563 - microchip,ksz8563 + - microchip,ksz8567 reset-gpios: description: diff --git a/dts/Bindings/net/dsa/qca,ar9331.yaml b/dts/Bindings/net/dsa/qca,ar9331.yaml new file mode 100644 index 0000000000..fd9ddc59d3 --- /dev/null +++ b/dts/Bindings/net/dsa/qca,ar9331.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/qca,ar9331.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros AR9331 built-in switch + +maintainers: + - Oleksij Rempel <o.rempel@pengutronix.de> + +description: + Qualcomm Atheros AR9331 is a switch built-in to Atheros AR9331 WiSoC and + addressable over internal MDIO bus. All PHYs are built-in as well. + +properties: + compatible: + const: qca,ar9331-switch + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + properties: + interrupt-parent: true + + patternProperties: + '(ethernet-)?phy@[0-4]+$': + type: object + unevaluatedProperties: false + + properties: + reg: true + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: switch + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - mdio + - ports + - resets + - reset-names + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch10: switch@10 { + compatible = "qca,ar9331-switch"; + reg = <0x10>; + + interrupt-parent = <&miscintc>; + interrupts = <12>; + interrupt-controller; + #interrupt-cells = <1>; + + resets = <&rst 8>; + reset-names = "switch"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + ethernet = <ð1>; + + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <0x1>; + phy-handle = <&phy_port0>; + phy-mode = "internal"; + }; + + port@2 { + reg = <0x2>; + phy-handle = <&phy_port1>; + phy-mode = "internal"; + }; + + port@3 { + reg = <0x3>; + phy-handle = <&phy_port2>; + phy-mode = "internal"; + }; + + port@4 { + reg = <0x4>; + phy-handle = <&phy_port3>; + phy-mode = "internal"; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&switch10>; + + phy_port0: ethernet-phy@0 { + reg = <0x0>; + interrupts = <0>; + }; + + phy_port1: ethernet-phy@1 { + reg = <0x1>; + interrupts = <0>; + }; + + phy_port2: ethernet-phy@2 { + reg = <0x2>; + interrupts = <0>; + }; + + phy_port3: ethernet-phy@3 { + reg = <0x3>; + interrupts = <0>; + }; + + phy_port4: ethernet-phy@4 { + reg = <0x4>; + interrupts = <0>; + }; + }; + }; + }; diff --git a/dts/Bindings/net/dsa/realtek.yaml b/dts/Bindings/net/dsa/realtek.yaml index cce692f57b..70b6bda3cf 100644 --- a/dts/Bindings/net/dsa/realtek.yaml +++ b/dts/Bindings/net/dsa/realtek.yaml @@ -59,6 +59,9 @@ properties: description: GPIO to be used to reset the whole device maxItems: 1 + resets: + maxItems: 1 + realtek,disable-leds: type: boolean description: | @@ -127,7 +130,6 @@ else: - mdc-gpios - mdio-gpios - mdio - - reset-gpios required: - compatible diff --git a/dts/Bindings/net/ethernet-controller.yaml b/dts/Bindings/net/ethernet-controller.yaml index d14d123ad7..b2785b0313 100644 --- a/dts/Bindings/net/ethernet-controller.yaml +++ b/dts/Bindings/net/ethernet-controller.yaml @@ -14,7 +14,6 @@ properties: pattern: "^ethernet(@.*)?$" label: - $ref: /schemas/types.yaml#/definitions/string description: Human readable label on a port of a box. local-mac-address: diff --git a/dts/Bindings/net/ethernet-phy-package.yaml b/dts/Bindings/net/ethernet-phy-package.yaml new file mode 100644 index 0000000000..e567101e6f --- /dev/null +++ b/dts/Bindings/net/ethernet-phy-package.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ethernet PHY Package Common Properties + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: + PHY packages are multi-port Ethernet PHY of the same family + and each Ethernet PHY is affected by the global configuration + of the PHY package. + + Each reg of the PHYs defined in the PHY package node is + absolute and describe the real address of the Ethernet PHY on + the MDIO bus. + +properties: + $nodename: + pattern: "^ethernet-phy-package@[a-f0-9]+$" + + reg: + minimum: 0 + maximum: 31 + description: + The base ID number for the PHY package. + Commonly the ID of the first PHY in the PHY package. + + Some PHY in the PHY package might be not defined but + still occupy ID on the device (just not attached to + anything) hence the PHY package reg might correspond + to a not attached PHY (offset 0). + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + ^ethernet-phy@[a-f0-9]+$: + $ref: ethernet-phy.yaml# + +required: + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: true diff --git a/dts/Bindings/net/fsl,fec.yaml b/dts/Bindings/net/fsl,fec.yaml index 8948a11c99..5536c06139 100644 --- a/dts/Bindings/net/fsl,fec.yaml +++ b/dts/Bindings/net/fsl,fec.yaml @@ -224,6 +224,9 @@ properties: Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. + iommus: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/net/nfc/ti,trf7970a.yaml b/dts/Bindings/net/nfc/ti,trf7970a.yaml index 9cc236ec42..d0332eb76a 100644 --- a/dts/Bindings/net/nfc/ti,trf7970a.yaml +++ b/dts/Bindings/net/nfc/ti,trf7970a.yaml @@ -73,7 +73,7 @@ examples: #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> - i2c { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/net/qca,qca808x.yaml b/dts/Bindings/net/qca,qca808x.yaml new file mode 100644 index 0000000000..e255265590 --- /dev/null +++ b/dts/Bindings/net/qca,qca808x.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qca,qca808x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros QCA808X PHY + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: + QCA808X PHYs can have up to 3 LEDs attached. + All 3 LEDs are disabled by default. + 2 LEDs have dedicated pins with the 3rd LED having the + double function of Interrupt LEDs/GPIO or additional LED. + + By default this special PIN is set to LED function. + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + compatible: + enum: + - ethernet-phy-id004d.d101 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-id004d.d101"; + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; + }; + }; diff --git a/dts/Bindings/net/qcom,ethqos.yaml b/dts/Bindings/net/qcom,ethqos.yaml index 7bdb412a01..69a337c7e3 100644 --- a/dts/Bindings/net/qcom,ethqos.yaml +++ b/dts/Bindings/net/qcom,ethqos.yaml @@ -37,12 +37,14 @@ properties: items: - description: Combined signal for various interrupt events - description: The interrupt that occurs when Rx exits the LPI state + - description: The interrupt that occurs when HW safety error triggered interrupt-names: minItems: 1 items: - const: macirq - - const: eth_lpi + - enum: [eth_lpi, sfty] + - const: sfty clocks: maxItems: 4 @@ -89,8 +91,9 @@ examples: <&gcc GCC_ETH_PTP_CLK>, <&gcc GCC_ETH_RGMII_CLK>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_lpi"; + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi", "sfty"; rx-fifo-depth = <4096>; tx-fifo-depth = <4096>; diff --git a/dts/Bindings/net/qcom,ipa.yaml b/dts/Bindings/net/qcom,ipa.yaml index c30218684c..53cae71d99 100644 --- a/dts/Bindings/net/qcom,ipa.yaml +++ b/dts/Bindings/net/qcom,ipa.yaml @@ -159,7 +159,7 @@ properties: when the AP (not the modem) performs early initialization. firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: If present, name (or relative path) of the file within the firmware search path containing the firmware image used when diff --git a/dts/Bindings/net/qcom,ipq4019-mdio.yaml b/dts/Bindings/net/qcom,ipq4019-mdio.yaml index 3407e909e8..0029e197a8 100644 --- a/dts/Bindings/net/qcom,ipq4019-mdio.yaml +++ b/dts/Bindings/net/qcom,ipq4019-mdio.yaml @@ -44,6 +44,21 @@ properties: items: - const: gcc_mdio_ahb_clk + clock-frequency: + description: + The MDIO bus clock that must be output by the MDIO bus hardware, if + absent, the default hardware values are used. + + MDC rate is feed by an external clock (fixed 100MHz) and is divider + internally. The default divider is /256 resulting in the default rate + applied of 390KHz. + + To follow 802.3 standard that instruct up to 2.5MHz by default, if + this property is not declared and the divider is set to /256, by + default 1.5625Mhz is select. + enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ] + default: 1562500 + required: - compatible - reg diff --git a/dts/Bindings/net/qcom,qca807x.yaml b/dts/Bindings/net/qcom,qca807x.yaml new file mode 100644 index 0000000000..7290024024 --- /dev/null +++ b/dts/Bindings/net/qcom,qca807x.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,qca807x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCA807x Ethernet PHY + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + - Robert Marko <robert.marko@sartura.hr> + +description: | + Qualcomm QCA8072/5 Ethernet PHY is PHY package of 2 or 5 + IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and + 1000BASE-T PHY-s. + + They feature 2 SerDes, one for PSGMII or QSGMII connection with + MAC, while second one is SGMII for connection to MAC or fiber. + + Both models have a combo port that supports 1000BASE-X and + 100BASE-FX fiber. + + Each PHY inside of QCA807x series has 4 digitally controlled + output only pins that natively drive LED-s for up to 2 attached + LEDs. Some vendor also use these 4 output for GPIO usage without + attaching LEDs. + + Note that output pins can be set to drive LEDs OR GPIO, mixed + definition are not accepted. + +$ref: ethernet-phy-package.yaml# + +properties: + compatible: + enum: + - qcom,qca8072-package + - qcom,qca8075-package + + qcom,package-mode: + description: | + PHY package can be configured in 3 mode following this table: + + First Serdes mode Second Serdes mode + Option 1 PSGMII for copper Disabled + ports 0-4 + Option 2 PSGMII for copper 1000BASE-X / 100BASE-FX + ports 0-4 + Option 3 QSGMII for copper SGMII for + ports 0-3 copper port 4 + + PSGMII mode (option 1 or 2) is configured dynamically based on + the presence of a connected SFP device. + $ref: /schemas/types.yaml#/definitions/string + enum: + - qsgmii + - psgmii + default: psgmii + + qcom,tx-drive-strength-milliwatt: + description: set the TX Amplifier value in mv. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [140, 160, 180, 200, 220, + 240, 260, 280, 300, 320, + 400, 500, 600] + default: 600 + +patternProperties: + ^ethernet-phy@[a-f0-9]+$: + $ref: ethernet-phy.yaml# + + properties: + qcom,dac-full-amplitude: + description: + Set Analog MDI driver amplitude to FULL. + + With this not defined, amplitude is set to DSP. + (amplitude is adjusted based on cable length) + + With this enabled and qcom,dac-full-bias-current + and qcom,dac-disable-bias-current-tweak disabled, + bias current is half. + type: boolean + + qcom,dac-full-bias-current: + description: + Set Analog MDI driver bias current to FULL. + + With this not defined, bias current is set to DSP. + (bias current is adjusted based on cable length) + + Actual bias current might be different with + qcom,dac-disable-bias-current-tweak disabled. + type: boolean + + qcom,dac-disable-bias-current-tweak: + description: | + Set Analog MDI driver bias current to disable tweak + to bias current. + + With this not defined, bias current tweak are enabled + by default. + + With this enabled the following tweak are NOT applied: + - With both FULL amplitude and FULL bias current: bias current + is set to half. + - With only DSP amplitude: bias current is set to half and + is set to 1/4 with cable < 10m. + - With DSP bias current (included both DSP amplitude and + DSP bias current): bias current is half the detected current + with cable < 10m. + type: boolean + + gpio-controller: true + + '#gpio-cells': + const: 2 + + if: + required: + - gpio-controller + then: + properties: + leds: false + + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy-package@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,qca8075-package"; + reg = <0>; + + qcom,package-mode = "qsgmii"; + + ethernet-phy@0 { + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + ethernet-phy@1 { + reg = <1>; + }; + + ethernet-phy@2 { + reg = <2>; + + gpio-controller; + #gpio-cells = <2>; + }; + + ethernet-phy@3 { + reg = <3>; + }; + + ethernet-phy@4 { + reg = <4>; + }; + }; + }; diff --git a/dts/Bindings/net/renesas,etheravb.yaml b/dts/Bindings/net/renesas,etheravb.yaml index 890f7858d0..de7ba7f345 100644 --- a/dts/Bindings/net/renesas,etheravb.yaml +++ b/dts/Bindings/net/renesas,etheravb.yaml @@ -46,6 +46,7 @@ properties: - enum: - renesas,etheravb-r8a779a0 # R-Car V3U - renesas,etheravb-r8a779g0 # R-Car V4H + - renesas,etheravb-r8a779h0 # R-Car V4M - const: renesas,etheravb-rcar-gen4 # R-Car Gen4 - items: diff --git a/dts/Bindings/net/snps,dwmac.yaml b/dts/Bindings/net/snps,dwmac.yaml index 5c2769dc68..6b0341a8e0 100644 --- a/dts/Bindings/net/snps,dwmac.yaml +++ b/dts/Bindings/net/snps,dwmac.yaml @@ -95,6 +95,7 @@ properties: - snps,dwmac-5.20 - snps,dwxgmac - snps,dwxgmac-2.10 + - starfive,jh7100-dwmac - starfive,jh7110-dwmac reg: @@ -107,13 +108,15 @@ properties: - description: Combined signal for various interrupt events - description: The interrupt to manage the remote wake-up packet detection - description: The interrupt that occurs when Rx exits the LPI state + - description: The interrupt that occurs when HW safety error triggered interrupt-names: minItems: 1 items: - const: macirq - - enum: [eth_wake_irq, eth_lpi] - - const: eth_lpi + - enum: [eth_wake_irq, eth_lpi, sfty] + - enum: [eth_wake_irq, eth_lpi, sfty] + - enum: [eth_wake_irq, eth_lpi, sfty] clocks: minItems: 1 @@ -144,10 +147,12 @@ properties: - description: AHB reset reset-names: - minItems: 1 - items: - - const: stmmaceth - - const: ahb + oneOf: + - items: + - enum: [stmmaceth, ahb] + - items: + - const: stmmaceth + - const: ahb power-domains: maxItems: 1 diff --git a/dts/Bindings/net/starfive,jh7110-dwmac.yaml b/dts/Bindings/net/starfive,jh7110-dwmac.yaml index 5e7cfbbebc..0d1962980f 100644 --- a/dts/Bindings/net/starfive,jh7110-dwmac.yaml +++ b/dts/Bindings/net/starfive,jh7110-dwmac.yaml @@ -16,16 +16,20 @@ select: compatible: contains: enum: + - starfive,jh7100-dwmac - starfive,jh7110-dwmac required: - compatible properties: compatible: - items: - - enum: - - starfive,jh7110-dwmac - - const: snps,dwmac-5.20 + oneOf: + - items: + - const: starfive,jh7100-dwmac + - const: snps,dwmac + - items: + - const: starfive,jh7110-dwmac + - const: snps,dwmac-5.20 reg: maxItems: 1 @@ -46,24 +50,6 @@ properties: - const: tx - const: gtx - interrupts: - minItems: 3 - maxItems: 3 - - interrupt-names: - minItems: 3 - maxItems: 3 - - resets: - items: - - description: MAC Reset signal. - - description: AHB Reset signal. - - reset-names: - items: - - const: stmmaceth - - const: ahb - starfive,tx-use-rgmii-clk: description: Tx clock is provided by external rgmii clock. @@ -94,6 +80,48 @@ required: allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: starfive,jh7100-dwmac + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + + interrupt-names: + minItems: 2 + maxItems: 2 + + resets: + maxItems: 1 + + reset-names: + const: ahb + + - if: + properties: + compatible: + contains: + const: starfive,jh7110-dwmac + then: + properties: + interrupts: + minItems: 3 + maxItems: 3 + + interrupt-names: + minItems: 3 + maxItems: 3 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + unevaluatedProperties: false examples: diff --git a/dts/Bindings/net/ti,cpsw-switch.yaml b/dts/Bindings/net/ti,cpsw-switch.yaml index f07ae3173b..d5bd93ee4d 100644 --- a/dts/Bindings/net/ti,cpsw-switch.yaml +++ b/dts/Bindings/net/ti,cpsw-switch.yaml @@ -7,8 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI SoC Ethernet Switch Controller (CPSW) maintainers: - - Grygorii Strashko <grygorii.strashko@ti.com> - - Sekhar Nori <nsekhar@ti.com> + - Siddharth Vadapalli <s-vadapalli@ti.com> + - Ravi Gunasekaran <r-gunasekaran@ti.com> + - Roger Quadros <rogerq@kernel.org> description: The 3-port switch gigabit ethernet subsystem provides ethernet packet diff --git a/dts/Bindings/net/ti,dp83822.yaml b/dts/Bindings/net/ti,dp83822.yaml index db74474207..784866ea39 100644 --- a/dts/Bindings/net/ti,dp83822.yaml +++ b/dts/Bindings/net/ti,dp83822.yaml @@ -62,6 +62,40 @@ properties: for the PHY. The internal delay for the PHY is fixed to 3.5ns relative to transmit data. + ti,cfg-dac-minus-one-bp: + description: | + DP83826 PHY only. + Sets the voltage ratio (with respect to the nominal value) + of the logical level -1 for the MLT-3 encoded TX data. + enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000, + 10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000] + default: 10000 + + ti,cfg-dac-plus-one-bp: + description: | + DP83826 PHY only. + Sets the voltage ratio (with respect to the nominal value) + of the logical level +1 for the MLT-3 encoded TX data. + enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000, + 10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000] + default: 10000 + + ti,rmii-mode: + description: | + If present, select the RMII operation mode. Two modes are + available: + - RMII master, where the PHY outputs a 50MHz reference clock which can + be connected to the MAC. + - RMII slave, where the PHY expects a 50MHz reference clock input + shared with the MAC. + The RMII operation mode can also be configured by its straps. + If the strap pin is not set correctly or not set at all, then this can be + used to configure it. + $ref: /schemas/types.yaml#/definitions/string + enum: + - master + - slave + required: - reg diff --git a/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml b/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml index c9c25132d1..73ed5951d2 100644 --- a/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -7,8 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) maintainers: - - Grygorii Strashko <grygorii.strashko@ti.com> - - Sekhar Nori <nsekhar@ti.com> + - Siddharth Vadapalli <s-vadapalli@ti.com> + - Ravi Gunasekaran <r-gunasekaran@ti.com> + - Roger Quadros <rogerq@kernel.org> description: The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports diff --git a/dts/Bindings/net/ti,k3-am654-cpts.yaml b/dts/Bindings/net/ti,k3-am654-cpts.yaml index 3e910d3b24..b1c8753257 100644 --- a/dts/Bindings/net/ti,k3-am654-cpts.yaml +++ b/dts/Bindings/net/ti,k3-am654-cpts.yaml @@ -7,8 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module maintainers: - - Grygorii Strashko <grygorii.strashko@ti.com> - - Sekhar Nori <nsekhar@ti.com> + - Siddharth Vadapalli <s-vadapalli@ti.com> + - Ravi Gunasekaran <r-gunasekaran@ti.com> + - Roger Quadros <rogerq@kernel.org> description: |+ The TI AM654x/J721E CPTS module is used to facilitate host control of time diff --git a/dts/Bindings/net/wireless/mediatek,mt76.yaml b/dts/Bindings/net/wireless/mediatek,mt76.yaml index 252207adbc..eabceb8495 100644 --- a/dts/Bindings/net/wireless/mediatek,mt76.yaml +++ b/dts/Bindings/net/wireless/mediatek,mt76.yaml @@ -19,9 +19,6 @@ description: | Alternatively, it can specify the wireless part of the MT7628/MT7688 or MT7622/MT7986 SoC. -allOf: - - $ref: ieee80211.yaml# - properties: compatible: enum: @@ -38,7 +35,12 @@ properties: MT7986 should contain 3 regions consys, dcm, and sku, in this order. interrupts: - maxItems: 1 + minItems: 1 + items: + - description: major interrupt for rings + - description: additional interrupt for ring 19 + - description: additional interrupt for ring 4 + - description: additional interrupt for ring 5 power-domains: maxItems: 1 @@ -217,6 +219,24 @@ required: - compatible - reg +allOf: + - $ref: ieee80211.yaml# + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt7981-wmac + - mediatek,mt7986-wmac + then: + properties: + interrupts: + minItems: 4 + else: + properties: + interrupts: + maxItems: 1 + unevaluatedProperties: false examples: @@ -293,7 +313,10 @@ examples: reg = <0x18000000 0x1000000>, <0x10003000 0x1000>, <0x11d10000 0x1000>; - interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topckgen 50>, <&topckgen 62>; clock-names = "mcu", "ap2conn"; diff --git a/dts/Bindings/net/wireless/qcom,ath10k.yaml b/dts/Bindings/net/wireless/qcom,ath10k.yaml index 7758a55dd3..9b3ef4bc37 100644 --- a/dts/Bindings/net/wireless/qcom,ath10k.yaml +++ b/dts/Bindings/net/wireless/qcom,ath10k.yaml @@ -8,6 +8,7 @@ title: Qualcomm Technologies ath10k wireless devices maintainers: - Kalle Valo <kvalo@kernel.org> + - Jeff Johnson <jjohnson@kernel.org> description: Qualcomm Technologies, Inc. IEEE 802.11ac devices. diff --git a/dts/Bindings/net/wireless/qcom,ath11k-pci.yaml b/dts/Bindings/net/wireless/qcom,ath11k-pci.yaml index 817f02a8b4..41d023797d 100644 --- a/dts/Bindings/net/wireless/qcom,ath11k-pci.yaml +++ b/dts/Bindings/net/wireless/qcom,ath11k-pci.yaml @@ -9,6 +9,7 @@ title: Qualcomm Technologies ath11k wireless devices (PCIe) maintainers: - Kalle Valo <kvalo@kernel.org> + - Jeff Johnson <jjohnson@kernel.org> description: | Qualcomm Technologies IEEE 802.11ax PCIe devices diff --git a/dts/Bindings/net/wireless/qcom,ath11k.yaml b/dts/Bindings/net/wireless/qcom,ath11k.yaml index 7d5f982a3d..672282cdfc 100644 --- a/dts/Bindings/net/wireless/qcom,ath11k.yaml +++ b/dts/Bindings/net/wireless/qcom,ath11k.yaml @@ -9,6 +9,7 @@ title: Qualcomm Technologies ath11k wireless devices maintainers: - Kalle Valo <kvalo@kernel.org> + - Jeff Johnson <jjohnson@kernel.org> description: | These are dt entries for Qualcomm Technologies, Inc. IEEE 802.11ax diff --git a/dts/Bindings/nvmem/layouts/fixed-cell.yaml b/dts/Bindings/nvmem/layouts/fixed-cell.yaml index ac2381e660..8b3826243d 100644 --- a/dts/Bindings/nvmem/layouts/fixed-cell.yaml +++ b/dts/Bindings/nvmem/layouts/fixed-cell.yaml @@ -36,20 +36,18 @@ properties: allOf: - if: + properties: + compatible: + contains: + const: mac-base required: [ compatible ] then: - if: - properties: - compatible: - contains: - const: mac-base - then: - properties: - "#nvmem-cell-cells": - description: The first argument is a MAC address offset. - const: 1 - required: - - "#nvmem-cell-cells" + properties: + "#nvmem-cell-cells": + description: The first argument is a MAC address offset. + const: 1 + required: + - "#nvmem-cell-cells" required: - reg diff --git a/dts/Bindings/nvmem/nvmem-provider.yaml b/dts/Bindings/nvmem/nvmem-provider.yaml new file mode 100644 index 0000000000..4009a9a038 --- /dev/null +++ b/dts/Bindings/nvmem/nvmem-provider.yaml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/nvmem-provider.yaml# +$schema: http://devicetree.org/meta-schemas/base.yaml# + +title: NVMEM (Non Volatile Memory) Provider + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +select: true + +properties: + '#nvmem-cell-cells': + enum: [0, 1] + +additionalProperties: true diff --git a/dts/Bindings/nvmem/xlnx,zynqmp-nvmem.txt b/dts/Bindings/nvmem/xlnx,zynqmp-nvmem.txt deleted file mode 100644 index 4881561b3a..0000000000 --- a/dts/Bindings/nvmem/xlnx,zynqmp-nvmem.txt +++ /dev/null @@ -1,46 +0,0 @@ --------------------------------------------------------------------------- -= Zynq UltraScale+ MPSoC nvmem firmware driver binding = --------------------------------------------------------------------------- -The nvmem_firmware node provides access to the hardware related data -like soc revision, IDCODE... etc, By using the firmware interface. - -Required properties: -- compatible: should be "xlnx,zynqmp-nvmem-fw" - -= Data cells = -Are child nodes of silicon id, bindings of which as described in -bindings/nvmem/nvmem.txt - -------- - Example -------- -firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - method = "smc"; - - nvmem_firmware { - compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - soc_revision: soc_revision { - reg = <0x0 0x4>; - }; - }; - }; -}; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -For example: - pcap { - ... - - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; - - ... - }; diff --git a/dts/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml b/dts/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml new file mode 100644 index 0000000000..917c40d5c3 --- /dev/null +++ b/dts/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/xlnx,zynqmp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zynq UltraScale+ MPSoC Non Volatile Memory interface + +description: | + The ZynqMP MPSoC provides access to the hardware related data + like SOC revision, IDCODE and specific purpose efuses. + +maintainers: + - Kalyani Akula <kalyani.akula@amd.com> + - Praveen Teja Kundanala <praveen.teja.kundanala@amd.com> + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + const: xlnx,zynqmp-nvmem-fw + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + nvmem { + compatible = "xlnx,zynqmp-nvmem-fw"; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc-revision@0 { + reg = <0x0 0x4>; + }; + }; + }; diff --git a/dts/Bindings/opp/opp-v2-base.yaml b/dts/Bindings/opp/opp-v2-base.yaml index e2f8f7af3c..b1bb87c865 100644 --- a/dts/Bindings/opp/opp-v2-base.yaml +++ b/dts/Bindings/opp/opp-v2-base.yaml @@ -57,8 +57,6 @@ patternProperties: specific binding. minItems: 1 maxItems: 32 - items: - maxItems: 1 opp-microvolt: description: | diff --git a/dts/Bindings/pci/fsl,imx6q-pcie-common.yaml b/dts/Bindings/pci/fsl,imx6q-pcie-common.yaml index d91b639ae7..a8b34f58f8 100644 --- a/dts/Bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/dts/Bindings/pci/fsl,imx6q-pcie-common.yaml @@ -150,22 +150,6 @@ allOf: - {} - const: pcie_phy - const: pcie_aux - - if: - properties: - compatible: - not: - contains: - enum: - - fsl,imx6sx-pcie - - fsl,imx8mq-pcie - - fsl,imx6sx-pcie-ep - - fsl,imx8mq-pcie-ep - then: - properties: - clocks: - maxItems: 3 - clock-names: - maxItems: 3 - if: properties: @@ -223,6 +207,7 @@ allOf: - fsl,imx6sx-pcie - fsl,imx6q-pcie - fsl,imx6qp-pcie + - fsl,imx95-pcie - fsl,imx6sx-pcie-ep - fsl,imx6q-pcie-ep - fsl,imx6qp-pcie-ep diff --git a/dts/Bindings/pci/fsl,imx6q-pcie-ep.yaml b/dts/Bindings/pci/fsl,imx6q-pcie-ep.yaml index ee155ed5f1..a06f75df84 100644 --- a/dts/Bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/dts/Bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -22,14 +22,7 @@ properties: - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep - fsl,imx8mp-pcie-ep - - reg: - minItems: 2 - - reg-names: - items: - - const: dbi - - const: addr_space + - fsl,imx95-pcie-ep clocks: minItems: 3 @@ -66,7 +59,44 @@ allOf: properties: compatible: enum: + - fsl,imx8mm-pcie-ep + - fsl,imx8mq-pcie-ep + - fsl,imx8mp-pcie-ep + then: + properties: + reg: + minItems: 2 + maxItems: 2 + reg-names: + items: + - const: dbi + - const: addr_space + + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie-ep + then: + properties: + reg: + minItems: 6 + maxItems: 6 + reg-names: + items: + - const: dbi + - const: atu + - const: dbi2 + - const: app + - const: dma + - const: addr_space + + - if: + properties: + compatible: + enum: - fsl,imx8mq-pcie-ep + - fsl,imx95-pcie-ep then: properties: clocks: diff --git a/dts/Bindings/pci/fsl,imx6q-pcie.yaml b/dts/Bindings/pci/fsl,imx6q-pcie.yaml index 81bbb8728f..8b8d77b115 100644 --- a/dts/Bindings/pci/fsl,imx6q-pcie.yaml +++ b/dts/Bindings/pci/fsl,imx6q-pcie.yaml @@ -29,16 +29,7 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie - - reg: - items: - - description: Data Bus Interface (DBI) registers. - - description: PCIe configuration space region. - - reg-names: - items: - - const: dbi - - const: config + - fsl,imx95-pcie clocks: minItems: 3 @@ -94,6 +85,43 @@ allOf: properties: compatible: enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mq-pcie + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: dbi + - const: config + + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + items: + - const: dbi + - const: config + - const: atu + - const: app + + - if: + properties: + compatible: + enum: - fsl,imx6sx-pcie then: properties: @@ -111,6 +139,7 @@ allOf: compatible: enum: - fsl,imx8mq-pcie + - fsl,imx95-pcie then: properties: clocks: diff --git a/dts/Bindings/pci/qcom,pcie-common.yaml b/dts/Bindings/pci/qcom,pcie-common.yaml new file mode 100644 index 0000000000..0d1b23523f --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-common.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCI Express Root Complex Common Properties + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +properties: + reg: + minItems: 4 + maxItems: 6 + + reg-names: + minItems: 4 + maxItems: 6 + + interrupts: + minItems: 1 + maxItems: 8 + + interrupt-names: + minItems: 1 + maxItems: 8 + + iommu-map: + minItems: 1 + maxItems: 16 + + clocks: + minItems: 3 + maxItems: 13 + + clock-names: + minItems: 3 + maxItems: 13 + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: pcie-mem + - const: cpu-pcie + + phys: + maxItems: 1 + + phy-names: + items: + - const: pciephy + + power-domains: + maxItems: 1 + + required-opps: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 12 + + reset-names: + minItems: 1 + maxItems: 12 + + perst-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + +required: + - reg + - reg-names + - interrupt-map-mask + - interrupt-map + - clocks + - clock-names + +anyOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +additionalProperties: true diff --git a/dts/Bindings/pci/qcom,pcie-sa8775p.yaml b/dts/Bindings/pci/qcom,pcie-sa8775p.yaml new file mode 100644 index 0000000000..efde49d1be --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-sa8775p.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8775p PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sa8775p + + reg: + minItems: 6 + maxItems: 6 + + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 5 + maxItems: 5 + + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +required: + - interconnects + - interconnect-names + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + dma-coherent; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie-sc7280.yaml b/dts/Bindings/pci/qcom,pcie-sc7280.yaml new file mode 100644 index 0000000000..634da24ec3 --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-sc7280.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sc7280 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 13 + maxItems: 13 + + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: msi + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + + vddpe-3v3-supply: + description: PCIe endpoint power supply + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c08000 { + compatible = "qcom,pcie-sc7280"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <1>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie1_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + dma-coherent; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_n>; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&pp3300_ssd>; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie-sc8180x.yaml b/dts/Bindings/pci/qcom,pcie-sc8180x.yaml new file mode 100644 index 0000000000..baf1813ec0 --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-sc8180x.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8180x PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sc8180x + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc8180x.h> + #include <dt-bindings/interconnect/qcom,sc8180x.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + dma-coherent; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie-sc8280xp.yaml b/dts/Bindings/pci/qcom,pcie-sc8280xp.yaml new file mode 100644 index 0000000000..25c9f13ae9 --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-sc8280xp.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sa8540p + - qcom,pcie-sc8280xp + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr_4 # NoC aggregate 4 clock + - const: noc_aggr_south_sf # NoC aggregate South SF clock + - const: cnoc_qx # Configuration NoC QX clock + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + + vddpe-3v3-supply: + description: A phandle to the PCIe endpoint power supply + +required: + - interconnects + - interconnect-names + +allOf: + - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,sc8280xp.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c20000 { + compatible = "qcom,pcie-sc8280xp"; + reg = <0x0 0x01c20000 0x0 0x3000>, + <0x0 0x3c000000 0x0 0xf1d>, + <0x0 0x3c000f20 0x0 0xa8>, + <0x0 0x3c001000 0x0 0x1000>, + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <2>; + num-lanes = <4>; + + #address-cells = <3>; + #size-cells = <2>; + + assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; + assigned-clock-rates = <19200000>; + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf"; + + dma-coherent; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie2a_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie2a_default>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_2A_GDSC>; + + resets = <&gcc GCC_PCIE_2A_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&vreg_nvme>; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie-sm8150.yaml b/dts/Bindings/pci/qcom,pcie-sm8150.yaml new file mode 100644 index 0000000000..9d569644fd --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-sm8150.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8150 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ref # REFERENCE clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8150.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,sm8150.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@1c00000 { + compatible = "qcom,pcie-sm8150"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ref"; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie-sm8250.yaml b/dts/Bindings/pci/qcom,pcie-sm8250.yaml new file mode 100644 index 0000000000..4d060bce6f --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-sm8250.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8250 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + # Unfortunately the "optional" ref clock is used in the middle of the list + oneOf: + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8250.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,sm8250.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8250"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + dma-coherent; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie-sm8350.yaml b/dts/Bindings/pci/qcom,pcie-sm8350.yaml new file mode 100644 index 0000000000..9eb6e457b0 --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-sm8350.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8350 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8350.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,sm8350.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1", + "aggre0"; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie-sm8450.yaml b/dts/Bindings/pci/qcom,pcie-sm8450.yaml new file mode 100644 index 0000000000..1496d6993a --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-sm8450.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 11 + maxItems: 12 + + clock-names: + minItems: 11 + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8450-pcie0"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + msi-map = <0x0 &gic_its 0x5981 0x1>, + <0x100 &gic_its 0x5980 0x1>; + msi-map-mask = <0xff00>; + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie-sm8550.yaml b/dts/Bindings/pci/qcom,pcie-sm8550.yaml new file mode 100644 index 0000000000..24cb386735 --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-sm8550.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + oneOf: + - const: qcom,pcie-sm8550 + - items: + - enum: + - qcom,pcie-sm8650 + - const: qcom,pcie-sm8550 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 7 + maxItems: 8 + + clock-names: + minItems: 7 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,pcie-sm8550"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr"; + + dma-coherent; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc PCIE_0_GDSC>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie-x1e80100.yaml b/dts/Bindings/pci/qcom,pcie-x1e80100.yaml new file mode 100644 index 0000000000..1074310a8e --- /dev/null +++ b/dts/Bindings/pci/qcom,pcie-x1e80100.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-x1e80100 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 7 + maxItems: 7 + + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,x1e80100-gcc.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c08000 { + compatible = "qcom,pcie-x1e80100"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x7c000000 0 0xf1d>, + <0 0x7c000f40 0 0xa8>, + <0 0x7c001000 0 0x1000>, + <0 0x7c100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + dma-coherent; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + phys = <&pcie4_phy>; + phy-names = "pciephy"; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc GCC_PCIE_4_GDSC>; + + resets = <&gcc GCC_PCIE_4_BCR>; + reset-names = "pci"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/Bindings/pci/qcom,pcie.yaml b/dts/Bindings/pci/qcom,pcie.yaml index a93ab3b540..cf9a6910b5 100644 --- a/dts/Bindings/pci/qcom,pcie.yaml +++ b/dts/Bindings/pci/qcom,pcie.yaml @@ -28,23 +28,8 @@ properties: - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p - - qcom,pcie-sa8775p - - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 - - items: - - enum: - - qcom,pcie-sm8650 - - const: qcom,pcie-sm8550 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -106,9 +91,6 @@ properties: vdda_refclk-supply: description: A phandle to the core analog power supply for IC which generates reference clock - vddpe-3v3-supply: - description: A phandle to the PCIe endpoint power supply - phys: maxItems: 1 @@ -123,6 +105,9 @@ properties: description: GPIO controlled connection to PERST# signal maxItems: 1 + required-opps: + maxItems: 1 + wake-gpios: description: GPIO controlled connection to WAKE# signal maxItems: 1 @@ -143,7 +128,6 @@ anyOf: - "#interrupt-cells" - required: - msi-map - - msi-map-mask allOf: - $ref: /schemas/pci/pci-bus.yaml# @@ -217,16 +201,7 @@ allOf: compatible: contains: enum: - - qcom,pcie-sa8775p - - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdx55 - - qcom,pcie-sm8250 - - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: properties: reg: @@ -456,65 +431,6 @@ allOf: compatible: contains: enum: - - qcom,pcie-sc7280 - then: - properties: - clocks: - minItems: 13 - maxItems: 13 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sc8180x - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ref # REFERENCE clock - - const: tbu # PCIe TBU clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - qcom,pcie-sdm845 then: oneOf: @@ -558,229 +474,6 @@ allOf: compatible: contains: enum: - - qcom,pcie-sm8150 - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ref # REFERENCE clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8250 - then: - oneOf: - # Unfortunately the "optional" ref clock is used in the middle of the list - - properties: - clocks: - minItems: 9 - maxItems: 9 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ref # REFERENCE clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - properties: - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8350 - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie0 - then: - properties: - clocks: - minItems: 12 - maxItems: 12 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie1 - then: - properties: - clocks: - minItems: 11 - maxItems: 11 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8550 - then: - properties: - clocks: - minItems: 7 - maxItems: 8 - clock-names: - minItems: 7 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr # Aggre NoC PCIe AXI clock - - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock - resets: - minItems: 1 - maxItems: 2 - reset-names: - minItems: 1 - items: - - const: pci # PCIe core reset - - const: link_down # PCIe link down reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8540p - - qcom,pcie-sc8280xp - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr_4 # NoC aggregate 4 clock - - const: noc_aggr_south_sf # NoC aggregate South SF clock - - const: cnoc_qx # Configuration NoC QX clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - qcom,pcie-sdx55 then: properties: @@ -803,43 +496,6 @@ allOf: - const: pci # PCIe core reset - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8775p - then: - properties: - clocks: - minItems: 5 - maxItems: 5 - clock-names: - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8540p - - qcom,pcie-sa8775p - - qcom,pcie-sc8280xp - then: - required: - - interconnects - - interconnect-names - - - if: not: properties: compatible: @@ -874,16 +530,7 @@ allOf: contains: enum: - qcom,pcie-msm8996 - - qcom,pcie-sa8775p - - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - qcom,pcie-sdm845 - - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: oneOf: - properties: @@ -911,24 +558,6 @@ allOf: compatible: contains: enum: - - qcom,pcie-sc8280xp - then: - properties: - interrupts: - minItems: 4 - maxItems: 4 - interrupt-names: - items: - - const: msi0 - - const: msi1 - - const: msi2 - - const: msi3 - - - if: - properties: - compatible: - contains: - enum: - qcom,pcie-apq8064 - qcom,pcie-apq8084 - qcom,pcie-ipq4019 @@ -938,7 +567,6 @@ allOf: - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p then: properties: interrupts: diff --git a/dts/Bindings/perf/arm,coresight-pmu.yaml b/dts/Bindings/perf/arm,coresight-pmu.yaml new file mode 100644 index 0000000000..985b62990f --- /dev/null +++ b/dts/Bindings/perf/arm,coresight-pmu.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Coresight Performance Monitoring Unit Architecture + +maintainers: + - Robin Murphy <robin.murphy@arm.com> + +properties: + compatible: + const: arm,coresight-pmu + + reg: + items: + - description: Register page 0 + - description: Register page 1, if the PMU implements the dual-page extension + minItems: 1 + + interrupts: + items: + - description: Overflow interrupt + + cpus: + description: If the PMU is associated with a particular CPU or subset of CPUs, + array of phandles to the appropriate CPU node(s) + + reg-io-width: + description: Granularity at which PMU register accesses are single-copy atomic + default: 4 + enum: [4, 8] + +required: + - compatible + - reg + +additionalProperties: false diff --git a/dts/Bindings/perf/starfive,jh8100-starlink-pmu.yaml b/dts/Bindings/perf/starfive,jh8100-starlink-pmu.yaml new file mode 100644 index 0000000000..915c6b8140 --- /dev/null +++ b/dts/Bindings/perf/starfive,jh8100-starlink-pmu.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 StarLink PMU + +maintainers: + - Ji Sheng Teoh <jisheng.teoh@starfivetech.com> + +description: + StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a + shared L3 memory system. The PMU support overflow interrupt, up to + 16 programmable 64bit event counters, and an independent 64bit cycle + counter. StarFive's JH8100 StarLink PMU is accessed via MMIO. + +properties: + compatible: + const: starfive,jh8100-starlink-pmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pmu@12900000 { + compatible = "starfive,jh8100-starlink-pmu"; + reg = <0x0 0x12900000 0x0 0x10000>; + interrupts = <34>; + }; + }; diff --git a/dts/Bindings/phy/mediatek,mt8365-csi-rx.yaml b/dts/Bindings/phy/mediatek,mt8365-csi-rx.yaml new file mode 100644 index 0000000000..2127a5732f --- /dev/null +++ b/dts/Bindings/phy/mediatek,mt8365-csi-rx.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek, BayLibre +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Sensor Interface MIPI CSI CD-PHY + +maintainers: + - Julien Stephan <jstephan@baylibre.com> + - Andy Hsieh <andy.hsieh@mediatek.com> + +description: + The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2 + receivers. The number of PHYs depends on the SoC model. + Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only + capable. + +properties: + compatible: + enum: + - mediatek,mt8365-csi-rx + + reg: + maxItems: 1 + + num-lanes: + enum: [2, 3, 4] + + '#phy-cells': + enum: [0, 1] + description: | + If the PHY doesn't support mode selection then #phy-cells must be 0 and + PHY mode is described using phy-type property. + If the PHY supports mode selection, then #phy-cells must be 1 and mode + is set in the PHY cells. Supported modes are: + - PHY_TYPE_DPHY + - PHY_TYPE_CPHY + See include/dt-bindings/phy/phy.h for constants. + + phy-type: + description: + If the PHY doesn't support mode selection then this set the operating mode. + See include/dt-bindings/phy/phy.h for constants. + const: 10 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - num-lanes + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/phy/phy.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + csi0_rx: phy@11c10000 { + compatible = "mediatek,mt8365-csi-rx"; + reg = <0 0x11c10000 0 0x2000>; + num-lanes = <2>; + #phy-cells = <1>; + }; + + csi1_rx: phy@11c12000 { + compatible = "mediatek,mt8365-csi-rx"; + reg = <0 0x11c12000 0 0x2000>; + phy-type = <PHY_TYPE_DPHY>; + num-lanes = <2>; + #phy-cells = <0>; + }; + }; +... diff --git a/dts/Bindings/phy/phy-cadence-torrent.yaml b/dts/Bindings/phy/phy-cadence-torrent.yaml index dfb31314fa..15dc8efe6f 100644 --- a/dts/Bindings/phy/phy-cadence-torrent.yaml +++ b/dts/Bindings/phy/phy-cadence-torrent.yaml @@ -20,6 +20,7 @@ properties: compatible: enum: - cdns,torrent-phy + - ti,j7200-serdes-10g - ti,j721e-serdes-10g '#address-cells': @@ -35,14 +36,18 @@ properties: minItems: 1 maxItems: 2 description: - PHY reference clock for 1 item. Must contain an entry in clock-names. - Optional Parent to enable output reference clock. + PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1). + pll1_refclk is optional and used for multi-protocol configurations requiring + separate reference clock for each protocol. + Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used. + Optional parent clock (phy_en_refclk) to enable a reference clock output feature + on some platforms to output either derived or received reference clock. clock-names: minItems: 1 items: - const: refclk - - const: phy_en_refclk + - enum: [ pll1_refclk, phy_en_refclk ] reg: minItems: 1 diff --git a/dts/Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/dts/Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml new file mode 100644 index 0000000000..f1f4e4f833 --- /dev/null +++ b/dts/Bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (USB, MSM8998) + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + The QMP PHY controller supports physical layer functionality for USB-C on + several Qualcomm chipsets. + +properties: + compatible: + enum: + - qcom,msm8998-qmp-usb3-phy + - qcom,qcm2290-qmp-usb3-phy + - qcom,sdm660-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: phy_phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + + orientation-switch: + description: + Flag the PHY as possible handler of USB Type-C orientation switching + type: boolean + + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + description: Clamp register present in the TCSR + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the PHY + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the USB controller + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - clock-output-names + - "#phy-cells" + - qcom,tcsr-reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-usb3-phy + - qcom,sdm660-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: ref + - const: cfg_ahb + - const: pipe + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: cfg_ahb + - const: ref + - const: com_aux + - const: pipe + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8998.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + phy@c010000 { + compatible = "qcom,msm8998-qmp-usb3-phy"; + reg = <0x0c010000 0x1000>; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3_phy_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + + orientation-switch; + + qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&pmic_typec_mux_in>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; + }; diff --git a/dts/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/dts/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 6c03f2d5fc..ba966a78a1 100644 --- a/dts/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/dts/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -38,6 +38,8 @@ properties: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy reg: minItems: 1 @@ -151,6 +153,8 @@ allOf: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy then: properties: clocks: @@ -194,6 +198,8 @@ allOf: enum: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy then: properties: resets: diff --git a/dts/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/dts/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index 8474eef8d0..91a6cc38ff 100644 --- a/dts/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/dts/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -19,6 +19,7 @@ properties: - qcom,msm8996-qmp-ufs-phy - qcom,msm8998-qmp-ufs-phy - qcom,sa8775p-qmp-ufs-phy + - qcom,sc7180-qmp-ufs-phy - qcom,sc7280-qmp-ufs-phy - qcom,sc8180x-qmp-ufs-phy - qcom,sc8280xp-qmp-ufs-phy @@ -38,15 +39,12 @@ properties: maxItems: 1 clocks: - minItems: 1 + minItems: 2 maxItems: 3 clock-names: - minItems: 1 - items: - - const: ref - - const: ref_aux - - const: qref + minItems: 2 + maxItems: 3 power-domains: maxItems: 1 @@ -86,22 +84,9 @@ allOf: compatible: contains: enum: + - qcom,msm8998-qmp-ufs-phy - qcom,sa8775p-qmp-ufs-phy - qcom,sc7280-qmp-ufs-phy - - qcom,sm8450-qmp-ufs-phy - then: - properties: - clocks: - minItems: 3 - clock-names: - minItems: 3 - - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8998-qmp-ufs-phy - qcom,sc8180x-qmp-ufs-phy - qcom,sc8280xp-qmp-ufs-phy - qcom,sdm845-qmp-ufs-phy @@ -112,14 +97,19 @@ allOf: - qcom,sm8150-qmp-ufs-phy - qcom,sm8250-qmp-ufs-phy - qcom,sm8350-qmp-ufs-phy + - qcom,sm8450-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy then: properties: clocks: - maxItems: 2 + minItems: 3 + maxItems: 3 clock-names: - maxItems: 2 + items: + - const: ref + - const: ref_aux + - const: qref - if: properties: @@ -130,22 +120,28 @@ allOf: then: properties: clocks: - maxItems: 1 + minItems: 2 + maxItems: 2 clock-names: - maxItems: 1 + items: + - const: ref + - const: qref additionalProperties: false examples: - | #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> + #include <dt-bindings/clock/qcom,rpmh.h> ufs_mem_phy: phy@1d87000 { compatible = "qcom,sc8280xp-qmp-ufs-phy"; reg = <0x01d87000 0x1000>; - clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_REF_CLKREF_CLK>; + + clock-names = "ref", "ref_aux", "qref"; power-domains = <&gcc UFS_PHY_GDSC>; diff --git a/dts/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/dts/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml index 15d82c67f1..1e2d4ddc53 100644 --- a/dts/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +++ b/dts/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml @@ -20,15 +20,12 @@ properties: - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - - qcom,msm8998-qmp-usb3-phy - - qcom,qcm2290-qmp-usb3-phy - qcom,sa8775p-qmp-usb3-uni-phy - qcom,sc8280xp-qmp-usb3-uni-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy - qcom,sdx75-qmp-usb3-uni-phy - - qcom,sm6115-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8250-qmp-usb3-uni-phy - qcom,sm8350-qmp-usb3-uni-phy @@ -93,7 +90,6 @@ allOf: - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - - qcom,msm8998-qmp-usb3-phy - qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy - qcom,sdx75-qmp-usb3-uni-phy @@ -113,24 +109,6 @@ allOf: compatible: contains: enum: - - qcom,qcm2290-qmp-usb3-phy - - qcom,sm6115-qmp-usb3-phy - then: - properties: - clocks: - maxItems: 4 - clock-names: - items: - - const: cfg_ahb - - const: ref - - const: com_aux - - const: pipe - - - if: - properties: - compatible: - contains: - enum: - qcom,sa8775p-qmp-usb3-uni-phy - qcom,sc8280xp-qmp-usb3-uni-phy - qcom,sm8150-qmp-usb3-uni-phy diff --git a/dts/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml b/dts/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml new file mode 100644 index 0000000000..54e822c715 --- /dev/null +++ b/dts/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC HDMI/eDP Transmitter Combo PHY + +maintainers: + - Cristian Ciocaltea <cristian.ciocaltea@collabora.com> + +properties: + compatible: + enum: + - rockchip,rk3588-hdptx-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock + - description: APB clock + + clock-names: + items: + - const: ref + - const: apb + + "#phy-cells": + const: 0 + + resets: + items: + - description: PHY reset line + - description: APB reset line + - description: INIT reset line + - description: CMN reset line + - description: LANE reset line + - description: ROPLL reset line + - description: LCPLL reset line + + reset-names: + items: + - const: phy + - const: apb + - const: init + - const: cmn + - const: lane + - const: ropll + - const: lcpll + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: Some PHY related data is accessed through GRF regs. + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - resets + - reset-names + - rockchip,grf + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/reset/rockchip,rk3588-cru.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll"; + rockchip,grf = <&hdptxphy_grf>; + }; + }; diff --git a/dts/Bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml b/dts/Bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml index c7df4cd341..d9e0b2c48e 100644 --- a/dts/Bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml +++ b/dts/Bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml @@ -24,7 +24,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/dts/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml b/dts/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml index 0942ea60c6..108719bde0 100644 --- a/dts/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml +++ b/dts/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml @@ -21,7 +21,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/dts/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml b/dts/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml index e3c8bde305..dc277f2e2e 100644 --- a/dts/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml +++ b/dts/Bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml @@ -21,7 +21,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/dts/Bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml b/dts/Bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml index c1b03147e8..add83c6763 100644 --- a/dts/Bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml +++ b/dts/Bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml @@ -29,7 +29,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/dts/Bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml b/dts/Bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml index 4ec85b8248..412bbcc276 100644 --- a/dts/Bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml +++ b/dts/Bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml @@ -29,7 +29,7 @@ required: - compatible patternProperties: - "^bank@[0-9a-z]+$": + "^bank@[0-9a-f]+$": $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio unevaluatedProperties: false diff --git a/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt b/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt index e8abbdad7b..0aa1a53012 100644 --- a/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/dts/Bindings/pinctrl/atmel,at91-pinctrl.txt @@ -20,6 +20,7 @@ such as pull-up, multi drive, etc. Required properties for iomux controller: - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" + or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl" - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be configured in this periph mode. All the periph and bank need to be describe. @@ -120,6 +121,7 @@ Some requirements for using atmel,at91rm9200-pinctrl binding: For each bank the required properties are: - compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or "microchip,sam9x60-gpio" + or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio" - reg: physical base address and length of the controller's registers - interrupts: interrupt outputs from the controller - interrupt-controller: marks the device node as an interrupt controller diff --git a/dts/Bindings/pinctrl/awinic,aw9523-pinctrl.yaml b/dts/Bindings/pinctrl/awinic,aw9523-pinctrl.yaml new file mode 100644 index 0000000000..98c310a3c6 --- /dev/null +++ b/dts/Bindings/pinctrl/awinic,aw9523-pinctrl.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/awinic,aw9523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Awinic AW9523/AW9523B I2C GPIO Expander + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + +description: | + The Awinic AW9523/AW9523B I2C GPIO Expander featuring 16 multi-function + I/O, 256 steps PWM mode and interrupt support. + +properties: + compatible: + const: awinic,aw9523-pinctrl + + reg: + maxItems: 1 + + '#gpio-cells': + description: | + Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Specifies the INTN pin IRQ. + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + reset-gpios: + maxItems: 1 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. + items: + pattern: "^gpio([0-9]|1[0-5])$" + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the + specified pins. + + enum: [ gpio, pwm ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-open-drain: true + drive-push-pull: true + input-enable: true + input-disable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + # Example configuration to drive pins for a keyboard matrix + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + aw9523: gpio-expander@58 { + compatible = "awinic,aw9523-pinctrl"; + reg = <0x58>; + interrupt-parent = <&tlmm>; + interrupts = <50 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 16>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + + keyboard-matrix-col-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + input-disable; + output-low; + }; + + keyboard-matrix-row-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + bias-pull-up; + drive-open-drain; + input-enable; + }; + }; + }; diff --git a/dts/Bindings/pinctrl/cirrus,madera.yaml b/dts/Bindings/pinctrl/cirrus,madera.yaml index bb61a30321..482acda88e 100644 --- a/dts/Bindings/pinctrl/cirrus,madera.yaml +++ b/dts/Bindings/pinctrl/cirrus,madera.yaml @@ -93,7 +93,8 @@ properties: input-schmitt-disable: true - input-debounce: true + input-debounce: + maxItems: 1 output-low: true diff --git a/dts/Bindings/pinctrl/cypress,cy8c95x0.yaml b/dts/Bindings/pinctrl/cypress,cy8c95x0.yaml index 7f30ec2f1e..700ac86c26 100644 --- a/dts/Bindings/pinctrl/cypress,cy8c95x0.yaml +++ b/dts/Bindings/pinctrl/cypress,cy8c95x0.yaml @@ -45,7 +45,8 @@ properties: maxItems: 1 gpio-reserved-ranges: - maxItems: 1 + minItems: 1 + maxItems: 60 vdd-supply: description: @@ -85,6 +86,8 @@ patternProperties: bias-disable: true + input-enable: true + output-high: true output-low: true @@ -133,6 +136,23 @@ examples: interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; vdd-supply = <&p3v3>; - gpio-reserved-ranges = <5 1>; + gpio-reserved-ranges = <1 2>, <6 1>, <10 1>, <15 1>; + + pinctrl-0 = <&U62160_pins>, <&U62160_ipins>; + pinctrl-names = "default"; + + U62160_pins: cfg-pins { + pins = "gp03", "gp16", "gp20", "gp50", "gp51"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + U62160_ipins: icfg-pins { + pins = "gp04", "gp17", "gp21", "gp52", "gp53"; + function = "gpio"; + input-enable; + bias-pull-up; + }; }; }; diff --git a/dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt deleted file mode 100644 index 7ca4f6118d..0000000000 --- a/dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Freescale i.MX6 UltraLite IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or - "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller. -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val - input_val> are specified using a PIN_FUNC_ID macro, which can be found in - imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite - Reference Manual for detailed CONFIG settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (0 << 6) -PAD_CTL_SPEED_MED (1 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_260ohm (1 << 3) -PAD_CTL_DSE_130ohm (2 << 3) -PAD_CTL_DSE_87ohm (3 << 3) -PAD_CTL_DSE_65ohm (4 << 3) -PAD_CTL_DSE_52ohm (5 << 3) -PAD_CTL_DSE_43ohm (6 << 3) -PAD_CTL_DSE_37ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) diff --git a/dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml b/dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml new file mode 100644 index 0000000000..906b264a9e --- /dev/null +++ b/dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX6UL IOMUX Controller + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - fsl,imx6ul-iomuxc + - fsl,imx6ull-iomuxc-snvs + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm/boot/dts/imx6ul-pinfunc.h>. The last integer + CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX6UL Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied: + PAD_CTL_HYS (1 << 16) + PAD_CTL_PUS_100K_DOWN (0 << 14) + PAD_CTL_PUS_47K_UP (1 << 14) + PAD_CTL_PUS_100K_UP (2 << 14) + PAD_CTL_PUS_22K_UP (3 << 14) + PAD_CTL_PUE (1 << 13) + PAD_CTL_PKE (1 << 12) + PAD_CTL_ODE (1 << 11) + PAD_CTL_SPEED_LOW (0 << 6) + PAD_CTL_SPEED_MED (1 << 6) + PAD_CTL_SPEED_HIGH (3 << 6) + PAD_CTL_DSE_DISABLE (0 << 3) + PAD_CTL_DSE_260ohm (1 << 3) + PAD_CTL_DSE_130ohm (2 << 3) + PAD_CTL_DSE_87ohm (3 << 3) + PAD_CTL_DSE_65ohm (4 << 3) + PAD_CTL_DSE_52ohm (5 << 3) + PAD_CTL_DSE_43ohm (6 << 3) + PAD_CTL_DSE_37ohm (7 << 3) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + + mux_uart: uartgrp { + fsl,pins = < + 0x0084 0x0310 0x0000 0 0 0x1b0b1 + 0x0088 0x0314 0x0624 0 3 0x1b0b1 + >; + }; + }; + - | + iomuxc_snvs: pinctrl@2290000 { + compatible = "fsl,imx6ull-iomuxc-snvs"; + reg = <0x02290000 0x4000>; + + pinctrl_snvs_usbc_det: snvsusbcdetgrp { + fsl,pins = < + 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 + >; + }; + }; diff --git a/dts/Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml b/dts/Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml new file mode 100644 index 0000000000..5f00604bf4 --- /dev/null +++ b/dts/Bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 pin controller + +description: > + The EyeQ5 pin controller handles the two pin banks of the system. It belongs + to a system-controller block called OLB. + + Pin control is about bias (pull-down, pull-up), drive strength and muxing. Pin + muxing supports two functions for each pin: first is GPIO, second is + pin-dependent. + + Pins and groups are bijective. + +maintainers: + - Grégory Clement <gregory.clement@bootlin.com> + - Théo Lebrun <theo.lebrun@bootlin.com> + - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> + +$ref: pinctrl.yaml# + +properties: + compatible: + enum: + - mobileye,eyeq5-pinctrl + + reg: + maxItems: 1 + +patternProperties: + "-pins?$": + type: object + description: Pin muxing configuration. + $ref: pinmux-node.yaml# + additionalProperties: false + properties: + pins: true + function: + enum: [gpio, + # Bank A + timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0, + spi1, refclk0, + # Bank B + timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0] + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + required: + - pins + - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + pins: + items: # PA0 - PA28, PB0 - PB22 + pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$' + - if: + properties: + function: + const: timer0 + then: + properties: + pins: + items: + enum: [PA0, PA1] + - if: + properties: + function: + const: timer1 + then: + properties: + pins: + items: + enum: [PA2, PA3] + - if: + properties: + function: + const: timer2 + then: + properties: + pins: + items: + enum: [PA4, PA5] + - if: + properties: + function: + const: timer5 + then: + properties: + pins: + items: + enum: [PA6, PA7, PA8, PA9] + - if: + properties: + function: + const: uart0 + then: + properties: + pins: + items: + enum: [PA10, PA11] + - if: + properties: + function: + const: uart1 + then: + properties: + pins: + items: + enum: [PA12, PA13] + - if: + properties: + function: + const: can0 + then: + properties: + pins: + items: + enum: [PA14, PA15] + - if: + properties: + function: + const: can1 + then: + properties: + pins: + items: + enum: [PA16, PA17] + - if: + properties: + function: + const: spi0 + then: + properties: + pins: + items: + enum: [PA18, PA19, PA20, PA21, PA22] + - if: + properties: + function: + const: spi1 + then: + properties: + pins: + items: + enum: [PA23, PA24, PA25, PA26, PA27] + - if: + properties: + function: + const: refclk0 + then: + properties: + pins: + items: + enum: [PA28] + - if: + properties: + function: + const: timer3 + then: + properties: + pins: + items: + enum: [PB0, PB1] + - if: + properties: + function: + const: timer4 + then: + properties: + pins: + items: + enum: [PB2, PB3] + - if: + properties: + function: + const: timer6 + then: + properties: + pins: + items: + enum: [PB4, PB5, PB6, PB7] + - if: + properties: + function: + const: uart2 + then: + properties: + pins: + items: + enum: [PB8, PB9] + - if: + properties: + function: + const: can2 + then: + properties: + pins: + items: + enum: [PB10, PB11] + - if: + properties: + function: + const: spi2 + then: + properties: + pins: + items: + enum: [PB12, PB13, PB14, PB15, PB16] + - if: + properties: + function: + const: spi3 + then: + properties: + pins: + items: + enum: [PB17, PB18, PB19, PB20, PB21] + - if: + properties: + function: + const: mclk0 + then: + properties: + pins: + items: + enum: [PB22] + +required: + - compatible + - reg + +additionalProperties: false diff --git a/dts/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml b/dts/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml index 3e84728988..b55d9c3166 100644 --- a/dts/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +++ b/dts/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml @@ -152,7 +152,6 @@ patternProperties: description: Debouncing periods in microseconds, one period per interrupt bank found in the controller - $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 4 @@ -160,7 +159,6 @@ patternProperties: description: | 0: Low rate 1: High rate - $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] drive-strength: diff --git a/dts/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/dts/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml index 7b7f840ffc..08442c880f 100644 --- a/dts/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml +++ b/dts/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -103,7 +103,8 @@ patternProperties: items: pattern: "^gpio1?[0-9]{1,2}$" - input-debounce: true + input-debounce: + maxItems: 1 additionalProperties: false diff --git a/dts/Bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml b/dts/Bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml index f3deda9f71..db8224dfba 100644 --- a/dts/Bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml +++ b/dts/Bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml @@ -10,18 +10,21 @@ maintainers: - Thierry Reding <thierry.reding@gmail.com> - Jon Hunter <jonathanh@nvidia.com> -$ref: nvidia,tegra234-pinmux-common.yaml - properties: compatible: const: nvidia,tegra234-pinmux-aon + reg: + maxItems: 1 + patternProperties: "^pinmux(-[a-z0-9-]+)?$": type: object # pin groups additionalProperties: + $ref: nvidia,tegra234-pinmux-common.yaml + properties: nvidia,pins: items: diff --git a/dts/Bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml b/dts/Bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml index 4f9de78085..8cf9e4c915 100644 --- a/dts/Bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml +++ b/dts/Bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml @@ -10,57 +10,43 @@ maintainers: - Thierry Reding <thierry.reding@gmail.com> - Jon Hunter <jonathanh@nvidia.com> -properties: - reg: - items: - - description: pinmux registers - -patternProperties: - "^pinmux(-[a-z0-9-]+)?$": - type: object - - # pin groups - additionalProperties: - $ref: nvidia,tegra-pinmux-common.yaml - # We would typically use unevaluatedProperties here but that has the - # downside that all the properties in the common bindings become valid - # for all chip generations. In this case, however, we want the per-SoC - # bindings to be able to override which of the common properties are - # allowed, since not all pinmux generations support the same sets of - # properties. This way, the common bindings define the format of the - # properties but the per-SoC bindings define which of them apply to a - # given chip. - additionalProperties: false - properties: - nvidia,function: - enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2, - eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3, - pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi, - sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte, - usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd, - i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc, - dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4, - ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb, - displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3, - tsc_alt, istctrl, vi1_alt, dspk1, igpu ] +$ref: nvidia,tegra-pinmux-common.yaml - # out of the common properties, only these are allowed for Tegra234 - nvidia,pins: true - nvidia,pull: true - nvidia,tristate: true - nvidia,schmitt: true - nvidia,enable-input: true - nvidia,open-drain: true - nvidia,lock: true - nvidia,drive-type: true - nvidia,io-hv: true - - required: - - nvidia,pins +properties: + nvidia,function: + enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2, + eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3, + pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi, + sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte, + usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd, + i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc, + dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4, + ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb, + displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3, + tsc_alt, istctrl, vi1_alt, dspk1, igpu ] + + # out of the common properties, only these are allowed for Tegra234 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true required: - - compatible - - reg + - nvidia,pins + +# We would typically use unevaluatedProperties here but that has the +# downside that all the properties in the common bindings become valid +# for all chip generations. In this case, however, we want the per-SoC +# bindings to be able to override which of the common properties are +# allowed, since not all pinmux generations support the same sets of +# properties. This way, the common bindings define the format of the +# properties but the per-SoC bindings define which of them apply to a +# given chip. +additionalProperties: false -additionalProperties: true ... diff --git a/dts/Bindings/pinctrl/nvidia,tegra234-pinmux.yaml b/dts/Bindings/pinctrl/nvidia,tegra234-pinmux.yaml index 17b865ecfc..f5a3a881de 100644 --- a/dts/Bindings/pinctrl/nvidia,tegra234-pinmux.yaml +++ b/dts/Bindings/pinctrl/nvidia,tegra234-pinmux.yaml @@ -10,18 +10,21 @@ maintainers: - Thierry Reding <thierry.reding@gmail.com> - Jon Hunter <jonathanh@nvidia.com> -$ref: nvidia,tegra234-pinmux-common.yaml - properties: compatible: const: nvidia,tegra234-pinmux + reg: + maxItems: 1 + patternProperties: "^pinmux(-[a-z0-9-]+)?$": type: object # pin groups additionalProperties: + $ref: nvidia,tegra234-pinmux-common.yaml + properties: nvidia,pins: items: diff --git a/dts/Bindings/pinctrl/pincfg-node.yaml b/dts/Bindings/pinctrl/pincfg-node.yaml index be81ed22a0..d0af21a564 100644 --- a/dts/Bindings/pinctrl/pincfg-node.yaml +++ b/dts/Bindings/pinctrl/pincfg-node.yaml @@ -97,7 +97,7 @@ properties: description: disable schmitt-trigger mode input-debounce: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array description: Takes the debounce time in usec as argument or 0 to disable debouncing diff --git a/dts/Bindings/pinctrl/qcom,sm4450-tlmm.yaml b/dts/Bindings/pinctrl/qcom,sm4450-tlmm.yaml index bb08ca5a15..bb675c8ec2 100644 --- a/dts/Bindings/pinctrl/qcom,sm4450-tlmm.yaml +++ b/dts/Bindings/pinctrl/qcom,sm4450-tlmm.yaml @@ -17,7 +17,7 @@ allOf: properties: compatible: - const: qcom,sm4450-pinctrl + const: qcom,sm4450-tlmm reg: maxItems: 1 diff --git a/dts/Bindings/pinctrl/renesas,pfc.yaml b/dts/Bindings/pinctrl/renesas,pfc.yaml index 181cd1676c..5d84364d13 100644 --- a/dts/Bindings/pinctrl/renesas,pfc.yaml +++ b/dts/Bindings/pinctrl/renesas,pfc.yaml @@ -46,6 +46,7 @@ properties: - renesas,pfc-r8a779a0 # R-Car V3U - renesas,pfc-r8a779f0 # R-Car S4-8 - renesas,pfc-r8a779g0 # R-Car V4H + - renesas,pfc-r8a779h0 # R-Car V4M - renesas,pfc-sh73a0 # SH-Mobile AG5 reg: diff --git a/dts/Bindings/pinctrl/xlnx,zynq-pinctrl.yaml b/dts/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml index d2676f92ef..de6c10ba36 100644 --- a/dts/Bindings/pinctrl/xlnx,zynq-pinctrl.yaml +++ b/dts/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Pinctrl @@ -28,7 +28,7 @@ description: | properties: compatible: - const: xlnx,zynq-pinctrl + const: xlnx,pinctrl-zynq reg: description: Specifies the base address and size of the SLCR space. @@ -181,7 +181,7 @@ examples: - | #include <dt-bindings/pinctrl/pinctrl-zynq.h> pinctrl0: pinctrl@700 { - compatible = "xlnx,zynq-pinctrl"; + compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; diff --git a/dts/Bindings/power/qcom,rpmpd.yaml b/dts/Bindings/power/qcom,rpmpd.yaml index 2ff246cf8b..929b7ef9c1 100644 --- a/dts/Bindings/power/qcom,rpmpd.yaml +++ b/dts/Bindings/power/qcom,rpmpd.yaml @@ -24,6 +24,8 @@ properties: - qcom,msm8917-rpmpd - qcom,msm8939-rpmpd - qcom,msm8953-rpmpd + - qcom,msm8974-rpmpd + - qcom,msm8974pro-pma8084-rpmpd - qcom,msm8976-rpmpd - qcom,msm8994-rpmpd - qcom,msm8996-rpmpd diff --git a/dts/Bindings/power/renesas,rcar-sysc.yaml b/dts/Bindings/power/renesas,rcar-sysc.yaml index 0720b54881..e76fb27349 100644 --- a/dts/Bindings/power/renesas,rcar-sysc.yaml +++ b/dts/Bindings/power/renesas,rcar-sysc.yaml @@ -45,6 +45,7 @@ properties: - renesas,r8a779a0-sysc # R-Car V3U - renesas,r8a779f0-sysc # R-Car S4-8 - renesas,r8a779g0-sysc # R-Car V4H + - renesas,r8a779h0-sysc # R-Car V4M reg: maxItems: 1 diff --git a/dts/Bindings/power/wakeup-source.txt b/dts/Bindings/power/wakeup-source.txt index 75bc20b956..a6c8978964 100644 --- a/dts/Bindings/power/wakeup-source.txt +++ b/dts/Bindings/power/wakeup-source.txt @@ -27,7 +27,7 @@ List of legacy properties and respective binding document Documentation/devicetree/bindings/mfd/tc3589x.txt Documentation/devicetree/bindings/input/touchscreen/ads7846.txt 4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt -5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt +5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung,s3c6410-keypad.yaml 6. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt Examples diff --git a/dts/Bindings/pwm/atmel,hlcdc-pwm.yaml b/dts/Bindings/pwm/atmel,hlcdc-pwm.yaml new file mode 100644 index 0000000000..0e92868a2b --- /dev/null +++ b/dts/Bindings/pwm/atmel,hlcdc-pwm.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/atmel,hlcdc-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel's HLCDC's PWM controller + +maintainers: + - Nicolas Ferre <nicolas.ferre@microchip.com> + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - Claudiu Beznea <claudiu.beznea@tuxon.dev> + +description: + The LCDC integrates a Pulse Width Modulation (PWM) Controller. This block + generates the LCD contrast control signal (LCD_PWM) that controls the + display's contrast by software. LCDC_PWM is an 8-bit PWM signal that can be + converted to an analog voltage with a simple passive filter. LCD display + panels have different backlight specifications in terms of minimum/maximum + values for PWM frequency. If the LCDC PWM frequency range does not match the + LCD display panel, it is possible to use the standalone PWM Controller to + drive the backlight. + +properties: + compatible: + const: atmel,hlcdc-pwm + + "#pwm-cells": + const: 3 + +required: + - compatible + - "#pwm-cells" + +additionalProperties: false diff --git a/dts/Bindings/pwm/atmel-hlcdc-pwm.txt b/dts/Bindings/pwm/atmel-hlcdc-pwm.txt deleted file mode 100644 index afa501bf7f..0000000000 --- a/dts/Bindings/pwm/atmel-hlcdc-pwm.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver - -The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. -See ../mfd/atmel-hlcdc.txt for more details. - -Required properties: - - compatible: value should be one of the following: - "atmel,hlcdc-pwm" - - pinctr-names: the pin control state names. Should contain "default". - - pinctrl-0: should contain the pinctrl states described by pinctrl - default. - - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells - bindings defined in pwm.yaml in this directory. - -Example: - - hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; - reg = <0xf0030000 0x2000>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; - clock-names = "periph_clk","sys_clk", "slow_clk"; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; - }; diff --git a/dts/Bindings/pwm/marvell,pxa-pwm.yaml b/dts/Bindings/pwm/marvell,pxa-pwm.yaml new file mode 100644 index 0000000000..ba6325575e --- /dev/null +++ b/dts/Bindings/pwm/marvell,pxa-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/marvell,pxa-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA PWM + +maintainers: + - Duje Mihanović <duje.mihanovic@skole.hr> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - marvell,pxa250-pwm + - marvell,pxa270-pwm + - marvell,pxa168-pwm + - marvell,pxa910-pwm + + reg: + # Length should be 0x10 + maxItems: 1 + + "#pwm-cells": + # Used for specifying the period length in nanoseconds + const: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/pxa-clock.h> + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + }; diff --git a/dts/Bindings/pwm/mediatek,mt2712-pwm.yaml b/dts/Bindings/pwm/mediatek,mt2712-pwm.yaml index 0fbe8a6469..a5c3088016 100644 --- a/dts/Bindings/pwm/mediatek,mt2712-pwm.yaml +++ b/dts/Bindings/pwm/mediatek,mt2712-pwm.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt7629-pwm - mediatek,mt7981-pwm - mediatek,mt7986-pwm + - mediatek,mt7988-pwm - mediatek,mt8183-pwm - mediatek,mt8365-pwm - mediatek,mt8516-pwm diff --git a/dts/Bindings/pwm/opencores,pwm.yaml b/dts/Bindings/pwm/opencores,pwm.yaml new file mode 100644 index 0000000000..52a59d245c --- /dev/null +++ b/dts/Bindings/pwm/opencores,pwm.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenCores PWM controller + +maintainers: + - William Qiu <william.qiu@starfivetech.com> + +description: + The OpenCores PTC ip core contains a PWM controller. When operating in PWM + mode, the PTC core generates binary signal with user-programmable low and + high periods. All PTC counters and registers are 32-bit. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - enum: + - starfive,jh7100-pwm + - starfive,jh7110-pwm + - starfive,jh8100-pwm + - const: opencores,pwm-v1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg = <0x12490000 0x10000>; + clocks = <&clkgen 181>; + resets = <&rstgen 109>; + #pwm-cells = <3>; + }; diff --git a/dts/Bindings/pwm/pwm-amlogic.yaml b/dts/Bindings/pwm/pwm-amlogic.yaml index 527864a4d8..1d71d4f8f3 100644 --- a/dts/Bindings/pwm/pwm-amlogic.yaml +++ b/dts/Bindings/pwm/pwm-amlogic.yaml @@ -9,9 +9,6 @@ title: Amlogic PWM maintainers: - Heiner Kallweit <hkallweit1@gmail.com> -allOf: - - $ref: pwm.yaml# - properties: compatible: oneOf: @@ -24,31 +21,40 @@ properties: - amlogic,meson-g12a-ee-pwm - amlogic,meson-g12a-ao-pwm-ab - amlogic,meson-g12a-ao-pwm-cd - - amlogic,meson-s4-pwm + deprecated: true - items: - const: amlogic,meson-gx-pwm - const: amlogic,meson-gxbb-pwm + deprecated: true - items: - const: amlogic,meson-gx-ao-pwm - const: amlogic,meson-gxbb-ao-pwm + deprecated: true - items: - const: amlogic,meson8-pwm - const: amlogic,meson8b-pwm + deprecated: true + - enum: + - amlogic,meson8-pwm-v2 + - amlogic,meson-s4-pwm + - items: + - enum: + - amlogic,meson8b-pwm-v2 + - amlogic,meson-gxbb-pwm-v2 + - amlogic,meson-axg-pwm-v2 + - amlogic,meson-g12-pwm-v2 + - const: amlogic,meson8-pwm-v2 reg: maxItems: 1 clocks: minItems: 1 - maxItems: 2 + maxItems: 4 clock-names: - oneOf: - - items: - - enum: [clkin0, clkin1] - - items: - - const: clkin0 - - const: clkin1 + minItems: 1 + maxItems: 2 "#pwm-cells": const: 3 @@ -57,6 +63,79 @@ required: - compatible - reg +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm + - amlogic,meson8b-pwm + - amlogic,meson-gxbb-pwm + - amlogic,meson-gxbb-ao-pwm + - amlogic,meson-axg-ee-pwm + - amlogic,meson-axg-ao-pwm + - amlogic,meson-g12a-ee-pwm + - amlogic,meson-g12a-ao-pwm-ab + - amlogic,meson-g12a-ao-pwm-cd + then: + # Obsolete historic bindings tied to the driver implementation + # The clocks provided here are meant to be matched with the input + # known (hard-coded) in the driver and used to select pwm clock + # source. Currently, the linux driver ignores this. + # This is kept to maintain ABI backward compatibility. + properties: + clocks: + maxItems: 2 + clock-names: + oneOf: + - items: + - enum: [clkin0, clkin1] + - items: + - const: clkin0 + - const: clkin1 + + # Newer binding where clock describe the actual clock inputs of the pwm + # block. These are necessary but some inputs may be grounded. + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8-pwm-v2 + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock 0 of the pwm block + - description: input clock 1 of the pwm block + - description: input clock 2 of the pwm block + - description: input clock 3 of the pwm block + clock-names: false + required: + - clocks + + # Newer IP block take a single input per channel, instead of 4 inputs + # for both channels + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-s4-pwm + then: + properties: + clocks: + items: + - description: input clock of PWM channel A + - description: input clock of PWM channel B + clock-names: false + required: + - clocks + additionalProperties: false examples: @@ -68,3 +147,17 @@ examples: clock-names = "clkin0", "clkin1"; #pwm-cells = <3>; }; + - | + pwm@2000 { + compatible = "amlogic,meson8-pwm-v2"; + reg = <0x1000 0x10>; + clocks = <&xtal>, <0>, <&fdiv4>, <&fdiv5>; + #pwm-cells = <3>; + }; + - | + pwm@1000 { + compatible = "amlogic,meson-s4-pwm"; + reg = <0x1000 0x10>; + clocks = <&pwm_src_a>, <&pwm_src_b>; + #pwm-cells = <3>; + }; diff --git a/dts/Bindings/pwm/pxa-pwm.txt b/dts/Bindings/pwm/pxa-pwm.txt deleted file mode 100644 index 5ae9f1e3c3..0000000000 --- a/dts/Bindings/pwm/pxa-pwm.txt +++ /dev/null @@ -1,30 +0,0 @@ -Marvell PWM controller - -Required properties: -- compatible: should be one or more of: - - "marvell,pxa250-pwm" - - "marvell,pxa270-pwm" - - "marvell,pxa168-pwm" - - "marvell,pxa910-pwm" -- reg: Physical base address and length of the registers used by the PWM channel - Note that one device instance must be created for each PWM that is used, so the - length covers only the register window for one PWM output, not that of the - entire PWM controller. Currently length is 0x10 for all supported devices. -- #pwm-cells: Should be 1. This cell is used to specify the period in - nanoseconds. - -Example PWM device node: - -pwm0: pwm@40b00000 { - compatible = "marvell,pxa250-pwm"; - reg = <0x40b00000 0x10>; - #pwm-cells = <1>; -}; - -Example PWM client node: - -backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 5000000>; - ... -} diff --git a/dts/Bindings/regulator/gpio-regulator.yaml b/dts/Bindings/regulator/gpio-regulator.yaml index f4c1f36e52..a34e857546 100644 --- a/dts/Bindings/regulator/gpio-regulator.yaml +++ b/dts/Bindings/regulator/gpio-regulator.yaml @@ -47,6 +47,7 @@ properties: 1: HIGH Default is LOW if nothing else is specified. $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 maxItems: 8 items: enum: [0, 1] @@ -57,7 +58,8 @@ properties: regulator and matching GPIO configurations to achieve them. If there are no states in the "states" array, use a fixed regulator instead. $ref: /schemas/types.yaml#/definitions/uint32-matrix - maxItems: 8 + minItems: 2 + maxItems: 256 items: items: - description: Voltage in microvolts diff --git a/dts/Bindings/regulator/infineon,ir38060.yaml b/dts/Bindings/regulator/infineon,ir38060.yaml new file mode 100644 index 0000000000..e6ffbc2a22 --- /dev/null +++ b/dts/Bindings/regulator/infineon,ir38060.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/infineon,ir38060.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Infineon Buck Regulators with PMBUS interfaces + +maintainers: + - Not Me. + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + enum: + - infineon,ir38060 + - infineon,ir38064 + - infineon,ir38164 + - infineon,ir38263 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@34 { + compatible = "infineon,ir38060"; + reg = <0x34>; + + regulator-min-microvolt = <437500>; + regulator-max-microvolt = <1387500>; + }; + }; diff --git a/dts/Bindings/regulator/mcp16502-regulator.txt b/dts/Bindings/regulator/mcp16502-regulator.txt deleted file mode 100644 index 451cc4e86b..0000000000 --- a/dts/Bindings/regulator/mcp16502-regulator.txt +++ /dev/null @@ -1,144 +0,0 @@ -MCP16502 PMIC - -Required properties: -- compatible: "microchip,mcp16502" -- reg: I2C slave address -- lpm-gpios: GPIO for LPM pin. Note that this GPIO *must* remain high during - suspend-to-ram, keeping the PMIC into HIBERNATE mode; this - property is optional; -- regulators: A node that houses a sub-node for each regulator within - the device. Each sub-node is identified using the node's - name. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - -Regulators of MCP16502 PMIC: -1) VDD_IO - Buck (1.2 - 3.7 V) -2) VDD_DDR - Buck (0.6 - 1.85 V) -3) VDD_CORE - Buck (0.6 - 1.85 V) -4) VDD_OTHER - BUCK (0.6 - 1.85 V) -5) LDO1 - LDO (1.2 - 3.7 V) -6) LDO2 - LDO (1.2 - 3.7 V) - -Regulator modes: -2 - FPWM: higher precision, higher consumption -4 - AutoPFM: lower precision, lower consumption - -Each regulator is defined using the standard binding for regulators. - -Example: - -mcp16502@5b { - compatible = "microchip,mcp16502"; - reg = <0x5b>; - status = "okay"; - lpm-gpios = <&pioBU 7 GPIO_ACTIVE_HIGH>; - - regulators { - VDD_IO { - regulator-name = "VDD_IO"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - VDD_DDR { - regulator-name = "VDD_DDR"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - }; - - VDD_CORE { - regulator-name = "VDD_CORE"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - VDD_OTHER { - regulator-name = "VDD_OTHER"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1850000>; - regulator-initial-mode = <2>; - regulator-allowed-modes = <2>, <4>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-mode = <4>; - }; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - }; -}; diff --git a/dts/Bindings/regulator/microchip,mcp16502.yaml b/dts/Bindings/regulator/microchip,mcp16502.yaml new file mode 100644 index 0000000000..1aca364678 --- /dev/null +++ b/dts/Bindings/regulator/microchip,mcp16502.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MCP16502 - High-Performance PMIC + +maintainers: + - Andrei Simion <andrei.simion@microchip.com> + +description: + The MCP16502 is an optimally integrated PMIC compatible + with Microchip's eMPUs(Embedded Microprocessor Units), + requiring Dynamic Voltage Scaling (DVS) with the use + of High-Performance mode (HPM). + +properties: + compatible: + const: microchip,mcp16502 + + lpm-gpios: + maxItems: 1 + description: GPIO for LPM pin. + Note that this GPIO must remain high during + suspend-to-ram, keeping the PMIC into HIBERNATE mode. + + reg: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + description: List of regulators and its properties. + + patternProperties: + "^(VDD_(IO|CORE|DDR|OTHER)|LDO[1-2])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + properties: + regulator-initial-mode: + enum: [2, 4] + default: 2 + description: Initial operating mode + + regulator-allowed-modes: + items: + enum: [2, 4] + description: Supported modes + 2 - FPWM higher precision, higher consumption + 4 - AutoPFM lower precision, lower consumption + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + + regulators { + VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/regulator/qcom,usb-vbus-regulator.yaml b/dts/Bindings/regulator/qcom,usb-vbus-regulator.yaml index 534f87e987..33ae1f7868 100644 --- a/dts/Bindings/regulator/qcom,usb-vbus-regulator.yaml +++ b/dts/Bindings/regulator/qcom,usb-vbus-regulator.yaml @@ -19,8 +19,15 @@ allOf: properties: compatible: - enum: - - qcom,pm8150b-vbus-reg + oneOf: + - enum: + - qcom,pm8150b-vbus-reg + - items: + - enum: + - qcom,pm4125-vbus-reg + - qcom,pm6150-vbus-reg + - qcom,pmi632-vbus-reg + - const: qcom,pm8150b-vbus-reg reg: maxItems: 1 diff --git a/dts/Bindings/regulator/ti,tps65132.yaml b/dts/Bindings/regulator/ti,tps65132.yaml new file mode 100644 index 0000000000..6a6d1a3d6f --- /dev/null +++ b/dts/Bindings/regulator/ti,tps65132.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/ti,tps65132.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI TPS65132 Dual Output Power Regulators + +maintainers: + - devicetree@vger.kernel.org + +description: | + The TPS65132 is designed to supply positive/negative driven applications. + + Datasheet is available at: + https://www.ti.com/lit/gpn/tps65132 + +properties: + compatible: + enum: + - ti,tps65132 + + reg: + maxItems: 1 + +patternProperties: + "^out[pn]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single regulator. + + properties: + enable-gpios: + maxItems: 1 + description: + GPIO specifier to enable the GPIO control (on/off) for regulator. + + active-discharge-gpios: + maxItems: 1 + description: + GPIO specifier to actively discharge the delay mechanism. + + ti,active-discharge-time-us: + description: Regulator active discharge time in microseconds. + + dependencies: + active-discharge-gpios: [ 'ti,active-discharge-time-us' ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@3e { + compatible = "ti,tps65132"; + reg = <0x3e>; + + outp { + regulator-name = "outp"; + regulator-boot-on; + regulator-always-on; + enable-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + }; + + outn { + regulator-name = "outn"; + regulator-boot-on; + regulator-always-on; + regulator-active-discharge = <0>; + enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; + }; + }; + }; diff --git a/dts/Bindings/regulator/tps65132-regulator.txt b/dts/Bindings/regulator/tps65132-regulator.txt deleted file mode 100644 index 3a3505520c..0000000000 --- a/dts/Bindings/regulator/tps65132-regulator.txt +++ /dev/null @@ -1,46 +0,0 @@ -TPS65132 regulators - -Required properties: -- compatible: "ti,tps65132" -- reg: I2C slave address - -Optional Subnode: -Device supports two regulators OUTP and OUTN. A sub node within the - device node describe the properties of these regulators. The sub-node - names must be as follows: - -For regulator outp, the sub node name should be "outp". - -For regulator outn, the sub node name should be "outn". - --enable-gpios:(active high, output) Regulators are controlled by the input pins. - If it is connected to GPIO through host system then provide the - gpio number as per gpio.txt. --active-discharge-gpios: (active high, output) Some configurations use delay mechanisms - on the enable pin, to keep the regulator enabled for some time after - the enable signal goes low. This GPIO is used to actively discharge - the delay mechanism. Requires specification of ti,active-discharge-time-us --ti,active-discharge-time-us: how long the active discharge gpio should be - asserted for during active discharge, in microseconds. - -Each regulator is defined using the standard binding for regulators. - -Example: - - tps65132@3e { - compatible = "ti,tps65132"; - reg = <0x3e>; - - outp { - regulator-name = "outp"; - regulator-boot-on; - regulator-always-on; - enable-gpios = <&gpio 23 0>; - }; - - outn { - regulator-name = "outn"; - regulator-boot-on; - regulator-always-on; - regulator-active-discharge = <0>; - enable-gpios = <&gpio 40 0>; - }; - }; diff --git a/dts/Bindings/remoteproc/mtk,scp.yaml b/dts/Bindings/remoteproc/mtk,scp.yaml index 09102dda49..507f98f73d 100644 --- a/dts/Bindings/remoteproc/mtk,scp.yaml +++ b/dts/Bindings/remoteproc/mtk,scp.yaml @@ -47,7 +47,7 @@ properties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: If present, name (or relative path) of the file within the firmware search path containing the firmware image used when @@ -115,7 +115,7 @@ patternProperties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: If present, name (or relative path) of the file within the firmware search path containing the firmware image used when diff --git a/dts/Bindings/remoteproc/qcom,glink-rpm-edge.yaml b/dts/Bindings/remoteproc/qcom,glink-rpm-edge.yaml index 884158bccd..3766d4513b 100644 --- a/dts/Bindings/remoteproc/qcom,glink-rpm-edge.yaml +++ b/dts/Bindings/remoteproc/qcom,glink-rpm-edge.yaml @@ -18,7 +18,6 @@ properties: const: qcom,glink-rpm label: - $ref: /schemas/types.yaml#/definitions/string description: Name of the edge, used for debugging and identification purposes. The node name will be used if this is not present. diff --git a/dts/Bindings/remoteproc/qcom,qcs404-pas.yaml b/dts/Bindings/remoteproc/qcom,qcs404-pas.yaml index eb868a7ff4..ad45fd00ae 100644 --- a/dts/Bindings/remoteproc/qcom,qcs404-pas.yaml +++ b/dts/Bindings/remoteproc/qcom,qcs404-pas.yaml @@ -46,7 +46,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/dts/Bindings/remoteproc/qcom,sc7180-pas.yaml b/dts/Bindings/remoteproc/qcom,sc7180-pas.yaml index c054b84fdc..66b455d0a8 100644 --- a/dts/Bindings/remoteproc/qcom,sc7180-pas.yaml +++ b/dts/Bindings/remoteproc/qcom,sc7180-pas.yaml @@ -45,7 +45,7 @@ properties: smd-edge: false firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/dts/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml b/dts/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml index b6bd334385..9381c7022f 100644 --- a/dts/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml +++ b/dts/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml @@ -80,7 +80,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: The name of the firmware which should be loaded for this remote processor. diff --git a/dts/Bindings/remoteproc/qcom,sc8180x-pas.yaml b/dts/Bindings/remoteproc/qcom,sc8180x-pas.yaml index 4744a37b2b..45ee9fbe09 100644 --- a/dts/Bindings/remoteproc/qcom,sc8180x-pas.yaml +++ b/dts/Bindings/remoteproc/qcom,sc8180x-pas.yaml @@ -42,7 +42,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/dts/Bindings/remoteproc/qcom,sm6115-pas.yaml b/dts/Bindings/remoteproc/qcom,sm6115-pas.yaml index 0282872359..758adb06c8 100644 --- a/dts/Bindings/remoteproc/qcom,sm6115-pas.yaml +++ b/dts/Bindings/remoteproc/qcom,sm6115-pas.yaml @@ -47,7 +47,7 @@ properties: smd-edge: false firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/dts/Bindings/remoteproc/qcom,sm6350-pas.yaml b/dts/Bindings/remoteproc/qcom,sm6350-pas.yaml index f7e40fb166..c1a3cc308b 100644 --- a/dts/Bindings/remoteproc/qcom,sm6350-pas.yaml +++ b/dts/Bindings/remoteproc/qcom,sm6350-pas.yaml @@ -42,7 +42,7 @@ properties: smd-edge: false firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/dts/Bindings/remoteproc/qcom,sm6375-pas.yaml b/dts/Bindings/remoteproc/qcom,sm6375-pas.yaml index 3e4a03eb45..7286b2baa1 100644 --- a/dts/Bindings/remoteproc/qcom,sm6375-pas.yaml +++ b/dts/Bindings/remoteproc/qcom,sm6375-pas.yaml @@ -36,7 +36,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core smd-edge: false diff --git a/dts/Bindings/remoteproc/qcom,sm8150-pas.yaml b/dts/Bindings/remoteproc/qcom,sm8150-pas.yaml index 238c6e5e67..d67386c50f 100644 --- a/dts/Bindings/remoteproc/qcom,sm8150-pas.yaml +++ b/dts/Bindings/remoteproc/qcom,sm8150-pas.yaml @@ -46,7 +46,7 @@ properties: smd-edge: false firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/dts/Bindings/remoteproc/qcom,sm8350-pas.yaml b/dts/Bindings/remoteproc/qcom,sm8350-pas.yaml index 53cea8e53a..4b9fb74fb9 100644 --- a/dts/Bindings/remoteproc/qcom,sm8350-pas.yaml +++ b/dts/Bindings/remoteproc/qcom,sm8350-pas.yaml @@ -47,7 +47,7 @@ properties: description: Reference to the reserved-memory for the Hexagon core firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Firmware name for the Hexagon core required: diff --git a/dts/Bindings/remoteproc/qcom,sm8550-pas.yaml b/dts/Bindings/remoteproc/qcom,sm8550-pas.yaml index 58120829fb..73fda7565c 100644 --- a/dts/Bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/dts/Bindings/remoteproc/qcom,sm8550-pas.yaml @@ -19,6 +19,11 @@ properties: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas - qcom,sm8550-mpss-pas + - qcom,sm8650-adsp-pas + - qcom,sm8650-cdsp-pas + - qcom,sm8650-mpss-pas + - qcom,x1e80100-adsp-pas + - qcom,x1e80100-cdsp-pas reg: maxItems: 1 @@ -49,6 +54,8 @@ properties: - description: Memory region for main Firmware authentication - description: Memory region for Devicetree Firmware authentication - description: DSM Memory region + - description: DSM Memory region 2 + - description: Memory region for Qlink Logging required: - compatible @@ -63,6 +70,9 @@ allOf: enum: - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas + - qcom,sm8650-adsp-pas + - qcom,x1e80100-adsp-pas + - qcom,x1e80100-cdsp-pas then: properties: interrupts: @@ -71,7 +81,26 @@ allOf: maxItems: 5 memory-region: maxItems: 2 - else: + - if: + properties: + compatible: + enum: + - qcom,sm8650-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + memory-region: + minItems: 3 + maxItems: 3 + - if: + properties: + compatible: + enum: + - qcom,sm8550-mpss-pas + then: properties: interrupts: minItems: 6 @@ -79,12 +108,29 @@ allOf: minItems: 6 memory-region: minItems: 3 + maxItems: 3 + - if: + properties: + compatible: + enum: + - qcom,sm8650-mpss-pas + then: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + minItems: 5 + maxItems: 5 - if: properties: compatible: enum: - qcom,sm8550-adsp-pas + - qcom,sm8650-adsp-pas + - qcom,x1e80100-adsp-pas then: properties: power-domains: @@ -101,6 +147,7 @@ allOf: compatible: enum: - qcom,sm8550-mpss-pas + - qcom,sm8650-mpss-pas then: properties: power-domains: @@ -116,6 +163,8 @@ allOf: compatible: enum: - qcom,sm8550-cdsp-pas + - qcom,sm8650-cdsp-pas + - qcom,x1e80100-cdsp-pas then: properties: power-domains: diff --git a/dts/Bindings/remoteproc/qcom,wcnss-pil.yaml b/dts/Bindings/remoteproc/qcom,wcnss-pil.yaml index 45eb42bd3c..8e033b22d2 100644 --- a/dts/Bindings/remoteproc/qcom,wcnss-pil.yaml +++ b/dts/Bindings/remoteproc/qcom,wcnss-pil.yaml @@ -51,7 +51,7 @@ properties: - const: stop-ack firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Relative firmware image path for the WCNSS core. Defaults to "wcnss.mdt". diff --git a/dts/Bindings/remoteproc/ti,davinci-rproc.txt b/dts/Bindings/remoteproc/ti,davinci-rproc.txt index 25f8658e21..48a49c516b 100644 --- a/dts/Bindings/remoteproc/ti,davinci-rproc.txt +++ b/dts/Bindings/remoteproc/ti,davinci-rproc.txt @@ -1,9 +1,6 @@ TI Davinci DSP devices ======================= -Binding status: Unstable - Subject to changes for DT representation of clocks - and resets - The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that is used to offload some of the processor-intensive tasks or algorithms, for achieving various system level goals. diff --git a/dts/Bindings/reset/mobileye,eyeq5-reset.yaml b/dts/Bindings/reset/mobileye,eyeq5-reset.yaml new file mode 100644 index 0000000000..062b451834 --- /dev/null +++ b/dts/Bindings/reset/mobileye,eyeq5-reset.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 reset controller + +description: + The EyeQ5 reset driver handles three reset domains. Its registers live in a + shared region called OLB. + +maintainers: + - Grégory Clement <gregory.clement@bootlin.com> + - Théo Lebrun <theo.lebrun@bootlin.com> + - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> + +properties: + compatible: + const: mobileye,eyeq5-reset + + reg: + maxItems: 3 + + reg-names: + items: + - const: d0 + - const: d1 + - const: d2 + + "#reset-cells": + const: 2 + description: + The first cell is the domain (0 to 2 inclusive) and the second one is the + reset index inside that domain. + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + +additionalProperties: false diff --git a/dts/Bindings/reset/renesas,rst.yaml b/dts/Bindings/reset/renesas,rst.yaml index e7e4872477..58b4a45d33 100644 --- a/dts/Bindings/reset/renesas,rst.yaml +++ b/dts/Bindings/reset/renesas,rst.yaml @@ -50,6 +50,7 @@ properties: - renesas,r8a779a0-rst # R-Car V3U - renesas,r8a779f0-rst # R-Car S4-8 - renesas,r8a779g0-rst # R-Car V4H + - renesas,r8a779h0-rst # R-Car V4M reg: maxItems: 1 diff --git a/dts/Bindings/reset/sophgo,sg2042-reset.yaml b/dts/Bindings/reset/sophgo,sg2042-reset.yaml new file mode 100644 index 0000000000..76e1931f09 --- /dev/null +++ b/dts/Bindings/reset/sophgo,sg2042-reset.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC Reset Controller + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +properties: + compatible: + const: sophgo,sg2042-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rstgen: reset-controller@c00 { + compatible = "sophgo,sg2042-reset"; + reg = <0xc00 0xc>; + #reset-cells = <1>; + }; diff --git a/dts/Bindings/riscv/cpus.yaml b/dts/Bindings/riscv/cpus.yaml index 9d8670c00e..d87dd50f1a 100644 --- a/dts/Bindings/riscv/cpus.yaml +++ b/dts/Bindings/riscv/cpus.yaml @@ -75,6 +75,10 @@ properties: - riscv,sv57 - riscv,none + reg: + description: + The hart ID of this CPU node. + riscv,cbom-block-size: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -106,7 +110,11 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - const: andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc interrupt-controller: true diff --git a/dts/Bindings/riscv/extensions.yaml b/dts/Bindings/riscv/extensions.yaml index 63d81dc895..468c646247 100644 --- a/dts/Bindings/riscv/extensions.yaml +++ b/dts/Bindings/riscv/extensions.yaml @@ -477,5 +477,12 @@ properties: latency, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: xandespmu + description: + The Andes Technology performance monitor extension for counter overflow + and privilege mode filtering. For more details, see Counter Related + Registers in the AX45MP datasheet. + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + additionalProperties: true ... diff --git a/dts/Bindings/rng/atmel,at91-trng.yaml b/dts/Bindings/rng/atmel,at91-trng.yaml index 3ce45456d8..b38f825234 100644 --- a/dts/Bindings/rng/atmel,at91-trng.yaml +++ b/dts/Bindings/rng/atmel,at91-trng.yaml @@ -21,6 +21,10 @@ properties: - enum: - microchip,sama7g5-trng - const: atmel,at91sam9g45-trng + - items: + - enum: + - microchip,sam9x7-trng + - const: microchip,sam9x60-trng clocks: maxItems: 1 diff --git a/dts/Bindings/rtc/abracon,abx80x.txt b/dts/Bindings/rtc/abracon,abx80x.txt deleted file mode 100644 index 2405e35a1b..0000000000 --- a/dts/Bindings/rtc/abracon,abx80x.txt +++ /dev/null @@ -1,31 +0,0 @@ -Abracon ABX80X I2C ultra low power RTC/Alarm chip - -The Abracon ABX80X family consist of the ab0801, ab0803, ab0804, ab0805, ab1801, -ab1803, ab1804 and ab1805. The ab0805 is the superset of ab080x and the ab1805 -is the superset of ab180x. - -Required properties: - - - "compatible": should one of: - "abracon,abx80x" - "abracon,ab0801" - "abracon,ab0803" - "abracon,ab0804" - "abracon,ab0805" - "abracon,ab1801" - "abracon,ab1803" - "abracon,ab1804" - "abracon,ab1805" - "microcrystal,rv1805" - Using "abracon,abx80x" will enable chip autodetection. - - "reg": I2C bus address of the device - -Optional properties: - -The abx804 and abx805 have a trickle charger that is able to charge the -connected battery or supercap. Both the following properties have to be defined -and valid to enable charging: - - - "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V) - - "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output - resistor, the other values are in kOhm. diff --git a/dts/Bindings/rtc/abracon,abx80x.yaml b/dts/Bindings/rtc/abracon,abx80x.yaml new file mode 100644 index 0000000000..355b059841 --- /dev/null +++ b/dts/Bindings/rtc/abracon,abx80x.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/abracon,abx80x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Abracon ABX80X I2C ultra low power RTC/Alarm chip + +maintainers: + - linux-rtc@vger.kernel.org + +properties: + compatible: + description: + The wildcard 'abracon,abx80x' may be used to support a mix + of different abracon rtc`s. In this case the driver + must perform auto-detection from ID register. + enum: + - abracon,abx80x + - abracon,ab0801 + - abracon,ab0803 + - abracon,ab0804 + - abracon,ab0805 + - abracon,ab1801 + - abracon,ab1803 + - abracon,ab1804 + - abracon,ab1805 + - microcrystal,rv1805 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + abracon,tc-diode: + description: + Trickle-charge diode type. + Required to enable charging backup battery. + + Supported are 'standard' diodes with a 0.6V drop + and 'schottky' diodes with a 0.3V drop. + $ref: /schemas/types.yaml#/definitions/string + enum: + - standard + - schottky + + abracon,tc-resistor: + description: + Trickle-charge resistor value in kOhm. + Required to enable charging backup battery. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 3, 6, 11] + +dependentRequired: + abracon,tc-diode: ["abracon,tc-resistor"] + abracon,tc-resistor: ["abracon,tc-diode"] + +required: + - compatible + - reg + +allOf: + - $ref: rtc.yaml# + - if: + properties: + compatible: + not: + contains: + enum: + - abracon,abx80x + - abracon,ab0804 + - abracon,ab1804 + - abracon,ab0805 + - abracon,ab1805 + then: + properties: + abracon,tc-diode: false + abracon,tc-resistor: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@69 { + compatible = "abracon,abx80x"; + reg = <0x69>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + interrupts = <44 IRQ_TYPE_EDGE_FALLING>; + }; + }; diff --git a/dts/Bindings/rtc/atmel,at91sam9260-rtt.yaml b/dts/Bindings/rtc/atmel,at91sam9260-rtt.yaml index b80b85c394..a7f6c1d1a0 100644 --- a/dts/Bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/dts/Bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -19,7 +19,9 @@ properties: - items: - const: atmel,at91sam9260-rtt - items: - - const: microchip,sam9x60-rtt + - enum: + - microchip,sam9x60-rtt + - microchip,sam9x7-rtt - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt diff --git a/dts/Bindings/rtc/mediatek,mt2712-rtc.yaml b/dts/Bindings/rtc/mediatek,mt2712-rtc.yaml new file mode 100644 index 0000000000..75624ddf6d --- /dev/null +++ b/dts/Bindings/rtc/mediatek,mt2712-rtc.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/mediatek,mt2712-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT2712 on-SoC RTC + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Ran Bi <ran.bi@mediatek.com> + +properties: + compatible: + const: mediatek,mt2712-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + rtc@10011000 { + compatible = "mediatek,mt2712-rtc"; + reg = <0x10011000 0x1000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>; + }; diff --git a/dts/Bindings/rtc/mediatek,mt7622-rtc.yaml b/dts/Bindings/rtc/mediatek,mt7622-rtc.yaml new file mode 100644 index 0000000000..e74dfc161c --- /dev/null +++ b/dts/Bindings/rtc/mediatek,mt7622-rtc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/mediatek,mt7622-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7622 on-SoC RTC + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Sean Wang <sean.wang@mediatek.com> + +properties: + compatible: + items: + - const: mediatek,mt7622-rtc + - const: mediatek,soc-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: rtc + +required: + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt7622-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + rtc@10212800 { + compatible = "mediatek,mt7622-rtc", "mediatek,soc-rtc"; + reg = <0x10212800 0x200>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_RTC>; + clock-names = "rtc"; + }; diff --git a/dts/Bindings/rtc/rtc-mt2712.txt b/dts/Bindings/rtc/rtc-mt2712.txt deleted file mode 100644 index c33d87e5e7..0000000000 --- a/dts/Bindings/rtc/rtc-mt2712.txt +++ /dev/null @@ -1,14 +0,0 @@ -Device-Tree bindings for MediaTek SoC based RTC - -Required properties: -- compatible : Should be "mediatek,mt2712-rtc" : for MT2712 SoC -- reg : Specifies base physical address and size of the registers; -- interrupts : Should contain the interrupt for RTC alarm; - -Example: - -rtc: rtc@10011000 { - compatible = "mediatek,mt2712-rtc"; - reg = <0 0x10011000 0 0x1000>; - interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>; -}; diff --git a/dts/Bindings/rtc/rtc-mt7622.txt b/dts/Bindings/rtc/rtc-mt7622.txt deleted file mode 100644 index 09fe8f5147..0000000000 --- a/dts/Bindings/rtc/rtc-mt7622.txt +++ /dev/null @@ -1,21 +0,0 @@ -Device-Tree bindings for MediaTek SoC based RTC - -Required properties: -- compatible : Should be - "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC -- reg : Specifies base physical address and size of the registers; -- interrupts : Should contain the interrupt for RTC alarm; -- clocks : Specifies list of clock specifiers, corresponding to - entries in clock-names property; -- clock-names : Should contain "rtc" entries - -Example: - -rtc: rtc@10212800 { - compatible = "mediatek,mt7622-rtc", - "mediatek,soc-rtc"; - reg = <0 0x10212800 0 0x200>; - interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_RTC>; - clock-names = "rtc"; -}; diff --git a/dts/Bindings/rtc/sa1100-rtc.yaml b/dts/Bindings/rtc/sa1100-rtc.yaml index a16c355dcd..fcf52d2cac 100644 --- a/dts/Bindings/rtc/sa1100-rtc.yaml +++ b/dts/Bindings/rtc/sa1100-rtc.yaml @@ -12,7 +12,7 @@ allOf: maintainers: - Alessandro Zummo <a.zummo@towertech.it> - Alexandre Belloni <alexandre.belloni@bootlin.com> - - Rob Herring <robh+dt@kernel.org> + - Rob Herring <robh@kernel.org> properties: compatible: diff --git a/dts/Bindings/rtc/xlnx,zynqmp-rtc.yaml b/dts/Bindings/rtc/xlnx,zynqmp-rtc.yaml index d1f5eb996d..01cc90fee8 100644 --- a/dts/Bindings/rtc/xlnx,zynqmp-rtc.yaml +++ b/dts/Bindings/rtc/xlnx,zynqmp-rtc.yaml @@ -18,7 +18,13 @@ allOf: properties: compatible: - const: xlnx,zynqmp-rtc + oneOf: + - const: xlnx,zynqmp-rtc + - items: + - enum: + - xlnx,versal-rtc + - xlnx,versal-net-rtc + - const: xlnx,zynqmp-rtc reg: maxItems: 1 @@ -48,6 +54,9 @@ properties: default: 0x198233 deprecated: true + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/serial/cdns,uart.yaml b/dts/Bindings/serial/cdns,uart.yaml index e35ad1109e..2129247d7c 100644 --- a/dts/Bindings/serial/cdns,uart.yaml +++ b/dts/Bindings/serial/cdns,uart.yaml @@ -55,6 +55,7 @@ required: allOf: - $ref: serial.yaml# + - $ref: rs485.yaml# - if: properties: compatible: diff --git a/dts/Bindings/serial/fsl-lpuart.yaml b/dts/Bindings/serial/fsl-lpuart.yaml index 3a5b59f5d3..3f9ace89de 100644 --- a/dts/Bindings/serial/fsl-lpuart.yaml +++ b/dts/Bindings/serial/fsl-lpuart.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - fsl,imx93-lpuart + - fsl,imx95-lpuart - const: fsl,imx8ulp-lpuart - const: fsl,imx7ulp-lpuart - items: diff --git a/dts/Bindings/serial/renesas,hscif.yaml b/dts/Bindings/serial/renesas,hscif.yaml index 2046e2dc0a..9480ed3091 100644 --- a/dts/Bindings/serial/renesas,hscif.yaml +++ b/dts/Bindings/serial/renesas,hscif.yaml @@ -59,6 +59,7 @@ properties: - renesas,hscif-r8a779a0 # R-Car V3U - renesas,hscif-r8a779f0 # R-Car S4-8 - renesas,hscif-r8a779g0 # R-Car V4H + - renesas,hscif-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-hscif # R-Car Gen4 - const: renesas,hscif # generic HSCIF compatible UART diff --git a/dts/Bindings/serial/samsung_uart.yaml b/dts/Bindings/serial/samsung_uart.yaml index 133259ed3a..0f01310269 100644 --- a/dts/Bindings/serial/samsung_uart.yaml +++ b/dts/Bindings/serial/samsung_uart.yaml @@ -143,6 +143,8 @@ allOf: then: required: - samsung,uart-fifosize + properties: + reg-io-width: false unevaluatedProperties: false diff --git a/dts/Bindings/serial/serial.yaml b/dts/Bindings/serial/serial.yaml index 65804ca274..ffc9198ae2 100644 --- a/dts/Bindings/serial/serial.yaml +++ b/dts/Bindings/serial/serial.yaml @@ -88,7 +88,7 @@ properties: TX FIFO threshold configuration (in bytes). patternProperties: - "^(bluetooth|bluetooth-gnss|gnss|gps|mcu)$": + "^(bluetooth|bluetooth-gnss|gnss|gps|mcu|onewire)$": if: type: object then: diff --git a/dts/Bindings/serial/st,asc.yaml b/dts/Bindings/serial/st,asc.yaml new file mode 100644 index 0000000000..f2083388f3 --- /dev/null +++ b/dts/Bindings/serial/st,asc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/st,asc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STi SoCs Serial Port + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: st,asc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + st,hw-flow-ctrl: + description: When set, enable hardware flow control. + type: boolean + + st,force-m1: + description: When set, force asc to be in Mode-1. This is recommended for + high bit rates above 19.2K. + type: boolean + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/stih407-clks.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + serial@9830000 { + compatible = "st,asc"; + reg = <0x9830000 0x2c>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + }; +... diff --git a/dts/Bindings/serial/st,stm32-uart.yaml b/dts/Bindings/serial/st,stm32-uart.yaml index 1df8ffe95f..62f97da1b2 100644 --- a/dts/Bindings/serial/st,stm32-uart.yaml +++ b/dts/Bindings/serial/st,stm32-uart.yaml @@ -58,6 +58,9 @@ properties: wakeup-source: true + power-domains: + maxItems: 1 + rx-threshold: description: If value is set to 1, RX FIFO threshold is disabled. diff --git a/dts/Bindings/serial/st-asc.txt b/dts/Bindings/serial/st-asc.txt deleted file mode 100644 index a1b9b6f349..0000000000 --- a/dts/Bindings/serial/st-asc.txt +++ /dev/null @@ -1,18 +0,0 @@ -*st-asc(Serial Port) - -Required properties: -- compatible : Should be "st,asc". -- reg, reg-names, interrupts, interrupt-names : Standard way to define device - resources with names. look in - Documentation/devicetree/bindings/resource-names.txt - -Optional properties: -- st,hw-flow-ctrl bool flag to enable hardware flow control. -- st,force-m1 bool flat to force asc to be in Mode-1 recommended - for high bit rates (above 19.2K) -Example: -serial@fe440000{ - compatible = "st,asc"; - reg = <0xfe440000 0x2c>; - interrupts = <0 209 0>; -}; diff --git a/dts/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml b/dts/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml index 397f75909b..ce1a6505eb 100644 --- a/dts/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml +++ b/dts/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml @@ -51,7 +51,7 @@ properties: ranges: true patternProperties: - "^clock-controller@[0-9a-z]+$": + "^clock-controller@[0-9a-f]+$": $ref: /schemas/clock/fsl,flexspi-clock.yaml# required: diff --git a/dts/Bindings/soc/fsl/fsl,layerscape-scfg.yaml b/dts/Bindings/soc/fsl/fsl,layerscape-scfg.yaml index 8d088b5fe8..a6a511b00a 100644 --- a/dts/Bindings/soc/fsl/fsl,layerscape-scfg.yaml +++ b/dts/Bindings/soc/fsl/fsl,layerscape-scfg.yaml @@ -41,7 +41,7 @@ properties: ranges: true patternProperties: - "^interrupt-controller@[a-z0-9]+$": + "^interrupt-controller@[a-f0-9]+$": $ref: /schemas/interrupt-controller/fsl,ls-extirq.yaml# required: diff --git a/dts/Bindings/soc/imx/fsl,imx-anatop.yaml b/dts/Bindings/soc/imx/fsl,imx-anatop.yaml new file mode 100644 index 0000000000..c4ae4f2842 --- /dev/null +++ b/dts/Bindings/soc/imx/fsl,imx-anatop.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ANATOP register + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx6sl-anatop + - fsl,imx6sll-anatop + - fsl,imx6sx-anatop + - fsl,imx6ul-anatop + - fsl,imx7d-anatop + - const: fsl,imx6q-anatop + - const: syscon + - const: simple-mfd + - items: + - const: fsl,imx6q-anatop + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + items: + - description: Temperature sensor event + - description: Brown-out event on either of the support regulators + - description: Brown-out event on either the core, gpu or soc regulators + + tempmon: + type: object + unevaluatedProperties: false + $ref: /schemas/thermal/imx-thermal.yaml + +patternProperties: + "regulator-((1p1)|(2p5)|(3p0)|(vddcore)|(vddpu)|(vddsoc))$": + type: object + unevaluatedProperties: false + $ref: /schemas/regulator/anatop-regulator.yaml + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6ul-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + anatop: anatop@20c8000 { + compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", + "syscon", "simple-mfd"; + reg = <0x020c8000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + + reg_3p0: regulator-3p0 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; + }; + }; diff --git a/dts/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml b/dts/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml index 1da1b758b4..8451cb4dd8 100644 --- a/dts/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml +++ b/dts/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml @@ -17,7 +17,23 @@ properties: compatible: oneOf: - items: - - const: fsl,imx8mq-iomuxc-gpr + - enum: + - fsl,imx6q-iomuxc-gpr + - fsl,imx8mq-iomuxc-gpr + - const: syscon + - const: simple-mfd + - items: + - enum: + - fsl,imx6sl-iomuxc-gpr + - fsl,imx6sll-iomuxc-gpr + - fsl,imx6ul-iomuxc-gpr + - const: fsl,imx6q-iomuxc-gpr + - const: syscon + - items: + - enum: + - fsl,imx6sx-iomuxc-gpr + - fsl,imx7d-iomuxc-gpr + - const: fsl,imx6q-iomuxc-gpr - const: syscon - const: simple-mfd - items: diff --git a/dts/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml b/dts/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml index 1be4ce2a45..bd1cdaa4f5 100644 --- a/dts/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml +++ b/dts/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml @@ -27,8 +27,8 @@ properties: const: 1 power-domains: - minItems: 8 - maxItems: 8 + minItems: 10 + maxItems: 10 power-domain-names: items: @@ -40,10 +40,12 @@ properties: - const: trng - const: hdmi-tx - const: hdmi-tx-phy + - const: hdcp + - const: hrv clocks: - minItems: 4 - maxItems: 4 + minItems: 5 + maxItems: 5 clock-names: items: @@ -51,6 +53,7 @@ properties: - const: axi - const: ref_266m - const: ref_24m + - const: fdcc interconnects: maxItems: 3 @@ -82,12 +85,15 @@ examples: clocks = <&clk IMX8MP_CLK_HDMI_APB>, <&clk IMX8MP_CLK_HDMI_ROOT>, <&clk IMX8MP_CLK_HDMI_REF_266M>, - <&clk IMX8MP_CLK_HDMI_24M>; - clock-names = "apb", "axi", "ref_266m", "ref_24m"; + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, - <&pgc_hdmimix>, <&pgc_hdmi_phy>; + <&pgc_hdmimix>, <&pgc_hdmi_phy>, + <&pgc_hdmimix>, <&pgc_hdmimix>; power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng", - "hdmi-tx", "hdmi-tx-phy"; + "hdmi-tx", "hdmi-tx-phy", + "hdcp", "hrv"; #power-domain-cells = <1>; }; diff --git a/dts/Bindings/soc/qcom/qcom,pbs.yaml b/dts/Bindings/soc/qcom/qcom,pbs.yaml new file mode 100644 index 0000000000..b502ca7226 --- /dev/null +++ b/dts/Bindings/soc/qcom/qcom,pbs.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,pbs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Programmable Boot Sequencer + +maintainers: + - Anjelique Melendez <quic_amelende@quicinc.com> + +description: | + The Qualcomm Technologies, Inc. Programmable Boot Sequencer (PBS) + supports triggering power up and power down sequences for clients + upon request. + +properties: + compatible: + items: + - enum: + - qcom,pmi632-pbs + - const: qcom,pbs + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/spmi/spmi.h> + + pmic@0 { + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pbs@7400 { + compatible = "qcom,pmi632-pbs", "qcom,pbs"; + reg = <0x7400>; + }; + }; diff --git a/dts/Bindings/soc/qcom/qcom,pmic-glink.yaml b/dts/Bindings/soc/qcom/qcom,pmic-glink.yaml index 61df97ffe1..4310bae6c5 100644 --- a/dts/Bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/dts/Bindings/soc/qcom/qcom,pmic-glink.yaml @@ -23,6 +23,7 @@ properties: oneOf: - items: - enum: + - qcom,qcm6490-pmic-glink - qcom,sc8180x-pmic-glink - qcom,sc8280xp-pmic-glink - qcom,sm8350-pmic-glink @@ -32,6 +33,7 @@ properties: - items: - enum: - qcom,sm8650-pmic-glink + - qcom,x1e80100-pmic-glink - const: qcom,sm8550-pmic-glink - const: qcom,pmic-glink @@ -65,6 +67,7 @@ allOf: enum: - qcom,sm8450-pmic-glink - qcom,sm8550-pmic-glink + - qcom,x1e80100-pmic-glink then: properties: orientation-gpios: false diff --git a/dts/Bindings/soc/qcom/qcom,rpm-master-stats.yaml b/dts/Bindings/soc/qcom/qcom,rpm-master-stats.yaml index 031800985b..9410404f87 100644 --- a/dts/Bindings/soc/qcom/qcom,rpm-master-stats.yaml +++ b/dts/Bindings/soc/qcom/qcom,rpm-master-stats.yaml @@ -35,6 +35,8 @@ properties: description: Phandle to an RPM MSG RAM slice containing the master stats minItems: 1 maxItems: 5 + items: + maxItems: 1 qcom,master-names: $ref: /schemas/types.yaml#/definitions/string-array diff --git a/dts/Bindings/soc/qcom/qcom,spm.yaml b/dts/Bindings/soc/qcom/qcom,saw2.yaml index 20c8cd38ff..ca4bce8172 100644 --- a/dts/Bindings/soc/qcom/qcom,spm.yaml +++ b/dts/Bindings/soc/qcom/qcom,saw2.yaml @@ -1,23 +1,33 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml# +$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Subsystem Power Manager +title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2) maintainers: - Andy Gross <agross@kernel.org> - Bjorn Andersson <bjorn.andersson@linaro.org> description: | - This binding describes the Qualcomm Subsystem Power Manager, used to control - the peripheral logic surrounding the application cores in Qualcomm platforms. + The Qualcomm Subsystem Power Manager is used to control the peripheral logic + surrounding the application cores in Qualcomm platforms. + + The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the + Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable + power-controller that transitions a piece of hardware (like a processor or + subsystem) into and out of low power modes via a direct connection to + the PMIC. It can also be wired up to interact with other processors in the + system, notifying them when a low power state is entered or exited. properties: compatible: items: - enum: + - qcom,ipq4019-saw2-cpu + - qcom,ipq4019-saw2-l2 + - qcom,ipq8064-saw2-cpu - qcom,sdm660-gold-saw2-v4.1-l2 - qcom,sdm660-silver-saw2-v4.1-l2 - qcom,msm8998-gold-saw2-v4.1-l2 @@ -26,16 +36,27 @@ properties: - qcom,msm8916-saw2-v3.0-cpu - qcom,msm8939-saw2-v3.0-cpu - qcom,msm8226-saw2-v2.1-cpu + - qcom,msm8226-saw2-v2.1-l2 + - qcom,msm8960-saw2-cpu - qcom,msm8974-saw2-v2.1-cpu + - qcom,msm8974-saw2-v2.1-l2 - qcom,msm8976-gold-saw2-v2.3-l2 - qcom,msm8976-silver-saw2-v2.3-l2 - qcom,apq8084-saw2-v2.1-cpu + - qcom,apq8084-saw2-v2.1-l2 - qcom,apq8064-saw2-v1.1-cpu - const: qcom,saw2 reg: - description: Base address and size of the SPM register region - maxItems: 1 + items: + - description: Base address and size of the SPM register region + - description: Base address and size of the alias register region + minItems: 1 + + regulator: + $ref: /schemas/regulator/regulator.yaml# + description: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached to. required: - compatible @@ -82,4 +103,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... diff --git a/dts/Bindings/soc/renesas/renesas-soc.yaml b/dts/Bindings/soc/renesas/renesas-soc.yaml new file mode 100644 index 0000000000..5ddd31f30f --- /dev/null +++ b/dts/Bindings/soc/renesas/renesas-soc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas-soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SoC compatibles naming convention + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Niklas Söderlund <niklas.soderlund@ragnatech.se> + +description: | + Guidelines for new compatibles for SoC blocks/components. + When adding new compatibles in new bindings, use the format:: + renesas,SoC-IP + + For example:: + renesas,r8a77965-csi2 + + When adding new compatibles to existing bindings, use the format in the + existing binding, even if it contradicts the above. + +select: + properties: + compatible: + contains: + pattern: "^renesas,.+-.+$" + required: + - compatible + +properties: + compatible: + minItems: 1 + maxItems: 4 + items: + anyOf: + # Preferred naming style for compatibles of SoC components + - pattern: "^renesas,(emev2|r(7s|8a|9a)[a-z0-9]+|rcar|rmobile|rz[a-z0-9]*|sh(7[a-z0-9]+)?|mobile)-[a-z0-9-]+$" + - pattern: "^renesas,(condor|falcon|gr-peach|gray-hawk|salvator|sk-rz|smar(c(2)?)?|spider|white-hawk)(.*)?$" + + # Legacy compatibles + # + # New compatibles are not allowed. + - pattern: "^renesas,(can|cpg|dmac|du|(g)?ether(avb)?|gpio|hscif|(r)?i[i2]c|imr|intc|ipmmu|irqc|jpu|mmcif|msiof|mtu2|pci(e)?|pfc|pwm|[rq]spi|rcar_sound|sata|scif[ab]*|sdhi|thermal|tmu|tpu|usb(2|hs)?|vin|xhci)-[a-z0-9-]+$" + - pattern: "^renesas,(d|s)?bsc(3)?-(r8a73a4|r8a7740|sh73a0)$" + - pattern: "^renesas,em-(gio|sti|uart)$" + - pattern: "^renesas,fsi2-(r8a7740|sh73a0)$" + - pattern: "^renesas,hspi-r8a777[89]$" + - pattern: "^renesas,sysc-(r8a73a4|r8a7740|rmobile|sh73a0)$" + - enum: + - renesas,imr-lx4 + - renesas,mtu2-r7s72100 + + # None SoC component compatibles + # + # Compatibles with the Renesas vendor prefix that do not relate to any SoC + # component are OK. New compatibles are allowed. + - enum: + - renesas,smp-sram + + # Do not fail compatibles not matching the select pattern + # + # Some SoC components in addition to a Renesas compatible list + # compatibles not related to Renesas. The select pattern for this + # schema hits all compatibles that have at lest one Renesas compatible + # and try to validate all values in that compatible array, allow all + # that don't match the schema select pattern. For example, + # + # compatible = "renesas,r9a07g044-mali", "arm,mali-bifrost"; + - pattern: "^(?!renesas,.+-.+).+$" + +additionalProperties: true diff --git a/dts/Bindings/soc/renesas/renesas.yaml b/dts/Bindings/soc/renesas/renesas.yaml index 16ca3ff7b1..c1ce4da2dc 100644 --- a/dts/Bindings/soc/renesas/renesas.yaml +++ b/dts/Bindings/soc/renesas/renesas.yaml @@ -348,12 +348,25 @@ properties: - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000) - const: renesas,r8a779g0 + - description: R-Car V4H (R8A779G2) + items: + - enum: + - renesas,white-hawk-single # White Hawk Single board (RTP8A779G2ASKB0F10SA001) + - const: renesas,r8a779g2 + - const: renesas,r8a779g0 + - items: - enum: - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000) - const: renesas,white-hawk-cpu - const: renesas,r8a779g0 + - description: R-Car V4M (R8A779H0) + items: + - enum: + - renesas,gray-hawk-single # Gray Hawk Single board (RTP8A779H0ASKB0F10S) + - const: renesas,r8a779h0 + - description: R-Car H3e (R8A779M0) items: - enum: @@ -475,12 +488,6 @@ properties: - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L - const: renesas,r9a07g054 - - description: RZ/V2M (R9A09G011) - items: - - enum: - - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 - - const: renesas,r9a09g011 - - description: RZ/G3S (R9A08G045) items: - enum: @@ -500,6 +507,12 @@ properties: - const: renesas,r9a08g045s33 # PCIe support - const: renesas,r9a08g045 + - description: RZ/V2M (R9A09G011) + items: + - enum: + - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 + - const: renesas,r9a09g011 + additionalProperties: true ... diff --git a/dts/Bindings/soc/rockchip/grf.yaml b/dts/Bindings/soc/rockchip/grf.yaml index 9793ea6f0f..0b87c26676 100644 --- a/dts/Bindings/soc/rockchip/grf.yaml +++ b/dts/Bindings/soc/rockchip/grf.yaml @@ -22,12 +22,15 @@ properties: - rockchip,rk3568-usb2phy-grf - rockchip,rk3588-bigcore0-grf - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-hdptxphy-grf - rockchip,rk3588-ioc - rockchip,rk3588-php-grf - rockchip,rk3588-pipe-phy-grf - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf + - rockchip,rk3588-usb-grf + - rockchip,rk3588-usbdpphy-grf - rockchip,rk3588-vo-grf - rockchip,rk3588-vop-grf - rockchip,rv1108-usbgrf @@ -66,6 +69,9 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + "#address-cells": const: 1 @@ -248,6 +254,22 @@ allOf: unevaluatedProperties: false + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3588-vo-grf + + then: + required: + - clocks + + else: + properties: + clocks: false + + examples: - | #include <dt-bindings/clock/rk3399-cru.h> diff --git a/dts/Bindings/soc/samsung/samsung,exynos-sysreg.yaml b/dts/Bindings/soc/samsung/samsung,exynos-sysreg.yaml index 1794e3799f..c0c6ce8fc7 100644 --- a/dts/Bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/dts/Bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -72,6 +72,8 @@ allOf: compatible: contains: enum: + - google,gs101-peric0-sysreg + - google,gs101-peric1-sysreg - samsung,exynos850-cmgp-sysreg - samsung,exynos850-peri-sysreg - samsung,exynos850-sysreg diff --git a/dts/Bindings/soc/xilinx/xilinx.yaml b/dts/Bindings/soc/xilinx/xilinx.yaml index d4c0fe1fe4..131aba5ed9 100644 --- a/dts/Bindings/soc/xilinx/xilinx.yaml +++ b/dts/Bindings/soc/xilinx/xilinx.yaml @@ -117,20 +117,70 @@ properties: - const: xlnx,zynqmp - description: Xilinx Kria SOMs + minItems: 3 items: - - const: xlnx,zynqmp-sm-k26-rev1 - - const: xlnx,zynqmp-sm-k26-revB - - const: xlnx,zynqmp-sm-k26-revA - - const: xlnx,zynqmp-sm-k26 - - const: xlnx,zynqmp + enum: + - xlnx,zynqmp-sm-k26-rev2 + - xlnx,zynqmp-sm-k26-rev1 + - xlnx,zynqmp-sm-k26-revB + - xlnx,zynqmp-sm-k26-revA + - xlnx,zynqmp-sm-k26 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-sm-k26 - description: Xilinx Kria SOMs (starter) + minItems: 3 items: - - const: xlnx,zynqmp-smk-k26-rev1 - - const: xlnx,zynqmp-smk-k26-revB - - const: xlnx,zynqmp-smk-k26-revA - - const: xlnx,zynqmp-smk-k26 - - const: xlnx,zynqmp + enum: + - xlnx,zynqmp-smk-k26-rev2 + - xlnx,zynqmp-smk-k26-rev1 + - xlnx,zynqmp-smk-k26-revB + - xlnx,zynqmp-smk-k26-revA + - xlnx,zynqmp-smk-k26 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-smk-k26 + + - description: Xilinx Kria SOM KV260 revA/Y/Z + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kv260-revA + - xlnx,zynqmp-sk-kv260-revY + - xlnx,zynqmp-sk-kv260-revZ + - xlnx,zynqmp-sk-kv260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kv260-revA + - contains: + const: xlnx,zynqmp-sk-kv260 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KV260 rev2/1/B + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kv260-rev2 + - xlnx,zynqmp-sk-kv260-rev1 + - xlnx,zynqmp-sk-kv260-revB + - xlnx,zynqmp-sk-kv260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kv260-revB + - contains: + const: xlnx,zynqmp-sk-kv260 + - contains: + const: xlnx,zynqmp - description: AMD MicroBlaze V (QEMU) items: diff --git a/dts/Bindings/sound/atmel,asoc-wm8904.yaml b/dts/Bindings/sound/atmel,asoc-wm8904.yaml new file mode 100644 index 0000000000..89a67f8e33 --- /dev/null +++ b/dts/Bindings/sound/atmel,asoc-wm8904.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/atmel,asoc-wm8904.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel wm8904 audio codec complex + +maintainers: + - Dharma Balasubiramani <dharma.b@microchip.com> + +description: + The ASoC audio complex configuration for Atmel with WM8904 audio codec. + +properties: + compatible: + const: atmel,asoc-wm8904 + + atmel,model: + $ref: /schemas/types.yaml#/definitions/string + description: The user-visible name of this sound complex. + + atmel,ssc-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the SSC controller. + + atmel,audio-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the WM8731 audio codec. + + atmel,audio-routing: + description: + A list of the connections between audio components. Each entry is a pair + of strings, the first being the connection's sink, the second being the + connection's source. + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + items: + enum: + # Board Connectors + - Headphone Jack + - Line In Jack + - Mic + # WM8904 CODEC Pins + - IN1L + - IN1R + - IN2L + - IN2R + - IN3L + - IN3R + - HPOUTL + - HPOUTR + - LINEOUTL + - LINEOUTR + - MICBIAS + +required: + - compatible + - atmel,model + - atmel,audio-routing + - atmel,ssc-controller + - atmel,audio-codec + +additionalProperties: false + +examples: + - | + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_mck>; + + atmel,model = "wm8904 @ AT91SAM9N12EK"; + + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; diff --git a/dts/Bindings/sound/atmel,sam9x5-wm8731-audio.yaml b/dts/Bindings/sound/atmel,sam9x5-wm8731-audio.yaml new file mode 100644 index 0000000000..33717b728f --- /dev/null +++ b/dts/Bindings/sound/atmel,sam9x5-wm8731-audio.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/atmel,sam9x5-wm8731-audio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel at91sam9x5ek wm8731 audio complex + +maintainers: + - Dharma Balasubiramani <dharma.b@microchip.com> + +description: + The audio complex configuration for Atmel at91sam9x5ek with WM8731 audio codec. + +properties: + compatible: + const: atmel,sam9x5-wm8731-audio + + atmel,model: + $ref: /schemas/types.yaml#/definitions/string + description: The user-visible name of this sound complex. + + atmel,ssc-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the SSC controller. + + atmel,audio-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the WM8731 audio codec. + + atmel,audio-routing: + description: + A list of the connections between audio components. Each entry is a pair + of strings, the first being the connection's sink, the second being the + connection's source. + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + items: + enum: + # Board Connectors + - Headphone Jack + - Line In Jack + + # CODEC Pins + - LOUT + - ROUT + - LHPOUT + - RHPOUT + - LLINEIN + - RLINEIN + - MICIN + +required: + - compatible + - atmel,model + - atmel,ssc-controller + - atmel,audio-codec + - atmel,audio-routing + +additionalProperties: false + +examples: + - | + sound { + compatible = "atmel,sam9x5-wm8731-audio"; + + atmel,model = "wm8731 @ AT91SAM9X5EK"; + + atmel,audio-routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line In Jack", + "RLINEIN", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; diff --git a/dts/Bindings/sound/atmel,sama5d2-classd.yaml b/dts/Bindings/sound/atmel,sama5d2-classd.yaml index 43d04702ac..ae3162fcfe 100644 --- a/dts/Bindings/sound/atmel,sama5d2-classd.yaml +++ b/dts/Bindings/sound/atmel,sama5d2-classd.yaml @@ -18,7 +18,12 @@ description: properties: compatible: - const: atmel,sama5d2-classd + oneOf: + - items: + - const: atmel,sama5d2-classd + - items: + - const: microchip,sam9x7-classd + - const: atmel,sama5d2-classd reg: maxItems: 1 diff --git a/dts/Bindings/sound/atmel-sam9x5-wm8731-audio.txt b/dts/Bindings/sound/atmel-sam9x5-wm8731-audio.txt deleted file mode 100644 index 8facbce53d..0000000000 --- a/dts/Bindings/sound/atmel-sam9x5-wm8731-audio.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Atmel at91sam9x5ek wm8731 audio complex - -Required properties: - - compatible: "atmel,sam9x5-wm8731-audio" - - atmel,model: The user-visible name of this sound complex. - - atmel,ssc-controller: The phandle of the SSC controller - - atmel,audio-codec: The phandle of the WM8731 audio codec - - atmel,audio-routing: A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. - -Available audio endpoints for the audio-routing table: - -Board connectors: - * Headphone Jack - * Line In Jack - -wm8731 pins: -cf Documentation/devicetree/bindings/sound/wlf,wm8731.yaml - -Example: -sound { - compatible = "atmel,sam9x5-wm8731-audio"; - - atmel,model = "wm8731 @ AT91SAM9X5EK"; - - atmel,audio-routing = - "Headphone Jack", "RHPOUT", - "Headphone Jack", "LHPOUT", - "LLINEIN", "Line In Jack", - "RLINEIN", "Line In Jack"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; -}; diff --git a/dts/Bindings/sound/atmel-wm8904.txt b/dts/Bindings/sound/atmel-wm8904.txt deleted file mode 100644 index 8bbe50c884..0000000000 --- a/dts/Bindings/sound/atmel-wm8904.txt +++ /dev/null @@ -1,55 +0,0 @@ -Atmel ASoC driver with wm8904 audio codec complex - -Required properties: - - compatible: "atmel,asoc-wm8904" - - atmel,model: The user-visible name of this sound complex. - - atmel,audio-routing: A list of the connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. Valid names for sources and - sinks are the WM8904's pins, and the jacks on the board: - - WM8904 pins: - - * IN1L - * IN1R - * IN2L - * IN2R - * IN3L - * IN3R - * HPOUTL - * HPOUTR - * LINEOUTL - * LINEOUTR - * MICBIAS - - Board connectors: - - * Headphone Jack - * Line In Jack - * Mic - - - atmel,ssc-controller: The phandle of the SSC controller - - atmel,audio-codec: The phandle of the WM8904 audio codec - -Optional properties: - - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt - -Example: -sound { - compatible = "atmel,asoc-wm8904"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_mck>; - - atmel,model = "wm8904 @ AT91SAM9N12EK"; - - atmel,audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Mic", "MICBIAS", - "IN1L", "Mic"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8904>; -}; diff --git a/dts/Bindings/sound/audio-graph-port.yaml b/dts/Bindings/sound/audio-graph-port.yaml index b13c08de50..28b27e7e45 100644 --- a/dts/Bindings/sound/audio-graph-port.yaml +++ b/dts/Bindings/sound/audio-graph-port.yaml @@ -51,7 +51,7 @@ definitions: - $ref: /schemas/types.yaml#/definitions/phandle clocks: description: Indicates system clock - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 system-clock-frequency: $ref: simple-card.yaml#/definitions/system-clock-frequency system-clock-direction-out: diff --git a/dts/Bindings/sound/cirrus,cs35l45.yaml b/dts/Bindings/sound/cirrus,cs35l45.yaml index 4c9acb8d4c..70f6c62aed 100644 --- a/dts/Bindings/sound/cirrus,cs35l45.yaml +++ b/dts/Bindings/sound/cirrus,cs35l45.yaml @@ -25,6 +25,9 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 1 + '#sound-dai-cells': const: 1 diff --git a/dts/Bindings/sound/cirrus,cs42l43.yaml b/dts/Bindings/sound/cirrus,cs42l43.yaml index 7f9d8c7a63..99a536601c 100644 --- a/dts/Bindings/sound/cirrus,cs42l43.yaml +++ b/dts/Bindings/sound/cirrus,cs42l43.yaml @@ -185,11 +185,12 @@ properties: gpio-ranges: items: - - description: A phandle to the CODEC pinctrl node - minimum: 0 - - const: 0 - - const: 0 - - const: 3 + - items: + - description: A phandle to the CODEC pinctrl node + minimum: 0 + - const: 0 + - const: 0 + - const: 3 patternProperties: "-state$": diff --git a/dts/Bindings/sound/cs4341.txt b/dts/Bindings/sound/cs4341.txt index 12b4aa8ef0..c1d5c8ad1a 100644 --- a/dts/Bindings/sound/cs4341.txt +++ b/dts/Bindings/sound/cs4341.txt @@ -9,7 +9,7 @@ Required properties: number for SPI. For required properties on I2C-bus, please consult -Documentation/devicetree/bindings/i2c/i2c.txt +dtschema schemas/i2c/i2c-controller.yaml For required properties on SPI-bus, please consult Documentation/devicetree/bindings/spi/spi-bus.txt diff --git a/dts/Bindings/sound/everest,es8326.yaml b/dts/Bindings/sound/everest,es8326.yaml index 07781408e7..8c82d47375 100644 --- a/dts/Bindings/sound/everest,es8326.yaml +++ b/dts/Bindings/sound/everest,es8326.yaml @@ -38,6 +38,7 @@ properties: default: 0x0f everest,mic1-src: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint8 description: the value of reg 2A when headset plugged. @@ -46,6 +47,7 @@ properties: default: 0x22 everest,mic2-src: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint8 description: the value of reg 2A when headset unplugged. @@ -87,7 +89,7 @@ properties: 0 means the chip detect jack type again after button released. minimum: 0 maximum: 0x7f - default: 0x45 + default: 0x00 required: - compatible @@ -107,10 +109,8 @@ examples: clocks = <&clks 10>; clock-names = "mclk"; #sound-dai-cells = <0>; - everest,mic1-src = [22]; - everest,mic2-src = [44]; everest,jack-pol = [0e]; everest,interrupt-src = [08]; - everest,interrupt-clk = [45]; + everest,interrupt-clk = [00]; }; }; diff --git a/dts/Bindings/sound/fsl,asrc.txt b/dts/Bindings/sound/fsl,asrc.txt deleted file mode 100644 index 998b4c8a7f..0000000000 --- a/dts/Bindings/sound/fsl,asrc.txt +++ /dev/null @@ -1,80 +0,0 @@ -Freescale Asynchronous Sample Rate Converter (ASRC) Controller - -The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a -signal associated with an input clock into a signal associated with a different -output clock. The driver currently works as a Front End of DPCM with other Back -Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support -three substreams within totally 10 channels. - -Required properties: - - - compatible : Compatible list, should contain one of the following - compatibles: - "fsl,imx35-asrc", - "fsl,imx53-asrc", - "fsl,imx8qm-asrc", - "fsl,imx8qxp-asrc", - - - reg : Offset and length of the register set for the device. - - - interrupts : Contains the spdif interrupt. - - - dmas : Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. - - - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc". - - - clocks : Contains an entry for each entry in clock-names. - - - clock-names : Contains the following entries - "mem" Peripheral access clock to access registers. - "ipg" Peripheral clock to driver module. - "asrck_<0-f>" Clock sources for input and output clock. - "spba" The spba clock is required when ASRC is placed as a - bus slave of the Shared Peripheral Bus and when two - or more bus masters (CPU, DMA or DSP) try to access - it. This property is optional depending on the SoC - design. - - - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends. - - - fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends. - - - fsl,asrc-clk-map : Defines clock map used in driver. which is required - by imx8qm/imx8qxp platform - <0> - select the map for asrc0 in imx8qm/imx8qxp - <1> - select the map for asrc1 in imx8qm/imx8qxp - -Optional properties: - - - big-endian : If this property is absent, the little endian mode - will be in use as default. Otherwise, the big endian - mode will be in use for all the device registers. - - - fsl,asrc-format : Defines a mutual sample format used by DPCM Back - Ends, which can replace the fsl,asrc-width. - The value is 2 (S16_LE), or 6 (S24_LE). - -Example: - -asrc: asrc@2034000 { - compatible = "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 107>, <&clks 107>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, - <&clks 107>, <&clks 0>, <&clks 0>; - clock-names = "mem", "ipg", "asrck0", - "asrck_1", "asrck_2", "asrck_3", "asrck_4", - "asrck_5", "asrck_6", "asrck_7", "asrck_8", - "asrck_9", "asrck_a", "asrck_b", "asrck_c", - "asrck_d", "asrck_e", "asrck_f"; - dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, - <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; - dma-names = "rxa", "rxb", "rxc", - "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; - fsl,asrc-width = <16>; -}; diff --git a/dts/Bindings/sound/fsl,easrc.yaml b/dts/Bindings/sound/fsl,easrc.yaml index a680d7aff2..0782f3f994 100644 --- a/dts/Bindings/sound/fsl,easrc.yaml +++ b/dts/Bindings/sound/fsl,easrc.yaml @@ -51,8 +51,8 @@ properties: - const: ctx3_tx firmware-name: - $ref: /schemas/types.yaml#/definitions/string - const: imx/easrc/easrc-imx8mn.bin + items: + - const: imx/easrc/easrc-imx8mn.bin description: The coefficient table for the filters fsl,asrc-rate: diff --git a/dts/Bindings/sound/fsl,imx-asrc.yaml b/dts/Bindings/sound/fsl,imx-asrc.yaml new file mode 100644 index 0000000000..bfef2fcb75 --- /dev/null +++ b/dts/Bindings/sound/fsl,imx-asrc.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/fsl,imx-asrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Asynchronous Sample Rate Converter (ASRC) Controller + +description: + The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of + a signal associated with an input clock into a signal associated with a + different output clock. The driver currently works as a Front End of DPCM + with other Back Ends Audio controller such as ESAI, SSI and SAI. It has + three pairs to support three substreams within totally 10 channels. + +maintainers: + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + +properties: + compatible: + oneOf: + - enum: + - fsl,imx35-asrc + - fsl,imx53-asrc + - fsl,imx8qm-asrc + - fsl,imx8qxp-asrc + - items: + - enum: + - fsl,imx6sx-asrc + - fsl,imx6ul-asrc + - const: fsl,imx53-asrc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + maxItems: 6 + + dma-names: + items: + - const: rxa + - const: rxb + - const: rxc + - const: txa + - const: txb + - const: txc + + clocks: + maxItems: 19 + + clock-names: + items: + - const: mem + - const: ipg + - const: asrck_0 + - const: asrck_1 + - const: asrck_2 + - const: asrck_3 + - const: asrck_4 + - const: asrck_5 + - const: asrck_6 + - const: asrck_7 + - const: asrck_8 + - const: asrck_9 + - const: asrck_a + - const: asrck_b + - const: asrck_c + - const: asrck_d + - const: asrck_e + - const: asrck_f + - const: spba + + fsl,asrc-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The mutual sample rate used by DPCM Back Ends + + fsl,asrc-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The mutual sample width used by DPCM Back Ends + enum: [16, 24] + + fsl,asrc-clk-map: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines clock map used in driver + <0> - select the map for asrc0 in imx8qm/imx8qxp + <1> - select the map for asrc1 in imx8qm/imx8qxp + enum: [0, 1] + + big-endian: + type: boolean + description: + If this property is absent, the little endian mode will be in use as + default. Otherwise, the big endian mode will be in use for all the + device registers. + + fsl,asrc-format: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines a mutual sample format used by DPCM Back Ends, which can + replace the fsl,asrc-width. The value is 2 (S16_LE), or 6 (S24_LE). + enum: [2, 6] + +required: + - compatible + - reg + - interrupts + - dmas + - dma-names + - clocks + - clock-names + - fsl,asrc-rate + - fsl,asrc-width + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-asrc + - fsl,imx8qxp-asrc + then: + required: + - fsl,asrc-clk-map + else: + properties: + fsl,asrc-clk-map: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/imx6qdl-clock.h> + asrc: asrc@2034000 { + compatible = "fsl,imx53-asrc"; + reg = <0x02034000 0x4000>; + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, + <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, + <&clks IMX6QDL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + }; diff --git a/dts/Bindings/sound/fsl,micfil.yaml b/dts/Bindings/sound/fsl,micfil.yaml index b7e6058356..c1e9803fc1 100644 --- a/dts/Bindings/sound/fsl,micfil.yaml +++ b/dts/Bindings/sound/fsl,micfil.yaml @@ -15,10 +15,16 @@ description: | properties: compatible: - enum: - - fsl,imx8mm-micfil - - fsl,imx8mp-micfil - - fsl,imx93-micfil + oneOf: + - items: + - enum: + - fsl,imx95-micfil + - const: fsl,imx93-micfil + + - enum: + - fsl,imx8mm-micfil + - fsl,imx8mp-micfil + - fsl,imx93-micfil reg: maxItems: 1 diff --git a/dts/Bindings/sound/fsl,sai.yaml b/dts/Bindings/sound/fsl,sai.yaml index 088c26b001..2456d958ad 100644 --- a/dts/Bindings/sound/fsl,sai.yaml +++ b/dts/Bindings/sound/fsl,sai.yaml @@ -39,6 +39,7 @@ properties: - fsl,imx8qm-sai - fsl,imx8ulp-sai - fsl,imx93-sai + - fsl,imx95-sai - fsl,vf610-sai reg: @@ -75,12 +76,17 @@ properties: - const: pll11k minItems: 4 + power-domains: + maxItems: 1 + dmas: + minItems: 1 items: - description: DMA controller phandle and request line for RX - description: DMA controller phandle and request line for TX dma-names: + minItems: 1 items: - const: rx - const: tx diff --git a/dts/Bindings/sound/infineon,peb2466.yaml b/dts/Bindings/sound/infineon,peb2466.yaml index 66993d378a..5e11ce2c13 100644 --- a/dts/Bindings/sound/infineon,peb2466.yaml +++ b/dts/Bindings/sound/infineon,peb2466.yaml @@ -51,7 +51,7 @@ properties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: Filters coefficients file to load. If this property is omitted, internal filters are disabled. diff --git a/dts/Bindings/sound/microchip,sama7g5-i2smcc.yaml b/dts/Bindings/sound/microchip,sama7g5-i2smcc.yaml index 651f61c7c2..fb630a1843 100644 --- a/dts/Bindings/sound/microchip,sama7g5-i2smcc.yaml +++ b/dts/Bindings/sound/microchip,sama7g5-i2smcc.yaml @@ -24,9 +24,14 @@ properties: const: 0 compatible: - enum: - - microchip,sam9x60-i2smcc - - microchip,sama7g5-i2smcc + oneOf: + - enum: + - microchip,sam9x60-i2smcc + - microchip,sama7g5-i2smcc + - items: + - enum: + - microchip,sam9x7-i2smcc + - const: microchip,sam9x60-i2smcc reg: maxItems: 1 diff --git a/dts/Bindings/sound/qcom,q6usb.yaml b/dts/Bindings/sound/qcom,q6usb.yaml new file mode 100644 index 0000000000..37161d2aa9 --- /dev/null +++ b/dts/Bindings/sound/qcom,q6usb.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,q6usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ASoC DPCM USB backend DAI + +maintainers: + - Wesley Cheng <quic_wcheng@quicinc.com> + +description: + The USB port is a supported AFE path on the Q6 DSP. This ASoC DPCM + backend DAI will communicate the required settings to initialize the + XHCI host controller properly for enabling the offloaded audio stream. + Parameters defined under this node will carry settings, which will be + passed along during the QMI stream enable request and configuration of + the XHCI host controller. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - qcom,q6usb + + iommus: + maxItems: 1 + + "#sound-dai-cells": + const: 1 + + qcom,usb-audio-intr-idx: + description: + Desired XHCI interrupter number to use. Depending on the audio DSP + on the platform, it will operate on a specific XHCI interrupter. + $ref: /schemas/types.yaml#/definitions/uint16 + maximum: 8 + +required: + - compatible + - "#sound-dai-cells" + - qcom,usb-audio-intr-idx + +additionalProperties: false + +examples: + - | + dais { + compatible = "qcom,q6usb"; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x180f 0x0>; + qcom,usb-audio-intr-idx = /bits/ 16 <2>; + }; diff --git a/dts/Bindings/sound/qcom,sm8250.yaml b/dts/Bindings/sound/qcom,sm8250.yaml index 6f41974727..2ab6871e89 100644 --- a/dts/Bindings/sound/qcom,sm8250.yaml +++ b/dts/Bindings/sound/qcom,sm8250.yaml @@ -107,7 +107,7 @@ patternProperties: properties: sound-dai: minItems: 1 - maxItems: 4 + maxItems: 8 required: - link-name diff --git a/dts/Bindings/sound/qcom,wcd938x.yaml b/dts/Bindings/sound/qcom,wcd938x.yaml index adbfa67f88..cf6c3787ad 100644 --- a/dts/Bindings/sound/qcom,wcd938x.yaml +++ b/dts/Bindings/sound/qcom,wcd938x.yaml @@ -15,6 +15,7 @@ description: | allOf: - $ref: dai-common.yaml# + - $ref: qcom,wcd93xx-common.yaml# properties: compatible: @@ -22,92 +23,12 @@ properties: - qcom,wcd9380-codec - qcom,wcd9385-codec - reset-gpios: - description: GPIO spec for reset line to use - maxItems: 1 - us-euro-gpios: description: GPIO spec for swapping gnd and mic segments maxItems: 1 - vdd-buck-supply: - description: A reference to the 1.8V buck supply - - vdd-rxtx-supply: - description: A reference to the 1.8V rx supply - - vdd-io-supply: - description: A reference to the 1.8V I/O supply - - vdd-mic-bias-supply: - description: A reference to the 3.8V mic bias supply - - qcom,tx-device: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: A reference to Soundwire tx device phandle - - qcom,rx-device: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: A reference to Soundwire rx device phandle - - qcom,micbias1-microvolt: - description: micbias1 voltage - minimum: 1800000 - maximum: 2850000 - - qcom,micbias2-microvolt: - description: micbias2 voltage - minimum: 1800000 - maximum: 2850000 - - qcom,micbias3-microvolt: - description: micbias3 voltage - minimum: 1800000 - maximum: 2850000 - - qcom,micbias4-microvolt: - description: micbias4 voltage - minimum: 1800000 - maximum: 2850000 - - qcom,hphl-jack-type-normally-closed: - description: Indicates that HPHL jack switch type is normally closed - type: boolean - - qcom,ground-jack-type-normally-closed: - description: Indicates that Headset Ground switch type is normally closed - type: boolean - - qcom,mbhc-headset-vthreshold-microvolt: - description: Voltage threshold value for headset detection - minimum: 0 - maximum: 2850000 - - qcom,mbhc-headphone-vthreshold-microvolt: - description: Voltage threshold value for headphone detection - minimum: 0 - maximum: 2850000 - - qcom,mbhc-buttons-vthreshold-microvolt: - description: - Array of 8 Voltage threshold values corresponding to headset - button0 - button7 - minItems: 8 - maxItems: 8 - - '#sound-dai-cells': - const: 1 - required: - compatible - - reset-gpios - - qcom,tx-device - - qcom,rx-device - - qcom,micbias1-microvolt - - qcom,micbias2-microvolt - - qcom,micbias3-microvolt - - qcom,micbias4-microvolt - - "#sound-dai-cells" unevaluatedProperties: false diff --git a/dts/Bindings/sound/qcom,wcd939x-sdw.yaml b/dts/Bindings/sound/qcom,wcd939x-sdw.yaml new file mode 100644 index 0000000000..67ed7701b5 --- /dev/null +++ b/dts/Bindings/sound/qcom,wcd939x-sdw.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd939x-sdw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SoundWire devices on WCD9390/WCD9395 + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC. + It has RX and TX Soundwire devices. This bindings is for the devices. + +properties: + compatible: + const: sdw20217010e00 + + reg: + maxItems: 1 + + qcom,tx-port-mapping: + description: | + Specifies static port mapping between device and host tx ports. + In the order of the device port index. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 4 + maxItems: 4 + + qcom,rx-port-mapping: + description: | + Specifies static port mapping between device and host rx ports. + In the order of device port index. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 6 + maxItems: 6 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soundwire@3210000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03210000 0x2000>; + wcd938x_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5 6>; + }; + }; + + soundwire@3230000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03230000 0x2000>; + wcd938x_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 3 4 5>; + }; + }; + +... diff --git a/dts/Bindings/sound/qcom,wcd939x.yaml b/dts/Bindings/sound/qcom,wcd939x.yaml new file mode 100644 index 0000000000..6e76f6a863 --- /dev/null +++ b/dts/Bindings/sound/qcom,wcd939x.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd939x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm WCD9380/WCD9385 Audio Codec + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC. + It has RX and TX Soundwire devices. + The WCD9390/WCD9395 IC has a functionally separate USB-C Mux subsystem + accessible over an I2C interface. + The Audio Headphone and Microphone data path between the Codec and the USB-C Mux + subsystems are external to the IC, thus requiring DT port-endpoint graph description + to handle USB-C altmode & orientation switching for Audio Accessory Mode. + +allOf: + - $ref: dai-common.yaml# + - $ref: qcom,wcd93xx-common.yaml# + +properties: + compatible: + oneOf: + - const: qcom,wcd9390-codec + - items: + - const: qcom,wcd9395-codec + - const: qcom,wcd9390-codec + + mode-switch: + description: Flag the port as possible handler of altmode switching + type: boolean + + orientation-switch: + description: Flag the port as possible handler of orientation switching + type: boolean + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node to link the WCD939x Codec node to USB MUX subsystems for the + purpose of handling altmode muxing and orientation switching to detect and + enable Audio Accessory Mode. + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + codec { + compatible = "qcom,wcd9390-codec"; + reset-gpios = <&tlmm 32 IRQ_TYPE_NONE>; + #sound-dai-cells = <1>; + qcom,tx-device = <&wcd939x_tx>; + qcom,rx-device = <&wcd939x_rx>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,hphl-jack-type-normally-closed; + qcom,ground-jack-type-normally-closed; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + }; + + /* ... */ + + soundwire@3210000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03210000 0x2000>; + wcd939x_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5 6>; + }; + }; + + soundwire@3230000 { + #address-cells = <2>; + #size-cells = <0>; + reg = <0x03230000 0x2000>; + wcd938x_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 3 4 5>; + }; + }; + +... diff --git a/dts/Bindings/sound/qcom,wcd93xx-common.yaml b/dts/Bindings/sound/qcom,wcd93xx-common.yaml new file mode 100644 index 0000000000..f78ba148ad --- /dev/null +++ b/dts/Bindings/sound/qcom,wcd93xx-common.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd93xx-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for Qualcomm WCD93xx Audio Codec + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +properties: + reset-gpios: + description: GPIO spec for reset line to use + maxItems: 1 + + vdd-buck-supply: + description: A reference to the 1.8V buck supply + + vdd-rxtx-supply: + description: A reference to the 1.8V rx supply + + vdd-io-supply: + description: A reference to the 1.8V I/O supply + + vdd-mic-bias-supply: + description: A reference to the 3.8V mic bias supply + + qcom,tx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire tx device phandle + + qcom,rx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire rx device phandle + + qcom,micbias1-microvolt: + description: micbias1 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias2-microvolt: + description: micbias2 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias3-microvolt: + description: micbias3 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias4-microvolt: + description: micbias4 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,hphl-jack-type-normally-closed: + description: Indicates that HPHL jack switch type is normally closed + type: boolean + + qcom,ground-jack-type-normally-closed: + description: Indicates that Headset Ground switch type is normally closed + type: boolean + + qcom,mbhc-headset-vthreshold-microvolt: + description: Voltage threshold value for headset detection + minimum: 0 + maximum: 2850000 + + qcom,mbhc-headphone-vthreshold-microvolt: + description: Voltage threshold value for headphone detection + minimum: 0 + maximum: 2850000 + + qcom,mbhc-buttons-vthreshold-microvolt: + description: + Array of 8 Voltage threshold values corresponding to headset + button0 - button7 + minItems: 8 + maxItems: 8 + + '#sound-dai-cells': + const: 1 + +required: + - reset-gpios + - qcom,tx-device + - qcom,rx-device + - qcom,micbias1-microvolt + - qcom,micbias2-microvolt + - qcom,micbias3-microvolt + - qcom,micbias4-microvolt + - "#sound-dai-cells" + +additionalProperties: true diff --git a/dts/Bindings/sound/qcom,wsa8840.yaml b/dts/Bindings/sound/qcom,wsa8840.yaml index d717017b0f..22798d22d9 100644 --- a/dts/Bindings/sound/qcom,wsa8840.yaml +++ b/dts/Bindings/sound/qcom,wsa8840.yaml @@ -28,6 +28,10 @@ properties: description: Powerdown/Shutdown line to use (pin SD_N) maxItems: 1 + reset-gpios: + description: Powerdown/Shutdown line to use (pin SD_N) + maxItems: 1 + '#sound-dai-cells': const: 0 @@ -37,11 +41,16 @@ properties: required: - compatible - reg - - powerdown-gpios - '#sound-dai-cells' - vdd-1p8-supply - vdd-io-supply +oneOf: + - required: + - powerdown-gpios + - required: + - reset-gpios + unevaluatedProperties: false examples: diff --git a/dts/Bindings/sound/realtek,rt1015.yaml b/dts/Bindings/sound/realtek,rt1015.yaml new file mode 100644 index 0000000000..880196081a --- /dev/null +++ b/dts/Bindings/sound/realtek,rt1015.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/realtek,rt1015.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RT1015 Mono Class D Audio Amplifier + +maintainers: + - Jack Yu <jack.yu@realtek.com> + +properties: + compatible: + enum: + - realtek,rt1015 + + reg: + maxItems: 1 + + realtek,power-up-delay-ms: + description: Set a delay time for flush work to be completed, + this vlaue is adjustable depending on platform. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + codec@28 { + compatible = "realtek,rt1015"; + reg = <0x28>; + realtek,power-up-delay-ms = <50>; + }; + }; diff --git a/dts/Bindings/sound/rt1015.txt b/dts/Bindings/sound/rt1015.txt deleted file mode 100644 index e498966d43..0000000000 --- a/dts/Bindings/sound/rt1015.txt +++ /dev/null @@ -1,23 +0,0 @@ -RT1015 Mono Class D Audio Amplifier - -This device supports I2C only. - -Required properties: - -- compatible : "realtek,rt1015". - -- reg : The I2C address of the device. - -Optional properties: - -- realtek,power-up-delay-ms - Set a delay time for flush work to be completed, - this value is adjustable depending on platform. - -Example: - -rt1015: codec@28 { - compatible = "realtek,rt1015"; - reg = <0x28>; - realtek,power-up-delay-ms = <50>; -}; diff --git a/dts/Bindings/sound/samsung,tm2.yaml b/dts/Bindings/sound/samsung,tm2.yaml index 7605925991..cbc7ba3736 100644 --- a/dts/Bindings/sound/samsung,tm2.yaml +++ b/dts/Bindings/sound/samsung,tm2.yaml @@ -25,8 +25,11 @@ properties: description: Phandles to the codecs. $ref: /schemas/types.yaml#/definitions/phandle-array items: - - description: Phandle to the WM5110 audio codec. - - description: Phandle to the HDMI transmitter node. + - items: + - description: Phandle to the WM5110 audio codec. + - items: + - description: Phandle to the HDMI transmitter node. + samsung,audio-routing: description: | diff --git a/dts/Bindings/spi/atmel,at91rm9200-spi.yaml b/dts/Bindings/spi/atmel,at91rm9200-spi.yaml index 58367587bf..32e7c14033 100644 --- a/dts/Bindings/spi/atmel,at91rm9200-spi.yaml +++ b/dts/Bindings/spi/atmel,at91rm9200-spi.yaml @@ -22,7 +22,6 @@ properties: - const: atmel,at91rm9200-spi - items: - const: microchip,sam9x7-spi - - const: microchip,sam9x60-spi - const: atmel,at91rm9200-spi reg: diff --git a/dts/Bindings/spi/samsung,spi.yaml b/dts/Bindings/spi/samsung,spi.yaml index 79da99ca0e..f681372da8 100644 --- a/dts/Bindings/spi/samsung,spi.yaml +++ b/dts/Bindings/spi/samsung,spi.yaml @@ -17,11 +17,13 @@ properties: compatible: oneOf: - enum: + - google,gs101-spi - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 - samsung,s3c6410-spi - samsung,s5pv210-spi # for S5PV210 and S5PC110 - samsung,exynos4210-spi - samsung,exynos5433-spi + - samsung,exynos850-spi - samsung,exynosautov9-spi - tesla,fsd-spi - const: samsung,exynos7-spi @@ -74,8 +76,6 @@ required: - compatible - clocks - clock-names - - dmas - - dma-names - interrupts - reg diff --git a/dts/Bindings/spi/spi-controller.yaml b/dts/Bindings/spi/spi-controller.yaml index 524f6fe8c2..093150c0cb 100644 --- a/dts/Bindings/spi/spi-controller.yaml +++ b/dts/Bindings/spi/spi-controller.yaml @@ -69,6 +69,21 @@ properties: Should be generally avoided and be replaced by spi-cs-high + ACTIVE_HIGH. + fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the RX and TX data FIFOs in bytes. + + rx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the RX data FIFO in bytes. + + tx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the TX data FIFO in bytes. + num-cs: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -116,6 +131,10 @@ patternProperties: - compatible - reg +dependencies: + rx-fifo-depth: [ tx-fifo-depth ] + tx-fifo-depth: [ rx-fifo-depth ] + allOf: - if: not: @@ -129,6 +148,14 @@ allOf: properties: "#address-cells": const: 0 + - not: + required: + - fifo-depth + - rx-fifo-depth + - not: + required: + - fifo-depth + - tx-fifo-depth additionalProperties: true diff --git a/dts/Bindings/spi/spi-fsl-lpspi.yaml b/dts/Bindings/spi/spi-fsl-lpspi.yaml index 727c5346b8..2ff1742447 100644 --- a/dts/Bindings/spi/spi-fsl-lpspi.yaml +++ b/dts/Bindings/spi/spi-fsl-lpspi.yaml @@ -22,6 +22,7 @@ properties: - enum: - fsl,imx8ulp-spi - fsl,imx93-spi + - fsl,imx95-spi - const: fsl,imx7ulp-spi reg: maxItems: 1 diff --git a/dts/Bindings/spi/spi-nxp-fspi.yaml b/dts/Bindings/spi/spi-nxp-fspi.yaml index 7fd5911454..4a5f41bde0 100644 --- a/dts/Bindings/spi/spi-nxp-fspi.yaml +++ b/dts/Bindings/spi/spi-nxp-fspi.yaml @@ -15,12 +15,18 @@ allOf: properties: compatible: - enum: - - nxp,imx8dxl-fspi - - nxp,imx8mm-fspi - - nxp,imx8mp-fspi - - nxp,imx8qxp-fspi - - nxp,lx2160a-fspi + oneOf: + - enum: + - nxp,imx8dxl-fspi + - nxp,imx8mm-fspi + - nxp,imx8mp-fspi + - nxp,imx8qxp-fspi + - nxp,lx2160a-fspi + - items: + - enum: + - nxp,imx93-fspi + - nxp,imx95-fspi + - const: nxp,imx8mm-fspi reg: items: diff --git a/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml b/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml index a1c9698595..cf07b8f787 100644 --- a/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -56,7 +56,7 @@ properties: ranges: true patternProperties: - "^sram@[a-z0-9]+": + "^sram@[a-f0-9]+": $ref: /schemas/sram/sram.yaml# unevaluatedProperties: false diff --git a/dts/Bindings/submitting-patches.rst b/dts/Bindings/submitting-patches.rst index 36a17b250c..a64f21a5f2 100644 --- a/dts/Bindings/submitting-patches.rst +++ b/dts/Bindings/submitting-patches.rst @@ -15,6 +15,11 @@ I. For patch submitters "dt-bindings: <binding dir>: ..." + Few subsystems, like ASoC, media, regulators and SPI, expect reverse order + of the prefixes:: + + "<binding dir>: dt-bindings: ..." + The 80 characters of the subject are precious. It is recommended to not use "Documentation" or "doc" because that is implied. All bindings are docs. Repeating "binding" again should also be avoided. @@ -42,28 +47,18 @@ I. For patch submitters the code implementing the binding. 6) Any compatible strings used in a chip or board DTS file must be - previously documented in the corresponding DT binding text file + previously documented in the corresponding DT binding file in Documentation/devicetree/bindings. This rule applies even if the Linux device driver does not yet match on the compatible string. [ checkpatch will emit warnings if this step is not followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864 ("checkpatch: add DT compatible string documentation checks"). ] - 7) The wildcard "<chip>" may be used in compatible strings, as in - the following example: - - - compatible: Must contain '"nvidia,<chip>-pcie", - "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ... - - As in the above example, the known values of "<chip>" should be - documented if it is used. - - 8) If a documented compatible string is not yet matched by the + 7) If a documented compatible string is not yet matched by the driver, the documentation should also include a compatible - string that is matched by the driver (as in the "nvidia,tegra20-pcie" - example above). + string that is matched by the driver. - 9) Bindings are actively used by multiple projects other than the Linux + 8) Bindings are actively used by multiple projects other than the Linux Kernel, extra care and consideration may need to be taken when making changes to existing bindings. diff --git a/dts/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/dts/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml index 9b2272a9ec..6b3aea6d73 100644 --- a/dts/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/dts/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -21,6 +21,7 @@ properties: - allwinner,sun50i-a100-ths - allwinner,sun50i-h5-ths - allwinner,sun50i-h6-ths + - allwinner,sun50i-h616-ths clocks: minItems: 1 @@ -50,6 +51,10 @@ properties: nvmem-cell-names: const: calibration + allwinner,sram: + maxItems: 1 + description: phandle to device controlling temperate offset SYS_CFG register + # See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details "#thermal-sensor-cells": enum: @@ -65,6 +70,7 @@ allOf: - allwinner,sun20i-d1-ths - allwinner,sun50i-a100-ths - allwinner,sun50i-h6-ths + - allwinner,sun50i-h616-ths then: properties: @@ -83,6 +89,17 @@ allOf: minItems: 2 - if: + not: + properties: + compatible: + contains: + const: allwinner,sun50i-h616-ths + + then: + properties: + allwinner,sram: false + + - if: properties: compatible: contains: @@ -101,17 +118,12 @@ allOf: const: 1 - if: - properties: - compatible: - contains: - enum: - - allwinner,sun8i-h3-ths - - allwinner,sun8i-r40-ths - - allwinner,sun20i-d1-ths - - allwinner,sun50i-a64-ths - - allwinner,sun50i-a100-ths - - allwinner,sun50i-h5-ths - - allwinner,sun50i-h6-ths + not: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-ths then: required: diff --git a/dts/Bindings/thermal/da9062-thermal.txt b/dts/Bindings/thermal/da9062-thermal.txt deleted file mode 100644 index e241bb5a55..0000000000 --- a/dts/Bindings/thermal/da9062-thermal.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Dialog DA9062/61 TJUNC Thermal Module - -This module is part of the DA9061/DA9062. For more details about entire -DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt - -Junction temperature thermal module uses an interrupt signal to identify -high THERMAL_TRIP_HOT temperatures for the PMIC device. - -Required properties: - -- compatible: should be one of the following valid compatible string lines: - "dlg,da9061-thermal", "dlg,da9062-thermal" - "dlg,da9062-thermal" - -Optional properties: - -- polling-delay-passive : Specify the polling period, measured in - milliseconds, between thermal zone device update checks. - -Example: DA9062 - - pmic0: da9062@58 { - thermal { - compatible = "dlg,da9062-thermal"; - polling-delay-passive = <3000>; - }; - }; - -Example: DA9061 using a fall-back compatible for the DA9062 onkey driver - - pmic0: da9061@58 { - thermal { - compatible = "dlg,da9061-thermal", "dlg,da9062-thermal"; - polling-delay-passive = <3000>; - }; - }; diff --git a/dts/Bindings/thermal/dlg,da9062-thermal.yaml b/dts/Bindings/thermal/dlg,da9062-thermal.yaml new file mode 100644 index 0000000000..e8b2cac410 --- /dev/null +++ b/dts/Bindings/thermal/dlg,da9062-thermal.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/dlg,da9062-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dialog DA9062/61 TJUNC Thermal Module + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + This module is part of the DA9061/DA9062. For more details about entire + DA906{1,2} chips see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml + + Junction temperature thermal module uses an interrupt signal to identify + high THERMAL_TRIP_HOT temperatures for the PMIC device. + +properties: + compatible: + oneOf: + - const: dlg,da9062-thermal + - items: + - const: dlg,da9061-thermal + - const: dlg,da9062-thermal + + polling-delay-passive: + description: + Specify the polling period, measured in milliseconds, between + thermal zone device update checks. + +required: + - compatible + +additionalProperties: false diff --git a/dts/Bindings/thermal/qoriq-thermal.yaml b/dts/Bindings/thermal/qoriq-thermal.yaml index 1457440272..d155d6799d 100644 --- a/dts/Bindings/thermal/qoriq-thermal.yaml +++ b/dts/Bindings/thermal/qoriq-thermal.yaml @@ -33,7 +33,8 @@ properties: description: | The values to be programmed into TTRnCR, as specified by the SoC reference manual. The first cell is TTR0CR, the second is TTR1CR, etc. - maxItems: 4 + minItems: 2 + maxItems: 7 fsl,tmu-calibration: $ref: /schemas/types.yaml#/definitions/uint32-matrix diff --git a/dts/Bindings/thermal/rcar-gen3-thermal.yaml b/dts/Bindings/thermal/rcar-gen3-thermal.yaml index ecf276fd15..6a81cb6e11 100644 --- a/dts/Bindings/thermal/rcar-gen3-thermal.yaml +++ b/dts/Bindings/thermal/rcar-gen3-thermal.yaml @@ -29,6 +29,7 @@ properties: - renesas,r8a779a0-thermal # R-Car V3U - renesas,r8a779f0-thermal # R-Car S4-8 - renesas,r8a779g0-thermal # R-Car V4H + - renesas,r8a779h0-thermal # R-Car V4M reg: true @@ -90,6 +91,7 @@ else: enum: - renesas,r8a779f0-thermal - renesas,r8a779g0-thermal + - renesas,r8a779h0-thermal then: required: - interrupts diff --git a/dts/Bindings/thermal/thermal-zones.yaml b/dts/Bindings/thermal/thermal-zones.yaml index dbd52620d2..68398e7e86 100644 --- a/dts/Bindings/thermal/thermal-zones.yaml +++ b/dts/Bindings/thermal/thermal-zones.yaml @@ -228,8 +228,6 @@ patternProperties: additionalProperties: false required: - - polling-delay - - polling-delay-passive - thermal-sensors - trips diff --git a/dts/Bindings/timer/arm,arch_timer_mmio.yaml b/dts/Bindings/timer/arm,arch_timer_mmio.yaml index 7a4a6ab859..ab8f289931 100644 --- a/dts/Bindings/timer/arm,arch_timer_mmio.yaml +++ b/dts/Bindings/timer/arm,arch_timer_mmio.yaml @@ -60,7 +60,7 @@ properties: be implemented in an always-on power domain." patternProperties: - '^frame@[0-9a-z]*$': + '^frame@[0-9a-f]+$': type: object additionalProperties: false description: A timer node has up to 8 frame sub-nodes, each with the following properties. diff --git a/dts/Bindings/timer/cdns,ttc.yaml b/dts/Bindings/timer/cdns,ttc.yaml index dbba780c9b..da342464d3 100644 --- a/dts/Bindings/timer/cdns,ttc.yaml +++ b/dts/Bindings/timer/cdns,ttc.yaml @@ -32,12 +32,23 @@ properties: description: | Bit width of the timer, necessary if not 16. + "#pwm-cells": + const: 3 + required: - compatible - reg - - interrupts - clocks +allOf: + - if: + not: + required: + - "#pwm-cells" + then: + required: + - interrupts + additionalProperties: false examples: @@ -50,3 +61,12 @@ examples: clocks = <&cpu_clk 3>; timer-width = <32>; }; + + - | + pwm: pwm@f8002000 { + compatible = "cdns,ttc"; + reg = <0xf8002000 0x1000>; + clocks = <&cpu_clk 3>; + timer-width = <32>; + #pwm-cells = <3>; + }; diff --git a/dts/Bindings/timer/mediatek,mtk-timer.txt b/dts/Bindings/timer/mediatek,mtk-timer.txt deleted file mode 100644 index b3e797e8aa..0000000000 --- a/dts/Bindings/timer/mediatek,mtk-timer.txt +++ /dev/null @@ -1,48 +0,0 @@ -MediaTek Timers ---------------- - -MediaTek SoCs have different timers on different platforms, -- CPUX (ARM/ARM64 System Timer) -- GPT (General Purpose Timer) -- SYST (System Timer) - -The proper timer will be selected automatically by driver. - -Required properties: -- compatible should contain: - For those SoCs that use GPT - * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) - * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) - * "mediatek,mt6582-timer" for MT6582 compatible timers (GPT) - * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) - * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT) - * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT) - * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT) - * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT) - * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT) - * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT) - - For those SoCs that use SYST - * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST) - * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST) - * "mediatek,mt8188-timer" for MT8188 compatible timers (SYST) - * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST) - * "mediatek,mt8195-timer" for MT8195 compatible timers (SYST) - * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) - * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST) - - For those SoCs that use CPUX - * "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX) - * "mediatek,mt8365-systimer" for MT8365 compatible timers (CPUX) - -- reg: Should contain location and length for timer register. -- clocks: Should contain system clock. - -Examples: - - timer@10008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; - clocks = <&system_clk>; - }; diff --git a/dts/Bindings/timer/mediatek,timer.yaml b/dts/Bindings/timer/mediatek,timer.yaml new file mode 100644 index 0000000000..f68fc7050c --- /dev/null +++ b/dts/Bindings/timer/mediatek,timer.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/mediatek,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC timers + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +description: + MediaTek SoCs have different timers on different platforms, + CPUX (ARM/ARM64 System Timer), GPT (General Purpose Timer) + and SYST (System Timer). + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt6577-timer + - mediatek,mt6765-timer + - mediatek,mt6795-systimer + # GPT Timers + - items: + - enum: + - mediatek,mt2701-timer + - mediatek,mt6580-timer + - mediatek,mt6582-timer + - mediatek,mt6589-timer + - mediatek,mt7623-timer + - mediatek,mt8127-timer + - mediatek,mt8135-timer + - mediatek,mt8173-timer + - mediatek,mt8516-timer + - const: mediatek,mt6577-timer + # SYST Timers + - items: + - enum: + - mediatek,mt7629-timer + - mediatek,mt8183-timer + - mediatek,mt8186-timer + - mediatek,mt8188-timer + - mediatek,mt8192-timer + - mediatek,mt8195-timer + - mediatek,mt8365-systimer + - const: mediatek,mt6765-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: Timer clock + - description: RTC or bus clock + + clock-names: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + timer@10008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; + clocks = <&system_clk>; + }; diff --git a/dts/Bindings/timer/mrvl,mmp-timer.yaml b/dts/Bindings/timer/mrvl,mmp-timer.yaml index 1ee4aab695..fe6bc41737 100644 --- a/dts/Bindings/timer/mrvl,mmp-timer.yaml +++ b/dts/Bindings/timer/mrvl,mmp-timer.yaml @@ -9,7 +9,7 @@ title: Marvell MMP Timer maintainers: - Daniel Lezcano <daniel.lezcano@linaro.org> - Thomas Gleixner <tglx@linutronix.de> - - Rob Herring <robh+dt@kernel.org> + - Rob Herring <robh@kernel.org> properties: $nodename: diff --git a/dts/Bindings/timer/nxp,sysctr-timer.yaml b/dts/Bindings/timer/nxp,sysctr-timer.yaml index 2b9653dafa..891cca0095 100644 --- a/dts/Bindings/timer/nxp,sysctr-timer.yaml +++ b/dts/Bindings/timer/nxp,sysctr-timer.yaml @@ -18,7 +18,9 @@ description: | properties: compatible: - const: nxp,sysctr-timer + enum: + - nxp,imx95-sysctr-timer + - nxp,sysctr-timer reg: maxItems: 1 diff --git a/dts/Bindings/timer/ralink,cevt-systick.yaml b/dts/Bindings/timer/ralink,cevt-systick.yaml new file mode 100644 index 0000000000..59d97feddf --- /dev/null +++ b/dts/Bindings/timer/ralink,cevt-systick.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/ralink,cevt-systick.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: System tick counter present in Ralink family SoCs + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +properties: + compatible: + const: ralink,cevt-systick + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + systick@d00 { + compatible = "ralink,cevt-systick"; + reg = <0xd00 0x10>; + + interrupt-parent = <&cpuintc>; + interrupts = <7>; + }; +... diff --git a/dts/Bindings/timer/renesas,ostm.yaml b/dts/Bindings/timer/renesas,ostm.yaml index 7207929e5c..8b06a68176 100644 --- a/dts/Bindings/timer/renesas,ostm.yaml +++ b/dts/Bindings/timer/renesas,ostm.yaml @@ -23,7 +23,7 @@ properties: - enum: - renesas,r7s72100-ostm # RZ/A1H - renesas,r7s9210-ostm # RZ/A2M - - renesas,r9a07g043-ostm # RZ/G2UL + - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five - renesas,r9a07g044-ostm # RZ/G2{L,LC} - renesas,r9a07g054-ostm # RZ/V2L - const: renesas,ostm # Generic diff --git a/dts/Bindings/timer/renesas,tmu.yaml b/dts/Bindings/timer/renesas,tmu.yaml index a67e427a9e..84bbe15028 100644 --- a/dts/Bindings/timer/renesas,tmu.yaml +++ b/dts/Bindings/timer/renesas,tmu.yaml @@ -46,7 +46,19 @@ properties: interrupts: minItems: 2 - maxItems: 3 + items: + - description: Underflow interrupt, channel 0 + - description: Underflow interrupt, channel 1 + - description: Underflow interrupt, channel 2 + - description: Input capture interrupt, channel 2 + + interrupt-names: + minItems: 2 + items: + - const: tuni0 + - const: tuni1 + - const: tuni2 + - const: ticpi2 clocks: maxItems: 1 @@ -100,7 +112,9 @@ examples: reg = <0xffd80000 0x30>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; diff --git a/dts/Bindings/timer/samsung,exynos4210-mct.yaml b/dts/Bindings/timer/samsung,exynos4210-mct.yaml index 829bd2227f..774b7992a0 100644 --- a/dts/Bindings/timer/samsung,exynos4210-mct.yaml +++ b/dts/Bindings/timer/samsung,exynos4210-mct.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - axis,artpec8-mct + - google,gs101-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -127,6 +128,7 @@ allOf: contains: enum: - axis,artpec8-mct + - google,gs101-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct diff --git a/dts/Bindings/tpm/tcg,tpm_tis-spi.yaml b/dts/Bindings/tpm/tcg,tpm_tis-spi.yaml index c3413b47ac..6cb2de7cb5 100644 --- a/dts/Bindings/tpm/tcg,tpm_tis-spi.yaml +++ b/dts/Bindings/tpm/tcg,tpm_tis-spi.yaml @@ -20,6 +20,7 @@ properties: compatible: items: - enum: + - atmel,attpm20p - infineon,slb9670 - st,st33htpm-spi - st,st33zp24-spi diff --git a/dts/Bindings/trivial-devices.yaml b/dts/Bindings/trivial-devices.yaml index 79dcd92c4a..e07be7bf83 100644 --- a/dts/Bindings/trivial-devices.yaml +++ b/dts/Bindings/trivial-devices.yaml @@ -28,6 +28,7 @@ properties: compatible: items: + # Entries are sorted alphanumerically by the compatible - enum: # Acbel fsg032 power supply - acbel,fsg032 @@ -47,14 +48,16 @@ properties: - adi,lt7182s # AMS iAQ-Core VOC Sensor - ams,iaq-core + # Temperature monitoring of Astera Labs PT5161L PCIe retimer + - asteralabs,pt5161l # i2c serial eeprom (24cxx) - at,24c08 + # i2c h/w elliptic curve crypto module + - atmel,atecc508a # ATSHA204 - i2c h/w symmetric crypto module - atmel,atsha204 # ATSHA204A - i2c h/w symmetric crypto module - atmel,atsha204a - # i2c h/w elliptic curve crypto module - - atmel,atecc508a # BPA-RS600: Power Supply - blutek,bpa-rs600 # Bosch Sensortec pressure, temperature, humididty and VOC sensor @@ -115,20 +118,6 @@ properties: - fsl,mpl3115 # MPR121: Proximity Capacitive Touch Sensor Controller - fsl,mpr121 - # Monolithic Power Systems Inc. multi-phase controller mp2856 - - mps,mp2856 - # Monolithic Power Systems Inc. multi-phase controller mp2857 - - mps,mp2857 - # Monolithic Power Systems Inc. multi-phase controller mp2888 - - mps,mp2888 - # Monolithic Power Systems Inc. multi-phase controller mp2971 - - mps,mp2971 - # Monolithic Power Systems Inc. multi-phase controller mp2973 - - mps,mp2973 - # Monolithic Power Systems Inc. multi-phase controller mp2975 - - mps,mp2975 - # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990 - - mps,mp5990 # Honeywell Humidicon HIH-6130 humidity/temperature sensor - honeywell,hi6130 # IBM Common Form Factor Power Supply Versions (all versions) @@ -137,16 +126,10 @@ properties: - ibm,cffps1 # IBM Common Form Factor Power Supply Versions 2 - ibm,cffps2 + # Infineon barometric pressure and temperature sensor + - infineon,dps310 # Infineon IR36021 digital POL buck controller - infineon,ir36021 - # Infineon IR38060 Voltage Regulator - - infineon,ir38060 - # Infineon IR38064 Voltage Regulator - - infineon,ir38064 - # Infineon IR38164 Voltage Regulator - - infineon,ir38164 - # Infineon IR38263 Voltage Regulator - - infineon,ir38263 # Infineon IRPS5401 Voltage Regulator (PMIC) - infineon,irps5401 # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor @@ -195,6 +178,8 @@ properties: - maxim,max1237 # Temperature Sensor, I2C interface - maxim,max1619 + # 3-Channel Remote Temperature Sensor + - maxim,max31730 # 10-bit 10 kOhm linear programmable voltage divider - maxim,max5481 # 10-bit 50 kOhm linear programmable voltage divider @@ -207,8 +192,6 @@ properties: - maxim,max6621 # 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface - maxim,max6625 - # 3-Channel Remote Temperature Sensor - - maxim,max31730 # mCube 3-axis 8-bit digital accelerometer - mcube,mc3230 # Measurement Specialities I2C temperature and humidity sensor @@ -239,8 +222,6 @@ properties: - memsic,mxc6655 # Menlo on-board CPLD trivial SPI device - menlo,m53cpld - # Micron SPI NOR Authenta - - micron,spi-authenta # Microchip differential I2C ADC, 1 Channel, 18 bit - microchip,mcp3421 # Microchip differential I2C ADC, 2 Channel, 18 bit @@ -257,40 +238,58 @@ properties: - microchip,mcp3427 # Microchip differential I2C ADC, 4 Channel, 16 bit - microchip,mcp3428 - # Microchip 7-bit Single I2C Digital POT (5k) - - microchip,mcp4017-502 # Microchip 7-bit Single I2C Digital POT (10k) - microchip,mcp4017-103 - # Microchip 7-bit Single I2C Digital POT (50k) - - microchip,mcp4017-503 # Microchip 7-bit Single I2C Digital POT (100k) - microchip,mcp4017-104 # Microchip 7-bit Single I2C Digital POT (5k) - - microchip,mcp4018-502 + - microchip,mcp4017-502 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4017-503 # Microchip 7-bit Single I2C Digital POT (10k) - microchip,mcp4018-103 - # Microchip 7-bit Single I2C Digital POT (50k) - - microchip,mcp4018-503 # Microchip 7-bit Single I2C Digital POT (100k) - microchip,mcp4018-104 # Microchip 7-bit Single I2C Digital POT (5k) - - microchip,mcp4019-502 + - microchip,mcp4018-502 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4018-503 # Microchip 7-bit Single I2C Digital POT (10k) - microchip,mcp4019-103 - # Microchip 7-bit Single I2C Digital POT (50k) - - microchip,mcp4019-503 # Microchip 7-bit Single I2C Digital POT (100k) - microchip,mcp4019-104 + # Microchip 7-bit Single I2C Digital POT (5k) + - microchip,mcp4019-502 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4019-503 # PWM Fan Speed Controller With Fan Fault Detection - microchip,tc654 # PWM Fan Speed Controller With Fan Fault Detection - microchip,tc655 + # Micron SPI NOR Authenta + - micron,spi-authenta # MiraMEMS DA226 2-axis 14-bit digital accelerometer - miramems,da226 # MiraMEMS DA280 3-axis 14-bit digital accelerometer - miramems,da280 # MiraMEMS DA311 3-axis 12-bit digital accelerometer - miramems,da311 + # Monolithic Power Systems Inc. multi-phase controller mp2856 + - mps,mp2856 + # Monolithic Power Systems Inc. multi-phase controller mp2857 + - mps,mp2857 + # Monolithic Power Systems Inc. multi-phase controller mp2888 + - mps,mp2888 + # Monolithic Power Systems Inc. multi-phase controller mp2971 + - mps,mp2971 + # Monolithic Power Systems Inc. multi-phase controller mp2973 + - mps,mp2973 + # Monolithic Power Systems Inc. multi-phase controller mp2975 + - mps,mp2975 + # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990 + - mps,mp5990 + # Monolithic Power Systems Inc. synchronous step-down converter mpq8785 + - mps,mpq8785 # Temperature sensor with integrated fan control - national,lm63 # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor @@ -321,12 +320,12 @@ properties: - samsung,exynos-sataphy-i2c # Semtech sx1301 baseband processor - semtech,sx1301 - # Sensirion low power multi-pixel gas sensor with I2C interface - - sensirion,sgpc3 # Sensirion multi-pixel gas sensor with I2C interface - sensirion,sgp30 # Sensirion gas sensor with I2C interface - sensirion,sgp40 + # Sensirion low power multi-pixel gas sensor with I2C interface + - sensirion,sgpc3 # Sensirion temperature & humidity sensor with I2C interface - sensirion,sht4x # Sensortek 3 axis accelerometer @@ -372,8 +371,6 @@ properties: - ti,lm74 # Temperature sensor with integrated fan control - ti,lm96000 - # I2C Touch-Screen Controller - - ti,tsc2003 # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface - ti,tmp103 # Thermometer with SPI interface @@ -395,10 +392,12 @@ properties: - ti,tps544b25 - ti,tps544c20 - ti,tps544c25 - # Winbond/Nuvoton H/W Monitor - - winbond,w83793 + # I2C Touch-Screen Controller + - ti,tsc2003 # Vicor Corporation Digital Supervisor - vicor,pli1209bc + # Winbond/Nuvoton H/W Monitor + - winbond,w83793 required: - compatible diff --git a/dts/Bindings/ufs/qcom,ufs.yaml b/dts/Bindings/ufs/qcom,ufs.yaml index 10c146424b..cd3680dc00 100644 --- a/dts/Bindings/ufs/qcom,ufs.yaml +++ b/dts/Bindings/ufs/qcom,ufs.yaml @@ -27,10 +27,13 @@ properties: - qcom,msm8996-ufshc - qcom,msm8998-ufshc - qcom,sa8775p-ufshc + - qcom,sc7180-ufshc - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6115-ufshc + - qcom,sm6125-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - qcom,sm8250-ufshc @@ -42,11 +45,11 @@ properties: - const: jedec,ufs-2.0 clocks: - minItems: 8 + minItems: 7 maxItems: 11 clock-names: - minItems: 8 + minItems: 7 maxItems: 11 dma-coherent: true @@ -117,9 +120,35 @@ allOf: compatible: contains: enum: + - qcom,sc7180-ufshc + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + reg: + maxItems: 1 + reg-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: - qcom,msm8998-ufshc - qcom,sa8775p-ufshc - qcom,sc7280-ufshc + - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc @@ -215,6 +244,7 @@ allOf: contains: enum: - qcom,sm6115-ufshc + - qcom,sm6125-ufshc then: properties: clocks: @@ -248,7 +278,7 @@ allOf: reg: maxItems: 1 clocks: - minItems: 8 + minItems: 7 maxItems: 8 else: properties: @@ -256,7 +286,7 @@ allOf: minItems: 1 maxItems: 2 clocks: - minItems: 8 + minItems: 7 maxItems: 11 unevaluatedProperties: false diff --git a/dts/Bindings/usb/analogix,anx7411.yaml b/dts/Bindings/usb/analogix,anx7411.yaml index e4d893369d..3f5857aee3 100644 --- a/dts/Bindings/usb/analogix,anx7411.yaml +++ b/dts/Bindings/usb/analogix,anx7411.yaml @@ -23,24 +23,11 @@ properties: connector: type: object $ref: ../connector/usb-connector.yaml - unevaluatedProperties: false - - description: - Properties for usb c connector. properties: compatible: const: usb-c-connector - power-role: true - - data-role: true - - try-power-role: true - - required: - - compatible - required: - compatible - reg diff --git a/dts/Bindings/usb/ci-hdrc-usb2.yaml b/dts/Bindings/usb/ci-hdrc-usb2.yaml index b7e664f739..3b56e0edb1 100644 --- a/dts/Bindings/usb/ci-hdrc-usb2.yaml +++ b/dts/Bindings/usb/ci-hdrc-usb2.yaml @@ -313,7 +313,7 @@ properties: usb-phy: description: phandle for the PHY device. Use "phys" instead. - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 deprecated: true fsl,usbphy: diff --git a/dts/Bindings/usb/cypress,hx3.yaml b/dts/Bindings/usb/cypress,hx3.yaml index 47add0d85f..28096619a8 100644 --- a/dts/Bindings/usb/cypress,hx3.yaml +++ b/dts/Bindings/usb/cypress,hx3.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/usb/cypress,hx3.yaml# diff --git a/dts/Bindings/usb/fcs,fsa4480.yaml b/dts/Bindings/usb/fcs,fsa4480.yaml index f9410eb76a..8b25b9a01c 100644 --- a/dts/Bindings/usb/fcs,fsa4480.yaml +++ b/dts/Bindings/usb/fcs,fsa4480.yaml @@ -27,13 +27,8 @@ properties: vcc-supply: description: power supply (2.7V-5.5V) - mode-switch: - description: Flag the port as possible handle of altmode switching - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + mode-switch: true + orientation-switch: true port: $ref: /schemas/graph.yaml#/$defs/port-base @@ -79,6 +74,9 @@ required: - reg - port +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/dts/Bindings/usb/generic-ehci.yaml b/dts/Bindings/usb/generic-ehci.yaml index 87986c45be..2ed178f16a 100644 --- a/dts/Bindings/usb/generic-ehci.yaml +++ b/dts/Bindings/usb/generic-ehci.yaml @@ -77,6 +77,7 @@ properties: - const: usb-ehci - enum: - generic-ehci + - marvell,ac5-ehci - marvell,armada-3700-ehci - marvell,orion-ehci - nuvoton,npcm750-ehci diff --git a/dts/Bindings/usb/gpio-sbu-mux.yaml b/dts/Bindings/usb/gpio-sbu-mux.yaml index d3b2b666ec..88e1607cf0 100644 --- a/dts/Bindings/usb/gpio-sbu-mux.yaml +++ b/dts/Bindings/usb/gpio-sbu-mux.yaml @@ -33,13 +33,8 @@ properties: vcc-supply: description: power supply - mode-switch: - description: Flag the port as possible handle of altmode switching - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + mode-switch: true + orientation-switch: true port: $ref: /schemas/graph.yaml#/properties/port @@ -54,6 +49,9 @@ required: - orientation-switch - port +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/dts/Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml b/dts/Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml new file mode 100644 index 0000000000..f301169439 --- /dev/null +++ b/dts/Bindings/usb/hisilicon,hi3798mv200-dwc3.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/hisilicon,hi3798mv200-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Hi3798MV200 DWC3 USB SoC controller + +maintainers: + - Yang Xiwen <forbidden405@foxmail.com> + +properties: + compatible: + const: hisilicon,hi3798mv200-dwc3 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + + clocks: + items: + - description: Controller bus clock + - description: Controller suspend clock + - description: Controller reference clock + - description: Controller gm clock + - description: Controller gs clock + - description: Controller utmi clock + - description: Controller pipe clock + + clock-names: + items: + - const: bus + - const: suspend + - const: ref + - const: gm + - const: gs + - const: utmi + - const: pipe + + resets: + maxItems: 1 + + reset-names: + const: soft + +patternProperties: + '^usb@[0-9a-f]+$': + $ref: snps,dwc3.yaml# + +required: + - compatible + - ranges + - '#address-cells' + - '#size-cells' + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + usb { + compatible = "hisilicon,hi3798mv200-dwc3"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&clk_bus>, + <&clk_suspend>, + <&clk_ref>, + <&clk_gm>, + <&clk_gs>, + <&clk_utmi>, + <&clk_pipe>; + clock-names = "bus", "suspend", "ref", "gm", "gs", "utmi", "pipe"; + resets = <&crg 0xb0 12>; + reset-names = "soft"; + + usb@98a0000 { + compatible = "snps,dwc3"; + reg = <0x98a0000 0x10000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_bus>, + <&clk_suspend>, + <&clk_ref>; + clock-names = "bus_early", "suspend", "ref"; + phys = <&usb2_phy1_port2>, <&combphy0 0>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; + dr_mode = "host"; + }; + }; diff --git a/dts/Bindings/usb/ite,it5205.yaml b/dts/Bindings/usb/ite,it5205.yaml new file mode 100644 index 0000000000..36ec4251b5 --- /dev/null +++ b/dts/Bindings/usb/ite,it5205.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ite,it5205.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ITE IT5202 Type-C USB Alternate Mode Passive MUX + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Tianping Fang <tianping.fang@mediatek.com> + +properties: + compatible: + const: ite,it5205 + + reg: + maxItems: 1 + + vcc-supply: + description: Power supply for VCC pin (3.3V) + + mode-switch: + description: Flag the port as possible handle of altmode switching + type: boolean + + orientation-switch: + description: Flag the port as possible handler of orientation switching + type: boolean + + ite,ovp-enable: + description: Enable Over Voltage Protection functionality + type: boolean + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node to link the IT5205 to a TypeC controller for the purpose of + handling altmode muxing and orientation switching. + +required: + - compatible + - reg + - orientation-switch + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + typec-mux@48 { + compatible = "ite,it5205"; + reg = <0x48>; + + mode-switch; + orientation-switch; + + vcc-supply = <&mt6359_vibr_ldo_reg>; + + port { + it5205_usbss_sbu: endpoint { + remote-endpoint = <&typec_controller>; + }; + }; + }; + }; +... diff --git a/dts/Bindings/usb/mediatek,mtu3.yaml b/dts/Bindings/usb/mediatek,mtu3.yaml index a59d91243a..d4e187c78a 100644 --- a/dts/Bindings/usb/mediatek,mtu3.yaml +++ b/dts/Bindings/usb/mediatek,mtu3.yaml @@ -185,7 +185,10 @@ properties: 2 - used by mt2712 etc, revision 2 with following IPM rule; 101 - used by mt8183, specific 1.01; 102 - used by mt8192, specific 1.02; - enum: [1, 2, 101, 102] + 103 - used by mt8195, IP0, specific 1.03; + 105 - used by mt8195, IP2, specific 1.05; + 106 - used by mt8195, IP3, specific 1.06; + enum: [1, 2, 101, 102, 103, 105, 106] mediatek,u3p-dis-msk: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/dts/Bindings/usb/microchip,usb5744.yaml b/dts/Bindings/usb/microchip,usb5744.yaml index 445183d9d6..e2a72deae7 100644 --- a/dts/Bindings/usb/microchip,usb5744.yaml +++ b/dts/Bindings/usb/microchip,usb5744.yaml @@ -72,8 +72,6 @@ allOf: i2c-bus: false else: $ref: /schemas/usb/usb-device.yaml - required: - - peer-hub additionalProperties: false diff --git a/dts/Bindings/usb/nxp,ptn36502.yaml b/dts/Bindings/usb/nxp,ptn36502.yaml index eee548ac1a..d805dde807 100644 --- a/dts/Bindings/usb/nxp,ptn36502.yaml +++ b/dts/Bindings/usb/nxp,ptn36502.yaml @@ -20,13 +20,8 @@ properties: vdd18-supply: description: Power supply for VDD18 pin - retimer-switch: - description: Flag the port as possible handle of SuperSpeed signals retiming - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + orientation-switch: true + retimer-switch: true ports: $ref: /schemas/graph.yaml#/properties/ports @@ -49,6 +44,9 @@ required: - compatible - reg +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/dts/Bindings/usb/nxp,ptn5110.yaml b/dts/Bindings/usb/nxp,ptn5110.yaml index eaedb4cc6b..65a8632b4d 100644 --- a/dts/Bindings/usb/nxp,ptn5110.yaml +++ b/dts/Bindings/usb/nxp,ptn5110.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: nxp,ptn5110 + items: + - const: nxp,ptn5110 + - const: tcpci reg: maxItems: 1 @@ -41,7 +43,7 @@ examples: #size-cells = <0>; tcpci@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; reg = <0x50>; interrupt-parent = <&gpio3>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; diff --git a/dts/Bindings/usb/onnn,nb7vpq904m.yaml b/dts/Bindings/usb/onnn,nb7vpq904m.yaml index c0201da002..589914d22b 100644 --- a/dts/Bindings/usb/onnn,nb7vpq904m.yaml +++ b/dts/Bindings/usb/onnn,nb7vpq904m.yaml @@ -21,14 +21,8 @@ properties: description: power supply (1.8V) enable-gpios: true - - retimer-switch: - description: Flag the port as possible handle of SuperSpeed signals retiming - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + orientation-switch: true + retimer-switch: true ports: $ref: /schemas/graph.yaml#/properties/ports @@ -95,6 +89,9 @@ required: - compatible - reg +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/dts/Bindings/usb/qcom,dwc3.yaml b/dts/Bindings/usb/qcom,dwc3.yaml index 63d150b216..38a3404ec7 100644 --- a/dts/Bindings/usb/qcom,dwc3.yaml +++ b/dts/Bindings/usb/qcom,dwc3.yaml @@ -102,7 +102,7 @@ properties: description: | Different types of interrupts are used based on HS PHY used on target: - pwr_event: Used for wakeup based on other power events. - - hs_phY_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is + - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is hs_phy_irq which is not triggered by default and its functionality is mutually exclusive to that of {dp/dm}_hs_phy_irq and qusb2_phy_irq. diff --git a/dts/Bindings/usb/qcom,pmic-typec.yaml b/dts/Bindings/usb/qcom,pmic-typec.yaml index 55df3129a0..d9694570c4 100644 --- a/dts/Bindings/usb/qcom,pmic-typec.yaml +++ b/dts/Bindings/usb/qcom,pmic-typec.yaml @@ -14,8 +14,19 @@ description: properties: compatible: - enum: - - qcom,pm8150b-typec + oneOf: + - enum: + - qcom,pmi632-typec + - qcom,pm8150b-typec + - items: + - enum: + - qcom,pm6150-typec + - const: qcom,pm8150b-typec + - items: + - enum: + - qcom,pm4125-typec + - const: qcom,pmi632-typec + connector: type: object @@ -24,9 +35,11 @@ properties: reg: description: Type-C port and pdphy SPMI register base offsets + minItems: 1 maxItems: 2 interrupts: + minItems: 8 items: - description: Type-C CC attach notification, VBUS error, tCCDebounce done - description: Type-C VCONN powered @@ -46,6 +59,7 @@ properties: - description: Power Domain Fast Role Swap event interrupt-names: + minItems: 8 items: - const: or-rid-detect-change - const: vpd-detect @@ -81,7 +95,33 @@ required: - interrupts - interrupt-names - vdd-vbus-supply - - vdd-pdphy-supply + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pmi632-typec + then: + properties: + reg: + maxItems: 1 + interrupts: + maxItems: 8 + interrupt-names: + maxItems: 8 + vdd-pdphy-supply: false + else: + properties: + reg: + maxItems: 2 + interrupts: + minItems: 16 + interrupt-names: + maxItems: 16 + required: + - vdd-pdphy-supply additionalProperties: false diff --git a/dts/Bindings/usb/qcom,wcd939x-usbss.yaml b/dts/Bindings/usb/qcom,wcd939x-usbss.yaml index 7ddfd3313a..96346723f3 100644 --- a/dts/Bindings/usb/qcom,wcd939x-usbss.yaml +++ b/dts/Bindings/usb/qcom,wcd939x-usbss.yaml @@ -35,13 +35,8 @@ properties: vdd-supply: description: USBSS VDD power supply - mode-switch: - description: Flag the port as possible handle of altmode switching - type: boolean - - orientation-switch: - description: Flag the port as possible handler of orientation switching - type: boolean + mode-switch: true + orientation-switch: true ports: $ref: /schemas/graph.yaml#/properties/ports @@ -63,6 +58,9 @@ required: - reg - ports +allOf: + - $ref: usb-switch.yaml# + additionalProperties: false examples: diff --git a/dts/Bindings/usb/realtek,rts5411.yaml b/dts/Bindings/usb/realtek,rts5411.yaml index f0784d2e86..0874fc21f6 100644 --- a/dts/Bindings/usb/realtek,rts5411.yaml +++ b/dts/Bindings/usb/realtek,rts5411.yaml @@ -21,6 +21,12 @@ properties: reg: true + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + vdd-supply: description: phandle to the regulator that provides power to the hub. @@ -30,6 +36,36 @@ properties: description: phandle to the peer hub on the controller. + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + 1st downstream facing USB port + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + 2nd downstream facing USB port + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: + 3rd downstream facing USB port + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: + 4th downstream facing USB port + +patternProperties: + '^.*@[1-4]$': + description: The hard wired USB devices + type: object + $ref: /schemas/usb/usb-device.yaml + required: - peer-hub - compatible @@ -50,6 +86,13 @@ examples: reg = <1>; vdd-supply = <&pp3300_hub>; peer-hub = <&hub_3_0>; + #address-cells = <1>; + #size-cells = <0>; + /* USB 2.0 device on port 2 */ + device@2 { + compatible = "usb123,4567"; + reg = <2>; + }; }; /* 3.0 hub on port 2 */ @@ -58,5 +101,17 @@ examples: reg = <2>; vdd-supply = <&pp3300_hub>; peer-hub = <&hub_2_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* Type-A connector on port 4 */ + port@4 { + reg = <4>; + endpoint { + remote-endpoint = <&usb_a0_ss>; + }; + }; + }; }; }; diff --git a/dts/Bindings/usb/ti,am62-usb.yaml b/dts/Bindings/usb/ti,am62-usb.yaml index fec5651f56..f6e6d084d1 100644 --- a/dts/Bindings/usb/ti,am62-usb.yaml +++ b/dts/Bindings/usb/ti,am62-usb.yaml @@ -14,7 +14,10 @@ properties: const: ti,am62-usb reg: - maxItems: 1 + minItems: 1 + items: + - description: USB CFG register space + - description: USB PHY2 register space ranges: true @@ -82,7 +85,8 @@ examples: usbss1: usb@f910000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; clocks = <&k3_clks 162 3>; clock-names = "ref"; ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; diff --git a/dts/Bindings/usb/ti,usb8020b.yaml b/dts/Bindings/usb/ti,usb8020b.yaml new file mode 100644 index 0000000000..8ef117793e --- /dev/null +++ b/dts/Bindings/usb/ti,usb8020b.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,usb8020b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI USB8020B USB 3.0 hub controller + +maintainers: + - Macpaul Lin <macpaul.lin@mediatek.com> + +allOf: + - $ref: usb-device.yaml# + +properties: + compatible: + enum: + - usb451,8025 + - usb451,8027 + + reg: true + + reset-gpios: + items: + - description: GPIO specifier for GRST# pin. + + vdd-supply: + description: + VDD power supply to the hub + + peer-hub: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the peer hub on the controller. + +required: + - compatible + - reg + - peer-hub + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + usb { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb451,8027"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&usb_hub_fixed_3v3>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb451,8025"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&usb_hub_fixed_3v3>; + }; + }; diff --git a/dts/Bindings/usb/usb-nop-xceiv.yaml b/dts/Bindings/usb/usb-nop-xceiv.yaml index 6734f4d3aa..9b3ea23654 100644 --- a/dts/Bindings/usb/usb-nop-xceiv.yaml +++ b/dts/Bindings/usb/usb-nop-xceiv.yaml @@ -37,10 +37,11 @@ properties: description: Should specify the GPIO detecting a VBus insertion maxItems: 1 - vbus-regulator: - description: Should specify the regulator supplying current drawn from - the VBus line. - $ref: /schemas/types.yaml#/definitions/phandle + vbus-supply: + description: regulator supplying VBUS. It will be enabled and disabled + dynamically in OTG mode. If the regulator is controlled by a + GPIO line, this should be modeled as a regulator-fixed and + referenced by this supply. wakeup-source: description: @@ -65,7 +66,7 @@ examples: vcc-supply = <&hsusb1_vcc_regulator>; reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; vbus-detect-gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - vbus-regulator = <&vbus_regulator>; + vbus-supply = <&vbus_regulator>; #phy-cells = <0>; }; diff --git a/dts/Bindings/usb/usb-switch.yaml b/dts/Bindings/usb/usb-switch.yaml new file mode 100644 index 0000000000..da76118e73 --- /dev/null +++ b/dts/Bindings/usb/usb-switch.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/usb-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: USB Orientation and Mode Switches Common Properties + +maintainers: + - Greg Kroah-Hartman <gregkh@linuxfoundation.org> + +description: + Common properties for devices handling USB mode and orientation switching. + +properties: + mode-switch: + description: Possible handler of altmode switching + type: boolean + + orientation-switch: + description: Possible handler of orientation switching + type: boolean + + retimer-switch: + description: Possible handler of SuperSpeed signals retiming + type: boolean + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node to link the device to a TypeC controller for the purpose of + handling altmode muxing and orientation switching. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Super Speed (SS) Output endpoint to the Type-C connector + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + description: + Super Speed (SS) Input endpoint from the Super-Speed PHY + unevaluatedProperties: false + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + uniqueItems: true + items: + maximum: 8 + +oneOf: + - required: + - port + - required: + - ports + +additionalProperties: true diff --git a/dts/Bindings/usb/usb.yaml b/dts/Bindings/usb/usb.yaml index 326b14f05d..1761b7aa92 100644 --- a/dts/Bindings/usb/usb.yaml +++ b/dts/Bindings/usb/usb.yaml @@ -25,6 +25,8 @@ properties: usb-phy: $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 description: List of all the USB PHYs on this HCD to be accepted by the legacy USB Physical Layer subsystem. diff --git a/dts/Bindings/vendor-prefixes.yaml b/dts/Bindings/vendor-prefixes.yaml index 1a0dc04f1d..b97d298b3e 100644 --- a/dts/Bindings/vendor-prefixes.yaml +++ b/dts/Bindings/vendor-prefixes.yaml @@ -39,6 +39,8 @@ patternProperties: description: ShenZhen Asia Better Technology Ltd. "^acbel,.*": description: Acbel Polytech Inc. + "^acelink,.*": + description: Acelink Technology Co., Ltd. "^acer,.*": description: Acer Inc. "^acme,.*": @@ -61,6 +63,8 @@ patternProperties: description: Analog Devices, Inc. "^adieng,.*": description: ADI Engineering, Inc. + "^admatec,.*": + description: admatec GmbH "^advantech,.*": description: Advantech Corporation "^aeroflexgaisler,.*": @@ -107,6 +111,8 @@ patternProperties: description: Amlogic, Inc. "^ampere,.*": description: Ampere Computing LLC + "^amphenol,.*": + description: Amphenol Advanced Sensors "^ampire,.*": description: Ampire Co., Ltd. "^ams,.*": @@ -159,6 +165,8 @@ patternProperties: description: ASPEED Technology Inc. "^asrock,.*": description: ASRock Inc. + "^asteralabs,.*": + description: Astera Labs, Inc. "^asus,.*": description: AsusTek Computer Inc. "^atheros,.*": @@ -230,6 +238,8 @@ patternProperties: description: ByteDance Ltd. "^calamp,.*": description: CalAmp Corp. + "^calao,.*": + description: CALAO Systems SAS "^calaosystems,.*": description: CALAO Systems SAS "^calxeda,.*": @@ -478,6 +488,9 @@ patternProperties: description: EZchip Semiconductor "^facebook,.*": description: Facebook + "^fairchild,.*": + description: Fairchild Semiconductor (deprecated, use 'onnn') + deprecated: true "^fairphone,.*": description: Fairphone B.V. "^faraday,.*": @@ -500,6 +513,8 @@ patternProperties: description: FocalTech Systems Co.,Ltd "^forlinx,.*": description: Baoding Forlinx Embedded Technology Co., Ltd. + "^freebox,.*": + description: Freebox SAS "^freecom,.*": description: Freecom Gmbh "^frida,.*": @@ -542,6 +557,8 @@ patternProperties: description: Giantec Semiconductor, Inc. "^giantplus,.*": description: Giantplus Technology Co., Ltd. + "^glinet,.*": + description: GL Intelligence, Inc. "^globalscale,.*": description: Globalscale Technologies, Inc. "^globaltop,.*": @@ -601,6 +618,8 @@ patternProperties: description: Honestar Technologies Co., Ltd. "^honeywell,.*": description: Honeywell + "^hoperf,.*": + description: Shenzhen Hope Microelectronics Co., Ltd. "^hoperun,.*": description: Jiangsu HopeRun Software Co., Ltd. "^hp,.*": @@ -631,12 +650,16 @@ patternProperties: description: Hyundai Technology "^i2se,.*": description: I2SE GmbH + "^IBM,.*": + description: International Business Machines (IBM) "^ibm,.*": description: International Business Machines (IBM) "^icplus,.*": description: IC Plus Corp. "^idt,.*": description: Integrated Device Technologies, Inc. + "^iei,.*": + description: IEI Integration Corp. "^ifi,.*": description: Ingenieurburo Fur Ic-Technologie (I/F/I) "^ilitek,.*": @@ -719,6 +742,8 @@ patternProperties: description: JetHome (IP Sokolov P.A.) "^jianda,.*": description: Jiandangjing Technology Co., Ltd. + "^jide,.*": + description: Jide Tech "^joz,.*": description: JOZ BV "^kam,.*": @@ -821,6 +846,8 @@ patternProperties: description: LSI Corp. (LSI Logic) "^lunzn,.*": description: Shenzhen Lunzn Technology Co., Ltd. + "^luxul,.*": + description: Lagrand | AV "^lwn,.*": description: Liebherr-Werk Nenzing GmbH "^lxa,.*": @@ -899,6 +926,9 @@ patternProperties: description: Miniand Tech "^minix,.*": description: MINIX Technology Ltd. + "^mips,.*": + description: MIPS Technology (deprecated, use 'mti' or 'img') + deprecated: true "^miramems,.*": description: MiraMEMS Sensing Technology Co., Ltd. "^mitsubishi,.*": @@ -911,6 +941,8 @@ patternProperties: description: Miyoo "^mntre,.*": description: MNT Research GmbH + "^mobileye,.*": + description: Mobileye Vision Technologies Ltd. "^modtronix,.*": description: Modtronix Engineering "^moortec,.*": @@ -993,6 +1025,9 @@ patternProperties: description: Novatek "^novtech,.*": description: NovTech, Inc. + "^numonyx,.*": + description: Numonyx (deprecated, use micron) + deprecated: true "^nutsboard,.*": description: NutsBoard "^nuvoton,.*": @@ -1297,6 +1332,8 @@ patternProperties: description: Skyworks Solutions, Inc. "^smartlabs,.*": description: SmartLabs LLC + "^smartrg,.*": + description: SmartRG, Inc. "^smi,.*": description: Silicon Motion Technology Corporation "^smsc,.*": @@ -1484,6 +1521,8 @@ patternProperties: description: Ufi Space Co., Ltd. "^ugoos,.*": description: Ugoos Industrial Co., Ltd. + "^uni-t,.*": + description: Uni-Trend Technology (China) Co., Ltd. "^uniwest,.*": description: United Western Technologies Corp (UniWest) "^upisemi,.*": @@ -1534,10 +1573,16 @@ patternProperties: description: VoCore Studio "^voipac,.*": description: Voipac Technologies s.r.o. + "^voltafield,.*": + description: Voltafield Technology Corp. "^vot,.*": description: Vision Optical Technology Co., Ltd. + "^vscom,.*": + description: VS Visions Systems GmbH "^vxt,.*": description: VXT Ltd + "^wacom,.*": + description: Wacom "^wanchanglong,.*": description: Wanchanglong Electronics Technology（SHENZHEN）Co.，Ltd. "^wand,.*": diff --git a/dts/Bindings/w1/w1-uart.yaml b/dts/Bindings/w1/w1-uart.yaml new file mode 100644 index 0000000000..bd7c62d780 --- /dev/null +++ b/dts/Bindings/w1/w1-uart.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/w1/w1-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UART 1-Wire Bus + +maintainers: + - Christoph Winklhofer <cj.winklhofer@gmail.com> + +description: | + UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus + to create the 1-Wire timing patterns. + + The UART peripheral must support full-duplex and operate in open-drain + mode. The timing patterns are generated by a specific combination of + baud-rate and transmitted byte, which corresponds to a 1-Wire read bit, + write bit or reset pulse. + + The default baud-rate for reset and presence detection is 9600 and for + a 1-Wire read or write operation 115200. In case the actual baud-rate + is different from the requested one, the transmitted byte is adapted + to generate the 1-Wire timing patterns. + + https://www.analog.com/en/technical-articles/using-a-uart-to-implement-a-1wire-bus-master.html + +properties: + compatible: + const: w1-uart + + reset-bps: + default: 9600 + description: + The baud rate for the 1-Wire reset and presence detect. + + write-0-bps: + default: 115200 + description: + The baud rate for the 1-Wire write-0 cycle. + + write-1-bps: + default: 115200 + description: + The baud rate for the 1-Wire write-1 and read cycle. + +required: + - compatible + +additionalProperties: + type: object + +examples: + - | + serial { + onewire { + compatible = "w1-uart"; + }; + }; diff --git a/dts/Bindings/watchdog/arm,sp805.yaml b/dts/Bindings/watchdog/arm,sp805.yaml index 7aea255b30..bd7c09ed19 100644 --- a/dts/Bindings/watchdog/arm,sp805.yaml +++ b/dts/Bindings/watchdog/arm,sp805.yaml @@ -50,6 +50,10 @@ properties: - const: wdog_clk - const: apb_pclk + resets: + maxItems: 1 + description: WDOGRESn input reset signal for sp805 module. + required: - compatible - reg @@ -67,4 +71,5 @@ examples: interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; clocks = <&wdt_clk>, <&apb_pclk>; clock-names = "wdog_clk", "apb_pclk"; + resets = <&wdt_rst>; }; diff --git a/dts/Bindings/watchdog/atmel,sama5d4-wdt.yaml b/dts/Bindings/watchdog/atmel,sama5d4-wdt.yaml index 816f85ee2c..cdf87db361 100644 --- a/dts/Bindings/watchdog/atmel,sama5d4-wdt.yaml +++ b/dts/Bindings/watchdog/atmel,sama5d4-wdt.yaml @@ -14,10 +14,14 @@ allOf: properties: compatible: - enum: - - atmel,sama5d4-wdt - - microchip,sam9x60-wdt - - microchip,sama7g5-wdt + oneOf: + - enum: + - atmel,sama5d4-wdt + - microchip,sam9x60-wdt + - microchip,sama7g5-wdt + - items: + - const: microchip,sam9x7-wdt + - const: microchip,sam9x60-wdt reg: maxItems: 1 diff --git a/dts/Bindings/watchdog/brcm,bcm2835-pm-wdog.txt b/dts/Bindings/watchdog/brcm,bcm2835-pm-wdog.txt deleted file mode 100644 index f801d71de1..0000000000 --- a/dts/Bindings/watchdog/brcm,bcm2835-pm-wdog.txt +++ /dev/null @@ -1,18 +0,0 @@ -BCM2835 Watchdog timer - -Required properties: - -- compatible : should be "brcm,bcm2835-pm-wdt" -- reg : Specifies base physical address and size of the registers. - -Optional properties: - -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - -watchdog { - compatible = "brcm,bcm2835-pm-wdt"; - reg = <0x7e100000 0x28>; - timeout-sec = <10>; -}; diff --git a/dts/Bindings/watchdog/qcom-wdt.yaml b/dts/Bindings/watchdog/qcom-wdt.yaml index a4f35c598c..47587971fb 100644 --- a/dts/Bindings/watchdog/qcom-wdt.yaml +++ b/dts/Bindings/watchdog/qcom-wdt.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer maintainers: - - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> + - Rajendra Nayak <quic_rjendra@quicinc.com> properties: $nodename: diff --git a/dts/Bindings/watchdog/renesas,wdt.yaml b/dts/Bindings/watchdog/renesas,wdt.yaml index 951a7d5413..ffb17add49 100644 --- a/dts/Bindings/watchdog/renesas,wdt.yaml +++ b/dts/Bindings/watchdog/renesas,wdt.yaml @@ -71,6 +71,7 @@ properties: - renesas,r8a779a0-wdt # R-Car V3U - renesas,r8a779f0-wdt # R-Car S4-8 - renesas,r8a779g0-wdt # R-Car V4H + - renesas,r8a779h0-wdt # R-Car V4M - const: renesas,rcar-gen4-wdt # R-Car Gen4 reg: diff --git a/dts/Bindings/watchdog/sprd,sp9860-wdt.yaml b/dts/Bindings/watchdog/sprd,sp9860-wdt.yaml new file mode 100644 index 0000000000..730d9a3a3c --- /dev/null +++ b/dts/Bindings/watchdog/sprd,sp9860-wdt.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/sprd,sp9860-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SP9860 watchdog timer + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: sprd,sp9860-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: enable + - const: rtc_enable + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - timeout-sec + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/sprd,sc9860-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + watchdog@40310000 { + compatible = "sprd,sp9860-wdt"; + reg = <0 0x40310000 0 0x1000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&aon_gate CLK_APCPU_WDG_EB>, <&aon_gate CLK_AP_WDG_RTC_EB>; + clock-names = "enable", "rtc_enable"; + timeout-sec = <12>; + }; + }; +... diff --git a/dts/Bindings/watchdog/sprd-wdt.txt b/dts/Bindings/watchdog/sprd-wdt.txt deleted file mode 100644 index aeaf3e0caf..0000000000 --- a/dts/Bindings/watchdog/sprd-wdt.txt +++ /dev/null @@ -1,19 +0,0 @@ -Spreadtrum SoCs Watchdog timer - -Required properties: -- compatible : Should be "sprd,sp9860-wdt". -- reg : Specifies base physical address and size of the registers. -- interrupts : Exactly one interrupt specifier. -- timeout-sec : Contain the default watchdog timeout in seconds. -- clock-names : Contain the input clock names. -- clocks : Phandles to input clocks. - -Example: - watchdog: watchdog@40310000 { - compatible = "sprd,sp9860-wdt"; - reg = <0 0x40310000 0 0x1000>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - timeout-sec = <12>; - clock-names = "enable", "rtc_enable"; - clocks = <&clk_aon_apb_gates1 8>, <&clk_aon_apb_rtc_gates 9>; - }; diff --git a/dts/Bindings/watchdog/starfive,jh7100-wdt.yaml b/dts/Bindings/watchdog/starfive,jh7100-wdt.yaml index 68f3f6fd08..e21f807b0b 100644 --- a/dts/Bindings/watchdog/starfive,jh7100-wdt.yaml +++ b/dts/Bindings/watchdog/starfive,jh7100-wdt.yaml @@ -19,14 +19,16 @@ description: isn't cleared, the watchdog will reset the system unless the watchdog reset is disabled. -allOf: - - $ref: watchdog.yaml# - properties: compatible: - enum: - - starfive,jh7100-wdt - - starfive,jh7110-wdt + oneOf: + - enum: + - starfive,jh7100-wdt + - starfive,jh7110-wdt + - items: + - enum: + - starfive,jh8100-wdt + - const: starfive,jh7110-wdt reg: maxItems: 1 @@ -45,9 +47,8 @@ properties: - const: core resets: - items: - - description: APB reset - - description: Core reset + minItems: 1 + maxItems: 2 required: - compatible @@ -56,6 +57,27 @@ required: - clock-names - resets +allOf: + - $ref: watchdog.yaml# + + - if: + properties: + compatible: + contains: + enum: + - starfive,jh8100-wdt + then: + properties: + resets: + items: + - description: Core reset + else: + properties: + resets: + items: + - description: APB reset + - description: Core reset + unevaluatedProperties: false examples: diff --git a/dts/Bindings/writing-schema.rst b/dts/Bindings/writing-schema.rst index 0a6cf19a14..7e71cdd1d6 100644 --- a/dts/Bindings/writing-schema.rst +++ b/dts/Bindings/writing-schema.rst @@ -31,7 +31,7 @@ $schema Indicates the meta-schema the schema file adheres to. title - A one-line description on the contents of the binding schema. + A one-line description of the hardware being described in the binding schema. maintainers A DT specific property. Contains a list of email address(es) @@ -39,7 +39,7 @@ maintainers description Optional. A multi-line text block containing any detailed - information about this binding. It should contain things such as what the block + information about this hardware. It should contain things such as what the block or device does, standards the device conforms to, and links to datasheets for more information. @@ -71,9 +71,31 @@ required A list of DT properties from the 'properties' section that must always be present. +additionalProperties / unevaluatedProperties + Keywords controlling how schema will validate properties not matched by this + schema's 'properties' or 'patternProperties'. Each schema is supposed to + have exactly one of these keywords in top-level part, so either + additionalProperties or unevaluatedProperties. Nested nodes, so properties + being objects, are supposed to have one as well. + + * additionalProperties: false + Most common case, where no additional schema is referenced or if this + binding allows subset of properties from other referenced schemas. + + * unevaluatedProperties: false + Used when this binding references other schema whose all properties + should be allowed. + + * additionalProperties: true + Rare case, used for schemas implementing common set of properties. Such + schemas are supposed to be referenced by other schemas, which then use + 'unevaluatedProperties: false'. Typically bus or common-part schemas. + examples - Optional. A list of one or more DTS hunks implementing the - binding. Note: YAML doesn't allow leading tabs, so spaces must be used instead. + Optional. A list of one or more DTS hunks implementing this binding only. + Example should not contain unrelated device nodes, e.g. consumer nodes in a + provider binding, other nodes referenced by phandle. + Note: YAML doesn't allow leading tabs, so spaces must be used instead. Unless noted otherwise, all properties are required. diff --git a/dts/include/dt-bindings/arm/qcom,ids.h b/dts/include/dt-bindings/arm/qcom,ids.h index 51e0f60594..19ac7b36f6 100644 --- a/dts/include/dt-bindings/arm/qcom,ids.h +++ b/dts/include/dt-bindings/arm/qcom,ids.h @@ -252,8 +252,11 @@ #define QCOM_ID_IPQ9510 521 #define QCOM_ID_QRB4210 523 #define QCOM_ID_QRB2210 524 +#define QCOM_ID_SM8475 530 +#define QCOM_ID_SM8475P 531 #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 +#define QCOM_ID_SM8475_2 540 #define QCOM_ID_QDU1000 545 #define QCOM_ID_SM8650 557 #define QCOM_ID_SM4450 568 @@ -265,6 +268,8 @@ #define QCOM_ID_IPQ5322 593 #define QCOM_ID_IPQ5312 594 #define QCOM_ID_IPQ5302 595 +#define QCOM_ID_QCS8550 603 +#define QCOM_ID_QCM8550 604 #define QCOM_ID_IPQ5300 624 /* diff --git a/dts/include/dt-bindings/clock/ast2600-clock.h b/dts/include/dt-bindings/clock/ast2600-clock.h index 712782177c..7ae96c7bd7 100644 --- a/dts/include/dt-bindings/clock/ast2600-clock.h +++ b/dts/include/dt-bindings/clock/ast2600-clock.h @@ -86,6 +86,7 @@ #define ASPEED_CLK_MAC3RCLK 69 #define ASPEED_CLK_MAC4RCLK 70 #define ASPEED_CLK_I3C 71 +#define ASPEED_CLK_FSI 72 /* Only list resets here that are not part of a clock gate + reset pair */ #define ASPEED_RESET_ADC 55 diff --git a/dts/include/dt-bindings/clock/exynos850.h b/dts/include/dt-bindings/clock/exynos850.h index 3090e09c9a..7666241520 100644 --- a/dts/include/dt-bindings/clock/exynos850.h +++ b/dts/include/dt-bindings/clock/exynos850.h @@ -88,6 +88,18 @@ #define CLK_MOUT_G3D_SWITCH 76 #define CLK_GOUT_G3D_SWITCH 77 #define CLK_DOUT_G3D_SWITCH 78 +#define CLK_MOUT_CPUCL0_DBG 79 +#define CLK_MOUT_CPUCL0_SWITCH 80 +#define CLK_GOUT_CPUCL0_DBG 81 +#define CLK_GOUT_CPUCL0_SWITCH 82 +#define CLK_DOUT_CPUCL0_DBG 83 +#define CLK_DOUT_CPUCL0_SWITCH 84 +#define CLK_MOUT_CPUCL1_DBG 85 +#define CLK_MOUT_CPUCL1_SWITCH 86 +#define CLK_GOUT_CPUCL1_DBG 87 +#define CLK_GOUT_CPUCL1_SWITCH 88 +#define CLK_DOUT_CPUCL1_DBG 89 +#define CLK_DOUT_CPUCL1_SWITCH 90 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +207,48 @@ #define CLK_GOUT_CMGP_USI1_PCLK 14 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 +/* CMU_CPUCL0 */ +#define CLK_FOUT_CPUCL0_PLL 1 +#define CLK_MOUT_PLL_CPUCL0 2 +#define CLK_MOUT_CPUCL0_SWITCH_USER 3 +#define CLK_MOUT_CPUCL0_DBG_USER 4 +#define CLK_MOUT_CPUCL0_PLL 5 +#define CLK_DOUT_CPUCL0_CPU 6 +#define CLK_DOUT_CPUCL0_CMUREF 7 +#define CLK_DOUT_CPUCL0_PCLK 8 +#define CLK_DOUT_CLUSTER0_ACLK 9 +#define CLK_DOUT_CLUSTER0_ATCLK 10 +#define CLK_DOUT_CLUSTER0_PCLKDBG 11 +#define CLK_DOUT_CLUSTER0_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER0_ATCLK 13 +#define CLK_GOUT_CLUSTER0_PCLK 14 +#define CLK_GOUT_CLUSTER0_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER0_SCLK 16 +#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17 +#define CLK_GOUT_CLUSTER0_CPU 18 +#define CLK_CLUSTER0_SCLK 19 + +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_SWITCH_USER 3 +#define CLK_MOUT_CPUCL1_DBG_USER 4 +#define CLK_MOUT_CPUCL1_PLL 5 +#define CLK_DOUT_CPUCL1_CPU 6 +#define CLK_DOUT_CPUCL1_CMUREF 7 +#define CLK_DOUT_CPUCL1_PCLK 8 +#define CLK_DOUT_CLUSTER1_ACLK 9 +#define CLK_DOUT_CLUSTER1_ATCLK 10 +#define CLK_DOUT_CLUSTER1_PCLKDBG 11 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER1_ATCLK 13 +#define CLK_GOUT_CLUSTER1_PCLK 14 +#define CLK_GOUT_CLUSTER1_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER1_SCLK 16 +#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17 +#define CLK_GOUT_CLUSTER1_CPU 18 +#define CLK_CLUSTER1_SCLK 19 + /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 #define CLK_MOUT_G3D_PLL 2 @@ -320,6 +374,8 @@ #define CLK_GOUT_SSS_PCLK 12 #define CLK_GOUT_GPIO_CORE_PCLK 13 #define CLK_GOUT_SYSREG_CORE_PCLK 14 +#define CLK_GOUT_PDMA_CORE_ACLK 15 +#define CLK_GOUT_SPDMA_CORE_ACLK 16 /* CMU_DPU */ #define CLK_MOUT_DPU_USER 1 diff --git a/dts/include/dt-bindings/clock/google,gs101.h b/dts/include/dt-bindings/clock/google,gs101.h index 21adec2238..3dac357778 100644 --- a/dts/include/dt-bindings/clock/google,gs101.h +++ b/dts/include/dt-bindings/clock/google,gs101.h @@ -389,4 +389,133 @@ #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_I3C_USER 2 +#define CLK_MOUT_PERIC0_USI0_UART_USER 3 +#define CLK_MOUT_PERIC0_USI14_USI_USER 4 +#define CLK_MOUT_PERIC0_USI1_USI_USER 5 +#define CLK_MOUT_PERIC0_USI2_USI_USER 6 +#define CLK_MOUT_PERIC0_USI3_USI_USER 7 +#define CLK_MOUT_PERIC0_USI4_USI_USER 8 +#define CLK_MOUT_PERIC0_USI5_USI_USER 9 +#define CLK_MOUT_PERIC0_USI6_USI_USER 10 +#define CLK_MOUT_PERIC0_USI7_USI_USER 11 +#define CLK_MOUT_PERIC0_USI8_USI_USER 12 +#define CLK_DOUT_PERIC0_I3C 13 +#define CLK_DOUT_PERIC0_USI0_UART 14 +#define CLK_DOUT_PERIC0_USI14_USI 15 +#define CLK_DOUT_PERIC0_USI1_USI 16 +#define CLK_DOUT_PERIC0_USI2_USI 17 +#define CLK_DOUT_PERIC0_USI3_USI 18 +#define CLK_DOUT_PERIC0_USI4_USI 19 +#define CLK_DOUT_PERIC0_USI5_USI 20 +#define CLK_DOUT_PERIC0_USI6_USI 21 +#define CLK_DOUT_PERIC0_USI7_USI 22 +#define CLK_DOUT_PERIC0_USI8_USI 23 +#define CLK_GOUT_PERIC0_IP 24 +#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25 +#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26 +#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27 +#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28 +#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29 +#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66 +#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67 +#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78 +#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_I3C_USER 2 +#define CLK_MOUT_PERIC1_USI0_USI_USER 3 +#define CLK_MOUT_PERIC1_USI10_USI_USER 4 +#define CLK_MOUT_PERIC1_USI11_USI_USER 5 +#define CLK_MOUT_PERIC1_USI12_USI_USER 6 +#define CLK_MOUT_PERIC1_USI13_USI_USER 7 +#define CLK_MOUT_PERIC1_USI9_USI_USER 8 +#define CLK_DOUT_PERIC1_I3C 9 +#define CLK_DOUT_PERIC1_USI0_USI 10 +#define CLK_DOUT_PERIC1_USI10_USI 11 +#define CLK_DOUT_PERIC1_USI11_USI 12 +#define CLK_DOUT_PERIC1_USI12_USI 13 +#define CLK_DOUT_PERIC1_USI13_USI 14 +#define CLK_DOUT_PERIC1_USI9_USI 15 +#define CLK_GOUT_PERIC1_IP 16 +#define CLK_GOUT_PERIC1_PCLK 17 +#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18 +#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19 +#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20 +#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21 +#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22 +#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38 +#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45 +#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ diff --git a/dts/include/dt-bindings/clock/microchip,mpfs-clock.h b/dts/include/dt-bindings/clock/microchip,mpfs-clock.h index 79775a5134..b52f19a2b4 100644 --- a/dts/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/dts/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -44,6 +44,11 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +#define CLK_MSSPLL0 34 +#define CLK_MSSPLL1 35 +#define CLK_MSSPLL2 36 +#define CLK_MSSPLL3 37 +/* 38 is reserved for MSS PLL internals */ /* Clock Conditioning Circuitry Clock IDs */ diff --git a/dts/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/dts/include/dt-bindings/clock/mobileye,eyeq5-clk.h new file mode 100644 index 0000000000..26d8930335 --- /dev/null +++ b/dts/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H +#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H + +#define EQ5C_PLL_CPU 0 +#define EQ5C_PLL_VMP 1 +#define EQ5C_PLL_PMA 2 +#define EQ5C_PLL_VDI 3 +#define EQ5C_PLL_DDR0 4 +#define EQ5C_PLL_PCI 5 +#define EQ5C_PLL_PER 6 +#define EQ5C_PLL_PMAC 7 +#define EQ5C_PLL_MPC 8 +#define EQ5C_PLL_DDR1 9 + +#define EQ5C_DIV_OSPI 10 + +#endif diff --git a/dts/include/dt-bindings/clock/qcom,gcc-msm8953.h b/dts/include/dt-bindings/clock/qcom,gcc-msm8953.h index 783162da61..13b4a62877 100644 --- a/dts/include/dt-bindings/clock/qcom,gcc-msm8953.h +++ b/dts/include/dt-bindings/clock/qcom,gcc-msm8953.h @@ -218,6 +218,10 @@ #define GCC_USB3PHY_PHY_BCR 3 #define GCC_USB3_PHY_BCR 4 #define GCC_USB_30_BCR 5 +#define GCC_MDSS_BCR 6 +#define GCC_CRYPTO_BCR 7 +#define GCC_SDCC1_BCR 8 +#define GCC_SDCC2_BCR 9 /* GDSCs */ #define CPP_GDSC 0 diff --git a/dts/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/dts/include/dt-bindings/clock/qcom,gcc-sc8180x.h index e893415ae1..90c6e021a0 100644 --- a/dts/include/dt-bindings/clock/qcom,gcc-sc8180x.h +++ b/dts/include/dt-bindings/clock/qcom,gcc-sc8180x.h @@ -246,6 +246,8 @@ #define GCC_PCIE_3_CLKREF_CLK 236 #define GCC_USB3_PRIM_CLKREF_CLK 237 #define GCC_USB3_SEC_CLKREF_CLK 238 +#define GCC_UFS_MEM_CLKREF_EN 239 +#define GCC_UFS_CARD_CLKREF_EN 240 #define GCC_EMAC_BCR 0 #define GCC_GPU_BCR 1 diff --git a/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h b/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h index dfefd5e8bf..921a33f24d 100644 --- a/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/dts/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -239,6 +239,9 @@ #define GCC_USB30_PRIM_BCR 26 #define GCC_USB30_SEC_BCR 27 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +#define GCC_VIDEO_AXIC_CLK_BCR 29 +#define GCC_VIDEO_AXI0_CLK_BCR 30 +#define GCC_VIDEO_AXI1_CLK_BCR 31 /* GCC GDSCRs */ #define PCIE_0_GDSC 0 diff --git a/dts/include/dt-bindings/clock/qcom,x1e80100-camcc.h b/dts/include/dt-bindings/clock/qcom,x1e80100-camcc.h new file mode 100644 index 0000000000..d72fdfb06a --- /dev/null +++ b/dts/include/dt-bindings/clock/qcom,x1e80100-camcc.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_CAMNOC_AXI_NRT_CLK 4 +#define CAM_CC_CAMNOC_AXI_RT_CLK 5 +#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6 +#define CAM_CC_CAMNOC_DCD_XO_CLK 7 +#define CAM_CC_CAMNOC_XO_CLK 8 +#define CAM_CC_CCI_0_CLK 9 +#define CAM_CC_CCI_0_CLK_SRC 10 +#define CAM_CC_CCI_1_CLK 11 +#define CAM_CC_CCI_1_CLK_SRC 12 +#define CAM_CC_CORE_AHB_CLK 13 +#define CAM_CC_CPAS_AHB_CLK 14 +#define CAM_CC_CPAS_BPS_CLK 15 +#define CAM_CC_CPAS_FAST_AHB_CLK 16 +#define CAM_CC_CPAS_IFE_0_CLK 17 +#define CAM_CC_CPAS_IFE_1_CLK 18 +#define CAM_CC_CPAS_IFE_LITE_CLK 19 +#define CAM_CC_CPAS_IPE_NPS_CLK 20 +#define CAM_CC_CPAS_SFE_0_CLK 21 +#define CAM_CC_CPHY_RX_CLK_SRC 22 +#define CAM_CC_CSI0PHYTIMER_CLK 23 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 24 +#define CAM_CC_CSI1PHYTIMER_CLK 25 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 26 +#define CAM_CC_CSI2PHYTIMER_CLK 27 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 28 +#define CAM_CC_CSI3PHYTIMER_CLK 29 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 30 +#define CAM_CC_CSI4PHYTIMER_CLK 31 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 32 +#define CAM_CC_CSI5PHYTIMER_CLK 33 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 34 +#define CAM_CC_CSID_CLK 35 +#define CAM_CC_CSID_CLK_SRC 36 +#define CAM_CC_CSID_CSIPHY_RX_CLK 37 +#define CAM_CC_CSIPHY0_CLK 38 +#define CAM_CC_CSIPHY1_CLK 39 +#define CAM_CC_CSIPHY2_CLK 40 +#define CAM_CC_CSIPHY3_CLK 41 +#define CAM_CC_CSIPHY4_CLK 42 +#define CAM_CC_CSIPHY5_CLK 43 +#define CAM_CC_FAST_AHB_CLK_SRC 44 +#define CAM_CC_GDSC_CLK 45 +#define CAM_CC_ICP_AHB_CLK 46 +#define CAM_CC_ICP_CLK 47 +#define CAM_CC_ICP_CLK_SRC 48 +#define CAM_CC_IFE_0_CLK 49 +#define CAM_CC_IFE_0_CLK_SRC 50 +#define CAM_CC_IFE_0_DSP_CLK 51 +#define CAM_CC_IFE_0_FAST_AHB_CLK 52 +#define CAM_CC_IFE_1_CLK 53 +#define CAM_CC_IFE_1_CLK_SRC 54 +#define CAM_CC_IFE_1_DSP_CLK 55 +#define CAM_CC_IFE_1_FAST_AHB_CLK 56 +#define CAM_CC_IFE_LITE_AHB_CLK 57 +#define CAM_CC_IFE_LITE_CLK 58 +#define CAM_CC_IFE_LITE_CLK_SRC 59 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 60 +#define CAM_CC_IFE_LITE_CSID_CLK 61 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 62 +#define CAM_CC_IPE_NPS_AHB_CLK 63 +#define CAM_CC_IPE_NPS_CLK 64 +#define CAM_CC_IPE_NPS_CLK_SRC 65 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 66 +#define CAM_CC_IPE_PPS_CLK 67 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 68 +#define CAM_CC_JPEG_CLK 69 +#define CAM_CC_JPEG_CLK_SRC 70 +#define CAM_CC_MCLK0_CLK 71 +#define CAM_CC_MCLK0_CLK_SRC 72 +#define CAM_CC_MCLK1_CLK 73 +#define CAM_CC_MCLK1_CLK_SRC 74 +#define CAM_CC_MCLK2_CLK 75 +#define CAM_CC_MCLK2_CLK_SRC 76 +#define CAM_CC_MCLK3_CLK 77 +#define CAM_CC_MCLK3_CLK_SRC 78 +#define CAM_CC_MCLK4_CLK 79 +#define CAM_CC_MCLK4_CLK_SRC 80 +#define CAM_CC_MCLK5_CLK 81 +#define CAM_CC_MCLK5_CLK_SRC 82 +#define CAM_CC_MCLK6_CLK 83 +#define CAM_CC_MCLK6_CLK_SRC 84 +#define CAM_CC_MCLK7_CLK 85 +#define CAM_CC_MCLK7_CLK_SRC 86 +#define CAM_CC_PLL0 87 +#define CAM_CC_PLL0_OUT_EVEN 88 +#define CAM_CC_PLL0_OUT_ODD 89 +#define CAM_CC_PLL1 90 +#define CAM_CC_PLL1_OUT_EVEN 91 +#define CAM_CC_PLL2 92 +#define CAM_CC_PLL3 93 +#define CAM_CC_PLL3_OUT_EVEN 94 +#define CAM_CC_PLL4 95 +#define CAM_CC_PLL4_OUT_EVEN 96 +#define CAM_CC_PLL6 97 +#define CAM_CC_PLL6_OUT_EVEN 98 +#define CAM_CC_PLL8 99 +#define CAM_CC_PLL8_OUT_EVEN 100 +#define CAM_CC_SFE_0_CLK 101 +#define CAM_CC_SFE_0_CLK_SRC 102 +#define CAM_CC_SFE_0_FAST_AHB_CLK 103 +#define CAM_CC_SLEEP_CLK 104 +#define CAM_CC_SLEEP_CLK_SRC 105 +#define CAM_CC_SLOW_AHB_CLK_SRC 106 +#define CAM_CC_XO_CLK_SRC 107 + +/* CAM_CC power domains */ +#define CAM_CC_BPS_GDSC 0 +#define CAM_CC_IFE_0_GDSC 1 +#define CAM_CC_IFE_1_GDSC 2 +#define CAM_CC_IPE_0_GDSC 3 +#define CAM_CC_SFE_0_GDSC 4 +#define CAM_CC_TITAN_TOP_GDSC 5 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IPE_0_BCR 4 +#define CAM_CC_SFE_0_BCR 5 + +#endif diff --git a/dts/include/dt-bindings/clock/qcom,x1e80100-dispcc.h b/dts/include/dt-bindings/clock/qcom,x1e80100-dispcc.h new file mode 100644 index 0000000000..d4a83e4fd0 --- /dev/null +++ b/dts/include/dt-bindings/clock/qcom,x1e80100-dispcc.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H +#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H + +/* DISP_CC clocks */ +#define DISP_CC_MDSS_ACCU_CLK 0 +#define DISP_CC_MDSS_AHB1_CLK 1 +#define DISP_CC_MDSS_AHB_CLK 2 +#define DISP_CC_MDSS_AHB_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_CLK 4 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 +#define DISP_CC_MDSS_BYTE1_CLK 8 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 11 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 12 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 14 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 23 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 25 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 34 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 36 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43 +#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 45 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 47 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52 +#define DISP_CC_MDSS_ESC0_CLK 53 +#define DISP_CC_MDSS_ESC0_CLK_SRC 54 +#define DISP_CC_MDSS_ESC1_CLK 55 +#define DISP_CC_MDSS_ESC1_CLK_SRC 56 +#define DISP_CC_MDSS_MDP1_CLK 57 +#define DISP_CC_MDSS_MDP_CLK 58 +#define DISP_CC_MDSS_MDP_CLK_SRC 59 +#define DISP_CC_MDSS_MDP_LUT1_CLK 60 +#define DISP_CC_MDSS_MDP_LUT_CLK 61 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62 +#define DISP_CC_MDSS_PCLK0_CLK 63 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 64 +#define DISP_CC_MDSS_PCLK1_CLK 65 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 66 +#define DISP_CC_MDSS_RSCC_AHB_CLK 67 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 68 +#define DISP_CC_MDSS_VSYNC1_CLK 69 +#define DISP_CC_MDSS_VSYNC_CLK 70 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 71 +#define DISP_CC_PLL0 72 +#define DISP_CC_PLL1 73 +#define DISP_CC_SLEEP_CLK 74 +#define DISP_CC_SLEEP_CLK_SRC 75 +#define DISP_CC_XO_CLK 76 +#define DISP_CC_XO_CLK_SRC 77 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 +#define MDSS_INT2_GDSC 1 + +#endif diff --git a/dts/include/dt-bindings/clock/qcom,x1e80100-gpucc.h b/dts/include/dt-bindings/clock/qcom,x1e80100-gpucc.h new file mode 100644 index 0000000000..61a3a8f3ac --- /dev/null +++ b/dts/include/dt-bindings/clock/qcom,x1e80100-gpucc.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H +#define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DEMET_DIV_CLK_SRC 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_GMU_CLK 12 +#define GPU_CC_GX_VSENSE_CLK 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_HUB_AON_CLK 15 +#define GPU_CC_HUB_CLK_SRC 16 +#define GPU_CC_HUB_CX_INT_CLK 17 +#define GPU_CC_MEMNOC_GFX_CLK 18 +#define GPU_CC_MND1X_0_GFX3D_CLK 19 +#define GPU_CC_MND1X_1_GFX3D_CLK 20 +#define GPU_CC_PLL0 21 +#define GPU_CC_PLL1 22 +#define GPU_CC_SLEEP_CLK 23 +#define GPU_CC_XO_CLK_SRC 24 +#define GPU_CC_XO_DIV_CLK_SRC 25 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/dts/include/dt-bindings/clock/qcom,x1e80100-tcsr.h b/dts/include/dt-bindings/clock/qcom,x1e80100-tcsr.h new file mode 100644 index 0000000000..bae2c4654e --- /dev/null +++ b/dts/include/dt-bindings/clock/qcom,x1e80100-tcsr.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H +#define _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H + +/* TCSR CC clocks */ +#define TCSR_PCIE_2L_4_CLKREF_EN 0 +#define TCSR_PCIE_2L_5_CLKREF_EN 1 +#define TCSR_PCIE_8L_CLKREF_EN 2 +#define TCSR_USB3_MP0_CLKREF_EN 3 +#define TCSR_USB3_MP1_CLKREF_EN 4 +#define TCSR_USB2_1_CLKREF_EN 5 +#define TCSR_UFS_PHY_CLKREF_EN 6 +#define TCSR_USB4_1_CLKREF_EN 7 +#define TCSR_USB4_2_CLKREF_EN 8 +#define TCSR_USB2_2_CLKREF_EN 9 +#define TCSR_PCIE_4L_CLKREF_EN 10 +#define TCSR_EDP_CLKREF_EN 11 + +#endif diff --git a/dts/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/dts/include/dt-bindings/clock/r8a779g0-cpg-mssr.h index 754c54a6eb..7850cdc62e 100644 --- a/dts/include/dt-bindings/clock/r8a779g0-cpg-mssr.h +++ b/dts/include/dt-bindings/clock/r8a779g0-cpg-mssr.h @@ -86,5 +86,6 @@ #define R8A779G0_CLK_CPEX 74 #define R8A779G0_CLK_CBFUSA 75 #define R8A779G0_CLK_R 76 +#define R8A779G0_CLK_CP 77 #endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ diff --git a/dts/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/dts/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h new file mode 100644 index 0000000000..7ab6cfbaf9 --- /dev/null +++ b/dts/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779h0 CPG Core Clocks */ + +#define R8A779H0_CLK_ZX 0 +#define R8A779H0_CLK_ZD 1 +#define R8A779H0_CLK_ZS 2 +#define R8A779H0_CLK_ZT 3 +#define R8A779H0_CLK_ZTR 4 +#define R8A779H0_CLK_S0D2 5 +#define R8A779H0_CLK_S0D3 6 +#define R8A779H0_CLK_S0D4 7 +#define R8A779H0_CLK_S0D1_VIO 8 +#define R8A779H0_CLK_S0D2_VIO 9 +#define R8A779H0_CLK_S0D4_VIO 10 +#define R8A779H0_CLK_S0D8_VIO 11 +#define R8A779H0_CLK_VIOBUSD1 12 +#define R8A779H0_CLK_VIOBUSD2 13 +#define R8A779H0_CLK_S0D1_VC 14 +#define R8A779H0_CLK_S0D2_VC 15 +#define R8A779H0_CLK_S0D4_VC 16 +#define R8A779H0_CLK_VCBUSD1 17 +#define R8A779H0_CLK_VCBUSD2 18 +#define R8A779H0_CLK_S0D2_MM 19 +#define R8A779H0_CLK_S0D4_MM 20 +#define R8A779H0_CLK_S0D2_U3DG 21 +#define R8A779H0_CLK_S0D4_U3DG 22 +#define R8A779H0_CLK_S0D2_RT 23 +#define R8A779H0_CLK_S0D3_RT 24 +#define R8A779H0_CLK_S0D4_RT 25 +#define R8A779H0_CLK_S0D6_RT 26 +#define R8A779H0_CLK_S0D2_PER 27 +#define R8A779H0_CLK_S0D3_PER 28 +#define R8A779H0_CLK_S0D4_PER 29 +#define R8A779H0_CLK_S0D6_PER 30 +#define R8A779H0_CLK_S0D12_PER 31 +#define R8A779H0_CLK_S0D24_PER 32 +#define R8A779H0_CLK_S0D1_HSC 33 +#define R8A779H0_CLK_S0D2_HSC 34 +#define R8A779H0_CLK_S0D4_HSC 35 +#define R8A779H0_CLK_S0D8_HSC 36 +#define R8A779H0_CLK_SVD1_IR 37 +#define R8A779H0_CLK_SVD2_IR 38 +#define R8A779H0_CLK_IMPAD1 39 +#define R8A779H0_CLK_IMPAD4 40 +#define R8A779H0_CLK_IMPB 41 +#define R8A779H0_CLK_SVD1_VIP 42 +#define R8A779H0_CLK_SVD2_VIP 43 +#define R8A779H0_CLK_CL 44 +#define R8A779H0_CLK_CL16M 45 +#define R8A779H0_CLK_CL16M_MM 46 +#define R8A779H0_CLK_CL16M_RT 47 +#define R8A779H0_CLK_CL16M_PER 48 +#define R8A779H0_CLK_CL16M_HSC 49 +#define R8A779H0_CLK_ZC0 50 +#define R8A779H0_CLK_ZC1 51 +#define R8A779H0_CLK_ZC2 52 +#define R8A779H0_CLK_ZC3 53 +#define R8A779H0_CLK_ZB3 54 +#define R8A779H0_CLK_ZB3D2 55 +#define R8A779H0_CLK_ZB3D4 56 +#define R8A779H0_CLK_ZG 57 +#define R8A779H0_CLK_SD0H 58 +#define R8A779H0_CLK_SD0 59 +#define R8A779H0_CLK_RPC 60 +#define R8A779H0_CLK_RPCD2 61 +#define R8A779H0_CLK_MSO 62 +#define R8A779H0_CLK_CANFD 63 +#define R8A779H0_CLK_CSI 64 +#define R8A779H0_CLK_FRAY 65 +#define R8A779H0_CLK_IPC 66 +#define R8A779H0_CLK_SASYNCRT 67 +#define R8A779H0_CLK_SASYNCPERD1 68 +#define R8A779H0_CLK_SASYNCPERD2 69 +#define R8A779H0_CLK_SASYNCPERD4 70 +#define R8A779H0_CLK_DSIEXT 71 +#define R8A779H0_CLK_DSIREF 72 +#define R8A779H0_CLK_ADGH 73 +#define R8A779H0_CLK_OSC 74 +#define R8A779H0_CLK_ZR0 75 +#define R8A779H0_CLK_ZR1 76 +#define R8A779H0_CLK_ZR2 77 +#define R8A779H0_CLK_RGMII 78 +#define R8A779H0_CLK_CPEX 79 +#define R8A779H0_CLK_CP 80 +#define R8A779H0_CLK_CBFUSA 81 +#define R8A779H0_CLK_R 82 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */ diff --git a/dts/include/dt-bindings/clock/rockchip,rk3588-cru.h b/dts/include/dt-bindings/clock/rockchip,rk3588-cru.h index 5790b13912..0c7d3ca2d5 100644 --- a/dts/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/dts/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -733,8 +733,7 @@ #define ACLK_AV1_PRE 718 #define PCLK_AV1_PRE 719 #define HCLK_SDIO_PRE 720 - -#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) +#define PCLK_VO1GRF 721 /* scmi-clocks indices */ diff --git a/dts/include/dt-bindings/input/linux-event-codes.h b/dts/include/dt-bindings/input/linux-event-codes.h index 022a520e31..03edf2ccdf 100644 --- a/dts/include/dt-bindings/input/linux-event-codes.h +++ b/dts/include/dt-bindings/input/linux-event-codes.h @@ -602,6 +602,7 @@ #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_ROTATE_LOCK_TOGGLE 0x231 /* Display rotation lock */ +#define KEY_REFRESH_RATE_TOGGLE 0x232 /* Display refresh rate toggle */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ diff --git a/dts/include/dt-bindings/interconnect/qcom,msm8909.h b/dts/include/dt-bindings/interconnect/qcom,msm8909.h new file mode 100644 index 0000000000..76365d8aec --- /dev/null +++ b/dts/include/dt-bindings/interconnect/qcom,msm8909.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm MSM8909 interconnect IDs + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H + +/* BIMC fabric */ +#define MAS_APPS_PROC 0 +#define MAS_OXILI 1 +#define MAS_SNOC_BIMC_0 2 +#define MAS_SNOC_BIMC_1 3 +#define MAS_TCU_0 4 +#define MAS_TCU_1 5 +#define SLV_EBI 6 +#define SLV_BIMC_SNOC 7 + +/* PCNOC fabric */ +#define MAS_AUDIO 0 +#define MAS_SPDM 1 +#define MAS_DEHR 2 +#define MAS_QPIC 3 +#define MAS_BLSP_1 4 +#define MAS_USB_HS 5 +#define MAS_CRYPTO 6 +#define MAS_SDCC_1 7 +#define MAS_SDCC_2 8 +#define MAS_SNOC_PCNOC 9 +#define PCNOC_M_0 10 +#define PCNOC_M_1 11 +#define PCNOC_INT_0 12 +#define PCNOC_INT_1 13 +#define PCNOC_S_0 14 +#define PCNOC_S_1 15 +#define PCNOC_S_2 16 +#define PCNOC_S_3 17 +#define PCNOC_S_4 18 +#define PCNOC_S_5 19 +#define PCNOC_S_7 20 +#define SLV_TCSR 21 +#define SLV_SDCC_1 22 +#define SLV_BLSP_1 23 +#define SLV_CRYPTO_0_CFG 24 +#define SLV_MESSAGE_RAM 25 +#define SLV_PDM 26 +#define SLV_PRNG 27 +#define SLV_USB_HS 28 +#define SLV_QPIC 29 +#define SLV_SPDM 30 +#define SLV_SDCC_2 31 +#define SLV_AUDIO 32 +#define SLV_DEHR_CFG 33 +#define SLV_SNOC_CFG 34 +#define SLV_QDSS_CFG 35 +#define SLV_USB_PHY 36 +#define SLV_CAMERA_SS_CFG 37 +#define SLV_DISP_SS_CFG 38 +#define SLV_VENUS_CFG 39 +#define SLV_TLMM 40 +#define SLV_GPU_CFG 41 +#define SLV_IMEM_CFG 42 +#define SLV_BIMC_CFG 43 +#define SLV_PMIC_ARB 44 +#define SLV_TCU 45 +#define SLV_PCNOC_SNOC 46 + +/* SNOC fabric */ +#define MAS_QDSS_BAM 0 +#define MAS_BIMC_SNOC 1 +#define MAS_MDP 2 +#define MAS_PCNOC_SNOC 3 +#define MAS_VENUS 4 +#define MAS_VFE 5 +#define MAS_QDSS_ETR 6 +#define MM_INT_0 7 +#define MM_INT_1 8 +#define MM_INT_2 9 +#define MM_INT_BIMC 10 +#define QDSS_INT 11 +#define SNOC_INT_0 12 +#define SNOC_INT_1 13 +#define SNOC_INT_BIMC 14 +#define SLV_KPSS_AHB 15 +#define SLV_SNOC_BIMC_0 16 +#define SLV_SNOC_BIMC_1 17 +#define SLV_IMEM 18 +#define SLV_SNOC_PCNOC 19 +#define SLV_QDSS_STM 20 +#define SLV_CATS_0 21 +#define SLV_CATS_1 22 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H */ diff --git a/dts/include/dt-bindings/interconnect/qcom,sm7150-rpmh.h b/dts/include/dt-bindings/interconnect/qcom,sm7150-rpmh.h new file mode 100644 index 0000000000..1f610eb832 --- /dev/null +++ b/dts/include/dt-bindings/interconnect/qcom,sm7150-rpmh.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Qualcomm SM7150 interconnect IDs + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QUP_0 1 +#define MASTER_TSIF 2 +#define MASTER_EMMC 3 +#define MASTER_SDCC_2 4 +#define MASTER_SDCC_4 5 +#define MASTER_UFS_MEM 6 +#define A1NOC_SNOC_SLV 7 +#define SLAVE_SERVICE_A1NOC 8 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QUP_1 2 +#define MASTER_CNOC_A2NOC 3 +#define MASTER_CRYPTO_CORE_0 4 +#define MASTER_IPA 5 +#define MASTER_PCIE 6 +#define MASTER_QDSS_ETR 7 +#define MASTER_USB3 8 +#define A2NOC_SNOC_SLV 9 +#define SLAVE_ANOC_PCIE_GEM_NOC 10 +#define SLAVE_SERVICE_A2NOC 11 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_RT_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define MASTER_CAMNOC_NRT_UNCOMP 3 +#define SLAVE_CAMNOC_UNCOMP 4 + +#define MASTER_NPU 0 +#define SLAVE_CDSP_GEM_NOC 1 + +#define MASTER_SPDM 0 +#define SNOC_CNOC_MAS 1 +#define MASTER_QDSS_DAP 2 +#define SLAVE_A1NOC_CFG 3 +#define SLAVE_A2NOC_CFG 4 +#define SLAVE_AHB2PHY_NORTH 5 +#define SLAVE_AHB2PHY_SOUTH 6 +#define SLAVE_AHB2PHY_WEST 7 +#define SLAVE_AOP 8 +#define SLAVE_AOSS 9 +#define SLAVE_CAMERA_CFG 10 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 12 +#define SLAVE_CLK_CTL 13 +#define SLAVE_CDSP_CFG 14 +#define SLAVE_RBCPR_CX_CFG 15 +#define SLAVE_RBCPR_MX_CFG 16 +#define SLAVE_CRYPTO_0_CFG 17 +#define SLAVE_CNOC_DDRSS 18 +#define SLAVE_DISPLAY_CFG 19 +#define SLAVE_DISPLAY_THROTTLE_CFG 20 +#define SLAVE_EMMC_CFG 21 +#define SLAVE_GLM 22 +#define SLAVE_GRAPHICS_3D_CFG 23 +#define SLAVE_IMEM_CFG 24 +#define SLAVE_IPA_CFG 25 +#define SLAVE_CNOC_MNOC_CFG 26 +#define SLAVE_PCIE_CFG 27 +#define SLAVE_PDM 28 +#define SLAVE_PIMEM_CFG 29 +#define SLAVE_PRNG 30 +#define SLAVE_QDSS_CFG 31 +#define SLAVE_QUP_0 32 +#define SLAVE_QUP_1 33 +#define SLAVE_SDCC_2 34 +#define SLAVE_SDCC_4 35 +#define SLAVE_SNOC_CFG 36 +#define SLAVE_SPDM_WRAPPER 37 +#define SLAVE_TCSR 38 +#define SLAVE_TLMM_NORTH 39 +#define SLAVE_TLMM_SOUTH 40 +#define SLAVE_TLMM_WEST 41 +#define SLAVE_TSIF 42 +#define SLAVE_UFS_MEM_CFG 43 +#define SLAVE_USB3 44 +#define SLAVE_VENUS_CFG 45 +#define SLAVE_VENUS_CVP_THROTTLE_CFG 46 +#define SLAVE_VENUS_THROTTLE_CFG 47 +#define SLAVE_VSENSE_CTRL_CFG 48 +#define SLAVE_CNOC_A2NOC 49 +#define SLAVE_SERVICE_CNOC 50 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_GEM_NOC_CFG 1 +#define SLAVE_LLCC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_SYS_TCU 1 +#define MASTER_GEM_NOC_CFG 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_MNOC_HF_MEM_NOC 4 +#define MASTER_MNOC_SF_MEM_NOC 5 +#define MASTER_GEM_NOC_PCIE_SNOC 6 +#define MASTER_SNOC_GC_MEM_NOC 7 +#define MASTER_SNOC_SF_MEM_NOC 8 +#define MASTER_GRAPHICS_3D 9 +#define SLAVE_MSS_PROC_MS_MPU_CFG 10 +#define SLAVE_GEM_NOC_SNOC 11 +#define SLAVE_LLCC 12 +#define SLAVE_SERVICE_GEM_NOC 13 + + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_NRT 2 +#define MASTER_CAMNOC_RT 3 +#define MASTER_CAMNOC_SF 4 +#define MASTER_MDP_PORT0 5 +#define MASTER_MDP_PORT1 6 +#define MASTER_ROTATOR 7 +#define MASTER_VIDEO_P0 8 +#define MASTER_VIDEO_P1 9 +#define MASTER_VIDEO_PROC 10 +#define SLAVE_MNOC_SF_MEM_NOC 11 +#define SLAVE_MNOC_HF_MEM_NOC 12 +#define SLAVE_SERVICE_MNOC 13 + +#define MASTER_SNOC_CFG 0 +#define A1NOC_SNOC_MAS 1 +#define A2NOC_SNOC_MAS 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_APPSS 6 +#define SNOC_CNOC_SLV 7 +#define SLAVE_SNOC_GEM_NOC_GC 8 +#define SLAVE_SNOC_GEM_NOC_SF 9 +#define SLAVE_OCIMEM 10 +#define SLAVE_PIMEM 11 +#define SLAVE_SERVICE_SNOC 12 +#define SLAVE_QDSS_STM 13 +#define SLAVE_TCU 14 + +#endif diff --git a/dts/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h b/dts/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h index a38c347269..7d97108811 100644 --- a/dts/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h +++ b/dts/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h @@ -112,11 +112,6 @@ #define SLAVE_GEM_NOC_CNOC 12 #define SLAVE_LLCC 13 #define SLAVE_MEM_NOC_PCIE_SNOC 14 -#define MASTER_MNOC_HF_MEM_NOC_DISP 15 -#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16 -#define SLAVE_LLCC_DISP 17 -#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18 -#define SLAVE_LLCC_PCIE 19 #define MASTER_LPIAON_NOC 0 #define SLAVE_LPASS_GEM_NOC 1 @@ -129,10 +124,6 @@ #define MASTER_LLCC 0 #define SLAVE_EBI1 1 -#define MASTER_LLCC_DISP 2 -#define SLAVE_EBI1_DISP 3 -#define MASTER_LLCC_PCIE 4 -#define SLAVE_EBI1_PCIE 5 #define MASTER_AV1_ENC 0 #define MASTER_CAMNOC_HF 1 @@ -147,8 +138,6 @@ #define SLAVE_MNOC_HF_MEM_NOC 10 #define SLAVE_MNOC_SF_MEM_NOC 11 #define SLAVE_SERVICE_MNOC 12 -#define MASTER_MDP_DISP 13 -#define SLAVE_MNOC_HF_MEM_NOC_DISP 14 #define MASTER_CDSP_PROC 0 #define SLAVE_CDSP_MEM_NOC 1 @@ -156,18 +145,11 @@ #define MASTER_PCIE_NORTH 0 #define MASTER_PCIE_SOUTH 1 #define SLAVE_ANOC_PCIE_GEM_NOC 2 -#define MASTER_PCIE_NORTH_PCIE 3 -#define MASTER_PCIE_SOUTH_PCIE 4 -#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5 #define MASTER_PCIE_3 0 #define MASTER_PCIE_4 1 #define MASTER_PCIE_5 2 #define SLAVE_PCIE_NORTH 3 -#define MASTER_PCIE_3_PCIE 4 -#define MASTER_PCIE_4_PCIE 5 -#define MASTER_PCIE_5_PCIE 6 -#define SLAVE_PCIE_NORTH_PCIE 7 #define MASTER_PCIE_0 0 #define MASTER_PCIE_1 1 @@ -175,12 +157,6 @@ #define MASTER_PCIE_6A 3 #define MASTER_PCIE_6B 4 #define SLAVE_PCIE_SOUTH 5 -#define MASTER_PCIE_0_PCIE 6 -#define MASTER_PCIE_1_PCIE 7 -#define MASTER_PCIE_2_PCIE 8 -#define MASTER_PCIE_6A_PCIE 9 -#define MASTER_PCIE_6B_PCIE 10 -#define SLAVE_PCIE_SOUTH_PCIE 11 #define MASTER_A1NOC_SNOC 0 #define MASTER_A2NOC_SNOC 1 diff --git a/dts/include/dt-bindings/leds/common.h b/dts/include/dt-bindings/leds/common.h index 9a0d33d027..ecea167930 100644 --- a/dts/include/dt-bindings/leds/common.h +++ b/dts/include/dt-bindings/leds/common.h @@ -100,7 +100,11 @@ #define LED_FUNCTION_TX "tx" #define LED_FUNCTION_USB "usb" #define LED_FUNCTION_WAN "wan" +#define LED_FUNCTION_WAN_ONLINE "wan-online" #define LED_FUNCTION_WLAN "wlan" +#define LED_FUNCTION_WLAN_2GHZ "wlan-2ghz" +#define LED_FUNCTION_WLAN_5GHZ "wlan-5ghz" +#define LED_FUNCTION_WLAN_6GHZ "wlan-6ghz" #define LED_FUNCTION_WPS "wps" #endif /* __DT_BINDINGS_LEDS_H */ diff --git a/dts/include/dt-bindings/mfd/stm32f7-rcc.h b/dts/include/dt-bindings/mfd/stm32f7-rcc.h index 8d73a9c51e..a4e4f92713 100644 --- a/dts/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/dts/include/dt-bindings/mfd/stm32f7-rcc.h @@ -108,6 +108,7 @@ #define STM32F7_RCC_APB2_SAI1 22 #define STM32F7_RCC_APB2_SAI2 23 #define STM32F7_RCC_APB2_LTDC 26 +#define STM32F7_RCC_APB2_DSI 27 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) diff --git a/dts/include/dt-bindings/power/amlogic,c3-pwrc.h b/dts/include/dt-bindings/power/amlogic,c3-pwrc.h index 1d98a25b08..61759df4b2 100644 --- a/dts/include/dt-bindings/power/amlogic,c3-pwrc.h +++ b/dts/include/dt-bindings/power/amlogic,c3-pwrc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2023 Amlogic, Inc. * Author: hongyu chen1 <hongyu.chen1@amlogic.com> diff --git a/dts/include/dt-bindings/power/qcom-rpmpd.h b/dts/include/dt-bindings/power/qcom-rpmpd.h index 7f4e2983a4..608087fb9a 100644 --- a/dts/include/dt-bindings/power/qcom-rpmpd.h +++ b/dts/include/dt-bindings/power/qcom-rpmpd.h @@ -308,6 +308,13 @@ #define MSM8953_VDDMX 5 #define MSM8953_VDDMX_AO 6 +/* MSM8974 Power Domain Indexes */ +#define MSM8974_VDDCX 0 +#define MSM8974_VDDCX_AO 1 +#define MSM8974_VDDCX_VFC 2 +#define MSM8974_VDDGFX 3 +#define MSM8974_VDDGFX_VFC 4 + /* MSM8976 Power Domain Indexes */ #define MSM8976_VDDCX 0 #define MSM8976_VDDCX_AO 1 diff --git a/dts/include/dt-bindings/power/renesas,r8a779h0-sysc.h b/dts/include/dt-bindings/power/renesas,r8a779h0-sysc.h new file mode 100644 index 0000000000..f27976f523 --- /dev/null +++ b/dts/include/dt-bindings/power/renesas,r8a779h0-sysc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779H0_PD_A1E0D0C0 0 +#define R8A779H0_PD_A1E0D0C1 1 +#define R8A779H0_PD_A1E0D0C2 2 +#define R8A779H0_PD_A1E0D0C3 3 +#define R8A779H0_PD_A2E0D0 16 +#define R8A779H0_PD_A3CR0 21 +#define R8A779H0_PD_A3CR1 22 +#define R8A779H0_PD_A3CR2 23 +#define R8A779H0_PD_A33DGA 24 +#define R8A779H0_PD_A23DGB 25 +#define R8A779H0_PD_C4 31 +#define R8A779H0_PD_A1DSP0 33 +#define R8A779H0_PD_A2IMP01 34 +#define R8A779H0_PD_A2PSC 35 +#define R8A779H0_PD_A2CV0 36 +#define R8A779H0_PD_A2CV1 37 +#define R8A779H0_PD_A3IMR0 38 +#define R8A779H0_PD_A3IMR1 39 +#define R8A779H0_PD_A3VC 40 +#define R8A779H0_PD_A2CN0 42 +#define R8A779H0_PD_A1CN0 44 +#define R8A779H0_PD_A1DSP1 45 +#define R8A779H0_PD_A2DMA 47 +#define R8A779H0_PD_A2CV2 48 +#define R8A779H0_PD_A2CV3 49 +#define R8A779H0_PD_A3IMR2 50 +#define R8A779H0_PD_A3IMR3 51 +#define R8A779H0_PD_A3PCI 52 +#define R8A779H0_PD_A2PCIPHY 53 +#define R8A779H0_PD_A3VIP0 56 +#define R8A779H0_PD_A3VIP2 58 +#define R8A779H0_PD_A3ISP0 60 +#define R8A779H0_PD_A3DUL 62 + +/* Always-on power area */ +#define R8A779H0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */ diff --git a/dts/include/dt-bindings/reset/mediatek,mt7988-resets.h b/dts/include/dt-bindings/reset/mediatek,mt7988-resets.h index 4933019713..0eb152889a 100644 --- a/dts/include/dt-bindings/reset/mediatek,mt7988-resets.h +++ b/dts/include/dt-bindings/reset/mediatek,mt7988-resets.h @@ -10,4 +10,10 @@ /* ETHWARP resets */ #define MT7988_ETHWARP_RST_SWITCH 0 +/* INFRA resets */ +#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0 +#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1 + + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ + diff --git a/dts/include/dt-bindings/reset/qcom,x1e80100-gpucc.h b/dts/include/dt-bindings/reset/qcom,x1e80100-gpucc.h new file mode 100644 index 0000000000..32b43e71a1 --- /dev/null +++ b/dts/include/dt-bindings/reset/qcom,x1e80100-gpucc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H +#define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H + +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_FF_BCR 4 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 +#define GPUCC_GPU_CC_GMU_BCR 6 +#define GPUCC_GPU_CC_GX_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +#endif diff --git a/dts/include/dt-bindings/reset/sophgo,sg2042-reset.h b/dts/include/dt-bindings/reset/sophgo,sg2042-reset.h new file mode 100644 index 0000000000..9ab0980625 --- /dev/null +++ b/dts/include/dt-bindings/reset/sophgo,sg2042-reset.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ +#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ + +#define RST_MAIN_AP 0 +#define RST_RISCV_CPU 1 +#define RST_RISCV_LOW_SPEED_LOGIC 2 +#define RST_RISCV_CMN 3 +#define RST_HSDMA 4 +#define RST_SYSDMA 5 +#define RST_EFUSE0 6 +#define RST_EFUSE1 7 +#define RST_RTC 8 +#define RST_TIMER 9 +#define RST_WDT 10 +#define RST_AHB_ROM0 11 +#define RST_AHB_ROM1 12 +#define RST_I2C0 13 +#define RST_I2C1 14 +#define RST_I2C2 15 +#define RST_I2C3 16 +#define RST_GPIO0 17 +#define RST_GPIO1 18 +#define RST_GPIO2 19 +#define RST_PWM 20 +#define RST_AXI_SRAM0 21 +#define RST_AXI_SRAM1 22 +#define RST_SF0 23 +#define RST_SF1 24 +#define RST_LPC 25 +#define RST_ETH0 26 +#define RST_EMMC 27 +#define RST_SD 28 +#define RST_UART0 29 +#define RST_UART1 30 +#define RST_UART2 31 +#define RST_UART3 32 +#define RST_SPI0 33 +#define RST_SPI1 34 +#define RST_DBG_I2C 35 +#define RST_PCIE0 36 +#define RST_PCIE1 37 +#define RST_DDR0 38 +#define RST_DDR1 39 +#define RST_DDR2 40 +#define RST_DDR3 41 +#define RST_FAU0 42 +#define RST_FAU1 43 +#define RST_FAU2 44 +#define RST_RXU0 45 +#define RST_RXU1 46 +#define RST_RXU2 47 +#define RST_RXU3 48 +#define RST_RXU4 49 +#define RST_RXU5 50 +#define RST_RXU6 51 +#define RST_RXU7 52 +#define RST_RXU8 53 +#define RST_RXU9 54 +#define RST_RXU10 55 +#define RST_RXU11 56 +#define RST_RXU12 57 +#define RST_RXU13 58 +#define RST_RXU14 59 +#define RST_RXU15 60 +#define RST_RXU16 61 +#define RST_RXU17 62 +#define RST_RXU18 63 +#define RST_RXU19 64 +#define RST_RXU20 65 +#define RST_RXU21 66 +#define RST_RXU22 67 +#define RST_RXU23 68 +#define RST_RXU24 69 +#define RST_RXU25 70 +#define RST_RXU26 71 +#define RST_RXU27 72 +#define RST_RXU28 73 +#define RST_RXU29 74 +#define RST_RXU30 75 +#define RST_RXU31 76 + +#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */ diff --git a/dts/src/arm/allwinner/sun8i-r40-feta40i.dtsi b/dts/src/arm/allwinner/sun8i-r40-feta40i.dtsi index 9f39b5a2bb..c12361d031 100644 --- a/dts/src/arm/allwinner/sun8i-r40-feta40i.dtsi +++ b/dts/src/arm/allwinner/sun8i-r40-feta40i.dtsi @@ -42,6 +42,13 @@ vcc-pg-supply = <®_dldo1>; }; +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-tv-usb"; +}; + ®_aldo2 { regulator-always-on; regulator-min-microvolt = <1800000>; diff --git a/dts/src/arm/amlogic/meson.dtsi b/dts/src/arm/amlogic/meson.dtsi index 8e3860d5d9..8cb0fc78b2 100644 --- a/dts/src/arm/amlogic/meson.dtsi +++ b/dts/src/arm/amlogic/meson.dtsi @@ -23,7 +23,7 @@ #size-cells = <1>; ranges; - cbus: cbus@c1100000 { + cbus: bus@c1100000 { compatible = "simple-bus"; reg = <0xc1100000 0x200000>; #address-cells = <1>; @@ -206,7 +206,7 @@ }; }; - aobus: aobus@c8100000 { + aobus: bus@c8100000 { compatible = "simple-bus"; reg = <0xc8100000 0x100000>; #address-cells = <1>; @@ -302,7 +302,7 @@ reg = <0xd9040000 0x10000>; }; - secbus: secbus@da000000 { + secbus: bus@da000000 { compatible = "simple-bus"; reg = <0xda000000 0x6000>; #address-cells = <1>; diff --git a/dts/src/arm/amlogic/meson8.dtsi b/dts/src/arm/amlogic/meson8.dtsi index 59932fbfd5..f57be9ae15 100644 --- a/dts/src/arm/amlogic/meson8.dtsi +++ b/dts/src/arm/amlogic/meson8.dtsi @@ -645,7 +645,6 @@ }; &hwrng { - compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; diff --git a/dts/src/arm/amlogic/meson8b.dtsi b/dts/src/arm/amlogic/meson8b.dtsi index 5198f5177c..2d9d24d3a9 100644 --- a/dts/src/arm/amlogic/meson8b.dtsi +++ b/dts/src/arm/amlogic/meson8b.dtsi @@ -620,7 +620,6 @@ }; &hwrng { - compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; diff --git a/dts/src/arm/arm/arm-realview-pb1176.dts b/dts/src/arm/arm/arm-realview-pb1176.dts index efed325af8..d99bac0223 100644 --- a/dts/src/arm/arm/arm-realview-pb1176.dts +++ b/dts/src/arm/arm/arm-realview-pb1176.dts @@ -451,7 +451,7 @@ /* Direct-mapped development chip ROM */ pb1176_rom@10200000 { - compatible = "direct-mapped"; + compatible = "mtd-rom"; reg = <0x10200000 0x4000>; bank-width = <1>; }; diff --git a/dts/src/arm/arm/integratorap-im-pd1.dts b/dts/src/arm/arm/integratorap-im-pd1.dts index 7072a70da0..367850ea09 100644 --- a/dts/src/arm/arm/integratorap-im-pd1.dts +++ b/dts/src/arm/arm/integratorap-im-pd1.dts @@ -129,8 +129,6 @@ bridge { compatible = "ti,ths8134b", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; @@ -154,6 +152,7 @@ vga { compatible = "vga-connector"; + label = "J30"; port { vga_con_in: endpoint { diff --git a/dts/src/arm/arm/versatile-ab.dts b/dts/src/arm/arm/versatile-ab.dts index f31dcf7e58..de45aa99e2 100644 --- a/dts/src/arm/arm/versatile-ab.dts +++ b/dts/src/arm/arm/versatile-ab.dts @@ -32,8 +32,6 @@ bridge { compatible = "ti,ths8134b", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; @@ -59,6 +57,7 @@ vga { compatible = "vga-connector"; + label = "J1"; port { vga_con_in: endpoint { diff --git a/dts/src/arm/arm/vexpress-v2p-ca9.dts b/dts/src/arm/arm/vexpress-v2p-ca9.dts index 5916e4877e..8bf3566641 100644 --- a/dts/src/arm/arm/vexpress-v2p-ca9.dts +++ b/dts/src/arm/arm/vexpress-v2p-ca9.dts @@ -20,7 +20,9 @@ #address-cells = <1>; #size-cells = <1>; - chosen { }; + chosen { + stdout-path = &v2m_serial0; + }; aliases { serial0 = &v2m_serial0; diff --git a/dts/src/arm/broadcom/bcm47622.dtsi b/dts/src/arm/broadcom/bcm47622.dtsi index 7cd38de118..485863f9c4 100644 --- a/dts/src/arm/broadcom/bcm47622.dtsi +++ b/dts/src/arm/broadcom/bcm47622.dtsi @@ -138,6 +138,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/dts/src/arm/broadcom/bcm63138.dtsi b/dts/src/arm/broadcom/bcm63138.dtsi index 4ef0228361..e74ba6bf37 100644 --- a/dts/src/arm/broadcom/bcm63138.dtsi +++ b/dts/src/arm/broadcom/bcm63138.dtsi @@ -229,7 +229,12 @@ reg-names = "nand", "nand-int-base"; status = "disabled"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "nand"; + interrupt-names = "nand_ctlrdy"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; }; serial@4400 { diff --git a/dts/src/arm/broadcom/bcm63148.dtsi b/dts/src/arm/broadcom/bcm63148.dtsi index 24431de181..53703827ee 100644 --- a/dts/src/arm/broadcom/bcm63148.dtsi +++ b/dts/src/arm/broadcom/bcm63148.dtsi @@ -119,5 +119,19 @@ num-cs = <8>; status = "disabled"; }; + + nand_controller: nand-controller@2000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x2000 0x600>, <0xf0 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; }; }; diff --git a/dts/src/arm/broadcom/bcm63178.dtsi b/dts/src/arm/broadcom/bcm63178.dtsi index 3f9aed96ba..6d8d334989 100644 --- a/dts/src/arm/broadcom/bcm63178.dtsi +++ b/dts/src/arm/broadcom/bcm63178.dtsi @@ -129,6 +129,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/dts/src/arm/broadcom/bcm6756.dtsi b/dts/src/arm/broadcom/bcm6756.dtsi index 1d8d957d65..6433f8fa5e 100644 --- a/dts/src/arm/broadcom/bcm6756.dtsi +++ b/dts/src/arm/broadcom/bcm6756.dtsi @@ -139,6 +139,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/dts/src/arm/broadcom/bcm6846.dtsi b/dts/src/arm/broadcom/bcm6846.dtsi index cf92cf8c46..ee361cb00b 100644 --- a/dts/src/arm/broadcom/bcm6846.dtsi +++ b/dts/src/arm/broadcom/bcm6846.dtsi @@ -119,5 +119,19 @@ num-cs = <8>; status = "disabled"; }; + + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; }; }; diff --git a/dts/src/arm/broadcom/bcm6855.dtsi b/dts/src/arm/broadcom/bcm6855.dtsi index 52d6bc89f9..52915ec6f3 100644 --- a/dts/src/arm/broadcom/bcm6855.dtsi +++ b/dts/src/arm/broadcom/bcm6855.dtsi @@ -129,6 +129,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/dts/src/arm/broadcom/bcm6878.dtsi b/dts/src/arm/broadcom/bcm6878.dtsi index 2c5d706bac..70cf23a65f 100644 --- a/dts/src/arm/broadcom/bcm6878.dtsi +++ b/dts/src/arm/broadcom/bcm6878.dtsi @@ -120,6 +120,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/dts/src/arm/broadcom/bcm947622.dts b/dts/src/arm/broadcom/bcm947622.dts index 93b8ce2267..6241485408 100644 --- a/dts/src/arm/broadcom/bcm947622.dts +++ b/dts/src/arm/broadcom/bcm947622.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm/broadcom/bcm963138.dts b/dts/src/arm/broadcom/bcm963138.dts index 1b405c2492..7fd87e05ec 100644 --- a/dts/src/arm/broadcom/bcm963138.dts +++ b/dts/src/arm/broadcom/bcm963138.dts @@ -29,3 +29,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm/broadcom/bcm963138dvt.dts b/dts/src/arm/broadcom/bcm963138dvt.dts index b5af61853a..f60d09908a 100644 --- a/dts/src/arm/broadcom/bcm963138dvt.dts +++ b/dts/src/arm/broadcom/bcm963138dvt.dts @@ -32,15 +32,15 @@ }; &nand_controller { + brcm,wp-not-connected; status = "okay"; +}; - nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - brcm,nand-oob-sectors-size = <16>; - }; +&nandcs { + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + nand-on-flash-bbt; }; &ahci { diff --git a/dts/src/arm/broadcom/bcm963148.dts b/dts/src/arm/broadcom/bcm963148.dts index 1f5d6d783f..44bca063a3 100644 --- a/dts/src/arm/broadcom/bcm963148.dts +++ b/dts/src/arm/broadcom/bcm963148.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm/broadcom/bcm963178.dts b/dts/src/arm/broadcom/bcm963178.dts index d036e99dd8..098a222cd7 100644 --- a/dts/src/arm/broadcom/bcm963178.dts +++ b/dts/src/arm/broadcom/bcm963178.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm/broadcom/bcm96756.dts b/dts/src/arm/broadcom/bcm96756.dts index 8b104f3fb1..402038d3cd 100644 --- a/dts/src/arm/broadcom/bcm96756.dts +++ b/dts/src/arm/broadcom/bcm96756.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm/broadcom/bcm96846.dts b/dts/src/arm/broadcom/bcm96846.dts index 55852c2296..943896afb7 100644 --- a/dts/src/arm/broadcom/bcm96846.dts +++ b/dts/src/arm/broadcom/bcm96846.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm/broadcom/bcm96855.dts b/dts/src/arm/broadcom/bcm96855.dts index 2ad880af21..571663d9a1 100644 --- a/dts/src/arm/broadcom/bcm96855.dts +++ b/dts/src/arm/broadcom/bcm96855.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm/broadcom/bcm96878.dts b/dts/src/arm/broadcom/bcm96878.dts index b7af8ade7a..8d6eddd54c 100644 --- a/dts/src/arm/broadcom/bcm96878.dts +++ b/dts/src/arm/broadcom/bcm96878.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm/gemini/gemini-dlink-dir-685.dts b/dts/src/arm/gemini/gemini-dlink-dir-685.dts index 3961496642..b4dbcf8f16 100644 --- a/dts/src/arm/gemini/gemini-dlink-dir-685.dts +++ b/dts/src/arm/gemini/gemini-dlink-dir-685.dts @@ -27,10 +27,10 @@ gpio_keys { compatible = "gpio-keys"; - button-esc { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_ESC>; + linux,code = <KEY_RESTART>; label = "reset"; /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; @@ -187,7 +187,7 @@ }; /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */ - switch { + ethernet-switch { compatible = "realtek,rtl8366rb"; /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; @@ -204,36 +204,36 @@ #interrupt-cells = <1>; }; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan0"; phy-handle = <&phy0>; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan1"; phy-handle = <&phy1>; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan2"; phy-handle = <&phy2>; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan3"; phy-handle = <&phy3>; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "wan"; phy-handle = <&phy4>; }; - rtl8366rb_cpu_port: port@5 { + rtl8366rb_cpu_port: ethernet-port@5 { reg = <5>; label = "cpu"; ethernet = <&gmac0>; @@ -252,27 +252,27 @@ #address-cells = <1>; #size-cells = <0>; - phy0: phy@0 { + phy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&switch_intc>; interrupts = <0>; }; - phy1: phy@1 { + phy1: ethernet-phy@1 { reg = <1>; interrupt-parent = <&switch_intc>; interrupts = <1>; }; - phy2: phy@2 { + phy2: ethernet-phy@2 { reg = <2>; interrupt-parent = <&switch_intc>; interrupts = <2>; }; - phy3: phy@3 { + phy3: ethernet-phy@3 { reg = <3>; interrupt-parent = <&switch_intc>; interrupts = <3>; }; - phy4: phy@4 { + phy4: ethernet-phy@4 { reg = <4>; interrupt-parent = <&switch_intc>; interrupts = <12>; diff --git a/dts/src/arm/gemini/gemini-dlink-dns-313.dts b/dts/src/arm/gemini/gemini-dlink-dns-313.dts index 138c47e1ac..8c54d3a5a7 100644 --- a/dts/src/arm/gemini/gemini-dlink-dns-313.dts +++ b/dts/src/arm/gemini/gemini-dlink-dns-313.dts @@ -33,10 +33,10 @@ gpio_keys { compatible = "gpio-keys"; - button-esc { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_ESC>; + linux,code = <KEY_RESTART>; label = "reset"; gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; }; diff --git a/dts/src/arm/gemini/gemini-sl93512r.dts b/dts/src/arm/gemini/gemini-sl93512r.dts index 91c19e8ebf..4992ec276d 100644 --- a/dts/src/arm/gemini/gemini-sl93512r.dts +++ b/dts/src/arm/gemini/gemini-sl93512r.dts @@ -43,7 +43,7 @@ button-setup { debounce-interval = <50>; wakeup-source; - linux,code = <KEY_SETUP>; + linux,code = <KEY_RESTART>; label = "factory reset"; /* Conflict with NAND flash */ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; @@ -93,7 +93,7 @@ cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - switch@0 { + ethernet-switch@0 { compatible = "vitesse,vsc7385"; reg = <0>; /* Specified for 2.5 MHz or below */ @@ -101,27 +101,27 @@ gpio-controller; #gpio-cells = <2>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan1"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan2"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan3"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan4"; }; - vsc: port@6 { + vsc: ethernet-port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac1>; diff --git a/dts/src/arm/gemini/gemini-sq201.dts b/dts/src/arm/gemini/gemini-sq201.dts index d0efd76695..f8c6f6e5cd 100644 --- a/dts/src/arm/gemini/gemini-sq201.dts +++ b/dts/src/arm/gemini/gemini-sq201.dts @@ -30,7 +30,7 @@ button-setup { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_SETUP>; + linux,code = <KEY_RESTART>; label = "factory reset"; /* Conflict with NAND flash */ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; @@ -78,7 +78,7 @@ cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - switch@0 { + ethernet-switch@0 { compatible = "vitesse,vsc7395"; reg = <0>; /* Specified for 2.5 MHz or below */ @@ -86,27 +86,27 @@ gpio-controller; #gpio-cells = <2>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan1"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan2"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan3"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan4"; }; - vsc: port@6 { + vsc: ethernet-port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac1>; diff --git a/dts/src/arm/gemini/gemini-wbd111.dts b/dts/src/arm/gemini/gemini-wbd111.dts index 3c88c59ab4..6a0c89e0c9 100644 --- a/dts/src/arm/gemini/gemini-wbd111.dts +++ b/dts/src/arm/gemini/gemini-wbd111.dts @@ -10,7 +10,7 @@ / { model = "Wiliboard WBD-111"; - compatible = "wiliboard,wbd111", "cortina,gemini"; + compatible = "wiligear,wiliboard-wbd111", "cortina,gemini"; #address-cells = <1>; #size-cells = <1>; @@ -28,10 +28,10 @@ gpio_keys { compatible = "gpio-keys"; - button-setup { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_SETUP>; + linux,code = <KEY_RESTART>; label = "reset"; /* Conflict with ICE */ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; diff --git a/dts/src/arm/gemini/gemini-wbd222.dts b/dts/src/arm/gemini/gemini-wbd222.dts index ff72bbc4db..d8b34ebad4 100644 --- a/dts/src/arm/gemini/gemini-wbd222.dts +++ b/dts/src/arm/gemini/gemini-wbd222.dts @@ -10,7 +10,7 @@ / { model = "Wiliboard WBD-222"; - compatible = "wiliboard,wbd222", "cortina,gemini"; + compatible = "wiligear,wiliboard-wbd222", "cortina,gemini"; #address-cells = <1>; #size-cells = <1>; @@ -27,10 +27,10 @@ gpio_keys { compatible = "gpio-keys"; - button-setup { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_SETUP>; + linux,code = <KEY_RESTART>; label = "reset"; /* Conflict with ICE */ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; diff --git a/dts/src/arm/marvell/armada-385-clearfog-gtr-l8.dts b/dts/src/arm/marvell/armada-385-clearfog-gtr-l8.dts index 1707d1b015..cb85f8e31d 100644 --- a/dts/src/arm/marvell/armada-385-clearfog-gtr-l8.dts +++ b/dts/src/arm/marvell/armada-385-clearfog-gtr-l8.dts @@ -4,6 +4,18 @@ / { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", + "marvell,armada380"; + + /* CON25 */ + sfp1: sfp-1 { + compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp1_pins>; + pinctrl-names = "default"; + i2c-bus = <&i2c0>; + mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + }; }; &mdio { @@ -20,57 +32,65 @@ ethernet-port@1 { reg = <1>; - label = "lan8"; + label = "lan1"; phy-handle = <&switch0phy0>; }; ethernet-port@2 { reg = <2>; - label = "lan7"; + label = "lan2"; phy-handle = <&switch0phy1>; }; ethernet-port@3 { reg = <3>; - label = "lan6"; + label = "lan3"; phy-handle = <&switch0phy2>; }; ethernet-port@4 { reg = <4>; - label = "lan5"; + label = "lan4"; phy-handle = <&switch0phy3>; }; ethernet-port@5 { reg = <5>; - label = "lan4"; + label = "lan5"; phy-handle = <&switch0phy4>; }; ethernet-port@6 { reg = <6>; - label = "lan3"; + label = "lan6"; phy-handle = <&switch0phy5>; }; ethernet-port@7 { reg = <7>; - label = "lan2"; + label = "lan7"; phy-handle = <&switch0phy6>; }; ethernet-port@8 { reg = <8>; - label = "lan1"; + label = "lan8"; phy-handle = <&switch0phy7>; }; + ethernet-port@9 { + reg = <9>; + label = "lan-sfp"; + phy-mode = "sgmii"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + ethernet-port@10 { reg = <10>; phy-mode = "2500base-x"; - ethernet = <ð1>; + fixed-link { speed = <2500>; full-duplex; diff --git a/dts/src/arm/marvell/armada-385-clearfog-gtr-s4.dts b/dts/src/arm/marvell/armada-385-clearfog-gtr-s4.dts index a7678a784c..5f83d98144 100644 --- a/dts/src/arm/marvell/armada-385-clearfog-gtr-s4.dts +++ b/dts/src/arm/marvell/armada-385-clearfog-gtr-s4.dts @@ -4,6 +4,8 @@ / { model = "SolidRun Clearfog GTR S4"; + compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385", + "marvell,armada380"; }; &sfp0 { diff --git a/dts/src/arm/marvell/armada-385-clearfog-gtr.dtsi b/dts/src/arm/marvell/armada-385-clearfog-gtr.dtsi index d1452a04e9..f3a3cb6ac3 100644 --- a/dts/src/arm/marvell/armada-385-clearfog-gtr.dtsi +++ b/dts/src/arm/marvell/armada-385-clearfog-gtr.dtsi @@ -141,18 +141,13 @@ }; pinctrl@18000 { - cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { - marvell,pins = "mpp22"; + cf_gtr_fan_pwm: cf-gtr-fan-pwm { + marvell,pins = "mpp23"; marvell,function = "gpio"; }; - cf_gtr_fan_pwm: cf-gtr-fan-pwm { - marvell,pins = "mpp23"; + cf_gtr_front_button_pins: cf-gtr-front-button-pins { + marvell,pins = "mpp53"; marvell,function = "gpio"; }; @@ -162,6 +157,37 @@ marvell,function = "i2c1"; }; + cf_gtr_isolation_pins: cf-gtr-isolation-pins { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + cf_gtr_led_pins: led-pins { + marvell,pins = "mpp42", "mpp52"; + marvell,function = "gpio"; + }; + + cf_gtr_lte_disable_pins: lte-disable-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + cf_gtr_pci_pins: pci-pins { + // pci reset + marvell,pins = "mpp33", "mpp35", "mpp44"; + marvell,function = "gpio"; + }; + + cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { marvell,pins = "mpp21", "mpp28", "mpp37", "mpp38", @@ -169,13 +195,15 @@ marvell,function = "sd0"; }; - cf_gtr_isolation_pins: cf-gtr-isolation-pins { - marvell,pins = "mpp47"; + cf_gtr_sfp0_pins: sfp0-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp25", "mpp46"; marvell,function = "gpio"; }; - cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { - marvell,pins = "mpp48"; + cf_gtr_sfp1_pins: sfp1-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp24", "mpp54"; marvell,function = "gpio"; }; @@ -184,13 +212,18 @@ marvell,function = "spi1"; }; - cf_gtr_front_button_pins: cf-gtr-front-button-pins { - marvell,pins = "mpp53"; + cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { + marvell,pins = "mpp18"; marvell,function = "gpio"; }; - cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { - marvell,pins = "mpp36"; + cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + cf_gtr_wifi_disable_pins: wifi-disable-pins { + marvell,pins = "mpp30", "mpp31"; marvell,function = "gpio"; }; }; @@ -221,21 +254,26 @@ }; pcie { + pinctrl-0 = <&cf_gtr_pci_pins>; + pinctrl-names = "default"; status = "okay"; /* * The PCIe units are accessible through * the mini-PCIe connectors on the board. */ + /* CON3 - serdes 0 */ pcie@1,0 { reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON4 - serdes 2 */ pcie@2,0 { reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON2 - serdes 4 */ pcie@3,0 { reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; @@ -243,10 +281,12 @@ }; }; - sfp0: sfp { + /* CON5 */ + sfp0: sfp-0 { compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp0_pins>; + pinctrl-names = "default"; i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; @@ -273,6 +313,8 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&cf_gtr_led_pins>; + pinctrl-names = "default"; led1 { function = LED_FUNCTION_CPU; @@ -408,7 +450,7 @@ }; &gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; + pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; wifi-disable { @@ -420,7 +462,7 @@ }; &gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; + pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; lte-disable { diff --git a/dts/src/arm/marvell/armada-388-clearfog.dts b/dts/src/arm/marvell/armada-388-clearfog.dts index 3290ccad23..09bf2e6d4e 100644 --- a/dts/src/arm/marvell/armada-388-clearfog.dts +++ b/dts/src/arm/marvell/armada-388-clearfog.dts @@ -10,8 +10,9 @@ / { model = "SolidRun Clearfog A1"; - compatible = "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; + compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1", + "marvell,armada388", "marvell,armada385", + "marvell,armada380"; soc { internal-regs { diff --git a/dts/src/arm/marvell/dove-cubox.dts b/dts/src/arm/marvell/dove-cubox.dts index bfde99486a..bcaaf8320c 100644 --- a/dts/src/arm/marvell/dove-cubox.dts +++ b/dts/src/arm/marvell/dove-cubox.dts @@ -101,7 +101,7 @@ /* connect xtal input as source of pll0 and pll1 */ silabs,pll-source = <0 0>, <1 0>; - clkout0 { + clkout@0 { reg = <0>; silabs,drive-strength = <8>; silabs,multisynth-source = <0>; @@ -109,7 +109,7 @@ silabs,pll-master; }; - clkout2 { + clkout@2 { reg = <2>; silabs,drive-strength = <8>; silabs,multisynth-source = <1>; diff --git a/dts/src/arm/marvell/mmp2-brownstone.dts b/dts/src/arm/marvell/mmp2-brownstone.dts index 04f1ae1382..bc64348b82 100644 --- a/dts/src/arm/marvell/mmp2-brownstone.dts +++ b/dts/src/arm/marvell/mmp2-brownstone.dts @@ -28,7 +28,7 @@ &twsi1 { status = "okay"; pmic: max8925@3c { - compatible = "maxium,max8925"; + compatible = "maxim,max8925"; reg = <0x3c>; interrupts = <1>; interrupt-parent = <&intcmux4>; diff --git a/dts/src/arm/microchip/at91-sama7g54_curiosity.dts b/dts/src/arm/microchip/at91-sama7g54_curiosity.dts new file mode 100644 index 0000000000..4f609e9e51 --- /dev/null +++ b/dts/src/arm/microchip/at91-sama7g54_curiosity.dts @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7g54_curiosity.dts - Device Tree file for SAMA7G54 Curiosity Board + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ +/dts-v1/; +#include "sama7g5-pinfunc.h" +#include "sama7g5.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/mfd/atmel-flexcom.h> +#include <dt-bindings/pinctrl/at91.h> + +/ { + model = "Microchip SAMA7G54 Curiosity"; + compatible = "microchip,sama7g54-curiosity", "microchip,sama7g5", "microchip,sama7"; + + aliases { + serial0 = &uart3; + i2c0 = &i2c10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-user { + label = "user-button"; + gpios = <&pioA PIN_PD19 GPIO_ACTIVE_LOW>; + linux,code = <KEY_PROG1>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + + led-red { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_POWER; + gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-green { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_BOOT; + gpios = <&pioA PIN_PD14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-blue { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_CPU; + gpios = <&pioA PIN_PB15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x10000000>; /* 256 MiB DDR3L-1066 16-bit */ + }; +}; + +&adc { + vddana-supply = <&vddout25>; + vref-supply = <&vddout25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; +}; + +&dma0 { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&ebi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_default>; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "nand: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "nand: u-boot"; + reg = <0x40000 0x100000>; + }; + + bootloaderenv@140000 { + label = "nand: u-boot env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "nand: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "nand: kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "nand: rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + uart3: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "okay"; + }; +}; + +&flx10 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c10: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx10_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + size = <256>; + vcc-supply = <&vdd_3v3>; + }; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-voltage = <1150000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-voltage = <1050000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-voltage = <1800000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-voltage = <3300000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; +}; + +&main_xtal { + clock-frequency = <24000000>; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; + +&pioA { + pinctrl_flx3_default: flx3-default { + pinmux = <PIN_PD16__FLEXCOM3_IO0>, + <PIN_PD17__FLEXCOM3_IO1>; + bias-pull-up; + }; + + pinctrl_flx10_default: flx10-default { + pinmux = <PIN_PC30__FLEXCOM10_IO0>, + <PIN_PC31__FLEXCOM10_IO1>; + bias-pull-up; + }; + + pinctrl_key_gpio_default: key-gpio-default { + pinmux = <PIN_PD19__GPIO>; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led-gpio-default { + pinmux = <PIN_PD13__GPIO>, + <PIN_PD14__GPIO>, + <PIN_PB15__GPIO>; + bias-pull-up; + }; + + pinctrl_mikrobus1_an_default: mikrobus1-an-default { + pinmux = <PIN_PC15__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus2_an_default: mikrobus2-an-default { + pinmux = <PIN_PC13__GPIO>; + bias-disable; + }; + + pinctrl_nand_default: nand-default { + pinmux = <PIN_PD9__D0>, + <PIN_PD10__D1>, + <PIN_PD11__D2>, + <PIN_PC21__D3>, + <PIN_PC22__D4>, + <PIN_PC23__D5>, + <PIN_PC24__D6>, + <PIN_PD2__D7>, + <PIN_PD3__NANDRDY>, + <PIN_PD4__NCS3_NANDCS>, + <PIN_PD5__NWE_NWR0_NANDWE>, + <PIN_PD6__NRD_NANDOE>, + <PIN_PD7__A21_NANDALE>, + <PIN_PD8__A22_NANDCLE>; + bias-disable; + slew-rate = <0>; + }; + + pinctrl_qspi1_default: qspi1-default { + pinmux = <PIN_PB22__QSPI1_IO3>, + <PIN_PB23__QSPI1_IO2>, + <PIN_PB24__QSPI1_IO1>, + <PIN_PB25__QSPI1_IO0>, + <PIN_PB26__QSPI1_CS>, + <PIN_PB27__QSPI1_SCK>; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc0_default: sdmmc0-default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_RSTN>, + <PIN_PA3__SDMMC0_DAT0>, + <PIN_PA4__SDMMC0_DAT1>, + <PIN_PA5__SDMMC0_DAT2>, + <PIN_PA6__SDMMC0_DAT3>; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc1_default: sdmmc1-default { + pinmux = <PIN_PB29__SDMMC1_CMD>, + <PIN_PB30__SDMMC1_CK>, + <PIN_PB31__SDMMC1_DAT0>, + <PIN_PC0__SDMMC1_DAT1>, + <PIN_PC1__SDMMC1_DAT2>, + <PIN_PC2__SDMMC1_DAT3>, + <PIN_PC4__SDMMC1_CD>; + bias-pull-up; + slew-rate = <0>; + }; +}; + +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + +/* M.2 slot for wireless card */ +&sdmmc0 { + bus-width = <4>; + cd-gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + disable-wp; + sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +/* micro SD socket */ +&sdmmc1 { + bus-width = <4>; + disable-wp; + sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&shdwc { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&trng { + status = "okay"; +}; + +&vddout25 { + vin-supply = <&vdd_3v3>; + status = "okay"; +}; diff --git a/dts/src/arm/microchip/at91sam9g25-gardena-smart-gateway.dts b/dts/src/arm/microchip/at91sam9g25-gardena-smart-gateway.dts index 92f2c05c87..af70eb8a3a 100644 --- a/dts/src/arm/microchip/at91sam9g25-gardena-smart-gateway.dts +++ b/dts/src/arm/microchip/at91sam9g25-gardena-smart-gateway.dts @@ -121,6 +121,8 @@ }; &usart3 { + atmel,use-dma-rx; + atmel,use-dma-tx; status = "okay"; pinctrl-0 = <&pinctrl_usart3 diff --git a/dts/src/arm/microchip/at91sam9x5ek.dtsi b/dts/src/arm/microchip/at91sam9x5ek.dtsi index 5f4eaa618a..9618b8d965 100644 --- a/dts/src/arm/microchip/at91sam9x5ek.dtsi +++ b/dts/src/arm/microchip/at91sam9x5ek.dtsi @@ -39,6 +39,8 @@ }; &dbgu { + atmel,use-dma-rx; + atmel,use-dma-tx; status = "okay"; }; diff --git a/dts/src/arm/microchip/sam9x60.dtsi b/dts/src/arm/microchip/sam9x60.dtsi index 73d570a172..291540e5d8 100644 --- a/dts/src/arm/microchip/sam9x60.dtsi +++ b/dts/src/arm/microchip/sam9x60.dtsi @@ -179,7 +179,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(8))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; @@ -202,7 +202,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(8))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; @@ -220,7 +220,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(8))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; @@ -248,7 +248,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; @@ -271,7 +271,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; @@ -289,7 +289,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; @@ -377,7 +377,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(22))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(23))>; @@ -399,7 +399,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(22))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(23))>; @@ -426,7 +426,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(24))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; @@ -448,7 +448,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(24))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; @@ -583,7 +583,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(12))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(13))>; @@ -605,7 +605,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(12))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(13))>; @@ -632,7 +632,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(14))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(15))>; @@ -654,7 +654,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(14))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(15))>; @@ -681,7 +681,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(17))>; @@ -703,7 +703,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(17))>; @@ -730,7 +730,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; @@ -753,7 +753,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; @@ -771,7 +771,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; @@ -798,7 +798,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; @@ -821,7 +821,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; @@ -839,7 +839,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; @@ -866,7 +866,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(4))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; @@ -889,7 +889,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(4))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; @@ -907,7 +907,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(4))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; @@ -934,7 +934,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; @@ -957,7 +957,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; @@ -975,7 +975,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; @@ -1057,7 +1057,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(18))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(19))>; @@ -1079,7 +1079,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(18))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(19))>; @@ -1106,7 +1106,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(20))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(21))>; @@ -1128,7 +1128,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(20))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(21))>; diff --git a/dts/src/arm/microchip/sama7g5.dtsi b/dts/src/arm/microchip/sama7g5.dtsi index 269e0a3ca2..75778be126 100644 --- a/dts/src/arm/microchip/sama7g5.dtsi +++ b/dts/src/arm/microchip/sama7g5.dtsi @@ -698,7 +698,7 @@ }; flx0: flexcom@e1818000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe1818000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; #address-cells = <1>; @@ -714,7 +714,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, - <&dma1 AT91_XDMAC_DT_PERID(5)>; + <&dma1 AT91_XDMAC_DT_PERID(5)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -723,7 +723,7 @@ }; flx1: flexcom@e181c000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe181c000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; #address-cells = <1>; @@ -740,14 +740,14 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, - <&dma0 AT91_XDMAC_DT_PERID(7)>; + <&dma0 AT91_XDMAC_DT_PERID(7)>; dma-names = "tx", "rx"; status = "disabled"; }; }; flx3: flexcom@e1824000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe1824000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; #address-cells = <1>; @@ -763,7 +763,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, - <&dma1 AT91_XDMAC_DT_PERID(11)>; + <&dma1 AT91_XDMAC_DT_PERID(11)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -791,7 +791,7 @@ }; flx4: flexcom@e2018000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2018000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; #address-cells = <1>; @@ -807,7 +807,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, - <&dma1 AT91_XDMAC_DT_PERID(13)>; + <&dma1 AT91_XDMAC_DT_PERID(13)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -817,7 +817,7 @@ }; flx7: flexcom@e2024000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2024000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; #address-cells = <1>; @@ -833,7 +833,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, - <&dma1 AT91_XDMAC_DT_PERID(19)>; + <&dma1 AT91_XDMAC_DT_PERID(19)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -911,7 +911,7 @@ }; flx8: flexcom@e2818000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2818000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; #address-cells = <1>; @@ -928,14 +928,14 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, - <&dma0 AT91_XDMAC_DT_PERID(21)>; + <&dma0 AT91_XDMAC_DT_PERID(21)>; dma-names = "tx", "rx"; status = "disabled"; }; }; flx9: flexcom@e281c000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe281c000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; #address-cells = <1>; @@ -952,14 +952,38 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, - <&dma0 AT91_XDMAC_DT_PERID(23)>; + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + flx10: flexcom@e2820000 { + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2820000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2820000 0x800>; + status = "disabled"; + + i2c10: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; dma-names = "tx", "rx"; status = "disabled"; }; }; flx11: flexcom@e2824000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2824000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; #address-cells = <1>; @@ -977,7 +1001,7 @@ #size-cells = <0>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, - <&dma0 AT91_XDMAC_DT_PERID(27)>; + <&dma0 AT91_XDMAC_DT_PERID(27)>; dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/dts/src/arm/nvidia/tegra124-nyan.dtsi b/dts/src/arm/nvidia/tegra124-nyan.dtsi index a2ee371802..8125c1b3e8 100644 --- a/dts/src/arm/nvidia/tegra124-nyan.dtsi +++ b/dts/src/arm/nvidia/tegra124-nyan.dtsi @@ -338,6 +338,7 @@ interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/dts/src/arm/nvidia/tegra124-venice2.dts b/dts/src/arm/nvidia/tegra124-venice2.dts index 3924ee385d..df98dc2a67 100644 --- a/dts/src/arm/nvidia/tegra124-venice2.dts +++ b/dts/src/arm/nvidia/tegra124-venice2.dts @@ -857,6 +857,7 @@ interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/dts/src/arm/nvidia/tegra30-asus-nexus7-grouper-common.dtsi b/dts/src/arm/nvidia/tegra30-asus-nexus7-grouper-common.dtsi index a9342e04b1..15f53babdc 100644 --- a/dts/src/arm/nvidia/tegra30-asus-nexus7-grouper-common.dtsi +++ b/dts/src/arm/nvidia/tegra30-asus-nexus7-grouper-common.dtsi @@ -915,6 +915,9 @@ reg = <0x1c>; realtek,dmic1-data-pin = <1>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "mclk"; }; nct72: temperature-sensor@4c { diff --git a/dts/src/arm/nvidia/tegra30-lg-p880.dts b/dts/src/arm/nvidia/tegra30-lg-p880.dts new file mode 100644 index 0000000000..2f7754fd42 --- /dev/null +++ b/dts/src/arm/nvidia/tegra30-lg-p880.dts @@ -0,0 +1,489 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus 4X HD P880"; + compatible = "lg,p880", "nvidia,tegra30"; + + aliases { + mmc1 = &sdmmc3; /* uSD slot */ + mmc2 = &sdmmc1; /* WiFi */ + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + host-wlan-wake { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GNSS UART-B pinmux */ + uartb-rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb-txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps-reset { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* MicroSD pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-data { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + microsd-detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO keys pinmux */ + volume-up { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + current-alert-irq { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* AUDIO pinmux */ + sub-mic-ldo { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + i2c@7000c400 { + touchscreen@20 { + rmi4-f11@11 { + syna,clip-x-high = <1110>; + syna,clip-y-high = <1973>; + + touchscreen-inverted-y; + }; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < 0x00050001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x77230303 0x001f0000 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emem-configuration = < 0x00000004 0xC0000030 + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000006 0x00000001 0x00000002 0x00000005 + 0x00000001 0x00000000 0x00000003 0x00000003 + 0x03030001 0x00090608 0x70040c09 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xC0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000000 + 0x00000001 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x0000002f 0x00000000 0x0000000b + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000002 0x00000002 + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x00000036 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000164 0xe0000000 0xff00ff00 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000001 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020002>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000018>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000f + 0x00000022 0x0000000b 0x00000004 0x00000005 + 0x00000005 0x00000001 0x00000007 0x00000004 + 0x00000004 0x00000002 0x00000002 0x00000000 + 0x00000002 0x00000005 0x00000002 0x0000000c + 0x0000000b 0x000003ef 0x00000000 0x000000fb + 0x00000001 0x00000001 0x00000004 0x00000000 + 0x00000001 0x00000009 0x00000026 0x00000026 + 0x00000004 0x0000000e 0x00000006 0x00000001 + 0x00000002 0x00000455 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x003200a4 + 0x00008000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00060000 0x00060000 0x00060000 + 0x00060000 0x000b0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000060 0x000a000a 0xa0f10000 0x00000000 + 0x00000000 0x800008ee 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x00000009 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000001 + 0x00000002 0x000008aa 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00090220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + battery: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <2150000>; + energy-full-design-microwatt-hours = <8200000>; + operating-range-celsius = <0 45>; + }; + + gpio-keys { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + sound { + compatible = "lg,tegra-audio-max98089-p880", + "nvidia,tegra-audio-max98089"; + nvidia,model = "LG Optimus 4X HD MAX98089"; + + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/dts/src/arm/nvidia/tegra30-lg-p895.dts b/dts/src/arm/nvidia/tegra30-lg-p895.dts new file mode 100644 index 0000000000..e32fafc7f5 --- /dev/null +++ b/dts/src/arm/nvidia/tegra30-lg-p895.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus Vu P895"; + compatible = "lg,p895", "nvidia,tegra30"; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* GNSS UART-B pinmux */ + uartb-cts-rxd { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb-rts-txd { + nvidia,pins = "uart2_rts_n_pj6", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps-reset { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* GPIO keys pinmux */ + memo-key { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + volume-up { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + current-alert-irq { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Panel pinmux */ + panel-vdd { + nvidia,pins = "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AUDIO pinmux */ + sub-mic-ldo { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Modem pinmux */ + usim-detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive-sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + + i2c@7000c400 { + touchscreen@20 { + rmi4-f11@11 { + syna,clip-x-high = <1535>; + syna,clip-y-high = <2047>; + }; + }; + }; + + memory-controller@7000f000 { + emc-timings-2 { + /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */ + nvidia,ram-code = <2>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x77230303 0x001f0000 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000030 + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000006 0x00000001 0x00000002 0x00000005 + 0x00000001 0x00000000 0x00000003 0x00000003 + 0x03030001 0x00090608 0x70040c09 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x0000000f 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-2 { + /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */ + nvidia,ram-code = <2>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000000 + 0x00000001 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x0000002f 0x00000000 0x0000000b + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000002 0x00000002 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x00000036 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000164 0xe0000000 0xff00ff00 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xd0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xd0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xd0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000004 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000005 0x00000004 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020002>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000018>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000f + 0x00000022 0x0000000b 0x00000004 0x00000005 + 0x00000005 0x00000001 0x00000007 0x00000004 + 0x00000004 0x00000002 0x00000002 0x00000000 + 0x00000002 0x00000005 0x00000002 0x0000000c + 0x0000000b 0x000003ef 0x00000000 0x000000fb + 0x00000001 0x00000001 0x00000004 0x00000000 + 0x00000001 0x00000009 0x00000026 0x00000026 + 0x00000004 0x0000000e 0x00000006 0x00000004 + 0x00000002 0x00000455 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x003200a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080002 0x00080002 0x00080002 + 0x00080002 0x000e0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000060 0x000a000a 0xa0f10000 0x00000000 + 0x00000000 0x800008ee 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x0000000a 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000c0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + battery: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <2080000>; + energy-full-design-microwatt-hours = <7700000>; + operating-range-celsius = <0 45>; + }; + + gpio-keys { + key-memo { + label = "Memo"; + gpios = <&gpio TEGRA_GPIO(B, 6) GPIO_ACTIVE_LOW>; + linux,code = <KEY_MEMO>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + gpio-leds { + led-power { + label = "power::white"; + gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + + linux,default-trigger = "battery-charging"; + + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_CHARGING; + }; + }; + + regulator-lcd3v { + gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "lg,tegra-audio-max98089-p895", + "nvidia,tegra-audio-max98089"; + nvidia,model = "LG Optimus Vu MAX98089"; + + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/dts/src/arm/nvidia/tegra30-lg-x3.dtsi b/dts/src/arm/nvidia/tegra30-lg-x3.dtsi new file mode 100644 index 0000000000..909260a5d0 --- /dev/null +++ b/dts/src/arm/nvidia/tegra30-lg-x3.dtsi @@ -0,0 +1,1812 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/mfd/max77620.h> +#include <dt-bindings/thermal/thermal.h> + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + chassis-type = "handset"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Console */ + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen { }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@bed00000 { + compatible = "ramoops"; + reg = <0xbed00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wlan-reset { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + wlan-host-wake { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GNSS UART-B pinmux */ + gps-pwr-en { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps-ldo-en { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps-clk-ref { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Bluetooth UART-C pinmux */ + uartc-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartc-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-reset { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-dev-wake { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-host-wake { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bt-pcm-dap4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* EMMC pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4-data { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4-reset { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + ddc-i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + mhl-i2c { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO keys pinmux */ + power-key { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + volume-down { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + sen-vdd { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + proxi-vdd { + nvidia,pins = "spi2_miso_px1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sen-vio { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nct-irq { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bat-irq { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + charger-irq { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mpu-irq { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + compass-irq { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + light-irq { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* LED pinmux */ + backlight-en { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + flash-led-en { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + keypad-led { + nvidia,pins = "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* NFC pinmux */ + nfc-irq { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + nfc-ven { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nfc-firm { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* DC pinmux */ + lcd-pwr { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd-wr-n { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd-id { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd-pclk { + nvidia,pins = "lcd_pclk_pb3", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd-rgb-blue { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d18_pm2", + "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd-rgb-green { + nvidia,pins = "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d20_pm4", + "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd-rgb-red { + nvidia,pins = "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d22_pm6", + "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bridge pinmux */ + bridge-reset { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rgb-ic-en { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bridge-clk { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + rgb-bridge { + nvidia,pins = "lcd_sdin_pz2", + "lcd_sdout_pn5", + "lcd_cs0_n_pn4", + "lcd_sck_pz4"; + nvidia,function = "spi5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Panel pinmux */ + panel-reset { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + panel-vio { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Touchscreen pinmux */ + touch-vdd { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch-vio { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch-irq-n { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + touch-rst-n { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch-maker-id { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* MHL pinmux */ + mhl-vio { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl-rst-n { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl-irq { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mhl-sel { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi-hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* AUDIO pinmux */ + hp-detect { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hp-hook { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ear-mic-en { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + audio-irq { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + audio-mclk { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap-i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap-i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* MUIC pinmux */ + muic-irq { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + muic-dp2t { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + muic-usif { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ifx-usb-vbus-en { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcb-rev { + nvidia,pins = "gmi_wait_pi7", + "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag-rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Camera pinmux */ + cam-mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam-pmic-en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + front-cam-rst { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + front-cam-vio { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear-cam-rst { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear-cam-eprom-pr { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear-cam-vcm-pwdn { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Haptic pinmux */ + haptic-en { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + haptic-osc { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Modem pinmux */ + cp2ap-ack1-host-active { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cp2ap-ack2-host-wakeup { + nvidia,pins = "pv0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp-ack2-suspend-req { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp-ack1-slave-wakeup { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cp-kkp { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cp-crash-irq { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp-uarta-tx-ipc { + nvidia,pins = "pu0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ap2cp-uarta-rx-ipc { + nvidia,pins = "pu1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + fota-ap-cts-cp-rts { + nvidia,pins = "pu2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + fota-ap-rts-cp-cts { + nvidia,pins = "pu3"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + modem-enable { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "hsi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + modem-reset { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap-i2s2 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive-i2c { + nvidia,pins = "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive-uart3 { + nvidia,pins = "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive-gmi { + nvidia,pins = "drive_at3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + status = "okay"; + + /* GNSS GSD5T */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(S, 4) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_vbat>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + uartd: serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + + /* Console */ + }; + + pwm@7000a000 { + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0x0e>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_EDGE_RISING>; + + avdd-supply = <&vdd_3v0_sen>; + dvdd-supply = <&vdd_1v8_vio>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + + max98089: audio-codec@10 { + compatible = "maxim,max98089"; + reg = <0x10>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "mclk"; + + assigned-clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + }; + + imu@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&vdd_3v0_sen>; + vddio-supply = <&vdd_1v8_sen>; + + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + }; + + gen2_i2c: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + /* Synaptics RMI4 S3203B touchcreen */ + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&vdd_3v0_touch>; + vio-supply = <&vdd_1v8_touch>; + + syna,reset-delay-ms = <20>; + syna,startup-delay-ms = <200>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + + syna,clip-x-low = <0>; + syna,clip-y-low = <0>; + }; + }; + }; + + cam_i2c: i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + dw9714: coil@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + + enable-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; + + vcc-supply = <&vcc_focuser>; + }; + + camera-pmic@7d { + compatible = "ti,lp8720"; + reg = <0x7d>; + + enable-gpios = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + + vt_1v2_front: ldo1 { + regulator-name = "vt_1v2_dig"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vt_2v7_front: ldo2 { + regulator-name = "vt_2v7_vana"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + vdd_2v7_rear: ldo3 { + regulator-name = "8m_2v7_vana"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + vio_1v8_rear: ldo4 { + regulator-name = "vio_1v8_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_focuser: ldo5 { + regulator-name = "8m_2v8_vcm"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vdd_1v2_rear: buck { + regulator-name = "8m_1v2_cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: max77663@1c { + compatible = "maxim,max77663"; + reg = <0x1c>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&max77663_default>; + + max77663_default: pinmux { + gpio1 { + pins = "gpio1"; + function = "gpio"; + drive-open-drain = <1>; + }; + + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + + regulators { + in-sd0-supply = <&vdd_5v0_vbus>; + in-sd1-supply = <&vdd_5v0_vbus>; + in-sd2-supply = <&vdd_5v0_vbus>; + in-sd3-supply = <&vdd_5v0_vbus>; + + in-ldo0-1-supply = <&vdd_1v8_vio>; + in-ldo2-supply = <&vdd_3v3_vbat>; + in-ldo3-5-supply = <&vdd_3v3_vbat>; + in-ldo4-6-supply = <&vdd_3v3_vbat>; + in-ldo7-8-supply = <&vdd_1v8_vio>; + + vdd_cpu: sd0 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + vdd_core: sd1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; + }; + + vdd_1v8_vio: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + sd3 { + regulator-name = "vddio_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + ldo0 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; + }; + + ldo1 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + avdd_3v3_periph: ldo2 { + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + vdd_usd: ldo3 { + regulator-name = "vdd_sdmmc3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; + }; + + avdd_1v8_hdmi_pll: ldo6 { + regulator-name = "avdd_osc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + vdd_1v2_mhl: ldo7 { + regulator-name = "vdd_1v2_mhl"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + ldo8 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + }; + }; + + fuel-gauge@36 { + compatible = "maxim,max17043"; + reg = <0x36>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_FALLING>; + + monitored-battery = <&battery>; + + maxim,alert-low-soc-level = <10>; + wakeup-source; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + + vs-supply = <&vdd_3v0_sen>; + }; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(I, 5) IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&vdd_3v0_sen>; + #thermal-sensor-cells = <1>; + }; + }; + + i2c-mhl { + compatible = "i2c-gpio"; + + sda-gpios = <&gpio TEGRA_GPIO(Q, 7) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio TEGRA_GPIO(Q, 6) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-gpio,delay-us = <5>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + + /* DSI bridge */ + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x1c>; + nvidia,reg-addr = <0x41>; + nvidia,reg-data = <0x02>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + /* HIFI CODEC */ + i2s@70080300 { /* i2s0 */ + status = "okay"; + }; + + /* BASEBAND */ + i2s@70080500 { /* i2s2 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + sdmmc1: mmc@78000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_vbat>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + bus-width = <8>; + + non-removable; + mmc-ddr-1_8v; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* Micro USB */ + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&avdd_3v3_periph>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gps_refclk: clock-gps { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + gps_osc: clock-gps-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; + clocks = <&gps_refclk>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-keypad { + label = "keypad::white"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; + }; + }; + + opp-table-actmon { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_5v0_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_vbat: regulator-vbat { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbat"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v0_vbus>; + }; + + vdd_3v0_sen: regulator-sen3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v0_sensor"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_3v0_proxi: regulator-proxi { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v0_proxi"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_1v8_sen: regulator-sen1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_sensor"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vcc_3v0_lcd: regulator-lcd3v { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v0_lcd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + vin-supply = <&vdd_3v3_vbat>; + }; + + iovcc_1v8_lcd: regulator-lcd1v8 { + compatible = "regulator-fixed"; + regulator-name = "iovcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vio_1v8_mhl: regulator-mhl1v8 { + compatible = "regulator-fixed"; + regulator-name = "vio_1v8_mhl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_3v0_touch: regulator-touchpwr { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v0_touch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_1v8_touch: regulator-touchvio { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_touch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(X, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vcc_1v8_gps: regulator-gps { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_gps"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(Y, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vio_1v8_front: regulator-frontvio { + compatible = "regulator-fixed"; + regulator-name = "vt_1v8_cam_vio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + sound { + nvidia,audio-routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Int Spk", "SPKL", + "Int Spk", "SPKR", + "Earpiece", "RECL", + "Earpiece", "RECR", + "INA1", "Mic Jack", + "MIC1", "MICBIAS", + "MICBIAS", "Internal Mic 1", + "MIC2", "Internal Mic 2"; + + nvidia,i2s-controller = <&tegra_i2s0>; + nvidia,audio-codec = <&max98089>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>; + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + nvidia,coupled-mic-hp-det; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * this device from getting too hot from a user's + * tactile perspective. The CPU zone is intended to + * protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 50C until temperature drops to 49.8C */ + temperature = <50000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 60C */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 75C until temperature drops to 74.8C */ + temperature = <75000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/dts/src/arm/nxp/imx/imx1-apf9328.dts b/dts/src/arm/nxp/imx/imx1-apf9328.dts index e66eef87a7..058e943552 100644 --- a/dts/src/arm/nxp/imx/imx1-apf9328.dts +++ b/dts/src/arm/nxp/imx/imx1-apf9328.dts @@ -54,7 +54,7 @@ #size-cells = <1>; }; - eth: eth@4,c00000 { + eth: ethernet@4,c00000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eth>; compatible = "davicom,dm9000"; diff --git a/dts/src/arm/nxp/imx/imx1.dtsi b/dts/src/arm/nxp/imx/imx1.dtsi index 1ac10965fd..389ecb1ebf 100644 --- a/dts/src/arm/nxp/imx/imx1.dtsi +++ b/dts/src/arm/nxp/imx/imx1.dtsi @@ -251,7 +251,7 @@ }; }; - weim: weim@220000 { + weim: memory-controller@220000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx1-weim"; diff --git a/dts/src/arm/nxp/imx/imx27.dtsi b/dts/src/arm/nxp/imx/imx27.dtsi index ec472695c7..ec3ccc8f40 100644 --- a/dts/src/arm/nxp/imx/imx27.dtsi +++ b/dts/src/arm/nxp/imx/imx27.dtsi @@ -568,7 +568,7 @@ status = "disabled"; }; - weim: weim@d8002000 { + weim: memory-controller@d8002000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx27-weim"; diff --git a/dts/src/arm/nxp/imx/imx31.dtsi b/dts/src/arm/nxp/imx/imx31.dtsi index e1ae7c175f..00006c90d9 100644 --- a/dts/src/arm/nxp/imx/imx31.dtsi +++ b/dts/src/arm/nxp/imx/imx31.dtsi @@ -352,7 +352,7 @@ status = "disabled"; }; - weim: weim@b8002000 { + weim: memory-controller@b8002000 { compatible = "fsl,imx31-weim", "fsl,imx27-weim"; reg = <0xb8002000 0x1000>; clocks = <&clks 56>; diff --git a/dts/src/arm/nxp/imx/imx35.dtsi b/dts/src/arm/nxp/imx/imx35.dtsi index 2d20e5541a..442dc15677 100644 --- a/dts/src/arm/nxp/imx/imx35.dtsi +++ b/dts/src/arm/nxp/imx/imx35.dtsi @@ -374,7 +374,7 @@ status = "disabled"; }; - weim: weim@b8002000 { + weim: memory-controller@b8002000 { #address-cells = <2>; #size-cells = <1>; clocks = <&clks 0>; diff --git a/dts/src/arm/nxp/imx/imx51.dtsi b/dts/src/arm/nxp/imx/imx51.dtsi index c96d6311df..4efce49022 100644 --- a/dts/src/arm/nxp/imx/imx51.dtsi +++ b/dts/src/arm/nxp/imx/imx51.dtsi @@ -578,7 +578,7 @@ reg = <0x83fd8000 0x1000>; }; - weim: weim@83fda000 { + weim: memory-controller@83fda000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx51-weim"; diff --git a/dts/src/arm/nxp/imx/imx53-qsb-hdmi.dtso b/dts/src/arm/nxp/imx/imx53-qsb-hdmi.dtso new file mode 100644 index 0000000000..c84e9b0525 --- /dev/null +++ b/dts/src/arm/nxp/imx/imx53-qsb-hdmi.dtso @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT overlay for MCIMXHDMICARD as used with the iMX53 QSB or QSRB boards + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + /delete-node/ panel; + + hdmi: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "1P2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_3p2v>; + }; +}; + +&display0 { + status = "okay"; +}; + +&display0 { + port@1 { + display0_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + sii9022: bridge-hdmi@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + interrupts-extended = <&gpio3 31 IRQ_TYPE_LEVEL_LOW>; + iovcc-supply = <®_3p2v>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&tve { + status = "disabled"; +}; diff --git a/dts/src/arm/nxp/imx/imx6dl-sielaff.dts b/dts/src/arm/nxp/imx/imx6dl-sielaff.dts new file mode 100644 index 0000000000..7de8d5f265 --- /dev/null +++ b/dts/src/arm/nxp/imx/imx6dl-sielaff.dts @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include <dt-bindings/clock/imx6qdl-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Sielaff i.MX6 Solo"; + compatible = "sielaff,imx6dl-board", "fsl,imx6dl"; + + chosen { + stdout-path = &uart2; + }; + + backlight: pwm-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm3 0 50000 0>; + brightness-levels = <0 0 64 88 112 136 184 232 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + power-supply = <®_backlight>; + }; + + cec { + compatible = "cec-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + hdmi-phandle = <&hdmi>; + }; + + enet_ref: clock-enet-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet-ref"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-0 { + gpios = <&gpio2 16 0>; + debounce-interval = <10>; + linux,code = <1>; + }; + + key-1 { + gpios = <&gpio3 27 0>; + debounce-interval = <10>; + linux,code = <2>; + }; + + key-2 { + gpios = <&gpio5 4 0>; + debounce-interval = <10>; + linux,code = <3>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-debug { + label = "debug-led"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + device_type = "memory"; + }; + + osc_eth_phy: clock-osc-eth-phy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc-eth-phy"; + }; + + panel { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_backlight>; + enable-active-high; + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + regulator-name = "backlight"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + /* + * Set PTP clock to external instead of internal reference, as the + * REF_CLK from the PHY is fed back into the i.MX6 and the GPR + * register needs to be set accordingly (see mach-imx6q.c). + */ + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&enet_ref>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + clocks = <&osc_eth_phy>; + clock-names = "rmii-ref"; + micrel,led-mode = <1>; + reset-assert-us = <500>; + reset-deassert-us = <100>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "key-out", "key-in", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "lan9500a-rst", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c4>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + touchscreen@55 { + compatible = "sitronix,st1633"; + reg = <0x55>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio5>; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <100000>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + usb1@1 { + compatible = "usb4b4,6570"; + reg = <1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <12000000 0>; + }; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "host"; + over-current-active-low; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_backlight: regbacklightgrp { + fsl,pins = < + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: regusbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1 + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/dts/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi b/dts/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi index 3be38a3c4b..c32ea040fe 100644 --- a/dts/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi +++ b/dts/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi @@ -117,17 +117,9 @@ #address-cells = <1>; #size-cells = <0>; - phy_port2: phy@1 { - reg = <1>; - }; - - phy_port3: phy@2 { - reg = <2>; - }; - switch@10 { compatible = "qca,qca8334"; - reg = <10>; + reg = <0x10>; reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; switch_ports: ports { @@ -149,15 +141,30 @@ eth2: port@2 { reg = <2>; label = "eth2"; + phy-mode = "internal"; phy-handle = <&phy_port2>; }; eth1: port@3 { reg = <3>; label = "eth1"; + phy-mode = "internal"; phy-handle = <&phy_port3>; }; }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port2: ethernet-phy@1 { + reg = <1>; + }; + + phy_port3: ethernet-phy@2 { + reg = <2>; + }; + }; }; }; }; diff --git a/dts/src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts b/dts/src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts new file mode 100644 index 0000000000..15d4a98ee9 --- /dev/null +++ b/dts/src/arm/nxp/imx/imx6q-apalis-eval-v1.2.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx6q-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2"; + compatible = "toradex,apalis_imx6q-eval-v1.2", "toradex,apalis_imx6q", + "fsl,imx6q"; + + reg_3v3_mmc: regulator-3v3-mmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_mmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_MMC"; + startup-delay-us = <10000>; + }; + + reg_3v3_sd: regulator-3v3-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_sd>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SD"; + startup-delay-us = <10000>; + }; + + reg_can1: regulator-can1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + regulator-name = "5V_SW_CAN1"; + startup-delay-us = <10000>; + }; + + reg_can2: regulator-can2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + regulator-name = "5V_SW_CAN2"; + startup-delay-us = <10000>; + }; + + sound-carrier { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "apalis-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&nau8822_1a>; + system-clock-frequency = <12288000>; + }; + + simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + }; +}; + +&can1 { + xceiver-supply = <®_can1>; + status = "okay"; +}; + +&can2 { + xceiver-supply = <®_can2>; + status = "okay"; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 */ +&i2c1 { + /* Audio Codec */ + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nau8822>; + #sound-dai-cells = <0>; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + + /* Temperature Sensor */ + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + size = <256>; + }; +}; + +&pcie { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +/* MMC1 */ +&usdhc1 { + bus-width = <4>; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; + vmmc-supply = <®_3v3_mmc>; + status = "okay"; +}; + +/* SD1 */ +&usdhc2 { + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; + vmmc-supply = <®_3v3_sd>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enable_3v3_mmc: enable3v3mmcgrp { + fsl,pins = < + /* MMC1_PWR_CTRL */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_enable_3v3_sd: enable3v3sdgrp { + fsl,pins = < + /* SD1_PWR_CTRL */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = < + /* CAN1_PWR_EN */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + >; + }; + + pinctrl_enable_can2_power: enablecan2powergrp { + fsl,pins = < + /* CAN2_PWR_EN */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + + pinctrl_nau8822: nau8822grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; +}; diff --git a/dts/src/arm/nxp/imx/imx6q-apalis-eval.dts b/dts/src/arm/nxp/imx/imx6q-apalis-eval.dts index 3fc079dfd6..e1077e2da5 100644 --- a/dts/src/arm/nxp/imx/imx6q-apalis-eval.dts +++ b/dts/src/arm/nxp/imx/imx6q-apalis-eval.dts @@ -7,29 +7,13 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" +#include "imx6q-apalis-eval.dtsi" / { model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board"; compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", "fsl,imx6q"; - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - reg_pcie_switch: regulator-pcie-switch { compatible = "regulator-fixed"; enable-active-high; @@ -40,14 +24,6 @@ startup-delay-us = <100000>; status = "okay"; }; - - reg_3v3_sw: regulator-3v3-sw { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "3.3V_SW"; - }; }; &can1 { @@ -62,102 +38,22 @@ /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ &i2c1 { - status = "okay"; - + /* PCIe Switch */ pcie-switch@58 { compatible = "plx,pex8605"; reg = <0x58>; }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; }; &pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; vpcie-supply = <®_pcie_switch>; status = "okay"; }; -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - &sound_spdif { status = "okay"; }; -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - /* MMC1 */ &usdhc1 { status = "okay"; diff --git a/dts/src/arm/nxp/imx/imx6q-apalis-eval.dtsi b/dts/src/arm/nxp/imx/imx6q-apalis-eval.dtsi new file mode 100644 index 0000000000..b6c45ad3f4 --- /dev/null +++ b/dts/src/arm/nxp/imx/imx6q-apalis-eval.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2024 Toradex + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" + +/ { + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SW"; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +®_usb_otg_vbus { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; diff --git a/dts/src/arm/nxp/imx/imx6qdl-hummingboard.dtsi b/dts/src/arm/nxp/imx/imx6qdl-hummingboard.dtsi index bfade71490..a955c77cd4 100644 --- a/dts/src/arm/nxp/imx/imx6qdl-hummingboard.dtsi +++ b/dts/src/arm/nxp/imx/imx6qdl-hummingboard.dtsi @@ -41,6 +41,11 @@ #include <dt-bindings/sound/fsl-imx-audmux.h> / { + aliases { + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + /* Will be filled by the bootloader */ memory@10000000 { device_type = "memory"; @@ -187,7 +192,7 @@ status = "okay"; /* Pro baseboard model */ - rtc@68 { + carrier_rtc: rtc@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; diff --git a/dts/src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi b/dts/src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi index 0883ef99cd..e6017f9bf6 100644 --- a/dts/src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi +++ b/dts/src/arm/nxp/imx/imx6qdl-hummingboard2.dtsi @@ -41,6 +41,11 @@ #include <dt-bindings/sound/fsl-imx-audmux.h> / { + aliases { + rtc0 = &pcf8523; + rtc1 = &snvs_rtc; + }; + /* Will be filled by the bootloader */ memory@10000000 { device_type = "memory"; diff --git a/dts/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi b/dts/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi index 2731faede1..d59d5d0e1d 100644 --- a/dts/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi +++ b/dts/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -13,10 +13,14 @@ aliases { can0 = &can1; can1 = &can2; + ethernet0 = &fec; + ethernet1 = &lan1; + ethernet2 = &lan2; mdio-gpio0 = &mdio; nand = &gpmi; rtc0 = &i2c_rtc; rtc1 = &snvs; + switch0 = &switch; usb0 = &usbh1; usb1 = &usbotg; }; @@ -60,7 +64,7 @@ gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, <&gpio1 22 GPIO_ACTIVE_HIGH>; - switch@0 { + switch: switch@0 { compatible = "microchip,ksz8873"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_switch>; @@ -73,13 +77,13 @@ #address-cells = <1>; #size-cells = <0>; - ports@0 { + lan1: ports@0 { reg = <0>; phy-mode = "internal"; label = "lan1"; }; - ports@1 { + lan2: ports@1 { reg = <1>; phy-mode = "internal"; label = "lan2"; diff --git a/dts/src/arm/nxp/imx/imx6qdl.dtsi b/dts/src/arm/nxp/imx/imx6qdl.dtsi index 81142c523f..8431b8a994 100644 --- a/dts/src/arm/nxp/imx/imx6qdl.dtsi +++ b/dts/src/arm/nxp/imx/imx6qdl.dtsi @@ -1158,7 +1158,7 @@ status = "disabled"; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6q-weim"; diff --git a/dts/src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts b/dts/src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts index 815119c12b..5636fb3661 100644 --- a/dts/src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts +++ b/dts/src/arm/nxp/imx/imx6sl-tolino-shine2hd.dts @@ -141,8 +141,10 @@ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&ldo1_reg>; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - x-size = <1072>; - y-size = <1448>; + touchscreen-size-x = <1072>; + touchscreen-size-y = <1448>; + touchscreen-swapped-x-y; + touchscreen-inverted-x; }; /* TODO: TPS65185 PMIC for E Ink at 0x68 */ diff --git a/dts/src/arm/nxp/imx/imx6sl.dtsi b/dts/src/arm/nxp/imx/imx6sl.dtsi index 28111efb19..6aa61235e3 100644 --- a/dts/src/arm/nxp/imx/imx6sl.dtsi +++ b/dts/src/arm/nxp/imx/imx6sl.dtsi @@ -949,7 +949,7 @@ clocks = <&clks IMX6SL_CLK_DUMMY>; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; reg = <0x021b8000 0x4000>; diff --git a/dts/src/arm/nxp/imx/imx6sx.dtsi b/dts/src/arm/nxp/imx/imx6sx.dtsi index df3a375f0a..0de359d62a 100644 --- a/dts/src/arm/nxp/imx/imx6sx.dtsi +++ b/dts/src/arm/nxp/imx/imx6sx.dtsi @@ -1107,7 +1107,7 @@ status = "disabled"; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; diff --git a/dts/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi b/dts/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi index 2ac40d6942..f10f052549 100644 --- a/dts/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/dts/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi @@ -321,7 +321,7 @@ &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xffff>; pre-charge-time = <0xfff>; status = "okay"; diff --git a/dts/src/arm/nxp/imx/imx6ul-geam.dts b/dts/src/arm/nxp/imx/imx6ul-geam.dts index 875ae699c5..2ca18f3dad 100644 --- a/dts/src/arm/nxp/imx/imx6ul-geam.dts +++ b/dts/src/arm/nxp/imx/imx6ul-geam.dts @@ -203,7 +203,7 @@ &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; &sai2 { diff --git a/dts/src/arm/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi b/dts/src/arm/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi index 18cac19aa9..af337f18a2 100644 --- a/dts/src/arm/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi +++ b/dts/src/arm/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi @@ -156,7 +156,7 @@ &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xffff>; pre-charge-time = <0xffff>; status = "okay"; diff --git a/dts/src/arm/nxp/imx/imx6ul.dtsi b/dts/src/arm/nxp/imx/imx6ul.dtsi index a27a7554c2..235aa67661 100644 --- a/dts/src/arm/nxp/imx/imx6ul.dtsi +++ b/dts/src/arm/nxp/imx/imx6ul.dtsi @@ -370,7 +370,7 @@ }; }; - tsc: tsc@2040000 { + tsc: touchscreen@2040000 { compatible = "fsl,imx6ul-tsc"; reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, @@ -538,6 +538,8 @@ fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 4>; fsl,magic-packet; + nvmem-cells = <&fec2_mac_addr>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -638,6 +640,7 @@ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; }; }; @@ -855,7 +858,6 @@ clocks = <&clks IMX6UL_CLK_USBOH3>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; @@ -897,6 +899,8 @@ fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 3>; fsl,magic-packet; + nvmem-cells = <&fec1_mac_addr>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -975,7 +979,7 @@ clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; @@ -1004,6 +1008,14 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec1_mac_addr: mac-addr@88 { + reg = <0x88 6>; + }; + + fec2_mac_addr: mac-addr@8e { + reg = <0x8e 6>; + }; }; csi: csi@21c4000 { diff --git a/dts/src/arm/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi b/dts/src/arm/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi index 040421f9c9..5e39f8dc13 100644 --- a/dts/src/arm/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi +++ b/dts/src/arm/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi @@ -14,10 +14,12 @@ */ /* - * To use usdhc1 as SD card, the WiFi node must be deleted. + * To use usdhc1 as SD card, the WiFi node must be deleted. The associated + * pwrseq node is also deleted in order to ensure that GPIO H is released. * BT is also not available, so remove BT from the UART node. */ /delete-node/ &brcmf; +/delete-node/ &usdhc1_pwrseq; /delete-node/ &bluetooth; / { diff --git a/dts/src/arm/nxp/imx/imx6ull-dhcom-som.dtsi b/dts/src/arm/nxp/imx/imx6ull-dhcom-som.dtsi index 830b5a5064..a74f5273f9 100644 --- a/dts/src/arm/nxp/imx/imx6ull-dhcom-som.dtsi +++ b/dts/src/arm/nxp/imx/imx6ull-dhcom-som.dtsi @@ -52,7 +52,7 @@ }; /* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */ - /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq { + usdhc1_pwrseq: usdhc1-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */ }; @@ -273,7 +273,7 @@ pinctrl-names = "default"; pre-charge-time = <0xfff>; touchscreen-average-samples = <32>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; /* DHCOM UART1 */ diff --git a/dts/src/arm/nxp/imx/imx6ull-dhcor-som.dtsi b/dts/src/arm/nxp/imx/imx6ull-dhcor-som.dtsi index 45315adfaa..75486e1b0c 100644 --- a/dts/src/arm/nxp/imx/imx6ull-dhcor-som.dtsi +++ b/dts/src/arm/nxp/imx/imx6ull-dhcor-som.dtsi @@ -28,10 +28,14 @@ /* * Due to the design as a solderable SOM, there are no capacitors * below the SoC, therefore higher voltages are required. + * Due to CPU lifetime consideration of the SoC manufacturer and + * the preferred area of operation in the industrial related + * environment, set the maximum frequency for each DHCOM i.MX6ULL + * to 792MHz, as with the industrial type. */ + clock-frequency = <792000000>; operating-points = < /* kHz uV */ - 900000 1275000 792000 1250000 /* Voltage increased */ 528000 1175000 396000 1025000 @@ -39,7 +43,6 @@ >; fsl,soc-operating-points = < /* KHz uV */ - 900000 1250000 792000 1250000 /* Voltage increased */ 528000 1175000 396000 1175000 diff --git a/dts/src/arm/nxp/imx/imx6ull.dtsi b/dts/src/arm/nxp/imx/imx6ull.dtsi index 2bccd45e9f..8a1776067e 100644 --- a/dts/src/arm/nxp/imx/imx6ull.dtsi +++ b/dts/src/arm/nxp/imx/imx6ull.dtsi @@ -75,7 +75,7 @@ clocks = <&clks IMX6UL_CLK_DUMMY>; }; - iomuxc_snvs: iomuxc-snvs@2290000 { + iomuxc_snvs: pinctrl@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; reg = <0x02290000 0x4000>; }; diff --git a/dts/src/arm/nxp/imx/imx7-mba7.dtsi b/dts/src/arm/nxp/imx/imx7-mba7.dtsi index 3df6dff773..52869e68f8 100644 --- a/dts/src/arm/nxp/imx/imx7-mba7.dtsi +++ b/dts/src/arm/nxp/imx/imx7-mba7.dtsi @@ -18,6 +18,8 @@ mmc0 = &usdhc3; mmc1 = &usdhc1; /delete-property/ mmc2; + rtc0 = &ds1339; + rtc1 = &snvs_rtc; }; beeper { @@ -32,11 +34,18 @@ gpio_buttons: gpio-keys { compatible = "gpio-keys"; + /* + * NOTE: These buttons are attached to a GPIO-expander. + * Enabling wakeup-source, enables wakeup on all inputs. + * If PE_GPIO[3..6] are used as inputs, they cause a + * wakeup as well. + */ button-0 { /* #SWITCH_A */ label = "S11"; linux,code = <KEY_1>; gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + wakeup-source; }; button-1 { @@ -44,6 +53,7 @@ label = "S12"; linux,code = <KEY_2>; gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + wakeup-source; }; button-2 { @@ -51,6 +61,7 @@ label = "S13"; linux,code = <KEY_3>; gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; @@ -171,6 +182,14 @@ regulator-always-on; }; + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + sound { compatible = "fsl,imx-audio-tlv320aic32x4"; model = "imx-audio-tlv320aic32x4"; @@ -198,9 +217,9 @@ &ecspi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>; cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, - <&gpio4 2 GPIO_ACTIVE_LOW>; + <&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -214,8 +233,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; phy-supply = <®_fec1_pwdn>; phy-handle = <ðphy1_0>; fsl,magic-packet; @@ -228,10 +245,15 @@ ethphy1_0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_phy>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <500>; }; }; }; @@ -290,13 +312,17 @@ lm75: temperature-sensor@49 { compatible = "national,lm75"; reg = <0x49>; + vs-supply = <®_vcc_3v3>; }; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_recovery>; + scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; tlv320aic32x4: audio-codec@18 { @@ -319,13 +345,17 @@ interrupts = <12 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + vcc-supply = <®_vcc_3v3>; }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -334,213 +364,213 @@ pinctrl-0 = <&pinctrl_hog_mba7_1>; pinctrl_ecspi1: ecspi1grp { + fsl,pins = + <MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c>, + <MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74>, + <MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74>, + <MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74>, + <MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74>, + <MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74>; + }; + + pinctrl_ecspi1_ss0: ecspi1ss0grp { fsl,pins = < - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74 - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74 - MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74 - MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74 - MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74 + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x74 >; }; pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c - MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 - MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 - MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74 - >; + fsl,pins = + <MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c>, + <MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74>, + <MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74>, + <MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74>; }; pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 + fsl,pins = + <MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02>, + <MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00>, + <MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71>, + <MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71>, + <MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71>, + <MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71>, + <MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71>, + <MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71>, + <MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79>, + <MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79>, + <MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79>, + <MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79>, + <MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79>, + <MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79>; + }; + + pinctrl_enet1_phy: enet1phygrp { + fsl,pins = /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070 + <MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070>, /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078 - >; + <MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078>; }; pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52 - >; + fsl,pins = + <MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a>, + <MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52>; }; pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52 - >; + fsl,pins = + <MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a>, + <MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52>; }; pinctrl_hog_mba7_1: hogmba71grp { - fsl,pins = < + fsl,pins = /* Limitation: WDOG2_B / WDOG2_RESET not usable */ - MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074 + <MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c>, + <MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074>, /* #BOOT_EN */ - MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010 - >; + <MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010>; }; pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078 - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078 - >; + fsl,pins = + <MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078>, + <MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078>; + }; + + pinctrl_i2c2_recovery: i2c2recoverygrp { + fsl,pins = + <MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x40000078>, + <MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x40000078>; }; pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078 - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078 - >; + fsl,pins = + <MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078>, + <MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078>; + }; + + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = + <MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x40000078>, + <MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x40000078>; }; pinctrl_pca9555: pca95550grp { - fsl,pins = < - MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 - >; + fsl,pins = + <MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78>; }; pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11 - MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c - MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c - MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c - - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14 - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14 - >; + fsl,pins = + <MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11>, + <MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c>, + <MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c>, + <MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c>, + + <MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c>, + <MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14>, + <MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14>; }; pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76 - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76 - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e - >; + fsl,pins = + <MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e>, + <MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76>, + <MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76>, + <MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e>; }; pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e - MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 - MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76 - MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e - >; + fsl,pins = + <MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e>, + <MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76>, + <MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76>, + <MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e>; }; pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e - MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76 - >; + fsl,pins = + <MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e>, + <MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76>; }; pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75 - MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75 - MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d - >; + fsl,pins = + <MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d>, + <MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75>, + <MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75>, + <MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d>; }; pinctrl_uart7: uart7grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e - MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76 - MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76 + fsl,pins = + <MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e>, + <MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76>, + <MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76>, /* Limitation: RTS is not connected */ - MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e - >; + <MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e>; }; - pinctrl_usdhc1_gpio: usdhc1grp_gpio { - fsl,pins = < + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = /* WP */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c + <MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c>, /* CD */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c + <MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c>, /* VSELECT */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 - >; + <MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59>; }; pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5e - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; + fsl,pins = + <MX7D_PAD_SD1_CMD__SD1_CMD 0x5e>, + <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>, + <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e>, + <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e>, + <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e>, + <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e>; + }; + + pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp { + fsl,pins = + <MX7D_PAD_SD1_CMD__SD1_CMD 0x5a>, + <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>, + <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a>, + <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a>, + <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a>, + <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a>; + }; + + pinctrl_usdhc1_200mhz: usdhc1_200mhzgrp { + fsl,pins = + <MX7D_PAD_SD1_CMD__SD1_CMD 0x5b>, + <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>, + <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b>, + <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b>, + <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b>, + <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b>; }; }; &iomuxc_lpsr { pinctrl_pwm1: pwm1grp { - fsl,pins = < + fsl,pins = /* LCD_CONTRAST */ - MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50 - >; + <MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50>; }; pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 - >; + fsl,pins = + <MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c>, + <MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59>; }; pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; + fsl,pins = + <MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>; }; }; @@ -560,6 +590,10 @@ status = "okay"; }; +&snvs_pwrkey { + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -605,6 +639,7 @@ }; &usbh { + disable-over-current; status = "okay"; }; @@ -630,6 +665,8 @@ vmmc-supply = <®_sd1_vmmc>; bus-width = <4>; no-1-8-v; + no-sdio; + no-mmc; status = "okay"; }; diff --git a/dts/src/arm/nxp/imx/imx7-tqma7.dtsi b/dts/src/arm/nxp/imx/imx7-tqma7.dtsi index 3fc3130f9d..028961eb71 100644 --- a/dts/src/arm/nxp/imx/imx7-tqma7.dtsi +++ b/dts/src/arm/nxp/imx/imx7-tqma7.dtsi @@ -30,8 +30,11 @@ }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; status = "okay"; @@ -109,7 +112,7 @@ }; vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -135,7 +138,7 @@ }; /* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */ - se97b: temperature-sensor-eeprom@1e { + se97b: temperature-sensor@1e { compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x1e>; }; @@ -143,15 +146,18 @@ /* ST M24C64 */ m24c64: eeprom@50 { compatible = "atmel,24c64"; + read-only; reg = <0x50>; pagesize = <32>; + vcc-supply = <&vgen4_reg>; status = "okay"; }; at24c02: eeprom@56 { - compatible = "atmel,24c02"; + compatible = "nxp,se97b", "atmel,24c02"; reg = <0x56>; pagesize = <16>; + vcc-supply = <&vgen4_reg>; status = "okay"; }; @@ -163,91 +169,89 @@ &iomuxc { pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 - >; + fsl,pins = + <MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078>, + <MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078>; + }; + + pinctrl_i2c1_recovery: i2c1recoverygrp { + fsl,pins = + <MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x40000078>, + <MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x40000078>; }; pinctrl_pmic1: pmic1grp { - fsl,pins = < - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C - >; + fsl,pins = + <MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C>; }; pinctrl_qspi: qspigrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 - MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 - >; + fsl,pins = + <MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A>, + <MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A>, + <MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A>, + <MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A>, + <MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11>, + <MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54>, + <MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54>; }; pinctrl_qspi_reset: qspi_resetgrp { - fsl,pins = < + fsl,pins = /* #QSPI_RESET */ - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52 - >; + <MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52>; }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x56 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; + fsl,pins = + <MX7D_PAD_SD3_CMD__SD3_CMD 0x59>, + <MX7D_PAD_SD3_CLK__SD3_CLK 0x56>, + <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59>, + <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59>, + <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59>, + <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59>, + <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59>, + <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59>, + <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59>, + <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59>, + <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19>; }; - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; + pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { + fsl,pins = + <MX7D_PAD_SD3_CMD__SD3_CMD 0x5a>, + <MX7D_PAD_SD3_CLK__SD3_CLK 0x51>, + <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a>, + <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a>, + <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a>, + <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a>, + <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a>, + <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a>, + <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a>, + <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a>, + <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a>; }; - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; + pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp { + fsl,pins = + <MX7D_PAD_SD3_CMD__SD3_CMD 0x5b>, + <MX7D_PAD_SD3_CLK__SD3_CLK 0x51>, + <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b>, + <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b>, + <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b>, + <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b>, + <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b>, + <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b>, + <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b>, + <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b>, + <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b>; }; }; &iomuxc_lpsr { pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; + fsl,pins = + <MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>; }; }; @@ -265,10 +269,6 @@ }; }; -&sdma { - status = "okay"; -}; - &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -278,6 +278,8 @@ assigned-clock-rates = <400000000>; bus-width = <8>; non-removable; + no-sd; + no-sdio; vmmc-supply = <&vgen4_reg>; vqmmc-supply = <&sw2_reg>; status = "okay"; diff --git a/dts/src/arm/nxp/imx/imx7d-mba7.dts b/dts/src/arm/nxp/imx/imx7d-mba7.dts index 32bf9fa9d0..0443faa3df 100644 --- a/dts/src/arm/nxp/imx/imx7d-mba7.dts +++ b/dts/src/arm/nxp/imx/imx7d-mba7.dts @@ -21,8 +21,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; phy-supply = <®_fec2_pwdn>; phy-handle = <ðphy2_0>; fsl,magic-packet; @@ -35,59 +33,85 @@ ethphy2_0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_phy>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <500>; }; }; }; +&gpio2 { + pcie-dis-hog { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie-dis"; + }; + + pcie-rst-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie-rst"; + }; +}; + &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_mba7_1>; + pinctrl-0 = <&pinctrl_hog_mba7_1>, <&pinctrl_hog_pcie>; pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02 - MX7D_PAD_SD2_WP__ENET2_MDC 0x00 - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79 + fsl,pins = + <MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02>, + <MX7D_PAD_SD2_WP__ENET2_MDC 0x00>, + <MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71>, + <MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71>, + <MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71>, + <MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71>, + <MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71>, + <MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71>, + <MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79>, + <MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79>, + <MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79>, + <MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79>, + <MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79>, + <MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79>; + }; + + pinctrl_enet2_phy: enet2phygrp { + fsl,pins = /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070 + <MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070>, /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078 - >; + <MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078>; }; - pinctrl_pcie: pciegrp { - fsl,pins = < - /* #pcie_wake */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70 + pinctrl_hog_pcie: hogpciegrp { + fsl,pins = /* #pcie_rst */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70 + <MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70>, /* #pcie_dis */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70 - >; + <MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70>; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = + /* #pcie_wake */ + <MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70>; }; }; &iomuxc_lpsr { pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 - >; + fsl,pins = + <MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c>, + <MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59>; }; }; @@ -98,16 +122,14 @@ /* probe deferral not supported */ /* pcie-bus-supply = <®_mpcie_1v5>; */ reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; - status = "okay"; + status = "disabled"; }; &usbotg2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg2>; vbus-supply = <®_usb_otg2_vbus>; - srp-disable; - hnp-disable; - adp-disable; + disable-over-current; dr_mode = "host"; status = "okay"; }; diff --git a/dts/src/arm/nxp/imx/imx7s-warp.dts b/dts/src/arm/nxp/imx/imx7s-warp.dts index ba7231b364..7bab113ca6 100644 --- a/dts/src/arm/nxp/imx/imx7s-warp.dts +++ b/dts/src/arm/nxp/imx/imx7s-warp.dts @@ -210,6 +210,7 @@ remote-endpoint = <&mipi_from_sensor>; clock-lanes = <0>; data-lanes = <1>; + link-frequencies = /bits/ 64 <330000000>; }; }; }; diff --git a/dts/src/arm/nxp/ls/ls1021a.dtsi b/dts/src/arm/nxp/ls/ls1021a.dtsi index d471cc5efa..e86998ca77 100644 --- a/dts/src/arm/nxp/ls/ls1021a.dtsi +++ b/dts/src/arm/nxp/ls/ls1021a.dtsi @@ -808,7 +808,9 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; pcie@3400000 { diff --git a/dts/src/arm/nxp/mxs/imx28-evk.dts b/dts/src/arm/nxp/mxs/imx28-evk.dts index 9ebb7371e2..330d3aff6b 100644 --- a/dts/src/arm/nxp/mxs/imx28-evk.dts +++ b/dts/src/arm/nxp/mxs/imx28-evk.dts @@ -198,7 +198,7 @@ clocks = <&saif0>; }; - at24@51 { + eeprom@51 { compatible = "atmel,24c32"; pagesize = <32>; reg = <0x51>; diff --git a/dts/src/arm/qcom/qcom-apq8026-lg-lenok.dts b/dts/src/arm/qcom/qcom-apq8026-lg-lenok.dts index 0a1fd5eb3c..a70de21bf1 100644 --- a/dts/src/arm/qcom/qcom-apq8026-lg-lenok.dts +++ b/dts/src/arm/qcom/qcom-apq8026-lg-lenok.dts @@ -7,6 +7,7 @@ #include "qcom-msm8226.dtsi" #include "pm8226.dtsi" +#include <dt-bindings/clock/qcom,mmcc-msm8974.h> /delete-node/ &adsp_region; @@ -56,6 +57,29 @@ pinctrl-names = "default"; pinctrl-0 = <&wlan_regulator_default_state>; }; + + pwm_vibrator: pwm { + compatible = "clk-pwm"; + clocks = <&mmcc CAMSS_GP0_CLK>; + + pinctrl-0 = <&vibrator_clk_default_state>; + pinctrl-names = "default"; + + #pwm-cells = <2>; + }; + + vibrator { + compatible = "pwm-vibrator"; + + pwms = <&pwm_vibrator 0 10000>; + pwm-names = "enable"; + + vcc-supply = <&pm8226_l28>; + enable-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&vibrator_en_default_state>; + pinctrl-names = "default"; + }; }; &adsp { @@ -330,6 +354,20 @@ }; }; + vibrator_clk_default_state: vibrator-clk-default-state { + pins = "gpio33"; + function = "gp0_clk"; + drive-strength = <2>; + bias-disable; + }; + + vibrator_en_default_state: vibrator-en-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wlan_hostwake_default_state: wlan-hostwake-default-state { pins = "gpio37"; function = "gpio"; diff --git a/dts/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts b/dts/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts index cffc069712..da3be658e8 100644 --- a/dts/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts +++ b/dts/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts @@ -5,142 +5,13 @@ /dts-v1/; -#include <dt-bindings/input/input.h> -#include "qcom-msm8226.dtsi" -#include "pm8226.dtsi" - -/delete-node/ &adsp_region; -/delete-node/ &smem_region; +#include "qcom-msm8226-samsung-matisse-common.dtsi" / { model = "Samsung Galaxy Tab 4 10.1"; compatible = "samsung,matisse-wifi", "qcom,apq8026"; chassis-type = "tablet"; - aliases { - mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_2; /* SDC2 SD card slot */ - display0 = &framebuffer0; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - stdout-path = "display0"; - - framebuffer0: framebuffer@3200000 { - compatible = "simple-framebuffer"; - reg = <0x03200000 0x800000>; - width = <1280>; - height = <800>; - stride = <(1280 * 3)>; - format = "r8g8b8"; - }; - }; - - gpio-hall-sensor { - compatible = "gpio-keys"; - - event-hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&tlmm 110 GPIO_ACTIVE_LOW>; - linux,input-type = <EV_SW>; - linux,code = <SW_LID>; - debounce-interval = <15>; - linux,can-disable; - wakeup-source; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - key-home { - label = "Home"; - gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; - linux,code = <KEY_HOMEPAGE>; - debounce-interval = <15>; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <15>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <15>; - }; - }; - - i2c-backlight { - compatible = "i2c-gpio"; - sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - - pinctrl-0 = <&backlight_i2c_default_state>; - pinctrl-names = "default"; - - i2c-gpio,delay-us = <4>; - - #address-cells = <1>; - #size-cells = <0>; - - backlight@2c { - compatible = "ti,lp8556"; - reg = <0x2c>; - - dev-ctrl = /bits/ 8 <0x80>; - init-brt = /bits/ 8 <0x3f>; - - pwms = <&backlight_pwm 0 100000>; - pwm-names = "lp8556"; - - rom-a0h { - rom-addr = /bits/ 8 <0xa0>; - rom-val = /bits/ 8 <0x44>; - }; - - rom-a1h { - rom-addr = /bits/ 8 <0xa1>; - rom-val = /bits/ 8 <0x6c>; - }; - - rom-a5h { - rom-addr = /bits/ 8 <0xa5>; - rom-val = /bits/ 8 <0x24>; - }; - }; - }; - - backlight_pwm: pwm { - compatible = "clk-pwm"; - #pwm-cells = <2>; - clocks = <&mmcc CAMSS_GP0_CLK>; - pinctrl-0 = <&backlight_pwm_default_state>; - pinctrl-names = "default"; - }; - - reg_tsp_1p8v: regulator-tsp-1p8v { - compatible = "regulator-fixed"; - regulator-name = "tsp_1p8v"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&tsp_en_default_state>; - }; - reg_tsp_3p3v: regulator-tsp-3p3v { compatible = "regulator-fixed"; regulator-name = "tsp_3p3v"; @@ -153,74 +24,6 @@ pinctrl-names = "default"; pinctrl-0 = <&tsp_en1_default_state>; }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer@3200000 { - reg = <0x03200000 0x800000>; - no-map; - }; - - mpss@8400000 { - reg = <0x08400000 0x1f00000>; - no-map; - }; - - mba@a300000 { - reg = <0x0a300000 0x100000>; - no-map; - }; - - reserved@cb00000 { - reg = <0x0cb00000 0x700000>; - no-map; - }; - - wcnss@d200000 { - reg = <0x0d200000 0x700000>; - no-map; - }; - - adsp_region: adsp@d900000 { - reg = <0x0d900000 0x1800000>; - no-map; - }; - - venus@f100000 { - reg = <0x0f100000 0x500000>; - no-map; - }; - - smem_region: smem@fa00000 { - reg = <0x0fa00000 0x100000>; - no-map; - }; - - reserved@fb00000 { - reg = <0x0fb00000 0x260000>; - no-map; - }; - - rfsa@fd60000 { - reg = <0x0fd60000 0x20000>; - no-map; - }; - - rmtfs@fd80000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0fd80000 0x180000>; - no-map; - - qcom,client-id = <1>; - }; - }; -}; - -&adsp { - status = "okay"; }; &blsp1_i2c2 { @@ -243,21 +46,6 @@ }; }; -&blsp1_i2c4 { - status = "okay"; - - muic: usb-switch@25 { - compatible = "siliconmitus,sm5502-muic"; - reg = <0x25>; - - interrupt-parent = <&tlmm>; - interrupts = <67 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&muic_int_default_state>; - }; -}; - &blsp1_i2c5 { status = "okay"; @@ -268,6 +56,13 @@ interrupt-parent = <&tlmm>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + linux,keycodes = <KEY_RESERVED>, + <KEY_RESERVED>, + <KEY_RESERVED>, + <KEY_RESERVED>, + <KEY_APPSELECT>, + <KEY_BACK>; + pinctrl-names = "default"; pinctrl-0 = <&tsp_int_rst_default_state>; @@ -278,242 +73,19 @@ }; }; -&rpm_requests { - regulators { - compatible = "qcom,rpm-pm8226-regulators"; - - pm8226_s3: s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - pm8226_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_s5: s5 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - - pm8226_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8226_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l3: l3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1337500>; - regulator-always-on; - }; - - pm8226_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l5: l5 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8226_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pm8226_l7: l7 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1850000>; - }; - - pm8226_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pm8226_l9: l9 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8226_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l14: l14 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <2750000>; - }; - - pm8226_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8226_l16: l16 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3350000>; - }; - - pm8226_l17: l17 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - - regulator-system-load = <200000>; - regulator-allow-set-load; - regulator-always-on; - }; - - pm8226_l18: l18 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l19: l19 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3000000>; - }; - - pm8226_l20: l20 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pm8226_l21: l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_l22: l22 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - - pm8226_l23: l23 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8226_l24: l24 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1350000>; - }; - - pm8226_l25: l25 { - regulator-min-microvolt = <1775000>; - regulator-max-microvolt = <2125000>; - }; - - pm8226_l26: l26 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1300000>; - }; - - pm8226_l27: l27 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8226_l28: l28 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8226_lvs1: lvs1 {}; - }; -}; - -&sdhc_1 { - vmmc-supply = <&pm8226_l17>; - vqmmc-supply = <&pm8226_l6>; - - bus-width = <8>; - non-removable; - - status = "okay"; +&pm8226_l3 { + regulator-max-microvolt = <1337500>; }; -&sdhc_2 { - vmmc-supply = <&pm8226_l18>; - vqmmc-supply = <&pm8226_l21>; - - bus-width = <4>; - cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; - - status = "okay"; +&pm8226_s4 { + regulator-max-microvolt = <1800000>; }; &tlmm { - accel_int_default_state: accel-int-default-state { - pins = "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - backlight_i2c_default_state: backlight-i2c-default-state { - pins = "gpio20", "gpio21"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - backlight_pwm_default_state: backlight-pwm-default-state { - pins = "gpio33"; - function = "gp0_clk"; - }; - - muic_int_default_state: muic-int-default-state { - pins = "gpio67"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - tsp_en_default_state: tsp-en-default-state { - pins = "gpio31"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - tsp_en1_default_state: tsp-en1-default-state { pins = "gpio73"; function = "gpio"; drive-strength = <2>; bias-disable; }; - - tsp_int_rst_default_state: tsp-int-rst-default-state { - pins = "gpio17"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; -}; - -&usb { - extcon = <&muic>, <&muic>; - status = "okay"; -}; - -&usb_hs_phy { - extcon = <&muic>; - v1p8-supply = <&pm8226_l10>; - v3p3-supply = <&pm8226_l20>; }; diff --git a/dts/src/arm/qcom/qcom-apq8064.dtsi b/dts/src/arm/qcom/qcom-apq8064.dtsi index 3faf57035d..9a5ba97877 100644 --- a/dts/src/arm/qcom/qcom-apq8064.dtsi +++ b/dts/src/arm/qcom/qcom-apq8064.dtsi @@ -190,7 +190,7 @@ cpu-pmu { compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; + interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; clocks { @@ -244,7 +244,7 @@ modem_smsm: modem@1 { reg = <1>; - interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; @@ -252,7 +252,7 @@ q6_smsm: q6@2 { reg = <2>; - interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; @@ -260,7 +260,7 @@ wcnss_smsm: wcnss@3 { reg = <3>; - interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; @@ -268,7 +268,7 @@ dsps_smsm: dsps@4 { reg = <4>; - interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; @@ -299,7 +299,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&ps_hold>; @@ -321,9 +321,9 @@ timer@200a000 { compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; reg = <0x0200a000 0x100>; clock-frequency = <27000000>; cpu-offset = <0x80000>; @@ -365,28 +365,44 @@ #clock-cells = <0>; }; - saw0: power-controller@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; - saw1: power-controller@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; - saw2: power-controller@20a9000 { + saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw2_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; - saw3: power-controller@20b9000 { + saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw3_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; sps_sic_non_secure: sps-sic-non-secure@12100000 { @@ -411,7 +427,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12450000 0x100>, <0x12400000 0x03>; - interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -423,7 +439,7 @@ pinctrl-1 = <&i2c1_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x12460000 0x1000>; - interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -452,7 +468,7 @@ pinctrl-0 = <&i2c2_pins>; pinctrl-1 = <&i2c2_pins_sleep>; pinctrl-names = "default", "sleep"; - interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; @@ -539,7 +555,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x1a240000 0x100>, <0x1a200000 0x03>; - interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -548,7 +564,7 @@ gsbi5_spi: spi@1a280000 { compatible = "qcom,spi-qup-v1.1.1"; reg = <0x1a280000 0x1000>; - interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&spi5_default>; pinctrl-1 = <&spi5_sleep>; pinctrl-names = "default", "sleep"; @@ -575,7 +591,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16540000 0x100>, <0x16500000 0x03>; - interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -611,7 +627,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16640000 0x1000>, <0x16600000 0x1000>; - interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -908,7 +924,7 @@ sdcc3bam: dma-controller@12182000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC3_H_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; @@ -936,7 +952,7 @@ sdcc4bam: dma-controller@121c2000 { compatible = "qcom,bam-v1.3.0"; reg = <0x121c2000 0x8000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC4_H_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; @@ -965,7 +981,7 @@ sdcc1bam: dma-controller@12402000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC1_H_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; diff --git a/dts/src/arm/qcom/qcom-apq8084.dtsi b/dts/src/arm/qcom/qcom-apq8084.dtsi index 2b1f9d0fb5..8204e64d9a 100644 --- a/dts/src/arm/qcom/qcom-apq8084.dtsi +++ b/dts/src/arm/qcom/qcom-apq8084.dtsi @@ -629,30 +629,29 @@ }; }; - saw0: power-controller@f9089000 { + saw0: power-manager@f9089000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; }; - saw1: power-controller@f9099000 { + saw1: power-manager@f9099000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; }; - saw2: power-controller@f90a9000 { + saw2: power-manager@f90a9000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; }; - saw3: power-controller@f90b9000 { + saw3: power-manager@f90b9000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; }; - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; + saw_l2: power-manager@f9012000 { + compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { diff --git a/dts/src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi b/dts/src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi index 0505270cf5..f7ac8f9d0b 100644 --- a/dts/src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi +++ b/dts/src/arm/qcom/qcom-ipq4019-ap.dk01.1.dtsi @@ -27,87 +27,83 @@ chosen { stdout-path = "serial0:115200n8"; }; +}; - soc { - rng@22000 { - status = "okay"; - }; - - pinctrl@1000000 { - serial_pins: serial_pinmux { - mux { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; - }; - - spi_0_pins: spi_0_pinmux { - pinmux { - function = "blsp_spi0"; - pins = "gpio55", "gpio56", "gpio57"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio54"; - }; - pinconf { - pins = "gpio55", "gpio56", "gpio57"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio54"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - }; +&prng { + status = "okay"; +}; - blsp_dma: dma-controller@7884000 { - status = "okay"; +&tlmm { + serial_pins: serial_pinmux { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; }; + }; - spi@78b5000 { - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "okay"; - cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; - - mx25l25635e@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "mx25l25635e"; - spi-max-frequency = <24000000>; - }; + spi_0_pins: spi_0_pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; }; - - serial@78af000 { - pinctrl-0 = <&serial_pins>; - pinctrl-names = "default"; - status = "okay"; + pinmux_cs { + function = "gpio"; + pins = "gpio54"; }; - - cryptobam: dma-controller@8e04000 { - status = "okay"; + pinconf { + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <12>; + bias-disable; }; - - crypto@8e3a000 { - status = "okay"; + pinconf_cs { + pins = "gpio54"; + drive-strength = <2>; + bias-disable; + output-high; }; + }; +}; - watchdog@b017000 { - status = "okay"; - }; +&blsp_dma { + status = "okay"; +}; - wifi@a000000 { - status = "okay"; - }; +&blsp1_spi1 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; - wifi@a800000 { - status = "okay"; - }; + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <24000000>; }; }; + +&blsp1_uart1 { + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&crypto { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi0 { + status = "okay"; +}; + +&wifi1 { + status = "okay"; +}; diff --git a/dts/src/arm/qcom/qcom-ipq4019.dtsi b/dts/src/arm/qcom/qcom-ipq4019.dtsi index f989bd741c..681cb3fc80 100644 --- a/dts/src/arm/qcom/qcom-ipq4019.dtsi +++ b/dts/src/arm/qcom/qcom-ipq4019.dtsi @@ -162,10 +162,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <48000000>; always-on; }; @@ -350,34 +350,29 @@ reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; }; - saw0: regulator@b089000 { - compatible = "qcom,saw2"; + saw0: power-manager@b089000 { + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; - regulator; }; - saw1: regulator@b099000 { - compatible = "qcom,saw2"; + saw1: power-manager@b099000 { + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; }; - saw2: regulator@b0a9000 { - compatible = "qcom,saw2"; + saw2: power-manager@b0a9000 { + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; - saw3: regulator@b0b9000 { - compatible = "qcom,saw2"; + saw3: power-manager@b0b9000 { + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; - saw_l2: regulator@b012000 { - compatible = "qcom,saw2"; + saw_l2: power-manager@b012000 { + compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2"; reg = <0xb012000 0x1000>; - regulator; }; blsp1_uart1: serial@78af000 { @@ -684,7 +679,7 @@ clocks = <&gcc GCC_USB2_MASTER_CLK>, <&gcc GCC_USB2_SLEEP_CLK>, <&gcc GCC_USB2_MOCK_UTMI_CLK>; - clock-names = "master", "sleep", "mock_utmi"; + clock-names = "core", "sleep", "mock_utmi"; ranges; status = "disabled"; diff --git a/dts/src/arm/qcom/qcom-ipq8064.dtsi b/dts/src/arm/qcom/qcom-ipq8064.dtsi index 6a7f4dd0f7..2eb6758b6a 100644 --- a/dts/src/arm/qcom/qcom-ipq8064.dtsi +++ b/dts/src/arm/qcom/qcom-ipq8064.dtsi @@ -586,10 +586,9 @@ #clock-cells = <0>; }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; + saw0: power-manager@2089000 { + compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; }; acc1: clock-controller@2098000 { @@ -601,10 +600,9 @@ #clock-cells = <0>; }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; + saw1: power-manager@2099000 { + compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; }; nss_common: syscon@3000000 { @@ -623,7 +621,6 @@ ranges; resets = <&gcc USB30_0_MASTER_RESET>; - reset-names = "master"; status = "disabled"; @@ -669,7 +666,6 @@ ranges; resets = <&gcc USB30_1_MASTER_RESET>; - reset-names = "master"; status = "disabled"; diff --git a/dts/src/arm/qcom/qcom-msm8226-samsung-matisse-common.dtsi b/dts/src/arm/qcom/qcom-msm8226-samsung-matisse-common.dtsi new file mode 100644 index 0000000000..a15a44fc01 --- /dev/null +++ b/dts/src/arm/qcom/qcom-msm8226-samsung-matisse-common.dtsi @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com> + */ + +#include <dt-bindings/input/input.h> +#include "qcom-msm8226.dtsi" +#include "pm8226.dtsi" + +/delete-node/ &adsp_region; +/delete-node/ &smem_region; + +/ { + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + display0 = &framebuffer0; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + stdout-path = "display0"; + + framebuffer0: framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + width = <1280>; + height = <800>; + stride = <(1280 * 3)>; + format = "r8g8b8"; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 110 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-home { + label = "Home"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + debounce-interval = <15>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + i2c-backlight { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&backlight_i2c_default_state>; + pinctrl-names = "default"; + + i2c-gpio,delay-us = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0x3f>; + + pwms = <&backlight_pwm 0 100000>; + pwm-names = "lp8556"; + + rom-a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0x44>; + }; + + rom-a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x6c>; + }; + + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x24>; + }; + }; + }; + + backlight_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + clocks = <&mmcc CAMSS_GP0_CLK>; + pinctrl-0 = <&backlight_pwm_default_state>; + pinctrl-names = "default"; + }; + + reg_tsp_1p8v: regulator-tsp-1p8v { + compatible = "regulator-fixed"; + regulator-name = "tsp_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en_default_state>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@3200000 { + reg = <0x03200000 0x800000>; + no-map; + }; + + mpss@8400000 { + reg = <0x08400000 0x1f00000>; + no-map; + }; + + mba@a300000 { + reg = <0x0a300000 0x100000>; + no-map; + }; + + reserved@cb00000 { + reg = <0x0cb00000 0x700000>; + no-map; + }; + + wcnss@d200000 { + reg = <0x0d200000 0x700000>; + no-map; + }; + + adsp_region: adsp@d900000 { + reg = <0x0d900000 0x1800000>; + no-map; + }; + + venus@f100000 { + reg = <0x0f100000 0x500000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + + reserved@fb00000 { + reg = <0x0fb00000 0x260000>; + no-map; + }; + + rfsa@fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; +}; + +&adsp { + status = "okay"; +}; + +&blsp1_i2c4 { + status = "okay"; + + muic: usb-switch@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + + interrupt-parent = <&tlmm>; + interrupts = <67 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_int_default_state>; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8226_l18>; + vqmmc-supply = <&pm8226_l21>; + + bus-width = <4>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + accel_int_default_state: accel-int-default-state { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_i2c_default_state: backlight-i2c-default-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_pwm_default_state: backlight-pwm-default-state { + pins = "gpio33"; + function = "gp0_clk"; + }; + + muic_int_default_state: muic-int-default-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en_default_state: tsp-en-default-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default_state: tsp-int-rst-default-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; diff --git a/dts/src/arm/qcom/qcom-msm8226.dtsi b/dts/src/arm/qcom/qcom-msm8226.dtsi index b492c95e5d..270973e856 100644 --- a/dts/src/arm/qcom/qcom-msm8226.dtsi +++ b/dts/src/arm/qcom/qcom-msm8226.dtsi @@ -20,11 +20,6 @@ chosen { }; - memory@0 { - device_type = "memory"; - reg = <0x0 0x0>; - }; - clocks { xo_board: xo_board { compatible = "fixed-clock"; @@ -39,6 +34,57 @@ }; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + CPU1: cpu@1 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + CPU2: cpu@2 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + }; + + CPU3: cpu@3 { + compatible = "arm,cortex-a7"; + enable-method = "qcom,msm8226-smp"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + firmware { scm { compatible = "qcom,scm-msm8226", "qcom,scm"; @@ -47,6 +93,11 @@ }; }; + memory@0 { + device_type = "memory"; + reg = <0x0 0x0>; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | @@ -185,6 +236,117 @@ reg = <0xf9011000 0x1000>; }; + saw_l2: power-manager@f9012000 { + compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2"; + reg = <0xf9012000 0x1000>; + }; + + watchdog@f9017000 { + compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt"; + reg = <0xf9017000 0x1000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; + clocks = <&sleep_clk>; + }; + + timer@f9020000 { + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@f9021000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + acc0: power-manager@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; + }; + + saw0: power-manager@f9089000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9089000 0x1000>; + }; + + acc1: power-manager@f9098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; + }; + + saw1: power-manager@f9099000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf9099000 0x1000>; + }; + + acc2: power-manager@f90a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; + }; + + saw2: power-manager@f90a9000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90a9000 0x1000>; + }; + + acc3: power-manager@f90b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; + }; + + saw3: power-manager@f90b9000 { + compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2"; + reg = <0xf90b9000 0x1000>; + }; + sdhc_1: mmc@f9824900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; @@ -201,35 +363,35 @@ status = "disabled"; }; - sdhc_2: mmc@f98a4900 { + sdhc_3: mmc@f9864900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names = "hc", "core"; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-names = "default"; - pinctrl-0 = <&sdhc2_default_state>; + pinctrl-0 = <&sdhc3_default_state>; status = "disabled"; }; - sdhc_3: mmc@f9864900 { + sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc", "core"; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC3_AHB_CLK>, - <&gcc GCC_SDCC3_APPS_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-names = "default"; - pinctrl-0 = <&sdhc3_default_state>; + pinctrl-0 = <&sdhc2_default_state>; status = "disabled"; }; @@ -272,7 +434,6 @@ }; blsp1_i2c1: i2c@f9923000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9923000 0x1000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; @@ -282,10 +443,10 @@ pinctrl-0 = <&blsp1_i2c1_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c2: i2c@f9924000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9924000 0x1000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; @@ -295,10 +456,10 @@ pinctrl-0 = <&blsp1_i2c2_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c3: i2c@f9925000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9925000 0x1000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; @@ -308,10 +469,10 @@ pinctrl-0 = <&blsp1_i2c3_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c4: i2c@f9926000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9926000 0x1000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; @@ -321,10 +482,10 @@ pinctrl-0 = <&blsp1_i2c4_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c5: i2c@f9927000 { - status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9927000 0x1000>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; @@ -334,6 +495,7 @@ pinctrl-0 = <&blsp1_i2c5_pins>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; blsp1_i2c6: i2c@f9928000 { @@ -351,33 +513,6 @@ status = "disabled"; }; - cci: cci@fda0c000 { - compatible = "qcom,msm8226-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfda0c000 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_CCI_CCI_AHB_CLK>, - <&mmcc CAMSS_CCI_CCI_CLK>; - clock-names = "camss_top_ahb", - "cci_ahb", - "cci"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cci_default>; - pinctrl-1 = <&cci_sleep>; - - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - usb: usb@f9a55000 { compatible = "qcom,ci-hdrc"; reg = <0xf9a55000 0x200>, @@ -417,6 +552,18 @@ }; }; + rng@f9bff000 { + compatible = "qcom,prng"; + reg = <0xf9bff000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + sram@fc190000 { + compatible = "qcom,msm8226-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + gcc: clock-controller@fc400000 { compatible = "qcom,gcc-msm8226"; reg = <0xfc400000 0x4000>; @@ -430,146 +577,28 @@ "sleep_clk"; }; - mmcc: clock-controller@fd8c0000 { - compatible = "qcom,mmcc-msm8226"; - reg = <0xfd8c0000 0x6000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GCC_MMSS_GPLL0_CLK_SRC>, - <&gcc GPLL0_VOTE>, - <&gcc GPLL1_VOTE>, - <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>; - clock-names = "xo", - "mmss_gpll0_vote", - "gpll0_vote", - "gpll1_vote", - "gfx3d_clk_src", - "dsi0pll", - "dsi0pllbyte"; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,msm8226-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 117>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - - blsp1_i2c1_pins: blsp1-i2c1-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c2_pins: blsp1-i2c2-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c3_pins: blsp1-i2c3-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c4_pins: blsp1-i2c4-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c5_pins: blsp1-i2c5-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_i2c6_pins: blsp1-i2c6-state { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - drive-strength = <2>; - bias-disable; - }; - - cci_default: cci-default-state { - pins = "gpio29", "gpio30"; - function = "cci_i2c0"; - - drive-strength = <2>; - bias-disable; - }; + rpm_msg_ram: sram@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; - cci_sleep: cci-sleep-state { - pins = "gpio29", "gpio30"; - function = "gpio"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfc428000 0x4000>; - drive-strength = <2>; - bias-disable; + apss_master_stats: sram@150 { + reg = <0x150 0x14>; }; - sdhc1_default_state: sdhc1-default-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; + mpss_master_stats: sram@b50 { + reg = <0xb50 0x14>; }; - sdhc2_default_state: sdhc2-default-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <10>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <10>; - bias-pull-up; - }; + lpss_master_stats: sram@1550 { + reg = <0x1550 0x14>; }; - sdhc3_default_state: sdhc3-default-state { - clk-pins { - pins = "gpio44"; - function = "sdc3"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio43"; - function = "sdc3"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio39", "gpio40", "gpio41", "gpio42"; - function = "sdc3"; - drive-strength = <8>; - bias-pull-up; - }; + pronto_master_stats: sram@1f50 { + reg = <0x1f50 0x14>; }; }; @@ -714,170 +743,153 @@ #interrupt-cells = <4>; }; - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; + tcsr_mutex: hwlock@fd484000 { + compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; + reg = <0xfd484000 0x1000>; + #hwlock-cells = <1>; }; - timer@f9020000 { - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - frame@f9021000 { - frame-number = <0>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8226-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 117>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - frame@f9023000 { - frame-number = <1>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xf9023000 0x1000>; - status = "disabled"; + blsp1_i2c1_pins: blsp1-i2c1-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; }; - frame@f9024000 { - frame-number = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xf9024000 0x1000>; - status = "disabled"; + blsp1_i2c2_pins: blsp1-i2c2-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; }; - frame@f9025000 { - frame-number = <3>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xf9025000 0x1000>; - status = "disabled"; + blsp1_i2c3_pins: blsp1-i2c3-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; }; - frame@f9026000 { - frame-number = <4>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xf9026000 0x1000>; - status = "disabled"; + blsp1_i2c4_pins: blsp1-i2c4-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; }; - frame@f9027000 { - frame-number = <5>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xf9027000 0x1000>; - status = "disabled"; + blsp1_i2c5_pins: blsp1-i2c5-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; }; - frame@f9028000 { - frame-number = <6>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xf9028000 0x1000>; - status = "disabled"; + blsp1_i2c6_pins: blsp1-i2c6-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; }; - }; - - sram@fc190000 { - compatible = "qcom,msm8226-rpm-stats"; - reg = <0xfc190000 0x10000>; - }; - - rpm_msg_ram: sram@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfc428000 0x4000>; - - apss_master_stats: sram@150 { - reg = <0x150 0x14>; - }; + cci_default: cci-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c0"; - mpss_master_stats: sram@b50 { - reg = <0xb50 0x14>; + drive-strength = <2>; + bias-disable; }; - lpss_master_stats: sram@1550 { - reg = <0x1550 0x14>; - }; + cci_sleep: cci-sleep-state { + pins = "gpio29", "gpio30"; + function = "gpio"; - pronto_master_stats: sram@1f50 { - reg = <0x1f50 0x14>; + drive-strength = <2>; + bias-disable; }; - }; - - tcsr_mutex: hwlock@fd484000 { - compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; - reg = <0xfd484000 0x1000>; - #hwlock-cells = <1>; - }; - adsp: remoteproc@fe200000 { - compatible = "qcom,msm8226-adsp-pil"; - reg = <0xfe200000 0x100>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - power-domains = <&rpmpd MSM8226_VDDCX>; - power-domain-names = "cx"; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; + sdhc1_default_state: sdhc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <10>; + bias-disable; + }; - smd-edge { - interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; - qcom,ipc = <&apcs 8 8>; - qcom,smd-edge = <1>; + sdhc2_default_state: sdhc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; - label = "lpass"; + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; }; - }; - sram@fdd00000 { - compatible = "qcom,msm8226-ocmem"; - reg = <0xfdd00000 0x2000>, - <0xfec00000 0x20000>; - reg-names = "ctrl", "mem"; - ranges = <0 0xfec00000 0x20000>; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; - clock-names = "core"; + sdhc3_default_state: sdhc3-default-state { + clk-pins { + pins = "gpio44"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; - #address-cells = <1>; - #size-cells = <1>; + cmd-pins { + pins = "gpio43"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; - gmu_sram: gmu-sram@0 { - reg = <0x0 0x20000>; + data-pins { + pins = "gpio39", "gpio40", "gpio41", "gpio42"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; }; }; - sram@fe805000 { - compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; - reg = <0xfe805000 0x1000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x65c>; + mmcc: clock-controller@fd8c0000 { + compatible = "qcom,mmcc-msm8226"; + reg = <0xfd8c0000 0x6000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; - mode-bootloader = <0x77665500>; - mode-normal = <0x77665501>; - mode-recovery = <0x77665502>; - }; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_MMSS_GPLL0_CLK_SRC>, + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", + "gpll1_vote", + "gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte"; }; mdss: display-subsystem@fd900000 { @@ -1007,6 +1019,33 @@ }; }; + cci: cci@fda0c000 { + compatible = "qcom,msm8226-cci"; + reg = <0xfda0c000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CCI_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci_default>; + pinctrl-1 = <&cci_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: adreno@fdb00000 { compatible = "qcom,adreno-305.18", "qcom,adreno"; reg = <0xfdb00000 0x10000>; @@ -1046,6 +1085,71 @@ }; }; }; + + sram@fdd00000 { + compatible = "qcom,msm8226-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x20000>; + reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x20000>; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; + clock-names = "core"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x20000>; + }; + }; + + adsp: remoteproc@fe200000 { + compatible = "qcom,msm8226-adsp-pil"; + reg = <0xfe200000 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8226_VDDCX>; + power-domain-names = "cx"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + smd-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 8>; + qcom,smd-edge = <1>; + + label = "lpass"; + }; + }; + + sram@fe805000 { + compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; + reg = <0xfe805000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + + mode-bootloader = <0x77665500>; + mode-normal = <0x77665501>; + mode-recovery = <0x77665502>; + }; + }; }; thermal-zones { diff --git a/dts/src/arm/qcom/qcom-msm8660.dtsi b/dts/src/arm/qcom/qcom-msm8660.dtsi index a7c245b9c8..455ba4bf1b 100644 --- a/dts/src/arm/qcom/qcom-msm8660.dtsi +++ b/dts/src/arm/qcom/qcom-msm8660.dtsi @@ -47,7 +47,7 @@ cpu-pmu { compatible = "qcom,scorpion-mp-pmu"; - interrupts = <1 9 0x304>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; clocks { @@ -89,12 +89,11 @@ timer@2000000 { compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; + interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; reg = <0x02000000 0x100>; - clock-frequency = <27000000>, - <32768>; + clock-frequency = <27000000>; cpu-offset = <0x40000>; }; @@ -105,7 +104,7 @@ gpio-controller; gpio-ranges = <&tlmm 0 0 173>; #gpio-cells = <2>; - interrupts = <0 16 0x4>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; @@ -283,7 +282,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x19c40000 0x1000>, <0x19c00000 0x1000>; - interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -292,7 +291,7 @@ gsbi12_i2c: i2c@19c80000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x19c80000 0x1000>; - interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; clock-names = "core", "iface"; #address-cells = <1>; diff --git a/dts/src/arm/qcom/qcom-msm8926-htc-memul.dts b/dts/src/arm/qcom/qcom-msm8926-htc-memul.dts index ed328b2433..3037344eb2 100644 --- a/dts/src/arm/qcom/qcom-msm8926-htc-memul.dts +++ b/dts/src/arm/qcom/qcom-msm8926-htc-memul.dts @@ -107,7 +107,20 @@ }; unknown@fb00000 { - reg = <0x0fb00000 0x1b00000>; + reg = <0x0fb00000 0x280000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + + unknown@ff00000 { + reg = <0x0ff00000 0x1700000>; no-map; }; }; diff --git a/dts/src/arm/qcom/qcom-msm8926-samsung-matisselte.dts b/dts/src/arm/qcom/qcom-msm8926-samsung-matisselte.dts new file mode 100644 index 0000000000..d0e1bc39f8 --- /dev/null +++ b/dts/src/arm/qcom/qcom-msm8926-samsung-matisselte.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com> + * Copyright (c) 2023, Stefan Hansson <newbyte@postmarketos.org> + */ + +/dts-v1/; + +#include "qcom-msm8226-samsung-matisse-common.dtsi" + +/ { + model = "Samsung Galaxy Tab 4 10.1 LTE"; + compatible = "samsung,matisselte", "qcom,msm8926", "qcom,msm8226"; + chassis-type = "tablet"; + + reg_tsp_3p3v: regulator-tsp-3p3v { + compatible = "regulator-fixed"; + regulator-name = "tsp_3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en1_default_state>; + }; +}; + +&tlmm { + tsp_en1_default_state: tsp-en1-default-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/dts/src/arm/qcom/qcom-msm8960-pins.dtsi b/dts/src/arm/qcom/qcom-msm8960-pins.dtsi new file mode 100644 index 0000000000..4fa9827712 --- /dev/null +++ b/dts/src/arm/qcom/qcom-msm8960-pins.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only + +&msmgpio { + i2c3_default_state: i2c3-default-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c3_sleep_state: i2c3-sleep-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; +}; diff --git a/dts/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts b/dts/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts index 1a5116336f..af6cc6393d 100644 --- a/dts/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/dts/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts @@ -4,6 +4,9 @@ #include "qcom-msm8960.dtsi" #include "pm8921.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/input/gpio-keys.h> / { model = "Samsung Galaxy Express SGH-I437"; @@ -19,6 +22,36 @@ chosen { stdout-path = "serial0:115200n8"; }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-home { + label = "Home"; + gpios = <&msmgpio 40 GPIO_ACTIVE_LOW>; + debounce-interval = <5>; + linux,code = <KEY_HOMEPAGE>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&msmgpio 50 GPIO_ACTIVE_LOW>; + debounce-interval = <5>; + linux,code = <KEY_VOLUMEUP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&msmgpio 81 GPIO_ACTIVE_LOW>; + debounce-interval = <5>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; }; &gsbi5 { @@ -52,6 +85,27 @@ status = "okay"; }; +&gsbi3 { + qcom,mode = <GSBI_PROT_I2C>; + status = "okay"; +}; + +&gsbi3_i2c { + status = "okay"; + + // Atmel mXT224S touchscreen + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + vdda-supply = <&pm8921_lvs6>; + vdd-supply = <&pm8921_l17>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen>; + }; +}; + &msmgpio { spi1_default: spi1-default-state { mosi-pins { @@ -83,6 +137,21 @@ bias-disable; }; }; + + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio40", "gpio50", "gpio81"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + touchscreen: touchscreen-int-state { + pins = "gpio11"; + function = "gpio"; + output-enable; + bias-disable; + drive-strength = <2>; + }; }; &pm8921 { @@ -245,7 +314,7 @@ }; pm8921_l17: l17 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; bias-pull-down; }; diff --git a/dts/src/arm/qcom/qcom-msm8960.dtsi b/dts/src/arm/qcom/qcom-msm8960.dtsi index f420740e06..922f9e4946 100644 --- a/dts/src/arm/qcom/qcom-msm8960.dtsi +++ b/dts/src/arm/qcom/qcom-msm8960.dtsi @@ -220,16 +220,24 @@ #clock-cells = <0>; }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; + saw0: power-manager@2089000 { + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; + saw1: power-manager@2099000 { + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; gsbi5: gsbi@16400000 { @@ -359,5 +367,33 @@ }; }; }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16200000 0x100>; + ranges; + cell-index = <3>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + gsbi3_i2c: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16280000 0x1000>; + pinctrl-0 = <&i2c3_default_state>; + pinctrl-1 = <&i2c3_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI3_QUP_CLK>, + <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; }; +#include "qcom-msm8960-pins.dtsi" diff --git a/dts/src/arm/qcom/qcom-msm8974.dtsi b/dts/src/arm/qcom/qcom-msm8974.dtsi index b141398378..5efc38d712 100644 --- a/dts/src/arm/qcom/qcom-msm8974.dtsi +++ b/dts/src/arm/qcom/qcom-msm8974.dtsi @@ -31,7 +31,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_PPI 9 0xf04>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; CPU0: cpu@0 { compatible = "qcom,krait"; @@ -110,7 +110,7 @@ pmu { compatible = "qcom,krait-pmu"; - interrupts = <GIC_PPI 7 0xf04>; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; rpm: remoteproc { @@ -346,10 +346,9 @@ reg = <0xf9011000 0x1000>; }; - saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; + saw_l2: power-manager@f9012000 { + compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; watchdog@f9017000 { @@ -424,7 +423,7 @@ reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; }; - saw0: power-controller@f9089000 { + saw0: power-manager@f9089000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; }; @@ -434,7 +433,7 @@ reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; }; - saw1: power-controller@f9099000 { + saw1: power-manager@f9099000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; }; @@ -444,7 +443,7 @@ reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; }; - saw2: power-controller@f90a9000 { + saw2: power-manager@f90a9000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; }; @@ -454,7 +453,7 @@ reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; }; - saw3: power-controller@f90b9000 { + saw3: power-manager@f90b9000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; }; @@ -538,7 +537,7 @@ status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9923000 0x1000>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; @@ -566,7 +565,7 @@ status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9925000 0x1000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; @@ -666,7 +665,7 @@ status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; reg = <0xf9968000 0x1000>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; @@ -1234,7 +1233,7 @@ qfprom: qfprom@fc4bc000 { compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; + reg = <0xfc4bc000 0x2100>; #address-cells = <1>; #size-cells = <1>; @@ -2403,10 +2402,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 2 0xf08>, - <GIC_PPI 3 0xf08>, - <GIC_PPI 4 0xf08>, - <GIC_PPI 1 0xf08>; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <19200000>; }; }; diff --git a/dts/src/arm/qcom/qcom-sdx55.dtsi b/dts/src/arm/qcom/qcom-sdx55.dtsi index 27429d0fed..edc9aaf828 100644 --- a/dts/src/arm/qcom/qcom-sdx55.dtsi +++ b/dts/src/arm/qcom/qcom-sdx55.dtsi @@ -580,12 +580,16 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 51 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, - <&pdc 10 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_GDSC>; @@ -727,57 +731,57 @@ frame@17821000 { frame-number = <0>; - interrupts = <GIC_SPI 7 0x4>, - <GIC_SPI 6 0x4>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17821000 0x1000>, <0x17822000 0x1000>; }; frame@17823000 { frame-number = <1>; - interrupts = <GIC_SPI 8 0x4>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17823000 0x1000>; status = "disabled"; }; frame@17824000 { frame-number = <2>; - interrupts = <GIC_SPI 9 0x4>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17824000 0x1000>; status = "disabled"; }; frame@17825000 { frame-number = <3>; - interrupts = <GIC_SPI 10 0x4>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17825000 0x1000>; status = "disabled"; }; frame@17826000 { frame-number = <4>; - interrupts = <GIC_SPI 11 0x4>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17826000 0x1000>; status = "disabled"; }; frame@17827000 { frame-number = <5>; - interrupts = <GIC_SPI 12 0x4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17827000 0x1000>; status = "disabled"; }; frame@17828000 { frame-number = <6>; - interrupts = <GIC_SPI 13 0x4>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17828000 0x1000>; status = "disabled"; }; frame@17829000 { frame-number = <7>; - interrupts = <GIC_SPI 14 0x4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17829000 0x1000>; status = "disabled"; }; diff --git a/dts/src/arm/qcom/qcom-sdx65.dtsi b/dts/src/arm/qcom/qcom-sdx65.dtsi index 40591a4da6..a949454212 100644 --- a/dts/src/arm/qcom/qcom-sdx65.dtsi +++ b/dts/src/arm/qcom/qcom-sdx65.dtsi @@ -492,23 +492,25 @@ clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, <&gcc GCC_USB30_MSTR_AXI_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", + "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>, <&pdc 18 IRQ_TYPE_EDGE_BOTH>, - <&pdc 19 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_GDSC>; @@ -667,57 +669,57 @@ frame@17821000 { frame-number = <0>; - interrupts = <GIC_SPI 7 0x4>, - <GIC_SPI 6 0x4>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17821000 0x1000>, <0x17822000 0x1000>; }; frame@17823000 { frame-number = <1>; - interrupts = <GIC_SPI 8 0x4>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17823000 0x1000>; status = "disabled"; }; frame@17824000 { frame-number = <2>; - interrupts = <GIC_SPI 9 0x4>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17824000 0x1000>; status = "disabled"; }; frame@17825000 { frame-number = <3>; - interrupts = <GIC_SPI 10 0x4>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17825000 0x1000>; status = "disabled"; }; frame@17826000 { frame-number = <4>; - interrupts = <GIC_SPI 11 0x4>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17826000 0x1000>; status = "disabled"; }; frame@17827000 { frame-number = <5>; - interrupts = <GIC_SPI 12 0x4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17827000 0x1000>; status = "disabled"; }; frame@17828000 { frame-number = <6>; - interrupts = <GIC_SPI 13 0x4>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17828000 0x1000>; status = "disabled"; }; frame@17829000 { frame-number = <7>; - interrupts = <GIC_SPI 14 0x4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17829000 0x1000>; status = "disabled"; }; @@ -804,10 +806,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 12 0xf08>, - <1 10 0xf08>, - <1 11 0xf08>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <19200000>; }; }; diff --git a/dts/src/arm/renesas/r8a73a4-ape6evm.dts b/dts/src/arm/renesas/r8a73a4-ape6evm.dts index ed75c01dbe..3d02f065f7 100644 --- a/dts/src/arm/renesas/r8a73a4-ape6evm.dts +++ b/dts/src/arm/renesas/r8a73a4-ape6evm.dts @@ -209,6 +209,18 @@ status = "okay"; }; +&extal1_clk { + clock-frequency = <26000000>; +}; + +&extal2_clk { + clock-frequency = <48000000>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + &pfc { scifa0_pins: scifa0 { groups = "scifa0_data"; diff --git a/dts/src/arm/renesas/r8a73a4.dtsi b/dts/src/arm/renesas/r8a73a4.dtsi index c390669670..ac654ff45d 100644 --- a/dts/src/arm/renesas/r8a73a4.dtsi +++ b/dts/src/arm/renesas/r8a73a4.dtsi @@ -450,17 +450,20 @@ extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <25000000>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <48000000>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; fsiack_clk: fsiack { compatible = "fixed-clock"; @@ -621,6 +624,13 @@ clock-div = <2>; clock-mult = <1>; }; + cp_clk: cp { + compatible = "fixed-factor-clock"; + clocks = <&main_div2_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; pll0_div2_clk: pll0_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; @@ -686,9 +696,8 @@ mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, - <&main_div2_clk>, - <&cpg_clocks R8A73A4_CLK_HP>, + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, + <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < @@ -702,7 +711,7 @@ mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 diff --git a/dts/src/arm/renesas/r8a7740.dtsi b/dts/src/arm/renesas/r8a7740.dtsi index 55884ec701..d13ab86c3a 100644 --- a/dts/src/arm/renesas/r8a7740.dtsi +++ b/dts/src/arm/renesas/r8a7740.dtsi @@ -459,6 +459,7 @@ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp1_clks R8A7740_CLK_TMU0>; clock-names = "fck"; power-domains = <&pd_a4r>; @@ -474,6 +475,7 @@ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp1_clks R8A7740_CLK_TMU1>; clock-names = "fck"; power-domains = <&pd_a4r>; diff --git a/dts/src/arm/renesas/r8a7778.dtsi b/dts/src/arm/renesas/r8a7778.dtsi index 8d4530ed2f..b80e832c92 100644 --- a/dts/src/arm/renesas/r8a7778.dtsi +++ b/dts/src/arm/renesas/r8a7778.dtsi @@ -199,7 +199,9 @@ reg = <0xffd80000 0x30>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU0>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -214,7 +216,9 @@ reg = <0xffd81000 0x30>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU1>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -230,6 +234,7 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp0_clks R8A7778_CLK_TMU2>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -250,6 +255,8 @@ reg = <0xffd90000 0x1000>, /* SRU */ <0xffd91000 0x240>, /* SSI */ <0xfffe0000 0x24>; /* ADG */ + reg-names = "sru", "ssi", "adg"; + clocks = <&mstp3_clks R8A7778_CLK_SSI8>, <&mstp3_clks R8A7778_CLK_SSI7>, <&mstp3_clks R8A7778_CLK_SSI6>, diff --git a/dts/src/arm/renesas/r8a7779.dtsi b/dts/src/arm/renesas/r8a7779.dtsi index 7743af5e2a..1944703cba 100644 --- a/dts/src/arm/renesas/r8a7779.dtsi +++ b/dts/src/arm/renesas/r8a7779.dtsi @@ -402,7 +402,9 @@ reg = <0xffd80000 0x30>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; @@ -417,7 +419,9 @@ reg = <0xffd81000 0x30>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU1>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; @@ -433,6 +437,7 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp0_clks R8A7779_CLK_TMU2>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; diff --git a/dts/src/arm/rockchip/rk3128-xpi-3128.dts b/dts/src/arm/rockchip/rk3128-xpi-3128.dts index 03a9788151..21c1678f4e 100644 --- a/dts/src/arm/rockchip/rk3128-xpi-3128.dts +++ b/dts/src/arm/rockchip/rk3128-xpi-3128.dts @@ -47,6 +47,17 @@ regulator-boot-on; }; + hdmi-connnector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + /* * This is a vbus-supply, which also supplies the GL852G usb hub, * thus has to be always-on @@ -239,6 +250,10 @@ cpu-supply = <&vdd_arm>; }; +&display_subsystem { + status = "okay"; +}; + &emmc { bus-width = <8>; vmmc-supply = <&vcc_io>; @@ -328,6 +343,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_connector_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + &mdio { phy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -423,3 +448,7 @@ &usb2phy_otg { status = "okay"; }; + +&vop { + status = "okay"; +}; diff --git a/dts/src/arm/rockchip/rk3128.dtsi b/dts/src/arm/rockchip/rk3128.dtsi index e2264c40b9..fb98873fd9 100644 --- a/dts/src/arm/rockchip/rk3128.dtsi +++ b/dts/src/arm/rockchip/rk3128.dtsi @@ -115,6 +115,12 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + gpu_opp_table: opp-table-1 { compatible = "operating-points-v2"; @@ -246,6 +252,32 @@ }; }; + vop: vop@1010e000 { + compatible = "rockchip,rk3126-vop"; + reg = <0x1010e000 0x300>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, + <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", + "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, + <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", + "dclk"; + power-domains = <&power RK3128_PD_VIO>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + qos_gpu: qos@1012d000 { compatible = "rockchip,rk3128-qos", "syscon"; reg = <0x1012d000 0x20>; @@ -436,6 +468,34 @@ }; }; + hdmi: hdmi@20034000 { + compatible = "rockchip,rk3128-inno-hdmi"; + reg = <0x20034000 0x4000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>; + clock-names = "pclk", "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; + power-domains = <&power RK3128_PD_VIO>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + hdmi_in_vop: endpoint { + remote-endpoint = <&vop_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + timer0: timer@20044000 { compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; diff --git a/dts/src/arm/rockchip/rk322x.dtsi b/dts/src/arm/rockchip/rk322x.dtsi index 831561fc18..96421355c2 100644 --- a/dts/src/arm/rockchip/rk322x.dtsi +++ b/dts/src/arm/rockchip/rk322x.dtsi @@ -736,14 +736,20 @@ status = "disabled"; ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_vop: endpoint { remote-endpoint = <&vop_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/dts/src/arm/rockchip/rk3288.dtsi b/dts/src/arm/rockchip/rk3288.dtsi index ead343dc3d..3f1d640afa 100644 --- a/dts/src/arm/rockchip/rk3288.dtsi +++ b/dts/src/arm/rockchip/rk3288.dtsi @@ -1240,27 +1240,37 @@ compatible = "rockchip,rk3288-dw-hdmi"; reg = <0x0 0xff980000 0x0 0x20000>; reg-io-width = <4>; - #sound-dai-cells = <0>; - rockchip,grf = <&grf>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; clock-names = "iahb", "isfr", "cec"; power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; status = "disabled"; ports { - hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; + hdmi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/dts/src/arm/rockchip/rv1126-sonoff-ihost.dtsi b/dts/src/arm/rockchip/rv1126-sonoff-ihost.dtsi index 32b329e87a..9a87dc0d5f 100644 --- a/dts/src/arm/rockchip/rv1126-sonoff-ihost.dtsi +++ b/dts/src/arm/rockchip/rv1126-sonoff-ihost.dtsi @@ -8,6 +8,8 @@ aliases { ethernet0 = &gmac; mmc0 = &emmc; + mmc1 = &sdio; + mmc2 = &sdmmc; }; chosen { @@ -325,7 +327,7 @@ pmuio1-supply = <&vcc3v3_sys>; vccio1-supply = <&vcc_1v8>; vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_1v8>; + vccio3-supply = <&vcc3v3_sd>; vccio4-supply = <&vcc_dovdd>; vccio5-supply = <&vcc_1v8>; vccio6-supply = <&vcc_1v8>; @@ -343,14 +345,14 @@ cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; - max-frequency = <100000000>; + max-frequency = <50000000>; mmc-pwrseq = <&sdio_pwrseq>; non-removable; pinctrl-names = "default"; pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; rockchip,default-sample-phase = <90>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sys>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vcc_1v8>; status = "okay"; }; diff --git a/dts/src/arm/samsung/exynos4412-i9300.dts b/dts/src/arm/samsung/exynos4412-i9300.dts index 61aca5798f..b79d456e97 100644 --- a/dts/src/arm/samsung/exynos4412-i9300.dts +++ b/dts/src/arm/samsung/exynos4412-i9300.dts @@ -18,7 +18,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x40000000>; + reg = <0x40000000 0x3fc00000>; }; }; diff --git a/dts/src/arm/samsung/exynos4412-i9305.dts b/dts/src/arm/samsung/exynos4412-i9305.dts index 77083f1a82..1048ef5d9b 100644 --- a/dts/src/arm/samsung/exynos4412-i9305.dts +++ b/dts/src/arm/samsung/exynos4412-i9305.dts @@ -11,7 +11,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x7fc00000>; }; }; diff --git a/dts/src/arm/samsung/exynos4412-n710x.dts b/dts/src/arm/samsung/exynos4412-n710x.dts index 0a151437fc..eee1000dea 100644 --- a/dts/src/arm/samsung/exynos4412-n710x.dts +++ b/dts/src/arm/samsung/exynos4412-n710x.dts @@ -9,7 +9,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x7fc00000>; }; /* bootargs are passed in by bootloader */ diff --git a/dts/src/arm/samsung/exynos4412-p4note.dtsi b/dts/src/arm/samsung/exynos4412-p4note.dtsi index 0b89d5682f..28a6058027 100644 --- a/dts/src/arm/samsung/exynos4412-p4note.dtsi +++ b/dts/src/arm/samsung/exynos4412-p4note.dtsi @@ -23,7 +23,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x7fc00000>; }; aliases { @@ -362,6 +362,39 @@ status = "okay"; }; +&i2c_1 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c1_bus>; + pinctrl-names = "default"; + status = "okay"; + + accelerometer@19 { + compatible = "st,lsm330dlc-accel"; + reg = <0x19>; + interrupt-parent = <&gpx0>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&accelerometer_irq>; + pinctrl-names = "default"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyro@6b { + compatible = "st,lsm330dlc-gyro"; + reg = <0x6b>; + interrupt-parent = <&gpx0>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&gyro_data_enable &gyro_irq>; + pinctrl-names = "default"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; +}; + &i2c_3 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; @@ -844,6 +877,12 @@ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; + gyro_data_enable: gyro-data-enable-pins { + samsung,pins = "gpl2-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + uart_sel: uart-sel-pins { samsung,pins = "gpl2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; @@ -894,12 +933,24 @@ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; }; + accelerometer_irq: accelerometer-irq-pins { + samsung,pins = "gpx0-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + stmpe_adc_irq: stmpe-adc-irq-pins { samsung,pins = "gpx0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; + gyro_irq: gyro-irq-pins { + samsung,pins = "gpx0-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + max77686_irq: max77686-irq-pins { samsung,pins = "gpx0-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/dts/src/arm/samsung/exynos5420-galaxy-tab-common.dtsi b/dts/src/arm/samsung/exynos5420-galaxy-tab-common.dtsi index f525b2f5e4..2460409670 100644 --- a/dts/src/arm/samsung/exynos5420-galaxy-tab-common.dtsi +++ b/dts/src/arm/samsung/exynos5420-galaxy-tab-common.dtsi @@ -30,6 +30,7 @@ aliases { mmc0 = &mmc_0; + mmc1 = &mmc_1; mmc2 = &mmc_2; }; @@ -39,7 +40,7 @@ memory@20000000 { device_type = "memory"; - reg = <0x20000000 0xc0000000>; + reg = <0x20000000 0xbfa00000>; }; firmware@2073000 { @@ -87,6 +88,13 @@ linux,code = <KEY_VOLUMEDOWN>; }; }; + + mmc1_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>; + clocks = <&s2mps11_osc S2MPS11_CLK_BT>; + clock-names = "ext_clock"; + }; }; &cci { @@ -620,6 +628,25 @@ vqmmc-supply = <&ldo3_reg>; }; +/* WiFi */ +&mmc_1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + card-detect-delay = <200>; + keep-power-in-suspend; + mmc-pwrseq = <&mmc1_pwrseq>; + non-removable; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, + <&sd1_bus4>, <&wifi_en>; + pinctrl-names = "default"; + vqmmc-supply = <&ldo2_reg>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-sdr-timing = <0 1>; + status = "okay"; +}; + /* External sdcard */ &mmc_2 { status = "okay"; @@ -649,6 +676,11 @@ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; + + wifi_en: wifi-en-pins { + samsung,pins = "gpy7-7"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; }; &rtc { diff --git a/dts/src/arm/samsung/exynos5420-peach-pit.dts b/dts/src/arm/samsung/exynos5420-peach-pit.dts index 4e757b6e28..3759742d38 100644 --- a/dts/src/arm/samsung/exynos5420-peach-pit.dts +++ b/dts/src/arm/samsung/exynos5420-peach-pit.dts @@ -967,6 +967,7 @@ reg = <0>; spi-max-frequency = <3125000>; google,has-vbc-nvram; + wakeup-source; controller-data { samsung,spi-feedback-delay = <1>; diff --git a/dts/src/arm/samsung/exynos5422-odroidxu3-common.dtsi b/dts/src/arm/samsung/exynos5422-odroidxu3-common.dtsi index b4a851aa88..4a4c55a4be 100644 --- a/dts/src/arm/samsung/exynos5422-odroidxu3-common.dtsi +++ b/dts/src/arm/samsung/exynos5422-odroidxu3-common.dtsi @@ -55,7 +55,7 @@ thermal-zones { cpu0_thermal: cpu0-thermal { thermal-sensors = <&tmu_cpu0>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu0_alert0: cpu-alert-0 { @@ -78,12 +78,6 @@ hysteresis = <0>; /* millicelsius */ type = "critical"; }; - /* - * Exynos542x supports only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu0_alert2 - */ cpu0_alert3: cpu-alert-3 { temperature = <70000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ @@ -144,7 +138,7 @@ }; cpu1_thermal: cpu1-thermal { thermal-sensors = <&tmu_cpu1>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu1_alert0: cpu-alert-0 { @@ -217,7 +211,7 @@ }; cpu2_thermal: cpu2-thermal { thermal-sensors = <&tmu_cpu2>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu2_alert0: cpu-alert-0 { @@ -290,7 +284,7 @@ }; cpu3_thermal: cpu3-thermal { thermal-sensors = <&tmu_cpu3>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu3_alert0: cpu-alert-0 { @@ -363,7 +357,7 @@ }; gpu_thermal: gpu-thermal { thermal-sensors = <&tmu_gpu>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { gpu_alert0: gpu-alert-0 { diff --git a/dts/src/arm/samsung/exynos5800-peach-pi.dts b/dts/src/arm/samsung/exynos5800-peach-pi.dts index f91bc4ae00..9bbbdce910 100644 --- a/dts/src/arm/samsung/exynos5800-peach-pi.dts +++ b/dts/src/arm/samsung/exynos5800-peach-pi.dts @@ -949,6 +949,7 @@ reg = <0>; spi-max-frequency = <3125000>; google,has-vbc-nvram; + wakeup-source; controller-data { samsung,spi-feedback-delay = <1>; diff --git a/dts/src/arm/st/stih407-pinctrl.dtsi b/dts/src/arm/st/stih407-pinctrl.dtsi index 7815669fe8..dcb821f567 100644 --- a/dts/src/arm/st/stih407-pinctrl.dtsi +++ b/dts/src/arm/st/stih407-pinctrl.dtsi @@ -462,14 +462,14 @@ serial0 { pinctrl_serial0: serial0-0 { st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; }; }; pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; cts = <&pio17 2 ALT1 IN>; rts = <&pio17 3 ALT1 OUT>; }; diff --git a/dts/src/arm/st/stm32f769-disco-mb1166-reva09.dts b/dts/src/arm/st/stm32f769-disco-mb1166-reva09.dts new file mode 100644 index 0000000000..ff7ff32371 --- /dev/null +++ b/dts/src/arm/st/stm32f769-disco-mb1166-reva09.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +#include "stm32f769-disco.dts" + +&panel0 { + compatible = "frida,frd400b25025", "novatek,nt35510"; + vddi-supply = <&vcc_3v3>; + vdd-supply = <&vcc_3v3>; + /delete-property/power-supply; +}; diff --git a/dts/src/arm/st/stm32f769-disco.dts b/dts/src/arm/st/stm32f769-disco.dts index 5d12ae25b3..52c5baf58a 100644 --- a/dts/src/arm/st/stm32f769-disco.dts +++ b/dts/src/arm/st/stm32f769-disco.dts @@ -41,7 +41,7 @@ */ /dts-v1/; -#include "stm32f746.dtsi" +#include "stm32f769.dtsi" #include "stm32f769-pinctrl.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> @@ -60,6 +60,19 @@ reg = <0xC0000000 0x1000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,dma { + compatible = "shared-dma-pool"; + linux,dma-default; + no-map; + size = <0x100000>; + }; + }; + aliases { serial0 = &usart1; }; @@ -92,9 +105,9 @@ clock-names = "main_clk"; }; - mmc_vcard: mmc_vcard { + vcc_3v3: vcc-3v3 { compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; + regulator-name = "vcc_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -114,6 +127,45 @@ clock-frequency = <25000000>; }; +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel0: panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; /* dsi virtual channel (0..3) */ + reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>; + power-supply = <&vcc_3v3>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; @@ -122,13 +174,23 @@ status = "okay"; }; +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; +}; + &rtc { status = "okay"; }; &sdio2 { status = "okay"; - vmmc-supply = <&mmc_vcard>; + vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; broken-cd; pinctrl-names = "default", "opendrain", "sleep"; diff --git a/dts/src/arm/st/stm32f769.dtsi b/dts/src/arm/st/stm32f769.dtsi new file mode 100644 index 0000000000..4e7d903214 --- /dev/null +++ b/dts/src/arm/st/stm32f769.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +#include "stm32f746.dtsi" + +/ { + soc { + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016c00 0x800>; + clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>; + clock-names = "pclk", "ref"; + resets = <&rcc STM32F7_APB2_RESET(DSI)>; + reset-names = "apb"; + status = "disabled"; + }; + }; +}; diff --git a/dts/src/arm/st/stm32mp131.dtsi b/dts/src/arm/st/stm32mp131.dtsi index b04d24c939..3900f32da7 100644 --- a/dts/src/arm/st/stm32mp131.dtsi +++ b/dts/src/arm/st/stm32mp131.dtsi @@ -1315,6 +1315,13 @@ status = "disabled"; }; + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; + status = "disabled"; + }; + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; diff --git a/dts/src/arm/st/stm32mp135f-dk.dts b/dts/src/arm/st/stm32mp135f-dk.dts index eea740d097..52171214a3 100644 --- a/dts/src/arm/st/stm32mp135f-dk.dts +++ b/dts/src/arm/st/stm32mp135f-dk.dts @@ -93,6 +93,14 @@ }; }; +&crc1 { + status = "okay"; +}; + +&cryp { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; diff --git a/dts/src/arm/st/stm32mp157.dtsi b/dts/src/arm/st/stm32mp157.dtsi index 6197d87889..97cd24227c 100644 --- a/dts/src/arm/st/stm32mp157.dtsi +++ b/dts/src/arm/st/stm32mp157.dtsi @@ -20,7 +20,7 @@ dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>; clock-names = "pclk", "ref", "px_clk"; phy-dsi-supply = <®18>; resets = <&rcc DSI_R>; diff --git a/dts/src/arm/st/stm32mp157a-dk1-scmi.dts b/dts/src/arm/st/stm32mp157a-dk1-scmi.dts index ce5937270a..306e1bc2a5 100644 --- a/dts/src/arm/st/stm32mp157a-dk1-scmi.dts +++ b/dts/src/arm/st/stm32mp157a-dk1-scmi.dts @@ -30,7 +30,7 @@ }; &dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/dts/src/arm/st/stm32mp157c-dk2-scmi.dts b/dts/src/arm/st/stm32mp157c-dk2-scmi.dts index c20a73841c..956da5f26c 100644 --- a/dts/src/arm/st/stm32mp157c-dk2-scmi.dts +++ b/dts/src/arm/st/stm32mp157c-dk2-scmi.dts @@ -36,7 +36,7 @@ &dsi { phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/dts/src/arm/st/stm32mp157c-ed1-scmi.dts b/dts/src/arm/st/stm32mp157c-ed1-scmi.dts index 5e2eaf57ce..8e4b0db198 100644 --- a/dts/src/arm/st/stm32mp157c-ed1-scmi.dts +++ b/dts/src/arm/st/stm32mp157c-ed1-scmi.dts @@ -35,7 +35,7 @@ }; &dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/dts/src/arm/st/stm32mp157c-ev1-scmi.dts b/dts/src/arm/st/stm32mp157c-ev1-scmi.dts index 3226fb945a..72b9cab2d9 100644 --- a/dts/src/arm/st/stm32mp157c-ev1-scmi.dts +++ b/dts/src/arm/st/stm32mp157c-ev1-scmi.dts @@ -36,7 +36,7 @@ &dsi { phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/dts/src/arm/st/stm32mp157c-lxa-tac-gen2.dts b/dts/src/arm/st/stm32mp157c-lxa-tac-gen2.dts index 8a34d15e90..4cc1770316 100644 --- a/dts/src/arm/st/stm32mp157c-lxa-tac-gen2.dts +++ b/dts/src/arm/st/stm32mp157c-lxa-tac-gen2.dts @@ -148,7 +148,7 @@ compatible = "ti,lmp92064"; reg = <0>; - reset-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; shunt-resistor-micro-ohms = <15000>; spi-max-frequency = <5000000>; vdd-supply = <®_pb_3v3>; diff --git a/dts/src/arm/st/stm32mp15xc-lxa-tac.dtsi b/dts/src/arm/st/stm32mp15xc-lxa-tac.dtsi index fc3a2386db..cfaf8adde3 100644 --- a/dts/src/arm/st/stm32mp15xc-lxa-tac.dtsi +++ b/dts/src/arm/st/stm32mp15xc-lxa-tac.dtsi @@ -409,7 +409,7 @@ baseboard_eeprom: &sip_eeprom { &spi2 { pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_c>; - cs-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpiof 12 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -471,6 +471,10 @@ baseboard_eeprom: &sip_eeprom { interrupt-parent = <&gpioa>; interrupts = <6 IRQ_TYPE_EDGE_RISING>; + /* Reduce RGMII EMI emissions by reducing drive strength */ + microchip,hi-drive-strength-microamp = <2000>; + microchip,lo-drive-strength-microamp = <8000>; + ports { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/src/arm/ti/davinci/da850.dtsi b/dts/src/arm/ti/davinci/da850.dtsi index f759fdfe1b..1d3fb5397c 100644 --- a/dts/src/arm/ti/davinci/da850.dtsi +++ b/dts/src/arm/ti/davinci/da850.dtsi @@ -536,7 +536,7 @@ reg = <0x40000 0x1000>; cap-sd-highspeed; cap-mmc-highspeed; - interrupts = <16>; + interrupts = <16>, <17>; dmas = <&edma0 16 0>, <&edma0 17 0>; dma-names = "rx", "tx"; clocks = <&psc0 5>; @@ -566,7 +566,7 @@ reg = <0x21b000 0x1000>; cap-sd-highspeed; cap-mmc-highspeed; - interrupts = <72>; + interrupts = <72>, <73>; dmas = <&edma1 28 0>, <&edma1 29 0>; dma-names = "rx", "tx"; clocks = <&psc1 18>; diff --git a/dts/src/arm/ti/keystone/keystone-clocks.dtsi b/dts/src/arm/ti/keystone/keystone-clocks.dtsi index 0397c3423d..20bab90ee0 100644 --- a/dts/src/arm/ti/keystone/keystone-clocks.dtsi +++ b/dts/src/arm/ti/keystone/keystone-clocks.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 clock tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/dts/src/arm/ti/keystone/keystone-k2e-clocks.dtsi b/dts/src/arm/ti/keystone/keystone-k2e-clocks.dtsi index cf30e007fe..74720dbf31 100644 --- a/dts/src/arm/ti/keystone/keystone-k2e-clocks.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2e-clocks.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Edison SoC specific device tree * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/dts/src/arm/ti/keystone/keystone-k2e-evm.dts b/dts/src/arm/ti/keystone/keystone-k2e-evm.dts index 6978d6a362..58099ce8d4 100644 --- a/dts/src/arm/ti/keystone/keystone-k2e-evm.dts +++ b/dts/src/arm/ti/keystone/keystone-k2e-evm.dts @@ -2,7 +2,7 @@ /* * Keystone 2 Edison EVM device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm/ti/keystone/keystone-k2e-netcp.dtsi b/dts/src/arm/ti/keystone/keystone-k2e-netcp.dtsi index 5c88a90903..e586350ae4 100644 --- a/dts/src/arm/ti/keystone/keystone-k2e-netcp.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2e-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 Edison Netcp driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/dts/src/arm/ti/keystone/keystone-k2e.dtsi b/dts/src/arm/ti/keystone/keystone-k2e.dtsi index 65c32946c5..662aa33cba 100644 --- a/dts/src/arm/ti/keystone/keystone-k2e.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2e.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Edison soc device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/reset/ti-syscon.h> diff --git a/dts/src/arm/ti/keystone/keystone-k2g-evm.dts b/dts/src/arm/ti/keystone/keystone-k2g-evm.dts index f0ddbbcdc9..bf5f67d702 100644 --- a/dts/src/arm/ti/keystone/keystone-k2g-evm.dts +++ b/dts/src/arm/ti/keystone/keystone-k2g-evm.dts @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G EVM * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm/ti/keystone/keystone-k2g-ice.dts b/dts/src/arm/ti/keystone/keystone-k2g-ice.dts index 6ceb0d5c63..264e1e0d23 100644 --- a/dts/src/arm/ti/keystone/keystone-k2g-ice.dts +++ b/dts/src/arm/ti/keystone/keystone-k2g-ice.dts @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G Industrial Communication Engine EVM * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm/ti/keystone/keystone-k2g-netcp.dtsi b/dts/src/arm/ti/keystone/keystone-k2g-netcp.dtsi index 7109ca0316..974c8f2fa7 100644 --- a/dts/src/arm/ti/keystone/keystone-k2g-netcp.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2g-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G Netcp driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@4020000 { diff --git a/dts/src/arm/ti/keystone/keystone-k2g.dtsi b/dts/src/arm/ti/keystone/keystone-k2g.dtsi index 102d59694d..790b29ab0f 100644 --- a/dts/src/arm/ti/keystone/keystone-k2g.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2g.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G SOC * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/dts/src/arm/ti/keystone/keystone-k2hk-clocks.dtsi b/dts/src/arm/ti/keystone/keystone-k2hk-clocks.dtsi index 4ba6912176..3ca4722087 100644 --- a/dts/src/arm/ti/keystone/keystone-k2hk-clocks.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2hk-clocks.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Kepler/Hawking SoC clock nodes * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/dts/src/arm/ti/keystone/keystone-k2hk-evm.dts b/dts/src/arm/ti/keystone/keystone-k2hk-evm.dts index 8dfb542950..b824fad9a4 100644 --- a/dts/src/arm/ti/keystone/keystone-k2hk-evm.dts +++ b/dts/src/arm/ti/keystone/keystone-k2hk-evm.dts @@ -2,7 +2,7 @@ /* * Keystone 2 Kepler/Hawking EVM device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi b/dts/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi index c2ee775eab..3ab1b5d6f9 100644 --- a/dts/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 Hawking Netcp driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/dts/src/arm/ti/keystone/keystone-k2hk.dtsi b/dts/src/arm/ti/keystone/keystone-k2hk.dtsi index da6d3934c2..4fdf4b3038 100644 --- a/dts/src/arm/ti/keystone/keystone-k2hk.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2hk.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Kepler/Hawking soc specific device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/reset/ti-syscon.h> diff --git a/dts/src/arm/ti/keystone/keystone-k2l-clocks.dtsi b/dts/src/arm/ti/keystone/keystone-k2l-clocks.dtsi index 635528064d..fcfc2fb6cc 100644 --- a/dts/src/arm/ti/keystone/keystone-k2l-clocks.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2l-clocks.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 lamarr SoC clock nodes * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/dts/src/arm/ti/keystone/keystone-k2l-evm.dts b/dts/src/arm/ti/keystone/keystone-k2l-evm.dts index be619e39a1..ccda63ab12 100644 --- a/dts/src/arm/ti/keystone/keystone-k2l-evm.dts +++ b/dts/src/arm/ti/keystone/keystone-k2l-evm.dts @@ -2,7 +2,7 @@ /* * Keystone 2 Lamarr EVM device tree * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm/ti/keystone/keystone-k2l-netcp.dtsi b/dts/src/arm/ti/keystone/keystone-k2l-netcp.dtsi index 1afebd7458..b8f880faaa 100644 --- a/dts/src/arm/ti/keystone/keystone-k2l-netcp.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2l-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 Lamarr Netcp driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/dts/src/arm/ti/keystone/keystone-k2l.dtsi b/dts/src/arm/ti/keystone/keystone-k2l.dtsi index 2062fe5616..330b437b66 100644 --- a/dts/src/arm/ti/keystone/keystone-k2l.dtsi +++ b/dts/src/arm/ti/keystone/keystone-k2l.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Lamarr SoC specific device tree * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/reset/ti-syscon.h> diff --git a/dts/src/arm/ti/keystone/keystone.dtsi b/dts/src/arm/ti/keystone/keystone.dtsi index 1fd04bb37a..ff16428860 100644 --- a/dts/src/arm/ti/keystone/keystone.dtsi +++ b/dts/src/arm/ti/keystone/keystone.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/dts/src/arm/ti/omap/am335x-baltos-ir2110.dts b/dts/src/arm/ti/omap/am335x-baltos-ir2110.dts index ea5882ed70..f82d2231df 100644 --- a/dts/src/arm/ti/omap/am335x-baltos-ir2110.dts +++ b/dts/src/arm/ti/omap/am335x-baltos-ir2110.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-baltos-ir3220.dts b/dts/src/arm/ti/omap/am335x-baltos-ir3220.dts index ea4f8dde64..74a2191af1 100644 --- a/dts/src/arm/ti/omap/am335x-baltos-ir3220.dts +++ b/dts/src/arm/ti/omap/am335x-baltos-ir3220.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-baltos-ir5221.dts b/dts/src/arm/ti/omap/am335x-baltos-ir5221.dts index ec914f27d1..723ff88f76 100644 --- a/dts/src/arm/ti/omap/am335x-baltos-ir5221.dts +++ b/dts/src/arm/ti/omap/am335x-baltos-ir5221.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-baltos-leds.dtsi b/dts/src/arm/ti/omap/am335x-baltos-leds.dtsi index 6a52e42b9e..049fd8e1b4 100644 --- a/dts/src/arm/ti/omap/am335x-baltos-leds.dtsi +++ b/dts/src/arm/ti/omap/am335x-baltos-leds.dtsi @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /*#include "am33xx.dtsi"*/ diff --git a/dts/src/arm/ti/omap/am335x-baltos.dtsi b/dts/src/arm/ti/omap/am335x-baltos.dtsi index c14d5b70c7..a4beb71855 100644 --- a/dts/src/arm/ti/omap/am335x-baltos.dtsi +++ b/dts/src/arm/ti/omap/am335x-baltos.dtsi @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ #include "am33xx.dtsi" diff --git a/dts/src/arm/ti/omap/am335x-base0033.dts b/dts/src/arm/ti/omap/am335x-base0033.dts index eba843e22e..46078af4b7 100644 --- a/dts/src/arm/ti/omap/am335x-base0033.dts +++ b/dts/src/arm/ti/omap/am335x-base0033.dts @@ -2,7 +2,7 @@ /* * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz */ #include "am335x-igep0033.dtsi" diff --git a/dts/src/arm/ti/omap/am335x-bone-common.dtsi b/dts/src/arm/ti/omap/am335x-bone-common.dtsi index 96451c8a81..2d0216840f 100644 --- a/dts/src/arm/ti/omap/am335x-bone-common.dtsi +++ b/dts/src/arm/ti/omap/am335x-bone-common.dtsi @@ -289,8 +289,8 @@ * For details, see linux-omap mailing list May 2015 thread * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html + * https://www.spinics.net/lists/linux-omap/msg118585.html + * https://www.spinics.net/lists/linux-omap/msg118615.html * * You can override this later with * &tps { /delete-property/ ti,pmic-shutdown-controller; } diff --git a/dts/src/arm/ti/omap/am335x-cm-t335.dts b/dts/src/arm/ti/omap/am335x-cm-t335.dts index 72990e7ffe..06767ea164 100644 --- a/dts/src/arm/ti/omap/am335x-cm-t335.dts +++ b/dts/src/arm/ti/omap/am335x-cm-t335.dts @@ -2,7 +2,7 @@ /* * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2014 - 2015 CompuLab Ltd. - https://www.compulab.co.il/ */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-evmsk.dts b/dts/src/arm/ti/omap/am335x-evmsk.dts index 57f78846c4..eba888dcd6 100644 --- a/dts/src/arm/ti/omap/am335x-evmsk.dts +++ b/dts/src/arm/ti/omap/am335x-evmsk.dts @@ -5,7 +5,7 @@ /* * AM335x Starter Kit - * http://www.ti.com/tool/tmdssk3358 + * https://www.ti.com/tool/tmdssk3358 */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-guardian.dts b/dts/src/arm/ti/omap/am335x-guardian.dts index 205fe0ed73..56e5d954a4 100644 --- a/dts/src/arm/ti/omap/am335x-guardian.dts +++ b/dts/src/arm/ti/omap/am335x-guardian.dts @@ -303,8 +303,8 @@ * For details, see linux-omap mailing list May 2015 thread * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html + * https://www.spinics.net/lists/linux-omap/msg118585.html + * https://www.spinics.net/lists/linux-omap/msg118615.html * * You can override this later with * &tps { /delete-property/ ti,pmic-shutdown-controller; } diff --git a/dts/src/arm/ti/omap/am335x-icev2.dts b/dts/src/arm/ti/omap/am335x-icev2.dts index 3c4228927f..6f0f4fba04 100644 --- a/dts/src/arm/ti/omap/am335x-icev2.dts +++ b/dts/src/arm/ti/omap/am335x-icev2.dts @@ -5,7 +5,7 @@ /* * AM335x ICE V2 board - * http://www.ti.com/tool/tmdsice3359 + * https://www.ti.com/tool/tmdsice3359 */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-igep0033.dtsi b/dts/src/arm/ti/omap/am335x-igep0033.dtsi index e85c33fd42..c7a4a54764 100644 --- a/dts/src/arm/ti/omap/am335x-igep0033.dtsi +++ b/dts/src/arm/ti/omap/am335x-igep0033.dtsi @@ -2,7 +2,7 @@ /* * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-myirtech-myc.dtsi b/dts/src/arm/ti/omap/am335x-myirtech-myc.dtsi index 5845992692..9c9359844a 100644 --- a/dts/src/arm/ti/omap/am335x-myirtech-myc.dtsi +++ b/dts/src/arm/ti/omap/am335x-myirtech-myc.dtsi @@ -2,7 +2,7 @@ /* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */ /* Based on code by myc_c335x.dts, MYiRtech.com */ -/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ +/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-myirtech-myd.dts b/dts/src/arm/ti/omap/am335x-myirtech-myd.dts index d3bba79b93..fd91a3c01a 100644 --- a/dts/src/arm/ti/omap/am335x-myirtech-myd.dts +++ b/dts/src/arm/ti/omap/am335x-myirtech-myd.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */ /* Based on code by myd_c335x.dts, MYiRtech.com */ -/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ +/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-nano.dts b/dts/src/arm/ti/omap/am335x-nano.dts index a475c0d913..26b5510cb3 100644 --- a/dts/src/arm/ti/omap/am335x-nano.dts +++ b/dts/src/arm/ti/omap/am335x-nano.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ + * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/ */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-netcan-plus-1xx.dts b/dts/src/arm/ti/omap/am335x-netcan-plus-1xx.dts index f7fad48e36..546e88f8fb 100644 --- a/dts/src/arm/ti/omap/am335x-netcan-plus-1xx.dts +++ b/dts/src/arm/ti/omap/am335x-netcan-plus-1xx.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-netcom-plus-2xx.dts b/dts/src/arm/ti/omap/am335x-netcom-plus-2xx.dts index 76751a324a..f66d57bb68 100644 --- a/dts/src/arm/ti/omap/am335x-netcom-plus-2xx.dts +++ b/dts/src/arm/ti/omap/am335x-netcom-plus-2xx.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-netcom-plus-8xx.dts b/dts/src/arm/ti/omap/am335x-netcom-plus-8xx.dts index 5a9fcec040..5fb2c629f3 100644 --- a/dts/src/arm/ti/omap/am335x-netcom-plus-8xx.dts +++ b/dts/src/arm/ti/omap/am335x-netcom-plus-8xx.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-pdu001.dts b/dts/src/arm/ti/omap/am335x-pdu001.dts index 3c9444e98c..f38f5bff2b 100644 --- a/dts/src/arm/ti/omap/am335x-pdu001.dts +++ b/dts/src/arm/ti/omap/am335x-pdu001.dts @@ -3,7 +3,7 @@ * * EETS GmbH PDU001 board device tree file * - * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/ * * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * diff --git a/dts/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts b/dts/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts index 5522759def..7c9f65126c 100644 --- a/dts/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts +++ b/dts/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2021 Sancloud Ltd - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-sancloud-bbe-lite.dts b/dts/src/arm/ti/omap/am335x-sancloud-bbe-lite.dts index b1b400226d..c6c96f6182 100644 --- a/dts/src/arm/ti/omap/am335x-sancloud-bbe-lite.dts +++ b/dts/src/arm/ti/omap/am335x-sancloud-bbe-lite.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2021 SanCloud Ltd */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am335x-sbc-t335.dts b/dts/src/arm/ti/omap/am335x-sbc-t335.dts index 596774c847..2841e95d9a 100644 --- a/dts/src/arm/ti/omap/am335x-sbc-t335.dts +++ b/dts/src/arm/ti/omap/am335x-sbc-t335.dts @@ -2,7 +2,7 @@ /* * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335 * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2014 - 2015 CompuLab Ltd. - https://www.compulab.co.il/ */ #include "am335x-cm-t335.dts" diff --git a/dts/src/arm/ti/omap/am335x-sl50.dts b/dts/src/arm/ti/omap/am335x-sl50.dts index 1115c812f6..757ebd96b3 100644 --- a/dts/src/arm/ti/omap/am335x-sl50.dts +++ b/dts/src/arm/ti/omap/am335x-sl50.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ + * Copyright (C) 2015 Toby Churchill - https://www.toby-churchill.com/ + * url above is defunct */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am33xx-clocks.dtsi b/dts/src/arm/ti/omap/am33xx-clocks.dtsi index d34483ae17..99b62c6b4c 100644 --- a/dts/src/arm/ti/omap/am33xx-clocks.dtsi +++ b/dts/src/arm/ti/omap/am33xx-clocks.dtsi @@ -108,30 +108,31 @@ compatible = "ti,clksel"; reg = <0x664>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ehrpwm0_tbclk: clock-ehrpwm0-tbclk { + ehrpwm0_tbclk: clock-ehrpwm0-tbclk@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "ehrpwm0_tbclk"; clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; }; - ehrpwm1_tbclk: clock-ehrpwm1-tbclk { + ehrpwm1_tbclk: clock-ehrpwm1-tbclk@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "ehrpwm1_tbclk"; clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; }; - ehrpwm2_tbclk: clock-ehrpwm2-tbclk { + ehrpwm2_tbclk: clock-ehrpwm2-tbclk@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "ehrpwm2_tbclk"; clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; }; }; }; @@ -566,17 +567,19 @@ compatible = "ti,clksel"; reg = <0x52c>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gfx_fclk_clksel_ck: clock-gfx-fclk-clksel { + gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "gfx_fclk_clksel_ck"; clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; }; - gfx_fck_div_ck: clock-gfx-fck-div { + gfx_fck_div_ck: clock-gfx-fck-div@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "gfx_fck_div_ck"; @@ -589,30 +592,32 @@ compatible = "ti,clksel"; reg = <0x700>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - sysclkout_pre_ck: clock-sysclkout-pre { + sysclkout_pre_ck: clock-sysclkout-pre@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "sysclkout_pre_ck"; clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; }; - clkout2_div_ck: clock-clkout2-div { + clkout2_div_ck: clock-clkout2-div@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "clkout2_div_ck"; clocks = <&sysclkout_pre_ck>; - ti,bit-shift = <3>; ti,max-div = <8>; }; - clkout2_ck: clock-clkout2 { + clkout2_ck: clock-clkout2@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "clkout2_ck"; clocks = <&clkout2_div_ck>; - ti,bit-shift = <7>; }; }; }; diff --git a/dts/src/arm/ti/omap/am33xx.dtsi b/dts/src/arm/ti/omap/am33xx.dtsi index 5b9e01a8aa..989d5a6ede 100644 --- a/dts/src/arm/ti/omap/am33xx.dtsi +++ b/dts/src/arm/ti/omap/am33xx.dtsi @@ -640,10 +640,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <37>; + }; }; }; }; diff --git a/dts/src/arm/ti/omap/am3517.dtsi b/dts/src/arm/ti/omap/am3517.dtsi index 77e58e686f..19aad715df 100644 --- a/dts/src/arm/ti/omap/am3517.dtsi +++ b/dts/src/arm/ti/omap/am3517.dtsi @@ -162,12 +162,13 @@ clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; + ranges = <0 0x50000000 0x10000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; }; }; diff --git a/dts/src/arm/ti/omap/am35xx-clocks.dtsi b/dts/src/arm/ti/omap/am35xx-clocks.dtsi index 0ee7afaa0e..b521139e6f 100644 --- a/dts/src/arm/ti/omap/am35xx-clocks.dtsi +++ b/dts/src/arm/ti/omap/am35xx-clocks.dtsi @@ -66,22 +66,23 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ipss_ick: clock-ipss-ick { + ipss_ick: clock-ipss-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,am35xx-interface-clock"; clock-output-names = "ipss_ick"; clocks = <&core_l3_ick>; - ti,bit-shift = <4>; }; - uart4_ick_am35xx: clock-uart4-ick-am35xx { + uart4_ick_am35xx: clock-uart4-ick-am35xx@23 { + reg = <23>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart4_ick_am35xx"; clocks = <&core_l4_ick>; - ti,bit-shift = <23>; }; }; @@ -101,14 +102,15 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - uart4_fck_am35xx: clock-uart4-fck-am35xx { + uart4_fck_am35xx: clock-uart4-fck-am35xx@23 { + reg = <23>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart4_fck_am35xx"; clocks = <&core_48m_fck>; - ti,bit-shift = <23>; }; }; }; diff --git a/dts/src/arm/ti/omap/am4372.dtsi b/dts/src/arm/ti/omap/am4372.dtsi index 9d2c064534..5fd1b380ec 100644 --- a/dts/src/arm/ti/omap/am4372.dtsi +++ b/dts/src/arm/ti/omap/am4372.dtsi @@ -719,6 +719,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; + + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; }; diff --git a/dts/src/arm/ti/omap/am437x-cm-t43.dts b/dts/src/arm/ti/omap/am437x-cm-t43.dts index 9ec75d03ea..172516a766 100644 --- a/dts/src/arm/ti/omap/am437x-cm-t43.dts +++ b/dts/src/arm/ti/omap/am437x-cm-t43.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/ */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am437x-sbc-t43.dts b/dts/src/arm/ti/omap/am437x-sbc-t43.dts index 34a5407bee..5ec57dcb06 100644 --- a/dts/src/arm/ti/omap/am437x-sbc-t43.dts +++ b/dts/src/arm/ti/omap/am437x-sbc-t43.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/ */ #include "am437x-cm-t43.dts" diff --git a/dts/src/arm/ti/omap/am5729-beagleboneai.dts b/dts/src/arm/ti/omap/am5729-beagleboneai.dts index 3e834fc7e3..eb1ec85aba 100644 --- a/dts/src/arm/ti/omap/am5729-beagleboneai.dts +++ b/dts/src/arm/ti/omap/am5729-beagleboneai.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/am57xx-cl-som-am57x.dts b/dts/src/arm/ti/omap/am57xx-cl-som-am57x.dts index 4fd831ff20..d6e3152b02 100644 --- a/dts/src/arm/ti/omap/am57xx-cl-som-am57x.dts +++ b/dts/src/arm/ti/omap/am57xx-cl-som-am57x.dts @@ -2,7 +2,7 @@ /* * Support for CompuLab CL-SOM-AM57x System-on-Module * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab Ltd. - https://www.compulab.co.il/ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> */ diff --git a/dts/src/arm/ti/omap/am57xx-sbc-am57x.dts b/dts/src/arm/ti/omap/am57xx-sbc-am57x.dts index 363115afb0..64675f4edb 100644 --- a/dts/src/arm/ti/omap/am57xx-sbc-am57x.dts +++ b/dts/src/arm/ti/omap/am57xx-sbc-am57x.dts @@ -2,7 +2,7 @@ /* * Support for CompuLab SBC-AM57x single board computer * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab Ltd. - https://www.compulab.co.il/ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> */ diff --git a/dts/src/arm/ti/omap/compulab-sb-som.dtsi b/dts/src/arm/ti/omap/compulab-sb-som.dtsi index f5e6216718..8a8fa1b2b2 100644 --- a/dts/src/arm/ti/omap/compulab-sb-som.dtsi +++ b/dts/src/arm/ti/omap/compulab-sb-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/ */ / { diff --git a/dts/src/arm/ti/omap/dra7-l4.dtsi b/dts/src/arm/ti/omap/dra7-l4.dtsi index 5733e3a4ea..6e67d99832 100644 --- a/dts/src/arm/ti/omap/dra7-l4.dtsi +++ b/dts/src/arm/ti/omap/dra7-l4.dtsi @@ -80,7 +80,7 @@ }; }; - phy_gmii_sel: phy-gmii-sel { + phy_gmii_sel: phy-gmii-sel@554 { compatible = "ti,dra7xx-phy-gmii-sel"; reg = <0x554 0x4>; #phy-cells = <1>; diff --git a/dts/src/arm/ti/omap/dra7.dtsi b/dts/src/arm/ti/omap/dra7.dtsi index 6509c742fb..164fa88c45 100644 --- a/dts/src/arm/ti/omap/dra7.dtsi +++ b/dts/src/arm/ti/omap/dra7.dtsi @@ -638,7 +638,7 @@ }; }; - abb_mpu: regulator-abb-mpu { + abb_mpu: regulator-abb-mpu@4ae07ddc { compatible = "ti,abb-v3"; regulator-name = "abb_mpu"; #address-cells = <0>; @@ -671,7 +671,7 @@ >; }; - abb_ivahd: regulator-abb-ivahd { + abb_ivahd: regulator-abb-ivahd@4ae07e34 { compatible = "ti,abb-v3"; regulator-name = "abb_ivahd"; #address-cells = <0>; @@ -704,7 +704,7 @@ >; }; - abb_dspeve: regulator-abb-dspeve { + abb_dspeve: regulator-abb-dspeve@4ae07e30 { compatible = "ti,abb-v3"; regulator-name = "abb_dspeve"; #address-cells = <0>; @@ -737,7 +737,7 @@ >; }; - abb_gpu: regulator-abb-gpu { + abb_gpu: regulator-abb-gpu@4ae07de4 { compatible = "ti,abb-v3"; regulator-name = "abb_gpu"; #address-cells = <0>; @@ -850,12 +850,19 @@ <SYSC_IDLE_SMART>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; + + gpu@0 { + compatible = "ti,am5728-gpu", "img,powervr-sgx544"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + }; }; crossbar_mpu: crossbar@4a002a48 { diff --git a/dts/src/arm/ti/omap/dra74x-p.dtsi b/dts/src/arm/ti/omap/dra74x-p.dtsi index 006189dad7..bb5239ae16 100644 --- a/dts/src/arm/ti/omap/dra74x-p.dtsi +++ b/dts/src/arm/ti/omap/dra74x-p.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/dts/src/arm/ti/omap/dra7xx-clocks.dtsi b/dts/src/arm/ti/omap/dra7xx-clocks.dtsi index 04a7a6d1d5..06466d36ca 100644 --- a/dts/src/arm/ti/omap/dra7xx-clocks.dtsi +++ b/dts/src/arm/ti/omap/dra7xx-clocks.dtsi @@ -1685,7 +1685,7 @@ reg = <0x0558>; }; - sys_32k_ck: clock-sys-32k { + sys_32k_ck: clock-sys-32k@6c4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "sys_32k_ck"; diff --git a/dts/src/arm/ti/omap/omap3430es1-clocks.dtsi b/dts/src/arm/ti/omap/omap3430es1-clocks.dtsi index 24adfac26b..6e754d265f 100644 --- a/dts/src/arm/ti/omap/omap3430es1-clocks.dtsi +++ b/dts/src/arm/ti/omap/omap3430es1-clocks.dtsi @@ -50,30 +50,31 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - d2d_26m_fck: clock-d2d-26m-fck { + d2d_26m_fck: clock-d2d-26m-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "d2d_26m_fck"; clocks = <&sys_ck>; - ti,bit-shift = <3>; }; - fshostusb_fck: clock-fshostusb-fck { + fshostusb_fck: clock-fshostusb-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "fshostusb_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <5>; }; - ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 { + ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clock-output-names = "ssi_ssr_gate_fck_3430es1"; clocks = <&corex2_fck>; - ti,bit-shift = <0>; }; }; @@ -81,23 +82,24 @@ compatible = "ti,clksel"; reg = <0xa40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 { + ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clock-output-names = "ssi_ssr_div_fck_3430es1"; clocks = <&corex2_fck>; - ti,bit-shift = <8>; ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; }; - usb_l4_div_ick: clock-usb-l4-div-ick { + usb_l4_div_ick: clock-usb-l4-div-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clock-output-names = "usb_l4_div_ick"; clocks = <&l4_ick>; - ti,bit-shift = <4>; ti,max-div = <1>; ti,index-starts-at-one; }; @@ -121,38 +123,39 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 { + hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clock-output-names = "hsotgusb_ick_3430es1"; clocks = <&core_l3_ick>; - ti,bit-shift = <4>; }; - fac_ick: clock-fac-ick { + fac_ick: clock-fac-ick@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "fac_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <8>; }; - ssi_ick: clock-ssi-ick-3430es1 { + ssi_ick: clock-ssi-ick-3430es1@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clock-output-names = "ssi_ick_3430es1"; clocks = <&ssi_l4_ick>; - ti,bit-shift = <0>; }; - usb_l4_gate_ick: clock-usb-l4-gate-ick { + usb_l4_gate_ick: clock-usb-l4-gate-ick@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,composite-interface-clock"; clock-output-names = "usb_l4_gate_ick"; clocks = <&l4_ick>; - ti,bit-shift = <5>; }; }; @@ -174,14 +177,15 @@ compatible = "ti,clksel"; reg = <0xe00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 { + dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "dss1_alwon_fck_3430es1"; clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; ti,set-rate-parent; }; }; diff --git a/dts/src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi b/dts/src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi index 8374532f20..ca6372711b 100644 --- a/dts/src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi +++ b/dts/src/arm/ti/omap/omap34xx-omap36xx-clocks.dtsi @@ -17,46 +17,47 @@ compatible = "ti,clksel"; reg = <0xa14>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - aes1_ick: clock-aes1-ick { + aes1_ick: clock-aes1-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "aes1_ick"; clocks = <&security_l4_ick2>; - ti,bit-shift = <3>; }; - rng_ick: clock-rng-ick { + rng_ick: clock-rng-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "rng_ick"; clocks = <&security_l4_ick2>; - ti,bit-shift = <2>; }; - sha11_ick: clock-sha11-ick { + sha11_ick: clock-sha11-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "sha11_ick"; clocks = <&security_l4_ick2>; - ti,bit-shift = <1>; }; - des1_ick: clock-des1-ick { + des1_ick: clock-des1-ick@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "des1_ick"; clocks = <&security_l4_ick2>; - ti,bit-shift = <0>; }; - pka_ick: clock-pka-ick { + pka_ick: clock-pka-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "pka_ick"; clocks = <&security_l3_ick>; - ti,bit-shift = <4>; }; }; @@ -65,23 +66,24 @@ compatible = "ti,clksel"; reg = <0xf00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - cam_mclk: clock-cam-mclk { + cam_mclk: clock-cam-mclk@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "cam_mclk"; clocks = <&dpll4_m5x2_ck>; - ti,bit-shift = <0>; ti,set-rate-parent; }; - csi2_96m_fck: clock-csi2-96m-fck { + csi2_96m_fck: clock-csi2-96m-fck@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "csi2_96m_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <1>; }; }; @@ -105,46 +107,47 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - icr_ick: clock-icr-ick { + icr_ick: clock-icr-ick@29 { + reg = <29>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "icr_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <29>; }; - des2_ick: clock-des2-ick { + des2_ick: clock-des2-ick@26 { + reg = <26>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "des2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <26>; }; - mspro_ick: clock-mspro-ick { + mspro_ick: clock-mspro-ick@23 { + reg = <23>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mspro_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <23>; }; - mailboxes_ick: clock-mailboxes-ick { + mailboxes_ick: clock-mailboxes-ick@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mailboxes_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <7>; }; - sad2d_ick: clock-sad2d-ick { + sad2d_ick: clock-sad2d-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "sad2d_ick"; clocks = <&l3_ick>; - ti,bit-shift = <3>; }; }; @@ -160,22 +163,23 @@ compatible = "ti,clksel"; reg = <0xc00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - sr1_fck: clock-sr1-fck { + sr1_fck: clock-sr1-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "sr1_fck"; clocks = <&sys_ck>; - ti,bit-shift = <6>; }; - sr2_fck: clock-sr2-fck { + sr2_fck: clock-sr2-fck@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "sr2_fck"; clocks = <&sys_ck>; - ti,bit-shift = <7>; }; }; @@ -228,22 +232,23 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - modem_fck: clock-modem-fck { + modem_fck: clock-modem-fck@31 { + reg = <31>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "modem_fck"; clocks = <&sys_ck>; - ti,bit-shift = <31>; }; - mspro_fck: clock-mspro-fck { + mspro_fck: clock-mspro-fck@23 { + reg = <23>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mspro_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <23>; }; }; @@ -252,14 +257,15 @@ compatible = "ti,clksel"; reg = <0xa18>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #ssize-cells = <0>; - mad2d_ick: clock-mad2d-ick { + mad2d_ick: clock-mad2d-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mad2d_ick"; clocks = <&l3_ick>; - ti,bit-shift = <3>; }; }; diff --git a/dts/src/arm/ti/omap/omap34xx.dtsi b/dts/src/arm/ti/omap/omap34xx.dtsi index fc7233ac18..acdd0ee344 100644 --- a/dts/src/arm/ti/omap/omap34xx.dtsi +++ b/dts/src/arm/ti/omap/omap34xx.dtsi @@ -164,12 +164,13 @@ clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; + ranges = <0 0x50000000 0x10000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; }; diff --git a/dts/src/arm/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/dts/src/arm/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index dcc5cfcd1f..656cf80f87 100644 --- a/dts/src/arm/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/dts/src/arm/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -138,14 +138,15 @@ compatible = "ti,clksel"; reg = <0xa18>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - usbtll_ick: clock-usbtll-ick { + usbtll_ick: clock-usbtll-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "usbtll_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <2>; }; }; @@ -153,14 +154,15 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - mmchs3_ick: clock-mmchs3-ick { + mmchs3_ick: clock-mmchs3-ick@30 { + reg = <30>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mmchs3_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <30>; }; }; @@ -168,14 +170,15 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - mmchs3_fck: clock-mmchs3-fck { + mmchs3_fck: clock-mmchs3-fck@30 { + reg = <30>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mmchs3_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <30>; }; }; @@ -183,14 +186,15 @@ compatible = "ti,clksel"; reg = <0xe00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 { + dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,dss-gate-clock"; clock-output-names = "dss1_alwon_fck_3430es2"; clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; ti,set-rate-parent; }; }; diff --git a/dts/src/arm/ti/omap/omap36xx-clocks.dtsi b/dts/src/arm/ti/omap/omap36xx-clocks.dtsi index c5fdb2bd76..1e90f2b1ef 100644 --- a/dts/src/arm/ti/omap/omap36xx-clocks.dtsi +++ b/dts/src/arm/ti/omap/omap36xx-clocks.dtsi @@ -62,14 +62,15 @@ compatible = "ti,clksel"; reg = <0x1000>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - uart4_fck: clock-uart4-fck { + uart4_fck: clock-uart4-fck@18 { + reg = <18>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart4_fck"; clocks = <&per_48m_fck>; - ti,bit-shift = <18>; }; }; }; diff --git a/dts/src/arm/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi b/dts/src/arm/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi index c94eb86d3d..798acb839d 100644 --- a/dts/src/arm/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi +++ b/dts/src/arm/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi @@ -9,14 +9,15 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { + ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clock-output-names = "ssi_ssr_gate_fck_3430es2"; clocks = <&corex2_fck>; - ti,bit-shift = <0>; }; }; @@ -24,14 +25,15 @@ compatible = "ti,clksel"; reg = <0xa40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 { + ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clock-output-names = "ssi_ssr_div_fck_3430es2"; clocks = <&corex2_fck>; - ti,bit-shift = <8>; ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; }; }; @@ -54,22 +56,23 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 { + hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-hsotgusb-interface-clock"; clock-output-names = "hsotgusb_ick_3430es2"; clocks = <&core_l3_ick>; - ti,bit-shift = <4>; }; - ssi_ick: clock-ssi-ick-3430es2 { + ssi_ick: clock-ssi-ick-3430es2@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-ssi-interface-clock"; clock-output-names = "ssi_ick_3430es2"; clocks = <&ssi_l4_ick>; - ti,bit-shift = <0>; }; }; @@ -85,14 +88,15 @@ compatible = "ti,clksel"; reg = <0xc00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - usim_gate_fck: clock-usim-gate-fck { + usim_gate_fck: clock-usim-gate-fck@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "usim_gate_fck"; clocks = <&omap_96m_fck>; - ti,bit-shift = <9>; }; }; @@ -172,14 +176,15 @@ compatible = "ti,clksel"; reg = <0xc40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - usim_mux_fck: clock-usim-mux-fck { + usim_mux_fck: clock-usim-mux-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "usim_mux_fck"; clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; - ti,bit-shift = <3>; ti,index-starts-at-one; }; }; @@ -194,14 +199,15 @@ compatible = "ti,clksel"; reg = <0xc10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - usim_ick: clock-usim-ick { + usim_ick: clock-usim-ick@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "usim_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <9>; }; }; }; diff --git a/dts/src/arm/ti/omap/omap36xx.dtsi b/dts/src/arm/ti/omap/omap36xx.dtsi index e6d8070c1b..c3d79ecd56 100644 --- a/dts/src/arm/ti/omap/omap36xx.dtsi +++ b/dts/src/arm/ti/omap/omap36xx.dtsi @@ -211,10 +211,11 @@ #size-cells = <1>; ranges = <0 0x50000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = <21>; + }; }; }; diff --git a/dts/src/arm/ti/omap/omap3xxx-clocks.dtsi b/dts/src/arm/ti/omap/omap3xxx-clocks.dtsi index 2e13ca11ce..901ee79a66 100644 --- a/dts/src/arm/ti/omap/omap3xxx-clocks.dtsi +++ b/dts/src/arm/ti/omap/omap3xxx-clocks.dtsi @@ -83,29 +83,31 @@ compatible = "ti,clksel"; reg = <0x68>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - mcbsp5_mux_fck: clock-mcbsp5-mux-fck { + mcbsp5_mux_fck: clock-mcbsp5-mux-fck@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp5_mux_fck"; clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; }; - mcbsp3_mux_fck: clock-mcbsp3-mux-fck { + mcbsp3_mux_fck: clock-mcbsp3-mux-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp3_mux_fck"; clocks = <&per_96m_fck>, <&mcbsp_clks>; }; - mcbsp4_mux_fck: clock-mcbsp4-mux-fck { + mcbsp4_mux_fck: clock-mcbsp4-mux-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp4_mux_fck"; clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; }; }; @@ -120,22 +122,23 @@ compatible = "ti,clksel"; reg = <0x4>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - mcbsp1_mux_fck: clock-mcbsp1-mux-fck { + mcbsp1_mux_fck: clock-mcbsp1-mux-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp1_mux_fck"; clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; }; - mcbsp2_mux_fck: clock-mcbsp2-mux-fck { + mcbsp2_mux_fck: clock-mcbsp2-mux-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "mcbsp2_mux_fck"; clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <6>; }; }; @@ -259,79 +262,81 @@ compatible = "ti,clksel"; reg = <0x1140>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dpll3_m3_ck: clock-dpll3-m3 { + dpll3_m3_ck: clock-dpll3-m3@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll3_m3_ck"; clocks = <&dpll3_ck>; - ti,bit-shift = <16>; ti,max-div = <31>; ti,index-starts-at-one; }; - dpll4_m6_ck: clock-dpll4-m6 { + dpll4_m6_ck: clock-dpll4-m6@24 { + reg = <24>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll4_m6_ck"; clocks = <&dpll4_ck>; - ti,bit-shift = <24>; ti,max-div = <63>; ti,index-starts-at-one; }; - emu_src_mux_ck: clock-emu-src-mux { + emu_src_mux_ck: clock-emu-src-mux@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "emu_src_mux_ck"; clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; }; - pclk_fck: clock-pclk-fck { + pclk_fck: clock-pclk-fck@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "pclk_fck"; clocks = <&emu_src_ck>; - ti,bit-shift = <8>; ti,max-div = <7>; ti,index-starts-at-one; }; - pclkx2_fck: clock-pclkx2-fck { + pclkx2_fck: clock-pclkx2-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "pclkx2_fck"; clocks = <&emu_src_ck>; - ti,bit-shift = <6>; ti,max-div = <3>; ti,index-starts-at-one; }; - atclk_fck: clock-atclk-fck { + atclk_fck: clock-atclk-fck@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "atclk_fck"; clocks = <&emu_src_ck>; - ti,bit-shift = <4>; ti,max-div = <3>; ti,index-starts-at-one; }; - traceclk_src_fck: clock-traceclk-src-fck { + traceclk_src_fck: clock-traceclk-src-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "traceclk_src_fck"; clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; }; - traceclk_fck: clock-traceclk-fck { + traceclk_fck: clock-traceclk-fck@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "traceclk_fck"; clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; ti,max-div = <7>; ti,index-starts-at-one; }; @@ -429,40 +434,41 @@ compatible = "ti,clksel"; reg = <0xd40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dpll3_m2_ck: clock-dpll3-m2 { + dpll3_m2_ck: clock-dpll3-m2@27 { + reg = <27>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll3_m2_ck"; clocks = <&dpll3_ck>; - ti,bit-shift = <27>; ti,max-div = <31>; ti,index-starts-at-one; }; - omap_96m_fck: clock-omap-96m-fck { + omap_96m_fck: clock-omap-96m-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "omap_96m_fck"; clocks = <&cm_96m_fck>, <&sys_ck>; - ti,bit-shift = <6>; }; - omap_54m_fck: clock-omap-54m-fck { + omap_54m_fck: clock-omap-54m-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "omap_54m_fck"; clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; - ti,bit-shift = <5>; }; - omap_48m_fck: clock-omap-48m-fck { + omap_48m_fck: clock-omap-48m-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "omap_48m_fck"; clocks = <&cm_96m_d2_fck>, <&sys_altclk>; - ti,bit-shift = <3>; }; }; @@ -471,19 +477,21 @@ compatible = "ti,clksel"; reg = <0xe40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dpll4_m3_ck: clock-dpll4-m3 { + dpll4_m3_ck: clock-dpll4-m3@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll4_m3_ck"; clocks = <&dpll4_ck>; - ti,bit-shift = <8>; ti,max-div = <32>; ti,index-starts-at-one; }; - dpll4_m4_ck: clock-dpll4-m4 { + dpll4_m4_ck: clock-dpll4-m4@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "dpll4_m4_ck"; @@ -603,29 +611,31 @@ compatible = "ti,clksel"; reg = <0xd70>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - clkout2_src_gate_ck: clock-clkout2-src-gate { + clkout2_src_gate_ck: clock-clkout2-src-gate@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clock-output-names = "clkout2_src_gate_ck"; clocks = <&core_ck>; - ti,bit-shift = <7>; }; - clkout2_src_mux_ck: clock-clkout2-src-mux { + clkout2_src_mux_ck: clock-clkout2-src-mux@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "clkout2_src_mux_ck"; clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; }; - sys_clkout2: clock-sys-clkout2 { + sys_clkout2: clock-sys-clkout2@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "sys_clkout2"; clocks = <&clkout2_src_ck>; - ti,bit-shift = <3>; ti,max-div = <64>; ti,index-power-of-two; }; @@ -666,9 +676,11 @@ compatible = "ti,clksel"; reg = <0xa40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - l3_ick: clock-l3-ick { + l3_ick: clock-l3-ick@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "l3_ick"; @@ -677,30 +689,30 @@ ti,index-starts-at-one; }; - l4_ick: clock-l4-ick { + l4_ick: clock-l4-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "l4_ick"; clocks = <&l3_ick>; - ti,bit-shift = <2>; ti,max-div = <3>; ti,index-starts-at-one; }; - gpt10_mux_fck: clock-gpt10-mux-fck { + gpt10_mux_fck: clock-gpt10-mux-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt10_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; }; - gpt11_mux_fck: clock-gpt11-mux-fck { + gpt11_mux_fck: clock-gpt11-mux-fck@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt11_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; }; }; @@ -709,19 +721,21 @@ compatible = "ti,clksel"; reg = <0xc40>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - rm_ick: clock-rm-ick { + rm_ick: clock-rm-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,divider-clock"; clock-output-names = "rm_ick"; clocks = <&l4_ick>; - ti,bit-shift = <1>; ti,max-div = <3>; ti,index-starts-at-one; }; - gpt1_mux_fck: clock-gpt1-mux-fck { + gpt1_mux_fck: clock-gpt1-mux-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt1_mux_fck"; @@ -734,134 +748,135 @@ compatible = "ti,clksel"; reg = <0xa00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gpt10_gate_fck: clock-gpt10-gate-fck { + gpt10_gate_fck: clock-gpt10-gate-fck@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt10_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <11>; }; - gpt11_gate_fck: clock-gpt11-gate-fck { + gpt11_gate_fck: clock-gpt11-gate-fck@12 { + reg = <12>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt11_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <12>; }; - mmchs2_fck: clock-mmchs2-fck { + mmchs2_fck: clock-mmchs2-fck@25 { + reg = <25>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mmchs2_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <25>; }; - mmchs1_fck: clock-mmchs1-fck { + mmchs1_fck: clock-mmchs1-fck@24 { + reg = <24>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mmchs1_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <24>; }; - i2c3_fck: clock-i2c3-fck { + i2c3_fck: clock-i2c3-fck@17 { + reg = <17>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "i2c3_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <17>; }; - i2c2_fck: clock-i2c2-fck { + i2c2_fck: clock-i2c2-fck@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "i2c2_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <16>; }; - i2c1_fck: clock-i2c1-fck { + i2c1_fck: clock-i2c1-fck@15 { + reg = <15>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "i2c1_fck"; clocks = <&core_96m_fck>; - ti,bit-shift = <15>; }; - mcbsp5_gate_fck: clock-mcbsp5-gate-fck { + mcbsp5_gate_fck: clock-mcbsp5-gate-fck@10 { + reg = <10>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp5_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <10>; }; - mcbsp1_gate_fck: clock-mcbsp1-gate-fck { + mcbsp1_gate_fck: clock-mcbsp1-gate-fck@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp1_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <9>; }; - mcspi4_fck: clock-mcspi4-fck { + mcspi4_fck: clock-mcspi4-fck@21 { + reg = <21>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mcspi4_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <21>; }; - mcspi3_fck: clock-mcspi3-fck { + mcspi3_fck: clock-mcspi3-fck@20 { + reg = <20>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mcspi3_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <20>; }; - mcspi2_fck: clock-mcspi2-fck { + mcspi2_fck: clock-mcspi2-fck@19 { + reg = <19>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mcspi2_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <19>; }; - mcspi1_fck: clock-mcspi1-fck { + mcspi1_fck: clock-mcspi1-fck@18 { + reg = <18>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "mcspi1_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <18>; }; - uart2_fck: clock-uart2-fck { + uart2_fck: clock-uart2-fck@14 { + reg = <14>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart2_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <14>; }; - uart1_fck: clock-uart1-fck { + uart1_fck: clock-uart1-fck@13 { + reg = <13>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart1_fck"; clocks = <&core_48m_fck>; - ti,bit-shift = <13>; }; - hdq_fck: clock-hdq-fck { + hdq_fck: clock-hdq-fck@22 { + reg = <22>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "hdq_fck"; clocks = <&core_12m_fck>; - ti,bit-shift = <22>; }; }; @@ -914,166 +929,167 @@ compatible = "ti,clksel"; reg = <0xa10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - sdrc_ick: clock-sdrc-ick { + sdrc_ick: clock-sdrc-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "sdrc_ick"; clocks = <&core_l3_ick>; - ti,bit-shift = <1>; }; - mmchs2_ick: clock-mmchs2-ick { + mmchs2_ick: clock-mmchs2-ick@25 { + reg = <25>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mmchs2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <25>; }; - mmchs1_ick: clock-mmchs1-ick { + mmchs1_ick: clock-mmchs1-ick@24 { + reg = <24>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mmchs1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <24>; }; - hdq_ick: clock-hdq-ick { + hdq_ick: clock-hdq-ick@22 { + reg = <22>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "hdq_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <22>; }; - mcspi4_ick: clock-mcspi4-ick { + mcspi4_ick: clock-mcspi4-ick@21 { + reg = <21>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcspi4_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <21>; }; - mcspi3_ick: clock-mcspi3-ick { + mcspi3_ick: clock-mcspi3-ick@20 { + reg = <20>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcspi3_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <20>; }; - mcspi2_ick: clock-mcspi2-ick { + mcspi2_ick: clock-mcspi2-ick@19 { + reg = <19>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcspi2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <19>; }; - mcspi1_ick: clock-mcspi1-ick { + mcspi1_ick: clock-mcspi1-ick@18 { + reg = <18>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcspi1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <18>; }; - i2c3_ick: clock-i2c3-ick { + i2c3_ick: clock-i2c3-ick@17 { + reg = <17>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "i2c3_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <17>; }; - i2c2_ick: clock-i2c2-ick { + i2c2_ick: clock-i2c2-ick@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "i2c2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <16>; }; - i2c1_ick: clock-i2c1-ick { + i2c1_ick: clock-i2c1-ick@15 { + reg = <15>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "i2c1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <15>; }; - uart2_ick: clock-uart2-ick { + uart2_ick: clock-uart2-ick@14 { + reg = <14>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <14>; }; - uart1_ick: clock-uart1-ick { + uart1_ick: clock-uart1-ick@13 { + reg = <13>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <13>; }; - gpt11_ick: clock-gpt11-ick { + gpt11_ick: clock-gpt11-ick@12 { + reg = <12>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt11_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <12>; }; - gpt10_ick: clock-gpt10-ick { + gpt10_ick: clock-gpt10-ick@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt10_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <11>; }; - mcbsp5_ick: clock-mcbsp5-ick { + mcbsp5_ick: clock-mcbsp5-ick@10 { + reg = <10>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp5_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <10>; }; - mcbsp1_ick: clock-mcbsp1-ick { + mcbsp1_ick: clock-mcbsp1-ick@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp1_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <9>; }; - omapctrl_ick: clock-omapctrl-ick { + omapctrl_ick: clock-omapctrl-ick@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "omapctrl_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <6>; }; - aes2_ick: clock-aes2-ick { + aes2_ick: clock-aes2-ick@28 { + reg = <28>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "aes2_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <28>; }; - sha12_ick: clock-sha12-ick { + sha12_ick: clock-sha12-ick@27 { + reg = <27>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "sha12_ick"; clocks = <&core_l4_ick>; - ti,bit-shift = <27>; }; }; @@ -1136,30 +1152,31 @@ compatible = "ti,clksel"; reg = <0xc00>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gpt1_gate_fck: clock-gpt1-gate-fck { + gpt1_gate_fck: clock-gpt1-gate-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt1_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <0>; }; - gpio1_dbck: clock-gpio1-dbck { + gpio1_dbck: clock-gpio1-dbck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio1_dbck"; clocks = <&wkup_32k_fck>; - ti,bit-shift = <3>; }; - wdt2_fck: clock-wdt2-fck { + wdt2_fck: clock-wdt2-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "wdt2_fck"; clocks = <&wkup_32k_fck>; - ti,bit-shift = <5>; }; }; @@ -1182,54 +1199,55 @@ compatible = "ti,clksel"; reg = <0xc10>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - wdt2_ick: clock-wdt2-ick { + wdt2_ick: clock-wdt2-ick@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "wdt2_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <5>; }; - wdt1_ick: clock-wdt1-ick { + wdt1_ick: clock-wdt1-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "wdt1_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <4>; }; - gpio1_ick: clock-gpio1-ick { + gpio1_ick: clock-gpio1-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio1_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <3>; }; - omap_32ksync_ick: clock-omap-32ksync-ick { + omap_32ksync_ick: clock-omap-32ksync-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "omap_32ksync_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <2>; }; - gpt12_ick: clock-gpt12-ick { + gpt12_ick: clock-gpt12-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt12_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <1>; }; - gpt1_ick: clock-gpt1-ick { + gpt1_ick: clock-gpt1-ick@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt1_ick"; clocks = <&wkup_l4_ick>; - ti,bit-shift = <0>; }; }; @@ -1254,150 +1272,151 @@ compatible = "ti,clksel"; reg = <0x1000>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - uart3_fck: clock-uart3-fck { + uart3_fck: clock-uart3-fck@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "uart3_fck"; clocks = <&per_48m_fck>; - ti,bit-shift = <11>; }; - gpt2_gate_fck: clock-gpt2-gate-fck { + gpt2_gate_fck: clock-gpt2-gate-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt2_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <3>; }; - gpt3_gate_fck: clock-gpt3-gate-fck { + gpt3_gate_fck: clock-gpt3-gate-fck@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt3_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <4>; }; - gpt4_gate_fck: clock-gpt4-gate-fck { + gpt4_gate_fck: clock-gpt4-gate-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt4_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <5>; }; - gpt5_gate_fck: clock-gpt5-gate-fck { + gpt5_gate_fck: clock-gpt5-gate-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt5_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <6>; }; - gpt6_gate_fck: clock-gpt6-gate-fck { + gpt6_gate_fck: clock-gpt6-gate-fck@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt6_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <7>; }; - gpt7_gate_fck: clock-gpt7-gate-fck { + gpt7_gate_fck: clock-gpt7-gate-fck@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt7_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <8>; }; - gpt8_gate_fck: clock-gpt8-gate-fck { + gpt8_gate_fck: clock-gpt8-gate-fck@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt8_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <9>; }; - gpt9_gate_fck: clock-gpt9-gate-fck { + gpt9_gate_fck: clock-gpt9-gate-fck@10 { + reg = <10>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "gpt9_gate_fck"; clocks = <&sys_ck>; - ti,bit-shift = <10>; }; - gpio6_dbck: clock-gpio6-dbck { + gpio6_dbck: clock-gpio6-dbck@17 { + reg = <17>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio6_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <17>; }; - gpio5_dbck: clock-gpio5-dbck { + gpio5_dbck: clock-gpio5-dbck@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio5_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <16>; }; - gpio4_dbck: clock-gpio4-dbck { + gpio4_dbck: clock-gpio4-dbck@15 { + reg = <15>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio4_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <15>; }; - gpio3_dbck: clock-gpio3-dbck { + gpio3_dbck: clock-gpio3-dbck@14 { + reg = <14>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio3_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <14>; }; - gpio2_dbck: clock-gpio2-dbck { + gpio2_dbck: clock-gpio2-dbck@13 { + reg = <13>; #clock-cells = <0>; compatible = "ti,gate-clock"; clock-output-names = "gpio2_dbck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <13>; }; - wdt3_fck: clock-wdt3-fck { + wdt3_fck: clock-wdt3-fck@12 { + reg = <12>; #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clock-output-names = "wdt3_fck"; clocks = <&per_32k_alwon_fck>; - ti,bit-shift = <12>; }; - mcbsp2_gate_fck: clock-mcbsp2-gate-fck { + mcbsp2_gate_fck: clock-mcbsp2-gate-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp2_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <0>; }; - mcbsp3_gate_fck: clock-mcbsp3-gate-fck { + mcbsp3_gate_fck: clock-mcbsp3-gate-fck@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp3_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <1>; }; - mcbsp4_gate_fck: clock-mcbsp4-gate-fck { + mcbsp4_gate_fck: clock-mcbsp4-gate-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clock-output-names = "mcbsp4_gate_fck"; clocks = <&mcbsp_clks>; - ti,bit-shift = <2>; }; }; @@ -1406,69 +1425,71 @@ compatible = "ti,clksel"; reg = <0x1040>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gpt2_mux_fck: clock-gpt2-mux-fck { + gpt2_mux_fck: clock-gpt2-mux-fck@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt2_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; }; - gpt3_mux_fck: clock-gpt3-mux-fck { + gpt3_mux_fck: clock-gpt3-mux-fck@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt3_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <1>; }; - gpt4_mux_fck: clock-gpt4-mux-fck { + gpt4_mux_fck: clock-gpt4-mux-fck@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt4_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <2>; }; - gpt5_mux_fck: clock-gpt5-mux-fck { + gpt5_mux_fck: clock-gpt5-mux-fck@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt5_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <3>; }; - gpt6_mux_fck: clock-gpt6-mux-fck { + gpt6_mux_fck: clock-gpt6-mux-fck@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt6_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <4>; }; - gpt7_mux_fck: clock-gpt7-mux-fck { + gpt7_mux_fck: clock-gpt7-mux-fck@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt7_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <5>; }; - gpt8_mux_fck: clock-gpt8-mux-fck { + gpt8_mux_fck: clock-gpt8-mux-fck@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt8_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; }; - gpt9_mux_fck: clock-gpt9-mux-fck { + gpt9_mux_fck: clock-gpt9-mux-fck@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clock-output-names = "gpt9_mux_fck"; clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; }; }; @@ -1541,158 +1562,159 @@ compatible = "ti,clksel"; reg = <0x1010>; #clock-cells = <2>; - #address-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - gpio6_ick: clock-gpio6-ick { + gpio6_ick: clock-gpio6-ick@17 { + reg = <17>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio6_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <17>; }; - gpio5_ick: clock-gpio5-ick { + gpio5_ick: clock-gpio5-ick@16 { + reg = <16>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio5_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <16>; }; - gpio4_ick: clock-gpio4-ick { + gpio4_ick: clock-gpio4-ick@15 { + reg = <15>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio4_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <15>; }; - gpio3_ick: clock-gpio3-ick { + gpio3_ick: clock-gpio3-ick@14 { + reg = <14>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <14>; }; - gpio2_ick: clock-gpio2-ick { + gpio2_ick: clock-gpio2-ick@13 { + reg = <13>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpio2_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <13>; }; - wdt3_ick: clock-wdt3-ick { + wdt3_ick: clock-wdt3-ick@12 { + reg = <12>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "wdt3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <12>; }; - uart3_ick: clock-uart3-ick { + uart3_ick: clock-uart3-ick@11 { + reg = <11>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <11>; }; - uart4_ick: clock-uart4-ick { + uart4_ick: clock-uart4-ick@18 { + reg = <18>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "uart4_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <18>; }; - gpt9_ick: clock-gpt9-ick { + gpt9_ick: clock-gpt9-ick@10 { + reg = <10>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt9_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <10>; }; - gpt8_ick: clock-gpt8-ick { + gpt8_ick: clock-gpt8-ick@9 { + reg = <9>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt8_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <9>; }; - gpt7_ick: clock-gpt7-ick { + gpt7_ick: clock-gpt7-ick@8 { + reg = <8>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt7_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <8>; }; - gpt6_ick: clock-gpt6-ick { + gpt6_ick: clock-gpt6-ick@7 { + reg = <7>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt6_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <7>; }; - gpt5_ick: clock-gpt5-ick { + gpt5_ick: clock-gpt5-ick@6 { + reg = <6>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt5_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <6>; }; - gpt4_ick: clock-gpt4-ick { + gpt4_ick: clock-gpt4-ick@5 { + reg = <5>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt4_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <5>; }; - gpt3_ick: clock-gpt3-ick { + gpt3_ick: clock-gpt3-ick@4 { + reg = <4>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <4>; }; - gpt2_ick: clock-gpt2-ick { + gpt2_ick: clock-gpt2-ick@3 { + reg = <3>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "gpt2_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <3>; }; - mcbsp2_ick: clock-mcbsp2-ick { + mcbsp2_ick: clock-mcbsp2-ick@0 { + reg = <0>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp2_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <0>; }; - mcbsp3_ick: clock-mcbsp3-ick { + mcbsp3_ick: clock-mcbsp3-ick@1 { + reg = <1>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp3_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <1>; }; - mcbsp4_ick: clock-mcbsp4-ick { + mcbsp4_ick: clock-mcbsp4-ick@2 { + reg = <2>; #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clock-output-names = "mcbsp4_ick"; clocks = <&per_l4_ick>; - ti,bit-shift = <2>; }; }; diff --git a/dts/src/arm/ti/omap/omap4-epson-embt2ws.dts b/dts/src/arm/ti/omap/omap4-epson-embt2ws.dts index 24f7d0285f..339e52ba36 100644 --- a/dts/src/arm/ti/omap/omap4-epson-embt2ws.dts +++ b/dts/src/arm/ti/omap/omap4-epson-embt2ws.dts @@ -85,6 +85,7 @@ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ interrupt-controller; #interrupt-cells = <1>; + system-power-controller; rtc { compatible = "ti,twl4030-rtc"; diff --git a/dts/src/arm/ti/omap/omap4-panda-common.dtsi b/dts/src/arm/ti/omap/omap4-panda-common.dtsi index f528511c25..97706d6296 100644 --- a/dts/src/arm/ti/omap/omap4-panda-common.dtsi +++ b/dts/src/arm/ti/omap/omap4-panda-common.dtsi @@ -408,6 +408,7 @@ reg = <0x48>; /* IRQ# = 7 */ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ + system-power-controller; }; twl6040: twl@4b { diff --git a/dts/src/arm/ti/omap/omap4-sdp.dts b/dts/src/arm/ti/omap/omap4-sdp.dts index b2cb93edbc..b535d24c61 100644 --- a/dts/src/arm/ti/omap/omap4-sdp.dts +++ b/dts/src/arm/ti/omap/omap4-sdp.dts @@ -439,7 +439,7 @@ /* * Ambient Light Sensor - * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf + * https://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf (defunct) */ bh1780@29 { compatible = "rohm,bh1780"; diff --git a/dts/src/arm/ti/omap/omap4.dtsi b/dts/src/arm/ti/omap/omap4.dtsi index 2bbff9032b..559b2bfe4c 100644 --- a/dts/src/arm/ti/omap/omap4.dtsi +++ b/dts/src/arm/ti/omap/omap4.dtsi @@ -501,10 +501,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap4430-gpu", "img,powervr-sgx540"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; }; /* diff --git a/dts/src/arm/ti/omap/omap5-igep0050.dts b/dts/src/arm/ti/omap/omap5-igep0050.dts index d4ca2e3a14..0368e32f67 100644 --- a/dts/src/arm/ti/omap/omap5-igep0050.dts +++ b/dts/src/arm/ti/omap/omap5-igep0050.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz/ + * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz/ */ /dts-v1/; diff --git a/dts/src/arm/ti/omap/omap5.dtsi b/dts/src/arm/ti/omap/omap5.dtsi index bac6fa8387..6a66214ad0 100644 --- a/dts/src/arm/ti/omap/omap5.dtsi +++ b/dts/src/arm/ti/omap/omap5.dtsi @@ -453,10 +453,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap5432-gpu", "img,powervr-sgx544"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; }; target-module@58000000 { diff --git a/dts/src/arm/ti/omap/twl4030.dtsi b/dts/src/arm/ti/omap/twl4030.dtsi index 93e07c1878..a5d9c57383 100644 --- a/dts/src/arm/ti/omap/twl4030.dtsi +++ b/dts/src/arm/ti/omap/twl4030.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/dts/src/arm/ti/omap/twl6030.dtsi b/dts/src/arm/ti/omap/twl6030.dtsi index 9d588cfaa5..8da969035c 100644 --- a/dts/src/arm/ti/omap/twl6030.dtsi +++ b/dts/src/arm/ti/omap/twl6030.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /* * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/twl6030.pdf + * https://www.ti.com/lit/ds/symlink/twl6030.pdf */ &twl { compatible = "ti,twl6030"; diff --git a/dts/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts b/dts/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts index 9ec49ac2f6..381d58cea0 100644 --- a/dts/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts +++ b/dts/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts @@ -291,6 +291,8 @@ }; &spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; diff --git a/dts/src/arm64/allwinner/sun50i-h6-tanix.dtsi b/dts/src/arm64/allwinner/sun50i-h6-tanix.dtsi index 4903d63581..855b7d43bc 100644 --- a/dts/src/arm64/allwinner/sun50i-h6-tanix.dtsi +++ b/dts/src/arm64/allwinner/sun50i-h6-tanix.dtsi @@ -166,6 +166,8 @@ }; &spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; diff --git a/dts/src/arm64/allwinner/sun50i-h6.dtsi b/dts/src/arm64/allwinner/sun50i-h6.dtsi index ca1d287a0a..d11e5041ba 100644 --- a/dts/src/arm64/allwinner/sun50i-h6.dtsi +++ b/dts/src/arm64/allwinner/sun50i-h6.dtsi @@ -406,6 +406,7 @@ function = "spi1"; }; + /omit-if-no-ref/ spdif_tx_pin: spdif-tx-pin { pins = "PH7"; function = "spdif"; @@ -655,10 +656,8 @@ clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; clock-names = "apb", "spdif"; resets = <&ccu RST_BUS_SPDIF>; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; + dmas = <&dma 2>, <&dma 2>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts b/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts index dbce61b355..4bfb52609c 100644 --- a/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts +++ b/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1-manta.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. */ diff --git a/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1.dtsi index 1fed2b46cf..af421ba24c 100644 --- a/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1.dtsi +++ b/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-cb1.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. */ @@ -93,7 +93,7 @@ interrupt-controller; #interrupt-cells = <1>; - regulators{ + regulators { reg_dcdc1: dcdc1 { regulator-name = "vdd-gpu-sys"; regulator-min-microvolt = <810000>; diff --git a/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-pi.dts b/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-pi.dts index 832f08b2b2..ff84a37944 100644 --- a/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-pi.dts +++ b/dts/src/arm64/allwinner/sun50i-h616-bigtreetech-pi.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2023 Martin Botka <martin@biqu3d.com>. */ diff --git a/dts/src/arm64/allwinner/sun50i-h616.dtsi b/dts/src/arm64/allwinner/sun50i-h616.dtsi index d549d277d9..b2e85e52d1 100644 --- a/dts/src/arm64/allwinner/sun50i-h616.dtsi +++ b/dts/src/arm64/allwinner/sun50i-h616.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/reset/sun50i-h616-ccu.h> #include <dt-bindings/reset/sun50i-h6-r-ccu.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; @@ -133,11 +134,28 @@ #reset-cells = <1>; }; + dma: dma-controller@3002000 { + compatible = "allwinner,sun50i-h616-dma", + "allwinner,sun50i-a100-dma"; + reg = <0x03002000 0x1000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + dma-channels = <16>; + dma-requests = <49>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + sid: efuse@3006000 { compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; reg = <0x03006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x8>; + }; }; watchdog: watchdog@30090a0 { @@ -240,6 +258,11 @@ function = "spi1"; }; + spdif_tx_pin: spdif-tx-pin { + pins = "PH4"; + function = "spdif"; + }; + uart0_ph_pins: uart0-ph-pins { pins = "PH0", "PH1"; function = "uart0"; @@ -256,6 +279,12 @@ pins = "PG8", "PG9"; function = "uart1"; }; + + /omit-if-no-ref/ + x32clk_fanout_pin: x32clk-fanout-pin { + pins = "PG10"; + function = "clock"; + }; }; gic: interrupt-controller@3021000 { @@ -339,6 +368,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; + dmas = <&dma 14>, <&dma 14>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -350,6 +381,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -361,6 +394,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; + dmas = <&dma 16>, <&dma 16>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; @@ -372,6 +407,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART3>; + dmas = <&dma 17>, <&dma 17>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART3>; status = "disabled"; }; @@ -383,6 +420,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART4>; + dmas = <&dma 18>, <&dma 18>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART4>; status = "disabled"; }; @@ -394,6 +433,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART5>; + dmas = <&dma 19>, <&dma 19>; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART5>; status = "disabled"; }; @@ -405,6 +446,8 @@ reg = <0x05002000 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C0>; + dmas = <&dma 43>, <&dma 43>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -420,6 +463,8 @@ reg = <0x05002400 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; + dmas = <&dma 44>, <&dma 44>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C1>; status = "disabled"; #address-cells = <1>; @@ -433,6 +478,8 @@ reg = <0x05002800 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; + dmas = <&dma 45>, <&dma 45>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C2>; status = "disabled"; #address-cells = <1>; @@ -446,6 +493,8 @@ reg = <0x05002c00 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C3>; + dmas = <&dma 46>, <&dma 46>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C3>; status = "disabled"; #address-cells = <1>; @@ -459,6 +508,8 @@ reg = <0x05003000 0x400>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C4>; + dmas = <&dma 47>, <&dma 47>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_I2C4>; status = "disabled"; #address-cells = <1>; @@ -472,6 +523,8 @@ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_SPI0>; status = "disabled"; #address-cells = <1>; @@ -485,6 +538,8 @@ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_SPI1>; status = "disabled"; #address-cells = <1>; @@ -511,6 +566,34 @@ }; }; + spdif: spdif@5093000 { + compatible = "allwinner,sun50i-h616-spdif"; + reg = <0x05093000 0x400>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + clock-names = "apb", "spdif"; + resets = <&ccu RST_BUS_SPDIF>; + dmas = <&dma 2>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ths: thermal-sensor@5070400 { + compatible = "allwinner,sun50i-h616-ths"; + reg = <0x05070400 0x400>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + allwinner,sram = <&syscon>; + #thermal-sensor-cells = <1>; + }; + usbotg: usb@5100000 { compatible = "allwinner,sun50i-h616-musb", "allwinner,sun8i-h3-musb"; @@ -734,6 +817,8 @@ reg = <0x07081400 0x400>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB2_I2C>; + dmas = <&dma 48>, <&dma 48>; + dma-names = "rx", "tx"; resets = <&r_ccu RST_R_APB2_I2C>; status = "disabled"; #address-cells = <1>; @@ -755,4 +840,74 @@ #size-cells = <0>; }; }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths 2>; + sustainable-power = <1000>; + + trips { + cpu_threshold: cpu-trip-0 { + temperature = <60000>; + type = "passive"; + hysteresis = <0>; + }; + cpu_target: cpu-trip-1 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + cpu_critical: cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <500>; + polling-delay = <1000>; + thermal-sensors = <&ths 0>; + sustainable-power = <1100>; + + trips { + gpu_temp_critical: gpu-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + ve-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + + trips { + ve_temp_critical: ve-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 3>; + + trips { + ddr_temp_critical: ddr-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + }; }; diff --git a/dts/src/arm64/allwinner/sun50i-h618-longan-module-3h.dtsi b/dts/src/arm64/allwinner/sun50i-h618-longan-module-3h.dtsi new file mode 100644 index 0000000000..8c1263a393 --- /dev/null +++ b/dts/src/arm64/allwinner/sun50i-h618-longan-module-3h.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) Jisheng Zhang <jszhang@kernel.org> + */ + +#include "sun50i-h616.dtsi" + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8-pll"; + }; + + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-io"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +}; diff --git a/dts/src/arm64/allwinner/sun50i-h618-longanpi-3h.dts b/dts/src/arm64/allwinner/sun50i-h618-longanpi-3h.dts new file mode 100644 index 0000000000..18b29c6b86 --- /dev/null +++ b/dts/src/arm64/allwinner/sun50i-h618-longanpi-3h.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) Jisheng Zhang <jszhang@kernel.org> + */ + +/dts-v1/; + +#include "sun50i-h618-longan-module-3h.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Sipeed Longan Pi 3H"; + compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618"; + + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ + }; + + led-1 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */ + }; + }; + + reg_vcc5v: regulator-vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vcc5v>; + }; +}; + +&axp313 { + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +/* WiFi & BT combo module is connected to this Host */ +&ehci3 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + phy-supply = <®_vcc3v3>; + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v>; + usb2_vbus-supply = <®_vcc5v>; + status = "okay"; +}; diff --git a/dts/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts b/dts/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts index 8ea1fd41ae..ac0a2b7ea6 100644 --- a/dts/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts +++ b/dts/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts @@ -15,6 +15,7 @@ compatible = "transpeed,8k618-t", "allwinner,sun50i-h618"; aliases { + ethernet1 = &sdio_wifi; serial0 = &uart0; }; @@ -39,6 +40,15 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; }; &ehci0 { @@ -60,6 +70,19 @@ status = "okay"; }; +&mmc1 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + }; +}; + &mmc2 { vmmc-supply = <®_dldo1>; vqmmc-supply = <®_aldo1>; diff --git a/dts/src/arm64/allwinner/sun50i-h64-remix-mini-pc.dts b/dts/src/arm64/allwinner/sun50i-h64-remix-mini-pc.dts new file mode 100644 index 0000000000..b6e3c16979 --- /dev/null +++ b/dts/src/arm64/allwinner/sun50i-h64-remix-mini-pc.dts @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2023 ARM Ltd. + +/dts-v1/; + +#include "sun50i-a64.dtsi" +#include "sun50i-a64-cpu-opp.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Remix Mini PC"; + compatible = "jide,remix-mini-pc", "allwinner,sun50i-h64", + "allwinner,sun50i-a64"; + + aliases { + ethernet1 = &rtl8723bs; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_vcc5v: regulator-5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + post-power-on-delay-ms = <200>; + }; +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu1 { + cpu-supply = <®_dcdc2>; +}; + +&cpu2 { + cpu-supply = <®_dcdc2>; +}; + +&cpu3 { + cpu-supply = <®_dcdc2>; +}; + +&dai { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hdmi { + hvcc-supply = <®_dldo1>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +/* Connects to the AC200 chip */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&i2c0_pins { + bias-pull-up; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_aldo1>; + vqmmc-supply = <®_dldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: wifi@1 { + reg = <1>; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_eldo1>; + bus-width = <8>; + non-removable; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_dcdc1>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_dcdc1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo4>; + vcc-ph-supply = <®_dcdc1>; +}; + +&r_ir { + status = "okay"; +}; + +&r_pio { + /* + * We cannot add that supply for now since it would create a circular + * dependency between pinctrl, the regulator and the RSB Bus. + * + * vcc-pl-supply = <®_aldo2>; + */ +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin5-supply = <®_vcc5v>; + vin6-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + dldoin-supply = <®_vcc5v>; + eldoin-supply = <®_vcc5v>; + fldoin-supply = <®_vcc5v>; + drivevbus-supply = <®_vcc5v>; + ips-supply = <®_vcc5v>; + + status = "okay"; + }; +}; + +#include "axp803.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +/* Deviates from the reset default of 1.1V. */ +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-sys"; +}; + +®_aldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_aldo2 { + /* Specifying R_PIO consumer would create circular dependency. */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +/* AC200 power supply */ +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ave-33"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-cpvdd-dram-emmc"; +}; + +/* Supplies the arisc management core, needed by TF-A to power off cores. */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_hdmi { + vcc-hdmi-supply = <®_dcdc1>; +}; + +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Left DAC", "DACL", + "Right DAC", "DACR", + "Headphone Jack", "HP", + "ADCL", "Left ADC", + "ADCR", "Right ADC", + "MIC2", "Microphone Jack"; + status = "okay"; +}; + +/* On the (unpopulated) UART pads. */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723bs-bt"; + enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + max-speed = <1500000>; + }; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_drivevbus>; + status = "okay"; +}; diff --git a/dts/src/arm64/amlogic/amlogic-c3.dtsi b/dts/src/arm64/amlogic/amlogic-c3.dtsi index 2ad1f8eef1..32a754fe79 100644 --- a/dts/src/arm64/amlogic/amlogic-c3.dtsi +++ b/dts/src/arm64/amlogic/amlogic-c3.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/amlogic,c3-reset.h> / { cpus { @@ -81,6 +82,12 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + reset: reset-controller@2000 { + compatible = "amlogic,c3-reset"; + reg = <0x0 0x2000 0x0 0x98>; + #reset-cells = <1>; + }; + watchdog@2100 { compatible = "amlogic,c3-wdt", "amlogic,t7-wdt"; reg = <0x0 0x2100 0x0 0x10>; diff --git a/dts/src/arm64/amlogic/amlogic-t7.dtsi b/dts/src/arm64/amlogic/amlogic-t7.dtsi index a03c7667d2..5248bdf824 100644 --- a/dts/src/arm64/amlogic/amlogic-t7.dtsi +++ b/dts/src/arm64/amlogic/amlogic-t7.dtsi @@ -54,7 +54,7 @@ enable-method = "psci"; }; - cpu101: cpu@101{ + cpu101: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x101>; @@ -171,6 +171,16 @@ }; }; + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,t7-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + uart_a: serial@78000 { compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; reg = <0x0 0x78000 0x0 0x18>; diff --git a/dts/src/arm64/amlogic/meson-a1-ad402.dts b/dts/src/arm64/amlogic/meson-a1-ad402.dts index 1c20516fa6..4bc30af058 100644 --- a/dts/src/arm64/amlogic/meson-a1-ad402.dts +++ b/dts/src/arm64/amlogic/meson-a1-ad402.dts @@ -106,7 +106,7 @@ pinctrl-0 = <&spifc_pins>; pinctrl-names = "default"; - spi_nand@0 { + flash@0 { compatible = "spi-nand"; status = "okay"; reg = <0>; diff --git a/dts/src/arm64/amlogic/meson-a1.dtsi b/dts/src/arm64/amlogic/meson-a1.dtsi index 648e7f4942..c03e207ea6 100644 --- a/dts/src/arm64/amlogic/meson-a1.dtsi +++ b/dts/src/arm64/amlogic/meson-a1.dtsi @@ -450,6 +450,8 @@ <&clkc_periphs CLKID_USB_BUS>, <&clkc_periphs CLKID_USB_CTRL_IN>; clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl"; + assigned-clocks = <&clkc_periphs CLKID_USB_BUS>; + assigned-clock-rates = <64000000>; resets = <&reset RESET_USBCTRL>; reset-name = "usb_ctrl"; diff --git a/dts/src/arm64/amlogic/meson-axg-jethome-jethub-j1xx.dtsi b/dts/src/arm64/amlogic/meson-axg-jethome-jethub-j1xx.dtsi index db605f3a22..9b65ae818e 100644 --- a/dts/src/arm64/amlogic/meson-axg-jethome-jethub-j1xx.dtsi +++ b/dts/src/arm64/amlogic/meson-axg-jethome-jethub-j1xx.dtsi @@ -35,7 +35,7 @@ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -44,7 +44,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC5V"; regulator-min-microvolt = <5000000>; @@ -52,7 +52,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -61,7 +61,7 @@ regulator-always-on; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -70,7 +70,7 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <3300000>; @@ -79,7 +79,7 @@ regulator-always-on; }; - vccq_1v8: regulator-vccq_1v8 { + vccq_1v8: regulator-vccq-1v8 { compatible = "regulator-fixed"; regulator-name = "VCCQ_1V8"; regulator-min-microvolt = <1800000>; @@ -88,7 +88,7 @@ regulator-always-on; }; - usb_pwr: regulator-usb_pwr { + usb_pwr: regulator-usb-pwr { compatible = "regulator-fixed"; regulator-name = "USB_PWR"; regulator-min-microvolt = <5000000>; @@ -332,19 +332,3 @@ "", "", "", "", "", // 80 - 84 "", ""; // 85-86 }; - -&cpu0 { - #cooling-cells = <2>; -}; - -&cpu1 { - #cooling-cells = <2>; -}; - -&cpu2 { - #cooling-cells = <2>; -}; - -&cpu3 { - #cooling-cells = <2>; -}; diff --git a/dts/src/arm64/amlogic/meson-axg-s400.dts b/dts/src/arm64/amlogic/meson-axg-s400.dts index c8905663bc..7ed526f451 100644 --- a/dts/src/arm64/amlogic/meson-axg-s400.dts +++ b/dts/src/arm64/amlogic/meson-axg-s400.dts @@ -12,7 +12,7 @@ compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; model = "Amlogic Meson AXG S400 Development Board"; - adc_keys { + keys { compatible = "adc-keys"; io-channels = <&saradc 0>; io-channel-names = "buttons"; @@ -111,7 +111,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -119,7 +119,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -128,7 +128,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC5V"; regulator-min-microvolt = <5000000>; @@ -139,7 +139,7 @@ enable-active-high; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -148,7 +148,7 @@ regulator-always-on; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -157,7 +157,7 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; @@ -166,7 +166,7 @@ regulator-always-on; }; - usb_pwr: regulator-usb_pwr { + usb_pwr: regulator-usb-pwr { compatible = "regulator-fixed"; regulator-name = "USB_PWR"; regulator-min-microvolt = <5000000>; diff --git a/dts/src/arm64/amlogic/meson-axg.dtsi b/dts/src/arm64/amlogic/meson-axg.dtsi index 7e5ac9db93..6d12b760b9 100644 --- a/dts/src/arm64/amlogic/meson-axg.dtsi +++ b/dts/src/arm64/amlogic/meson-axg.dtsi @@ -74,6 +74,8 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + dynamic-power-coefficient = <140>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -83,6 +85,8 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + dynamic-power-coefficient = <140>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -92,6 +96,8 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + dynamic-power-coefficient = <140>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -101,6 +107,8 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + dynamic-power-coefficient = <140>; + #cooling-cells = <2>; }; l2: l2-cache0 { diff --git a/dts/src/arm64/amlogic/meson-g12-common.dtsi b/dts/src/arm64/amlogic/meson-g12-common.dtsi index ff68b911b7..9d5eab6595 100644 --- a/dts/src/arm64/amlogic/meson-g12-common.dtsi +++ b/dts/src/arm64/amlogic/meson-g12-common.dtsi @@ -2502,6 +2502,9 @@ clocks = <&clkc CLKID_NNA_CORE_CLK>, <&clkc CLKID_NNA_AXI_CLK>; clock-names = "core", "bus"; + assigned-clocks = <&clkc CLKID_NNA_CORE_CLK>, + <&clkc CLKID_NNA_AXI_CLK>; + assigned-clock-rates = <800000000>, <800000000>; resets = <&reset RESET_NNA>; status = "disabled"; }; diff --git a/dts/src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso b/dts/src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso new file mode 100644 index 0000000000..9591fdc31e --- /dev/null +++ b/dts/src/arm64/amlogic/meson-g12a-fbx8am-brcm.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2024 Freebox SAS + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/gpio/meson-g12a-gpio.h> + +&uart_A { + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + vbat-supply = <&vddao_3v3>; + vddio-supply = <&vddio_ao1v8>; + }; +}; + +&sd_emmc_a { + /* Per mmc-controller.yaml */ + #address-cells = <1>; + #size-cells = <0>; + /* NB: may be either AP6398S or AP6398SR3 wifi module */ + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/dts/src/arm64/amlogic/meson-g12a-fbx8am-realtek.dtso b/dts/src/arm64/amlogic/meson-g12a-fbx8am-realtek.dtso new file mode 100644 index 0000000000..55fff35b09 --- /dev/null +++ b/dts/src/arm64/amlogic/meson-g12a-fbx8am-realtek.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2024 Freebox SAS + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/gpio/meson-g12a-gpio.h> + +&uart_A { + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; + }; +}; + +&sd_emmc_a { + /* No explicit compatible for rtl8822cs sdio */ +}; diff --git a/dts/src/arm64/amlogic/meson-g12a-fbx8am.dts b/dts/src/arm64/amlogic/meson-g12a-fbx8am.dts new file mode 100644 index 0000000000..af211d8f39 --- /dev/null +++ b/dts/src/arm64/amlogic/meson-g12a-fbx8am.dts @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2024 Freebox SAS + +/* + * SEI codename: SEI530FB (based on SEI510) + * Freebox codename: fbx8am + * Commercial names: Freebox Pop, Player TV Free 4K + */ + +/dts-v1/; + +#include "meson-g12a.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/meson-g12a-gpio.h> +#include <dt-bindings/sound/meson-g12a-tohdmitx.h> + +/ { + compatible = "freebox,fbx8am", "amlogic,g12a"; + model = "Freebox Player Pop"; + chassis-type = "embedded"; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + /* Physical user-accessible reset button near USB port */ + power-button { + label = "Reset"; + linux,code = <BTN_MISC>; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + }; + }; + + spdif_dit: audio-codec-2 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ao_5v: regulator-ao-5v { + compatible = "regulator-fixed"; + regulator-name = "AO_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + dc_in: regulator-dc-in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + emmc_1v8: regulator-emmc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ao_5v>; + regulator-always-on; + }; + + vddao_3v3_t: regulator-vddao-3v3-t { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3_T"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + }; + + vddcpu: regulator-vddcpu { + /* + * SY8120B1ABC DC/DC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + pwm-supply = <&ao_5v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddio_ao1v8: regulator-vddio-ao1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <10>; /* required for 43752 */ + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "fbx8am"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "SPDIFOUT_A IN 0", "FRDDR_A OUT 3", + "SPDIFOUT_A IN 1", "FRDDR_B OUT 3", + "SPDIFOUT_A IN 2", "FRDDR_C OUT 3"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* spdif hdmi or toslink interface */ + dai-link-4 { + sound-dai = <&spdifout_a>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + + codec-1 { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; + }; + }; + + /* spdif hdmi interface */ + dai-link-5 { + sound-dai = <&spdifout_b>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-6 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&clkc_audio { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&spdifout_a { + pinctrl-0 = <&spdif_out_h_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spdifout_b { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&pdm { + pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>, + <&pdm_din2_z_pins>, <&pdm_din3_z_pins>, + <&pdm_dclk_z_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao1v8>; +}; + +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + /* WiFi firmware requires power to be kept while in suspend */ + keep-power-in-suspend; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; diff --git a/dts/src/arm64/amlogic/meson-g12a-radxa-zero.dts b/dts/src/arm64/amlogic/meson-g12a-radxa-zero.dts index fcd7e1d8e1..15b9bc2807 100644 --- a/dts/src/arm64/amlogic/meson-g12a-radxa-zero.dts +++ b/dts/src/arm64/amlogic/meson-g12a-radxa-zero.dts @@ -60,7 +60,7 @@ clock-names = "ext_clock"; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -68,7 +68,7 @@ regulator-always-on; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -77,7 +77,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -86,7 +86,7 @@ regulator-always-on; }; - hdmi_pw: regulator-hdmi_pw { + hdmi_pw: regulator-hdmi-pw { compatible = "regulator-fixed"; regulator-name = "HDMI_PW"; regulator-min-microvolt = <5000000>; @@ -95,7 +95,7 @@ regulator-always-on; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -104,7 +104,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-g12a-sei510.dts b/dts/src/arm64/amlogic/meson-g12a-sei510.dts index 4c4550dd47..61cb8135a3 100644 --- a/dts/src/arm64/amlogic/meson-g12a-sei510.dts +++ b/dts/src/arm64/amlogic/meson-g12a-sei510.dts @@ -15,7 +15,7 @@ compatible = "seirobotics,sei510", "amlogic,g12a"; model = "SEI Robotics SEI510"; - adc_keys { + keys { compatible = "adc-keys"; io-channels = <&saradc 0>; io-channel-names = "buttons"; @@ -83,7 +83,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -92,7 +92,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -100,7 +100,7 @@ regulator-always-on; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_1V8"; regulator-min-microvolt = <1800000>; @@ -109,7 +109,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -118,7 +118,7 @@ regulator-always-on; }; - vddao_3v3_t: regultor-vddao_3v3_t { + vddao_3v3_t: regulator-vddao-3v3-t { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3_T"; regulator-min-microvolt = <3300000>; @@ -147,7 +147,7 @@ regulator-always-on; }; - vddio_ao1v8: regulator-vddio_ao1v8 { + vddio_ao1v8: regulator-vddio-ao1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; regulator-min-microvolt = <1800000>; diff --git a/dts/src/arm64/amlogic/meson-g12a-u200.dts b/dts/src/arm64/amlogic/meson-g12a-u200.dts index 8355ddd7e9..3da7922d83 100644 --- a/dts/src/arm64/amlogic/meson-g12a-u200.dts +++ b/dts/src/arm64/amlogic/meson-g12a-u200.dts @@ -75,7 +75,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -84,7 +84,7 @@ regulator-always-on; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -92,7 +92,7 @@ regulator-always-on; }; - usb_pwr_en: regulator-usb_pwr_en { + usb_pwr_en: regulator-usb-pwr-en { compatible = "regulator-fixed"; regulator-name = "USB_PWR_EN"; regulator-min-microvolt = <5000000>; @@ -103,7 +103,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -112,7 +112,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -122,7 +122,7 @@ /* FIXME: actually controlled by VDDCPU_B_EN */ }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC_5V"; regulator-min-microvolt = <5000000>; @@ -133,7 +133,7 @@ enable-active-high; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -142,7 +142,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-g12a-x96-max.dts b/dts/src/arm64/amlogic/meson-g12a-x96-max.dts index 9b55982b6a..05c7a1e3f1 100644 --- a/dts/src/arm64/amlogic/meson-g12a-x96-max.dts +++ b/dts/src/arm64/amlogic/meson-g12a-x96-max.dts @@ -66,7 +66,7 @@ clock-names = "ext_clock"; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -75,7 +75,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -83,7 +83,7 @@ regulator-always-on; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -92,7 +92,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -102,7 +102,7 @@ /* FIXME: actually controlled by VDDCPU_B_EN */ }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC_5V"; regulator-min-microvolt = <5000000>; @@ -112,7 +112,7 @@ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -121,7 +121,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi b/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi index 91c9769fda..d80dd9a3da 100644 --- a/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi +++ b/dts/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi @@ -19,7 +19,7 @@ status = "okay"; }; - hub_5v: regulator-hub_5v { + hub_5v: regulator-hub-5v { compatible = "regulator-fixed"; regulator-name = "HUB_5V"; regulator-min-microvolt = <5000000>; diff --git a/dts/src/arm64/amlogic/meson-g12b-odroid.dtsi b/dts/src/arm64/amlogic/meson-g12b-odroid.dtsi index 9e12a34b28..09d959aefb 100644 --- a/dts/src/arm64/amlogic/meson-g12b-odroid.dtsi +++ b/dts/src/arm64/amlogic/meson-g12b-odroid.dtsi @@ -48,7 +48,7 @@ }; }; - tflash_vdd: regulator-tflash_vdd { + tflash_vdd: regulator-tflash-vdd { compatible = "regulator-fixed"; regulator-name = "TFLASH_VDD"; @@ -60,7 +60,7 @@ regulator-always-on; }; - tf_io: gpio-regulator-tf_io { + tf_io: gpio-regulator-tf-io { compatible = "regulator-gpio"; regulator-name = "TF_IO"; @@ -74,7 +74,7 @@ <1800000 1>; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -83,7 +83,7 @@ regulator-always-on; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -91,7 +91,7 @@ regulator-always-on; }; - usb_pwr_en: regulator-usb_pwr_en { + usb_pwr_en: regulator-usb-pwr-en { compatible = "regulator-fixed"; regulator-name = "USB_PWR_EN"; regulator-min-microvolt = <5000000>; @@ -103,7 +103,7 @@ enable-active-high; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "5V"; regulator-min-microvolt = <5000000>; @@ -114,7 +114,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -123,7 +123,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -171,7 +171,7 @@ regulator-always-on; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -180,7 +180,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-g12b-w400.dtsi b/dts/src/arm64/amlogic/meson-g12b-w400.dtsi index ac8b717825..4cb6930ffb 100644 --- a/dts/src/arm64/amlogic/meson-g12b-w400.dtsi +++ b/dts/src/arm64/amlogic/meson-g12b-w400.dtsi @@ -39,7 +39,7 @@ clock-names = "ext_clock"; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -48,7 +48,7 @@ regulator-always-on; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -56,7 +56,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC_5V"; regulator-min-microvolt = <5000000>; @@ -67,7 +67,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -76,7 +76,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gx-libretech-pc.dtsi b/dts/src/arm64/amlogic/meson-gx-libretech-pc.dtsi index 5e7b9273b0..efd662a452 100644 --- a/dts/src/arm64/amlogic/meson-gx-libretech-pc.dtsi +++ b/dts/src/arm64/amlogic/meson-gx-libretech-pc.dtsi @@ -84,7 +84,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -93,7 +93,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -120,7 +120,7 @@ }; }; - vcc_card: regulator-vcc_card { + vcc_card: regulator-vcc-card { compatible = "regulator-fixed"; regulator-name = "VCC_CARD"; regulator-min-microvolt = <3300000>; @@ -141,7 +141,7 @@ gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -150,7 +150,7 @@ regulator-always-on; }; - vddio_ao3v3: regulator-vddio_ao3v3 { + vddio_ao3v3: regulator-vddio-ao3v3 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO3V3"; regulator-min-microvolt = <3300000>; @@ -159,7 +159,7 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; diff --git a/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi b/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi index e59c3c92b1..08d6b69ba4 100644 --- a/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi +++ b/dts/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi @@ -50,28 +50,28 @@ regulator-always-on; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts b/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts index 4aab1ab705..cca129ce2c 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/dts/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts @@ -78,21 +78,21 @@ <3300000 1>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts b/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts index e6d2de7c45..c431986e6a 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts +++ b/dts/src/arm64/amlogic/meson-gxbb-odroidc2.dts @@ -67,7 +67,7 @@ regulator-always-on; }; - hdmi_p5v0: regulator-hdmi_p5v0 { + hdmi_p5v0: regulator-hdmi-p5v0 { compatible = "regulator-fixed"; regulator-name = "HDMI_P5V0"; regulator-min-microvolt = <5000000>; @@ -76,7 +76,7 @@ vin-supply = <&p5v0>; }; - tflash_vdd: regulator-tflash_vdd { + tflash_vdd: regulator-tflash-vdd { compatible = "regulator-fixed"; regulator-name = "TFLASH_VDD"; @@ -92,7 +92,7 @@ vin-supply = <&vddio_ao3v3>; }; - tf_io: gpio-regulator-tf_io { + tf_io: gpio-regulator-tf-io { compatible = "regulator-gpio"; regulator-name = "TF_IO"; @@ -148,7 +148,7 @@ vin-supply = <&p5v0>; }; - ddr3_1v5: regulator-ddr3_1v5 { + ddr3_1v5: regulator-ddr3-1v5 { compatible = "regulator-fixed"; regulator-name = "DDR3_1V5"; regulator-min-microvolt = <1500000>; diff --git a/dts/src/arm64/amlogic/meson-gxbb-p200.dts b/dts/src/arm64/amlogic/meson-gxbb-p200.dts index 591455c50e..7f94716876 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-p200.dts +++ b/dts/src/arm64/amlogic/meson-gxbb-p200.dts @@ -21,14 +21,14 @@ sound-name-prefix = "DIT"; }; - avdd18_usb_adc: regulator-avdd18_usb_adc { + avdd18_usb_adc: regulator-avdd18-usb-adc { compatible = "regulator-fixed"; regulator-name = "AVDD18_USB_ADC"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - adc_keys { + keys { compatible = "adc-keys"; io-channels = <&saradc 0>; io-channel-names = "buttons"; diff --git a/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi b/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi index e803a466fe..52d57773a7 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi +++ b/dts/src/arm64/amlogic/meson-gxbb-p20x.dtsi @@ -53,21 +53,21 @@ regulator-settling-time-down-us = <150000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi index 74df325342..255e93a0b3 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi +++ b/dts/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi @@ -47,28 +47,28 @@ enable-active-high; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxbb-wetek.dtsi b/dts/src/arm64/amlogic/meson-gxbb-wetek.dtsi index 94dafb9553..deb2952271 100644 --- a/dts/src/arm64/amlogic/meson-gxbb-wetek.dtsi +++ b/dts/src/arm64/amlogic/meson-gxbb-wetek.dtsi @@ -49,21 +49,21 @@ enable-active-high; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -71,7 +71,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts b/dts/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts index a29b49f051..90ef9c17d8 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/dts/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -42,7 +42,7 @@ }; }; - dc_5v: regulator-dc_5v { + dc_5v: regulator-dc-5v { compatible = "regulator-fixed"; regulator-name = "DC_5V"; regulator-min-microvolt = <5000000>; @@ -89,7 +89,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -98,7 +98,7 @@ regulator-always-on; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -107,7 +107,7 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; diff --git a/dts/src/arm64/amlogic/meson-gxl-s805x-p241.dts b/dts/src/arm64/amlogic/meson-gxl-s805x-p241.dts index c0d6eb5510..08a4718219 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s805x-p241.dts +++ b/dts/src/arm64/amlogic/meson-gxl-s805x-p241.dts @@ -64,28 +64,28 @@ reg = <0x0 0x0 0x0 0x20000000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/dts/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index a18d6d241a..2b94b6e528 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/dts/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -37,28 +37,28 @@ stdout-path = "serial0:115200n8"; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts index c8d74e61de..89fe5110f7 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts +++ b/dts/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts @@ -42,21 +42,21 @@ <3300000 1>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 2825db91e4..63b2086006 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -67,7 +67,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -76,7 +76,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -93,7 +93,7 @@ regulator-always-on; }; - vcc_card: regulator-vcc_card { + vcc_card: regulator-vcc-card { compatible = "regulator-fixed"; regulator-name = "VCC_CARD"; regulator-min-microvolt = <3300000>; @@ -114,7 +114,7 @@ gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; }; - vddio_ao3v3: regulator-vddio_ao3v3 { + vddio_ao3v3: regulator-vddio-ao3v3 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO3V3"; regulator-min-microvolt = <3300000>; @@ -139,7 +139,7 @@ regulator-settling-time-down-us = <50000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -148,7 +148,7 @@ regulator-always-on; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC 1V8"; regulator-min-microvolt = <1800000>; diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts index 27093e6ac9..8b26c9661b 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/dts/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -93,7 +93,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -117,7 +117,7 @@ regulator-settling-time-down-us = <50000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -125,7 +125,7 @@ }; /* This is provided by LDOs on the eMMC daugther card */ - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts index f1acca5c44..c79f9f2099 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ b/dts/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts @@ -42,21 +42,21 @@ <3300000 1>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi b/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi index a150cc0e18..7e7dc87ede 100644 --- a/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi +++ b/dts/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi @@ -39,28 +39,28 @@ regulator-always-on; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxm-khadas-vim2.dts b/dts/src/arm64/amlogic/meson-gxm-khadas-vim2.dts index 860f307494..07e7c3bede 100644 --- a/dts/src/arm64/amlogic/meson-gxm-khadas-vim2.dts +++ b/dts/src/arm64/amlogic/meson-gxm-khadas-vim2.dts @@ -112,28 +112,28 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddio_boot: regulator-vddio_boot { + vddio_boot: regulator-vddio-boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-gxm-s912-libretech-pc.dts b/dts/src/arm64/amlogic/meson-gxm-s912-libretech-pc.dts index 4eda9f634c..a66f19851a 100644 --- a/dts/src/arm64/amlogic/meson-gxm-s912-libretech-pc.dts +++ b/dts/src/arm64/amlogic/meson-gxm-s912-libretech-pc.dts @@ -14,7 +14,7 @@ "amlogic,meson-gxm"; model = "Libre Computer AML-S912-PC"; - typec2_vbus: regulator-typec2_vbus { + typec2_vbus: regulator-typec2-vbus { compatible = "regulator-fixed"; regulator-name = "TYPEC2_VBUS"; regulator-min-microvolt = <5000000>; diff --git a/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi b/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi index 514a6dd4b1..e78cc9b577 100644 --- a/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi +++ b/dts/src/arm64/amlogic/meson-khadas-vim3.dtsi @@ -80,7 +80,7 @@ clock-names = "ext_clock"; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -88,7 +88,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "VCC_5V"; regulator-min-microvolt = <5000000>; @@ -99,7 +99,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -108,7 +108,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -118,7 +118,7 @@ /* FIXME: actually controlled by VDDCPU_B_EN */ }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; regulator-min-microvolt = <1800000>; @@ -127,7 +127,7 @@ regulator-always-on; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_AO1V8"; regulator-min-microvolt = <1800000>; @@ -136,7 +136,7 @@ regulator-always-on; }; - vsys_3v3: regulator-vsys_3v3 { + vsys_3v3: regulator-vsys-3v3 { compatible = "regulator-fixed"; regulator-name = "VSYS_3V3"; regulator-min-microvolt = <3300000>; @@ -145,7 +145,7 @@ regulator-always-on; }; - usb_pwr: regulator-usb_pwr { + usb_pwr: regulator-usb-pwr { compatible = "regulator-fixed"; regulator-name = "USB_PWR"; regulator-min-microvolt = <5000000>; diff --git a/dts/src/arm64/amlogic/meson-libretech-cottonwood.dtsi b/dts/src/arm64/amlogic/meson-libretech-cottonwood.dtsi index 35e8f5bae9..082b72703c 100644 --- a/dts/src/arm64/amlogic/meson-libretech-cottonwood.dtsi +++ b/dts/src/arm64/amlogic/meson-libretech-cottonwood.dtsi @@ -150,7 +150,7 @@ gpio-open-drain; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -171,7 +171,7 @@ pwm-dutycycle-range = <100 0>; }; - vddio_ao18: regulator-vddio_ao18 { + vddio_ao18: regulator-vddio-ao18 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; @@ -180,7 +180,7 @@ vin-supply = <&vddao_3v3>; }; - vddio_c: regulator-vddio_c { + vddio_c: regulator-vddio-c { compatible = "regulator-gpio"; regulator-name = "VDDIO_C"; regulator-min-microvolt = <1800000>; diff --git a/dts/src/arm64/amlogic/meson-sm1-ac2xx.dtsi b/dts/src/arm64/amlogic/meson-sm1-ac2xx.dtsi index 46a34731f7..d1fa8b8bf7 100644 --- a/dts/src/arm64/amlogic/meson-sm1-ac2xx.dtsi +++ b/dts/src/arm64/amlogic/meson-sm1-ac2xx.dtsi @@ -54,7 +54,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -63,7 +63,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -71,7 +71,7 @@ regulator-always-on; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_1V8"; regulator-min-microvolt = <1800000>; @@ -80,7 +80,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -105,7 +105,7 @@ regulator-always-on; }; - vddio_ao1v8: regulator-vddio_ao1v8 { + vddio_ao1v8: regulator-vddio-ao1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; regulator-min-microvolt = <1800000>; diff --git a/dts/src/arm64/amlogic/meson-sm1-bananapi.dtsi b/dts/src/arm64/amlogic/meson-sm1-bananapi.dtsi index 62404743e6..81dce86290 100644 --- a/dts/src/arm64/amlogic/meson-sm1-bananapi.dtsi +++ b/dts/src/arm64/amlogic/meson-sm1-bananapi.dtsi @@ -82,7 +82,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_1V8"; regulator-min-microvolt = <1800000>; @@ -91,7 +91,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -99,7 +99,7 @@ regulator-always-on; }; - vddio_c: regulator-vddio_c { + vddio_c: regulator-vddio-c { compatible = "regulator-gpio"; regulator-name = "VDDIO_C"; regulator-min-microvolt = <1800000>; @@ -116,7 +116,7 @@ <3300000 1>; }; - tflash_vdd: regulator-tflash_vdd { + tflash_vdd: regulator-tflash-vdd { compatible = "regulator-fixed"; regulator-name = "TFLASH_VDD"; regulator-min-microvolt = <3300000>; @@ -127,7 +127,7 @@ regulator-always-on; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -136,7 +136,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -165,7 +165,7 @@ }; /* USB Hub Power Enable */ - vl_pwr_en: regulator-vl_pwr_en { + vl_pwr_en: regulator-vl-pwr-en { compatible = "regulator-fixed"; regulator-name = "VL_PWR_EN"; regulator-min-microvolt = <5000000>; diff --git a/dts/src/arm64/amlogic/meson-sm1-odroid-hc4.dts b/dts/src/arm64/amlogic/meson-sm1-odroid-hc4.dts index 846a2d6c20..0170139b8d 100644 --- a/dts/src/arm64/amlogic/meson-sm1-odroid-hc4.dts +++ b/dts/src/arm64/amlogic/meson-sm1-odroid-hc4.dts @@ -43,7 +43,7 @@ }; /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ - p12v_0: regulator-p12v_0 { + p12v_0: regulator-p12v-0 { compatible = "regulator-fixed"; regulator-name = "P12V_0"; regulator-min-microvolt = <12000000>; @@ -56,7 +56,7 @@ }; /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ - p12v_1: regulator-p12v_1 { + p12v_1: regulator-p12v-1 { compatible = "regulator-fixed"; regulator-name = "P12V_1"; regulator-min-microvolt = <12000000>; diff --git a/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi b/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi index 1db2327bbd..951eb8e3f0 100644 --- a/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi +++ b/dts/src/arm64/amlogic/meson-sm1-odroid.dtsi @@ -28,7 +28,7 @@ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; }; - tflash_vdd: regulator-tflash_vdd { + tflash_vdd: regulator-tflash-vdd { compatible = "regulator-fixed"; regulator-name = "TFLASH_VDD"; @@ -40,7 +40,7 @@ regulator-always-on; }; - tf_io: gpio-regulator-tf_io { + tf_io: gpio-regulator-tf-io { compatible = "regulator-gpio"; regulator-name = "TF_IO"; @@ -59,7 +59,7 @@ <1800000 1>; }; - flash_1v8: regulator-flash_1v8 { + flash_1v8: regulator-flash-1v8 { compatible = "regulator-fixed"; regulator-name = "FLASH_1V8"; regulator-min-microvolt = <1800000>; @@ -68,7 +68,7 @@ regulator-always-on; }; - main_12v: regulator-main_12v { + main_12v: regulator-main-12v { compatible = "regulator-fixed"; regulator-name = "12V"; regulator-min-microvolt = <12000000>; @@ -76,7 +76,7 @@ regulator-always-on; }; - vcc_5v: regulator-vcc_5v { + vcc_5v: regulator-vcc-5v { compatible = "regulator-fixed"; regulator-name = "5V"; regulator-min-microvolt = <5000000>; @@ -87,7 +87,7 @@ enable-active-high; }; - vcc_1v8: regulator-vcc_1v8 { + vcc_1v8: regulator-vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; @@ -96,7 +96,7 @@ regulator-always-on; }; - vcc_3v3: regulator-vcc_3v3 { + vcc_3v3: regulator-vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; @@ -125,7 +125,7 @@ regulator-always-on; }; - usb_pwr_en: regulator-usb_pwr_en { + usb_pwr_en: regulator-usb-pwr-en { compatible = "regulator-fixed"; regulator-name = "USB_PWR_EN"; regulator-min-microvolt = <5000000>; @@ -137,7 +137,7 @@ enable-active-high; }; - vddao_1v8: regulator-vddao_1v8 { + vddao_1v8: regulator-vddao-1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; regulator-min-microvolt = <1800000>; @@ -146,7 +146,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; diff --git a/dts/src/arm64/amlogic/meson-sm1-sei610.dts b/dts/src/arm64/amlogic/meson-sm1-sei610.dts index 109932068d..3581e14cbf 100644 --- a/dts/src/arm64/amlogic/meson-sm1-sei610.dts +++ b/dts/src/arm64/amlogic/meson-sm1-sei610.dts @@ -127,7 +127,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; regulator-min-microvolt = <5000000>; @@ -136,7 +136,7 @@ regulator-always-on; }; - dc_in: regulator-dc_in { + dc_in: regulator-dc-in { compatible = "regulator-fixed"; regulator-name = "DC_IN"; regulator-min-microvolt = <5000000>; @@ -144,7 +144,7 @@ regulator-always-on; }; - emmc_1v8: regulator-emmc_1v8 { + emmc_1v8: regulator-emmc-1v8 { compatible = "regulator-fixed"; regulator-name = "EMMC_1V8"; regulator-min-microvolt = <1800000>; @@ -153,7 +153,7 @@ regulator-always-on; }; - vddao_3v3: regulator-vddao_3v3 { + vddao_3v3: regulator-vddao-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3"; regulator-min-microvolt = <3300000>; @@ -163,7 +163,7 @@ }; /* Used by Tuner, RGB Led & IR Emitter LED array */ - vddao_3v3_t: regulator-vddao_3v3_t { + vddao_3v3_t: regulator-vddao-3v3-t { compatible = "regulator-fixed"; regulator-name = "VDDAO_3V3_T"; regulator-min-microvolt = <3300000>; @@ -192,7 +192,7 @@ regulator-always-on; }; - vddio_ao1v8: regulator-vddio_ao1v8 { + vddio_ao1v8: regulator-vddio-ao1v8 { compatible = "regulator-fixed"; regulator-name = "VDDIO_AO1V8"; regulator-min-microvolt = <1800000>; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts b/dts/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts index 78204d71ec..999d937302 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts @@ -125,6 +125,11 @@ }; }; +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + &nandcs { nand-ecc-strength = <4>; nand-ecc-step-size = <512>; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts b/dts/src/arm64/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts index fcf092c81b..19fc03ef47 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts @@ -155,6 +155,11 @@ }; }; +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + &nandcs { nand-ecc-strength = <4>; nand-ecc-step-size = <512>; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts b/dts/src/arm64/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts index d94a53d683..2a0d4ee3bd 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts @@ -166,11 +166,15 @@ }; }; +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + &nandcs { nand-ecc-strength = <4>; nand-ecc-step-size = <512>; nand-on-flash-bbt; - brcm,nand-has-wp; #address-cells = <1>; #size-cells = <0>; @@ -181,16 +185,17 @@ #size-cells = <1>; partition@0 { - compatible = "nvmem-cells"; label = "cferom"; reg = <0x0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x100000>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - base_mac_addr: mac@106a0 { - reg = <0x106a0 0x6>; + base_mac_addr: mac@106a0 { + reg = <0x106a0 0x6>; + }; }; }; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm4908.dtsi b/dts/src/arm64/broadcom/bcmbca/bcm4908.dtsi index 2f124b027b..e01cf4f540 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm4908.dtsi +++ b/dts/src/arm64/broadcom/bcmbca/bcm4908.dtsi @@ -227,9 +227,6 @@ brcm,num-gphy = <5>; brcm,num-rgmii-ports = <2>; - #address-cells = <1>; - #size-cells = <0>; - ports: ports { #address-cells = <1>; #size-cells = <0>; @@ -589,7 +586,7 @@ status = "disabled"; }; - nand-controller@1800 { + nand_controller: nand-controller@1800 { #address-cells = <1>; #size-cells = <0>; compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; @@ -597,7 +594,7 @@ reg-names = "nand", "nand-int-base"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "nand_ctlrdy"; - status = "okay"; + status = "disabled"; nandcs: nand@0 { compatible = "brcm,nandcs"; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm4912.dtsi b/dts/src/arm64/broadcom/bcmbca/bcm4912.dtsi index d658c81f72..14b2adfb81 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm4912.dtsi +++ b/dts/src/arm64/broadcom/bcmbca/bcm4912.dtsi @@ -138,6 +138,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm63146.dtsi b/dts/src/arm64/broadcom/bcmbca/bcm63146.dtsi index 4f474d4702..589b8a1efc 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm63146.dtsi +++ b/dts/src/arm64/broadcom/bcmbca/bcm63146.dtsi @@ -119,6 +119,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm63158.dtsi b/dts/src/arm64/broadcom/bcmbca/bcm63158.dtsi index 909f254dc4..48d618e758 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm63158.dtsi +++ b/dts/src/arm64/broadcom/bcmbca/bcm63158.dtsi @@ -137,6 +137,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm6813.dtsi b/dts/src/arm64/broadcom/bcmbca/bcm6813.dtsi index 685ae32951..1d1303cf90 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm6813.dtsi +++ b/dts/src/arm64/broadcom/bcmbca/bcm6813.dtsi @@ -138,6 +138,20 @@ status = "disabled"; }; + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm6856.dtsi b/dts/src/arm64/broadcom/bcmbca/bcm6856.dtsi index 820553ce54..00c62c1e5d 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm6856.dtsi +++ b/dts/src/arm64/broadcom/bcmbca/bcm6856.dtsi @@ -119,5 +119,19 @@ num-cs = <8>; status = "disabled"; }; + + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; }; }; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm6858.dtsi b/dts/src/arm64/broadcom/bcmbca/bcm6858.dtsi index 0eb93c2982..caeaf428dc 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm6858.dtsi +++ b/dts/src/arm64/broadcom/bcmbca/bcm6858.dtsi @@ -156,5 +156,19 @@ num-cs = <8>; status = "disabled"; }; + + nand_controller: nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + status = "disabled"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; }; }; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm94908.dts b/dts/src/arm64/broadcom/bcmbca/bcm94908.dts index c4e6e71f63..030ffa5364 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm94908.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm94908.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm94912.dts b/dts/src/arm64/broadcom/bcmbca/bcm94912.dts index e69cd68321..4b779e6c22 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm94912.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm94912.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm963146.dts b/dts/src/arm64/broadcom/bcmbca/bcm963146.dts index db2c82d6df..2851e8e41b 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm963146.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm963146.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm963158.dts b/dts/src/arm64/broadcom/bcmbca/bcm963158.dts index 25c12bc635..17dc594fe8 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm963158.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm963158.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm96813.dts b/dts/src/arm64/broadcom/bcmbca/bcm96813.dts index faba21f031..34832a7347 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm96813.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm96813.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm96856.dts b/dts/src/arm64/broadcom/bcmbca/bcm96856.dts index 9808331eed..e1396b5544 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm96856.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm96856.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm64/broadcom/bcmbca/bcm96858.dts b/dts/src/arm64/broadcom/bcmbca/bcm96858.dts index 1f561c8e13..30bbf6f291 100644 --- a/dts/src/arm64/broadcom/bcmbca/bcm96858.dts +++ b/dts/src/arm64/broadcom/bcmbca/bcm96858.dts @@ -32,3 +32,13 @@ &hsspi { status = "okay"; }; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; +}; diff --git a/dts/src/arm64/exynos/exynos850.dtsi b/dts/src/arm64/exynos/exynos850.dtsi index da3f4a791e..2ba67c3d06 100644 --- a/dts/src/arm64/exynos/exynos850.dtsi +++ b/dts/src/arm64/exynos/exynos850.dtsi @@ -184,6 +184,16 @@ clock-names = "fin_pll", "mct"; }; + pdma0: dma-controller@120c0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x120c0000 0x1000>; + clocks = <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; + arm,pl330-broken-no-flushp; + }; + gic: interrupt-controller@12a01000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -728,6 +738,24 @@ <&cmu_peri CLK_GOUT_SPI0_IPCLK>; clock-names = "pclk", "ipclk"; status = "disabled"; + + spi_0: spi@13940000 { + compatible = "samsung,exynos850-spi"; + reg = <0x13940000 0x30>; + clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, + <&cmu_peri CLK_GOUT_SPI0_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 5>, <&pdma0 4>; + dma-names = "tx", "rx"; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usi_cmgp0: usi@11d000c0 { @@ -769,6 +797,24 @@ clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; + + spi_1: spi@11d00000 { + compatible = "samsung,exynos850-spi"; + reg = <0x11d00000 0x30>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 12>, <&pdma0 13>; + dma-names = "tx", "rx"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usi_cmgp1: usi@11d200c0 { @@ -810,6 +856,24 @@ clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; + + spi_2: spi@11d20000 { + compatible = "samsung,exynos850-spi"; + reg = <0x11d20000 0x30>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 14>, <&pdma0 15>; + dma-names = "tx", "rx"; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; }; diff --git a/dts/src/arm64/exynos/google/gs101-oriole.dts b/dts/src/arm64/exynos/google/gs101-oriole.dts index 4a71f75220..6ccade2c8c 100644 --- a/dts/src/arm64/exynos/google/gs101-oriole.dts +++ b/dts/src/arm64/exynos/google/gs101-oriole.dts @@ -63,6 +63,20 @@ clock-frequency = <200000000>; }; +&hsi2c_8 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&hsi2c_12 { + status = "okay"; + /* TODO: add the devices once drivers exist */ +}; + &pinctrl_far_alive { key_voldown: key-voldown-pins { samsung,pins = "gpa7-3"; @@ -99,6 +113,16 @@ status = "okay"; }; +&usi8 { + samsung,mode = <USI_V2_I2C>; + status = "okay"; +}; + +&usi12 { + samsung,mode = <USI_V2_I2C>; + status = "okay"; +}; + &watchdog_cl0 { timeout-sec = <30>; status = "okay"; diff --git a/dts/src/arm64/exynos/google/gs101-pinctrl.dtsi b/dts/src/arm64/exynos/google/gs101-pinctrl.dtsi index e6a9776d4d..a675f822ac 100644 --- a/dts/src/arm64/exynos/google/gs101-pinctrl.dtsi +++ b/dts/src/arm64/exynos/google/gs101-pinctrl.dtsi @@ -251,7 +251,7 @@ #interrupt-cells = <2>; }; - pcie0_clkreq: pcie0-clkreq-pins{ + pcie0_clkreq: pcie0-clkreq-pins { samsung,pins = "gph0-1"; samsung,pin-function = <GS101_PIN_FUNC_2>; samsung,pin-pud = <GS101_PIN_PULL_UP>; diff --git a/dts/src/arm64/exynos/google/gs101.dtsi b/dts/src/arm64/exynos/google/gs101.dtsi index d838e3a7af..55e6bcb368 100644 --- a/dts/src/arm64/exynos/google/gs101.dtsi +++ b/dts/src/arm64/exynos/google/gs101.dtsi @@ -73,7 +73,7 @@ compatible = "arm,cortex-a55"; reg = <0x0000>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -83,7 +83,7 @@ compatible = "arm,cortex-a55"; reg = <0x0100>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -93,7 +93,7 @@ compatible = "arm,cortex-a55"; reg = <0x0200>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -103,7 +103,7 @@ compatible = "arm,cortex-a55"; reg = <0x0300>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -113,7 +113,7 @@ compatible = "arm,cortex-a76"; reg = <0x0400>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&ENYO_CPU_SLEEP>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -123,7 +123,7 @@ compatible = "arm,cortex-a76"; reg = <0x0500>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&ENYO_CPU_SLEEP>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -133,7 +133,7 @@ compatible = "arm,cortex-x1"; reg = <0x0600>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&HERA_CPU_SLEEP>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; @@ -143,7 +143,7 @@ compatible = "arm,cortex-x1"; reg = <0x0700>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&HERA_CPU_SLEEP>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; @@ -180,14 +180,6 @@ }; }; - /* TODO replace with CCF clock */ - dummy_clk: clock-3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12345>; - clock-output-names = "pclk"; - }; - /* ect node is required to be present by bootloader */ ect { }; @@ -292,6 +284,26 @@ clock-names = "bus", "sss"; }; + timer@10050000 { + compatible = "google,gs101-mct", + "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + watchdog_cl0: watchdog@10060000 { compatible = "google,gs101-wdt"; reg = <0x10060000 0x100>; @@ -339,9 +351,20 @@ }; }; + cmu_peric0: clock-controller@10800000 { + compatible = "google,gs101-cmu-peric0"; + reg = <0x10800000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + sysreg_peric0: syscon@10820000 { compatible = "google,gs101-peric0-sysreg", "syscon"; reg = <0x10820000 0x10000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; }; pinctrl_peric0: pinctrl@10840000 { @@ -350,6 +373,35 @@ interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; }; + usi8: usi@109700c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; + + hsi2c_8: i2c@10970000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + usi_uart: usi@10a000c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi"; @@ -357,7 +409,8 @@ ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&dummy_clk>, <&dummy_clk>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; samsung,mode = <USI_V2_UART>; @@ -366,19 +419,30 @@ serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - reg-io-width = <4>; interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&dummy_clk 0>, <&dummy_clk 0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; status = "disabled"; }; }; + cmu_peric1: clock-controller@10c00000 { + compatible = "google,gs101-cmu-peric1"; + reg = <0x10c00000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + sysreg_peric1: syscon@10c20000 { compatible = "google,gs101-peric1-sysreg", "syscon"; reg = <0x10c20000 0x10000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; }; pinctrl_peric1: pinctrl@10c40000 { @@ -387,6 +451,35 @@ interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; }; + usi12: usi@10d500c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x10d500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1010>; + status = "disabled"; + + hsi2c_12: i2c@10d50000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d50000 0xc0>; + interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; diff --git a/dts/src/arm64/freescale/fsl-ls1012a.dtsi b/dts/src/arm64/freescale/fsl-ls1012a.dtsi index 1e3fe3897b..fe9093b3c0 100644 --- a/dts/src/arm64/freescale/fsl-ls1012a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1012a.dtsi @@ -290,7 +290,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1012a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -351,24 +351,26 @@ }; i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + scl-gpios = <&gpio0 2 0>; status = "disabled"; }; i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; + compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; + scl-gpios = <&gpio0 13 0>; status = "disabled"; }; @@ -499,6 +501,7 @@ snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; sata: sata@3200000 { @@ -550,6 +553,7 @@ <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + big-endian; status = "disabled"; }; diff --git a/dts/src/arm64/freescale/fsl-ls1046a.dtsi b/dts/src/arm64/freescale/fsl-ls1046a.dtsi index 1515cec231..754a64be73 100644 --- a/dts/src/arm64/freescale/fsl-ls1046a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1046a.dtsi @@ -485,7 +485,6 @@ <0x00030005 0x00000042>, <0x00030006 0x0000004c>, <0x00030007 0x00000056>; - big-endian; #thermal-sensor-cells = <1>; }; diff --git a/dts/src/arm64/freescale/fsl-ls1088a.dtsi b/dts/src/arm64/freescale/fsl-ls1088a.dtsi index 8616d5e0c3..604bf88d70 100644 --- a/dts/src/arm64/freescale/fsl-ls1088a.dtsi +++ b/dts/src/arm64/freescale/fsl-ls1088a.dtsi @@ -591,6 +591,8 @@ reg = <0x00 0x03400000 0x0 0x00100000>, <0x20 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ + interrupt-names = "pme"; num-ib-windows = <24>; num-ob-windows = <256>; max-functions = /bits/ 8 <2>; @@ -628,6 +630,8 @@ reg = <0x00 0x03500000 0x0 0x00100000>, <0x28 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ + interrupt-names = "pme"; num-ib-windows = <6>; num-ob-windows = <6>; status = "disabled"; @@ -664,6 +668,8 @@ reg = <0x00 0x03600000 0x0 0x00100000>, <0x30 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ + interrupt-names = "pme"; num-ib-windows = <6>; num-ob-windows = <6>; status = "disabled"; diff --git a/dts/src/arm64/freescale/fsl-lx2160a.dtsi b/dts/src/arm64/freescale/fsl-lx2160a.dtsi index 6640b49670..e665c629e1 100644 --- a/dts/src/arm64/freescale/fsl-lx2160a.dtsi +++ b/dts/src/arm64/freescale/fsl-lx2160a.dtsi @@ -949,34 +949,50 @@ }; uart0: serial@21c0000 { - compatible = "arm,sbsa-uart","arm,pl011"; + compatible = "arm,pl011", "arm,primecell"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + clock-names = "uartclk", "apb_pclk"; reg = <0x0 0x21c0000 0x0 0x1000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; status = "disabled"; }; uart1: serial@21d0000 { - compatible = "arm,sbsa-uart","arm,pl011"; + compatible = "arm,pl011", "arm,primecell"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + clock-names = "uartclk", "apb_pclk"; reg = <0x0 0x21d0000 0x0 0x1000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; status = "disabled"; }; uart2: serial@21e0000 { - compatible = "arm,sbsa-uart","arm,pl011"; + compatible = "arm,pl011", "arm,primecell"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + clock-names = "uartclk", "apb_pclk"; reg = <0x0 0x21e0000 0x0 0x1000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; status = "disabled"; }; uart3: serial@21f0000 { - compatible = "arm,sbsa-uart","arm,pl011"; + compatible = "arm,pl011", "arm,primecell"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(8)>; + clock-names = "uartclk", "apb_pclk"; reg = <0x0 0x21f0000 0x0 0x1000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - current-speed = <115200>; status = "disabled"; }; diff --git a/dts/src/arm64/freescale/imx8-apalis-eval-v1.1.dtsi b/dts/src/arm64/freescale/imx8-apalis-eval-v1.1.dtsi new file mode 100644 index 0000000000..0f77f78f4d --- /dev/null +++ b/dts/src/arm64/freescale/imx8-apalis-eval-v1.1.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +#include "imx8-apalis-eval.dtsi" + +/* Apalis CAN1 */ +&flexcan1 { + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + status = "okay"; +}; diff --git a/dts/src/arm64/freescale/imx8-apalis-eval-v1.2.dtsi b/dts/src/arm64/freescale/imx8-apalis-eval-v1.2.dtsi new file mode 100644 index 0000000000..f5c6a0164f --- /dev/null +++ b/dts/src/arm64/freescale/imx8-apalis-eval-v1.2.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +#include "imx8-apalis-eval.dtsi" + +/ { + reg_3v3_mmc: regulator-3v3-mmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_mmc>; + enable-active-high; + gpio = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_MMC"; + startup-delay-us = <10000>; + }; + + reg_3v3_sd: regulator-3v3-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_sd>; + enable-active-high; + gpio = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SD"; + startup-delay-us = <10000>; + }; + + reg_can1: regulator-can1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + enable-active-high; + gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>; + regulator-name = "5V_SW_CAN1"; + startup-delay-us = <10000>; + }; + + reg_can2: regulator-can2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + enable-active-high; + gpio = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + regulator-name = "5V_SW_CAN2"; + startup-delay-us = <10000>; + }; +}; + +/* Apalis CAN1 */ +&flexcan1 { + xceiver-supply = <®_can1>; + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + xceiver-supply = <®_can2>; + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + /* Power/Current Measurement Sensor */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + }; +}; + +/* Apalis MMC1 */ +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>; + bus-width = <4>; + vmmc-supply = <®_3v3_mmc>; + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + vmmc-supply = <®_3v3_sd>; + status = "okay"; +}; + +&iomuxc { + + pinctrl_enable_3v3_mmc: enable3v3mmcgrp { + fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>; /* MXM3_148 */ + }; + + pinctrl_enable_3v3_sd: enable3v3sdgrp { + fsl,pins = <IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x00000021>; /* MXM3_152 */ + }; + + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = <IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021>; /* MXM3_158 */ + }; + + pinctrl_enable_can2_power: enablecan2powergrp { + fsl,pins = <IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021>; /* MXM3_156 */ + }; +}; diff --git a/dts/src/arm64/freescale/imx8-apalis-eval.dtsi b/dts/src/arm64/freescale/imx8-apalis-eval.dtsi index 685d4294f4..deecb96a15 100644 --- a/dts/src/arm64/freescale/imx8-apalis-eval.dtsi +++ b/dts/src/arm64/freescale/imx8-apalis-eval.dtsi @@ -35,18 +35,6 @@ status = "okay"; }; -/* Apalis CAN1 */ -&flexcan1 { - status = "okay"; -}; - -/* Apalis CAN2 */ -&flexcan2 { - status = "okay"; -}; - -/* TODO: GPU */ - /* Apalis I2C1 */ &i2c2 { status = "okay"; @@ -132,13 +120,3 @@ }; /* TODO: Apalis USBH4 SuperSpeed */ - -/* Apalis MMC1 */ -&usdhc2 { - status = "okay"; -}; - -/* Apalis SD1 */ -&usdhc3 { - status = "okay"; -}; diff --git a/dts/src/arm64/freescale/imx8-apalis-v1.1.dtsi b/dts/src/arm64/freescale/imx8-apalis-v1.1.dtsi index f69b0c1756..160153853b 100644 --- a/dts/src/arm64/freescale/imx8-apalis-v1.1.dtsi +++ b/dts/src/arm64/freescale/imx8-apalis-v1.1.dtsi @@ -261,7 +261,6 @@ reset-assert-us = <2>; reset-deassert-us = <2>; reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; - reset-names = "phy"; }; }; }; diff --git a/dts/src/arm64/freescale/imx8-ss-audio.dtsi b/dts/src/arm64/freescale/imx8-ss-audio.dtsi index f057c6b21b..07afeb78ed 100644 --- a/dts/src/arm64/freescale/imx8-ss-audio.dtsi +++ b/dts/src/arm64/freescale/imx8-ss-audio.dtsi @@ -4,6 +4,7 @@ * Dong Aisheng <aisheng.dong@nxp.com> */ +#include <dt-bindings/clock/imx8-clock.h> #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> @@ -14,12 +15,174 @@ audio_ipg_clk: clock-audio-ipg { clock-output-names = "audio_ipg_clk"; }; +clk_ext_aud_mclk0: clock-ext-aud-mclk0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ext_aud_mclk0"; +}; + +clk_ext_aud_mclk1: clock-ext-aud-mclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ext_aud_mclk1"; +}; + +clk_esai0_rx_clk: clock-esai0-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai0_rx_clk"; +}; + +clk_esai0_rx_hf_clk: clock-esai0-rx-hf { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai0_rx_hf_clk"; +}; + +clk_esai0_tx_clk: clock-esai0-tx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai0_tx_clk"; +}; + +clk_esai0_tx_hf_clk: clock-esai0-tx-hf { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai0_tx_hf_clk"; +}; + +clk_spdif0_rx: clock-spdif0-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "spdif0_rx"; +}; + +clk_sai0_rx_bclk: clock-sai0-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai0_rx_bclk"; +}; + +clk_sai0_tx_bclk: clock-sai0-tx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai0_tx_bclk"; +}; + +clk_sai1_rx_bclk: clock-sai1-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai1_rx_bclk"; +}; + +clk_sai1_tx_bclk: clock-sai1-tx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai1_tx_bclk"; +}; + +clk_sai2_rx_bclk: clock-sai2-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai2_rx_bclk"; +}; + +clk_sai3_rx_bclk: clock-sai3-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai3_rx_bclk"; +}; + +clk_sai4_rx_bclk: clock-sai4-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai4_rx_bclk"; +}; + audio_subsys: bus@59000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x1000000>; + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59040000 0x10000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai0_lpcg 1>, + <&clk_dummy>, + <&sai0_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; + power-domains = <&pd IMX_SC_R_SAI_0>; + status = "disabled"; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59050000 0x10000>; + interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai1_lpcg 1>, + <&clk_dummy>, + <&sai1_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; + power-domains = <&pd IMX_SC_R_SAI_1>; + status = "disabled"; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59060000 0x10000>; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai2_lpcg 1>, + <&clk_dummy>, + <&sai2_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 16 0 1>; + power-domains = <&pd IMX_SC_R_SAI_2>; + status = "disabled"; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59070000 0x10000>; + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sai3_lpcg 1>, + <&clk_dummy>, + <&sai3_lpcg 0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 17 0 1>; + power-domains = <&pd IMX_SC_R_SAI_3>; + status = "disabled"; + }; + edma0: dma-controller@591f0000 { compatible = "fsl,imx8qm-edma"; reg = <0x591f0000 0x190000>; @@ -76,6 +239,54 @@ audio_subsys: bus@59000000 { <&pd IMX_SC_R_DMA_0_CH23>; }; + sai0_lpcg: clock-controller@59440000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59440000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "sai0_lpcg_mclk", + "sai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_0>; + }; + + sai1_lpcg: clock-controller@59450000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59450000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "sai1_lpcg_mclk", + "sai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_1>; + }; + + sai2_lpcg: clock-controller@59460000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59460000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "sai2_lpcg_mclk", + "sai2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_2>; + }; + + sai3_lpcg: clock-controller@59470000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59470000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "sai3_lpcg_mclk", + "sai3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_3>; + }; + dsp_lpcg: clock-controller@59580000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x59580000 0x10000>; @@ -151,4 +362,123 @@ audio_subsys: bus@59000000 { <&pd IMX_SC_R_DMA_1_CH9>, <&pd IMX_SC_R_DMA_1_CH10>; }; + + aud_rec0_lpcg: clock-controller@59d00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d00000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; + clock-indices = <IMX_LPCG_CLK_0>; + clock-output-names = "aud_rec_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_rec1_lpcg: clock-controller@59d10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d10000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>; + clock-indices = <IMX_LPCG_CLK_0>; + clock-output-names = "aud_rec_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + aud_pll_div0_lpcg: clock-controller@59d20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>; + clock-indices = <IMX_LPCG_CLK_0>; + clock-output-names = "aud_pll_div_clk0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; + }; + + aud_pll_div1_lpcg: clock-controller@59d30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d30000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>; + clock-indices = <IMX_LPCG_CLK_0>; + clock-output-names = "aud_pll_div_clk1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; + }; + + mclkout0_lpcg: clock-controller@59d50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>; + clock-indices = <IMX_LPCG_CLK_0>; + clock-output-names = "mclkout0_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; + }; + + mclkout1_lpcg: clock-controller@59d60000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59d60000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>; + clock-indices = <IMX_LPCG_CLK_0>; + clock-output-names = "mclkout1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_MCLK_OUT_1>; + }; + + acm: acm@59e00000 { + compatible = "fsl,imx8qxp-acm"; + reg = <0x59e00000 0x1d0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_esai0_rx_clk>, + <&clk_esai0_rx_hf_clk>, + <&clk_esai0_tx_clk>, + <&clk_esai0_tx_hf_clk>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>, + <&clk_sai4_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk"; + }; }; diff --git a/dts/src/arm64/freescale/imx8-ss-conn.dtsi b/dts/src/arm64/freescale/imx8-ss-conn.dtsi index 3c42240e78..4aaf5a0c1e 100644 --- a/dts/src/arm64/freescale/imx8-ss-conn.dtsi +++ b/dts/src/arm64/freescale/imx8-ss-conn.dtsi @@ -41,7 +41,7 @@ conn_subsys: bus@5b000000 { interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc1 0>; - clocks = <&usb2_lpcg 0>; + clocks = <&usb2_lpcg IMX_LPCG_CLK_6>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; @@ -58,7 +58,7 @@ conn_subsys: bus@5b000000 { usbphy1: usbphy@5b100000 { compatible = "fsl,imx7ulp-usbphy"; reg = <0x5b100000 0x1000>; - clocks = <&usb2_lpcg 1>; + clocks = <&usb2_lpcg IMX_LPCG_CLK_7>; power-domains = <&pd IMX_SC_R_USB_0_PHY>; status = "disabled"; }; @@ -67,8 +67,8 @@ conn_subsys: bus@5b000000 { interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b010000 0x10000>; clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, - <&sdhc0_lpcg IMX_LPCG_CLK_0>, - <&sdhc0_lpcg IMX_LPCG_CLK_5>; + <&sdhc0_lpcg IMX_LPCG_CLK_5>, + <&sdhc0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; power-domains = <&pd IMX_SC_R_SDHC_0>; status = "disabled"; @@ -78,8 +78,8 @@ conn_subsys: bus@5b000000 { interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b020000 0x10000>; clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, - <&sdhc1_lpcg IMX_LPCG_CLK_0>, - <&sdhc1_lpcg IMX_LPCG_CLK_5>; + <&sdhc1_lpcg IMX_LPCG_CLK_5>, + <&sdhc1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; @@ -91,8 +91,8 @@ conn_subsys: bus@5b000000 { interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b030000 0x10000>; clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, - <&sdhc2_lpcg IMX_LPCG_CLK_0>, - <&sdhc2_lpcg IMX_LPCG_CLK_5>; + <&sdhc2_lpcg IMX_LPCG_CLK_5>, + <&sdhc2_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; power-domains = <&pd IMX_SC_R_SDHC_2>; status = "disabled"; diff --git a/dts/src/arm64/freescale/imx8-ss-dma.dtsi b/dts/src/arm64/freescale/imx8-ss-dma.dtsi index b0bb77150a..f7a91d43a0 100644 --- a/dts/src/arm64/freescale/imx8-ss-dma.dtsi +++ b/dts/src/arm64/freescale/imx8-ss-dma.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/clock/imx8-lpcg.h> +#include <dt-bindings/dma/fsl-edma.h> #include <dt-bindings/firmware/imx/rsrc.h> dma_ipg_clk: clock-dma-ipg { @@ -27,8 +28,8 @@ dma_subsys: bus@5a000000 { #size-cells = <0>; interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&spi0_lpcg 0>, - <&spi0_lpcg 1>; + clocks = <&spi0_lpcg IMX_LPCG_CLK_0>, + <&spi0_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; @@ -43,8 +44,8 @@ dma_subsys: bus@5a000000 { #size-cells = <0>; interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&spi1_lpcg 0>, - <&spi1_lpcg 1>; + clocks = <&spi1_lpcg IMX_LPCG_CLK_0>, + <&spi1_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; @@ -59,8 +60,8 @@ dma_subsys: bus@5a000000 { #size-cells = <0>; interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&spi2_lpcg 0>, - <&spi2_lpcg 1>; + clocks = <&spi2_lpcg IMX_LPCG_CLK_0>, + <&spi2_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; @@ -75,8 +76,8 @@ dma_subsys: bus@5a000000 { #size-cells = <0>; interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&spi3_lpcg 0>, - <&spi3_lpcg 1>; + clocks = <&spi3_lpcg IMX_LPCG_CLK_0>, + <&spi3_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; @@ -93,8 +94,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_0>; - dma-names = "tx","rx"; - dmas = <&edma2 9 0 0>, <&edma2 8 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 8 0 FSL_EDMA_RX>, <&edma2 9 0 0>; status = "disabled"; }; @@ -107,8 +108,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_1>; - dma-names = "tx","rx"; - dmas = <&edma2 11 0 0>, <&edma2 10 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 11 0 0>; status = "disabled"; }; @@ -121,8 +122,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_2>; - dma-names = "tx","rx"; - dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>; status = "disabled"; }; @@ -135,8 +136,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_3>; - dma-names = "tx","rx"; - dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>; status = "disabled"; }; @@ -144,8 +145,8 @@ dma_subsys: bus@5a000000 { compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; reg = <0x5a190000 0x1000>; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&adma_pwm_lpcg 1>, - <&adma_pwm_lpcg 0>; + clocks = <&adma_pwm_lpcg IMX_LPCG_CLK_4>, + <&adma_pwm_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -192,29 +193,6 @@ dma_subsys: bus@5a000000 { <&pd IMX_SC_R_DMA_2_CH15>; }; - edma3: dma-controller@5a9f0000 { - compatible = "fsl,imx8qm-edma"; - reg = <0x5a9f0000 0x90000>; - #dma-cells = <3>; - dma-channels = <8>; - interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&pd IMX_SC_R_DMA_3_CH0>, - <&pd IMX_SC_R_DMA_3_CH1>, - <&pd IMX_SC_R_DMA_3_CH2>, - <&pd IMX_SC_R_DMA_3_CH3>, - <&pd IMX_SC_R_DMA_3_CH4>, - <&pd IMX_SC_R_DMA_3_CH5>, - <&pd IMX_SC_R_DMA_3_CH6>, - <&pd IMX_SC_R_DMA_3_CH7>; - }; - spi0_lpcg: clock-controller@5a400000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a400000 0x10000>; @@ -377,8 +355,8 @@ dma_subsys: bus@5a000000 { reg = <0x5a880000 0x10000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adc0_lpcg 0>, - <&adc0_lpcg 1>; + clocks = <&adc0_lpcg IMX_LPCG_CLK_0>, + <&adc0_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -392,8 +370,8 @@ dma_subsys: bus@5a000000 { reg = <0x5a890000 0x10000>; interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adc1_lpcg 0>, - <&adc1_lpcg 1>; + clocks = <&adc1_lpcg IMX_LPCG_CLK_0>, + <&adc1_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -406,8 +384,8 @@ dma_subsys: bus@5a000000 { reg = <0x5a8d0000 0x10000>; interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&can0_lpcg 1>, - <&can0_lpcg 0>; + clocks = <&can0_lpcg IMX_LPCG_CLK_4>, + <&can0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <40000000>; @@ -427,8 +405,8 @@ dma_subsys: bus@5a000000 { * CAN1 shares CAN0's clock and to enable CAN0's clock it * has to be powered on. */ - clocks = <&can0_lpcg 1>, - <&can0_lpcg 0>; + clocks = <&can0_lpcg IMX_LPCG_CLK_4>, + <&can0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <40000000>; @@ -448,8 +426,8 @@ dma_subsys: bus@5a000000 { * CAN2 shares CAN0's clock and to enable CAN0's clock it * has to be powered on. */ - clocks = <&can0_lpcg 1>, - <&can0_lpcg 0>; + clocks = <&can0_lpcg IMX_LPCG_CLK_4>, + <&can0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <40000000>; @@ -460,6 +438,29 @@ dma_subsys: bus@5a000000 { status = "disabled"; }; + edma3: dma-controller@5a9f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a9f0000 0x90000>; + #dma-cells = <3>; + dma-channels = <8>; + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH6>, + <&pd IMX_SC_R_DMA_3_CH7>; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; diff --git a/dts/src/arm64/freescale/imx8-ss-gpu0.dtsi b/dts/src/arm64/freescale/imx8-ss-gpu0.dtsi new file mode 100644 index 0000000000..9b8a44aa63 --- /dev/null +++ b/dts/src/arm64/freescale/imx8-ss-gpu0.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +gpu0_subsys: bus@53000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x53000000 0x0 0x53000000 0x1000000>; + + gpu_3d0: gpu@53100000 { + compatible = "vivante,gc"; + reg = <0x53100000 0x40000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd IMX_SC_R_GPU_0_PID0>; + }; +}; diff --git a/dts/src/arm64/freescale/imx8-ss-lsio.dtsi b/dts/src/arm64/freescale/imx8-ss-lsio.dtsi index 7e510b21bb..764c1a08e3 100644 --- a/dts/src/arm64/freescale/imx8-ss-lsio.dtsi +++ b/dts/src/arm64/freescale/imx8-ss-lsio.dtsi @@ -25,8 +25,8 @@ lsio_subsys: bus@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d000000 0x10000>; clock-names = "ipg", "per"; - clocks = <&pwm0_lpcg 4>, - <&pwm0_lpcg 1>; + clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>, + <&pwm0_lpcg IMX_LPCG_CLK_1>; assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <3>; @@ -38,8 +38,8 @@ lsio_subsys: bus@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d010000 0x10000>; clock-names = "ipg", "per"; - clocks = <&pwm1_lpcg 4>, - <&pwm1_lpcg 1>; + clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>, + <&pwm1_lpcg IMX_LPCG_CLK_1>; assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <3>; @@ -51,8 +51,8 @@ lsio_subsys: bus@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d020000 0x10000>; clock-names = "ipg", "per"; - clocks = <&pwm2_lpcg 4>, - <&pwm2_lpcg 1>; + clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>, + <&pwm2_lpcg IMX_LPCG_CLK_1>; assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <3>; @@ -64,8 +64,8 @@ lsio_subsys: bus@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d030000 0x10000>; clock-names = "ipg", "per"; - clocks = <&pwm3_lpcg 4>, - <&pwm3_lpcg 1>; + clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>, + <&pwm3_lpcg IMX_LPCG_CLK_1>; assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; #pwm-cells = <3>; diff --git a/dts/src/arm64/freescale/imx8dxl-evk.dts b/dts/src/arm64/freescale/imx8dxl-evk.dts index b972658efb..2123d431e0 100644 --- a/dts/src/arm64/freescale/imx8dxl-evk.dts +++ b/dts/src/arm64/freescale/imx8dxl-evk.dts @@ -81,6 +81,24 @@ status = "disabled"; }; + reg_can0_stby: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "can0-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_stby: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-3 { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; @@ -261,12 +279,81 @@ }; }; +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416_3: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio2>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + }; + + pca9548_2: i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; status = "okay"; }; +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can0_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + &lsio_gpio4 { status = "okay"; }; @@ -436,6 +523,20 @@ >; }; + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 + IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 + IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 diff --git a/dts/src/arm64/freescale/imx8dxl-ss-adma.dtsi b/dts/src/arm64/freescale/imx8dxl-ss-adma.dtsi index 0a477f6318..5d012c9522 100644 --- a/dts/src/arm64/freescale/imx8dxl-ss-adma.dtsi +++ b/dts/src/arm64/freescale/imx8dxl-ss-adma.dtsi @@ -15,6 +15,63 @@ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; }; +&edma0 { + reg = <0x591f0000 0x1a0000>; + #dma-cells = <3>; + dma-channels = <25>; + dma-channel-mask = <0x1c0cc0>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */ + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */ + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */ + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH10>, + <&pd IMX_SC_R_DMA_0_CH11>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH22>, + <&pd IMX_SC_R_DMA_0_CH23>, + <&pd IMX_SC_R_DMA_0_CH24>; +}; + &edma2 { interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, @@ -45,24 +102,44 @@ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; }; +&flexcan1 { + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; +}; + +&flexcan2 { + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; +}; + +&flexcan3 { + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; +}; + &i2c0 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>; }; &i2c1 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>; }; &i2c2 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>; }; &i2c3 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + dma-names = "tx","rx"; + dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>; }; &lpuart0 { diff --git a/dts/src/arm64/freescale/imx8dxl.dtsi b/dts/src/arm64/freescale/imx8dxl.dtsi index f580eb6db9..a0674c5c55 100644 --- a/dts/src/arm64/freescale/imx8dxl.dtsi +++ b/dts/src/arm64/freescale/imx8dxl.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/dma/fsl-edma.h> #include <dt-bindings/firmware/imx/rsrc.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/dts/src/arm64/freescale/imx8dxp-tqma8xdp-mba8xx.dts b/dts/src/arm64/freescale/imx8dxp-tqma8xdp-mba8xx.dts new file mode 100644 index 0000000000..f35514b7b3 --- /dev/null +++ b/dts/src/arm64/freescale/imx8dxp-tqma8xdp-mba8xx.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "imx8dxp-tqma8xdp.dtsi" +#include "mba8xx.dtsi" + +/ { + model = "TQ-Systems i.MX8DXP TQMa8XDP on MBa8Xx"; + compatible = "tq,imx8dxp-tqma8xdp-mba8xx", "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp"; +}; diff --git a/dts/src/arm64/freescale/imx8dxp-tqma8xdp.dtsi b/dts/src/arm64/freescale/imx8dxp-tqma8xdp.dtsi new file mode 100644 index 0000000000..e2de8517aa --- /dev/null +++ b/dts/src/arm64/freescale/imx8dxp-tqma8xdp.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include "imx8dxp.dtsi" +#include "tqma8xx.dtsi" + +/ { + model = "TQ-Systems i.MX8DXP TQMa8XDP"; + compatible = "tq,imx8dxp-tqma8xdp", "fsl,imx8dxp"; +}; + +&pmic_thermal { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/dts/src/arm64/freescale/imx8dxp.dtsi b/dts/src/arm64/freescale/imx8dxp.dtsi new file mode 100644 index 0000000000..a8f7352332 --- /dev/null +++ b/dts/src/arm64/freescale/imx8dxp.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8qxp.dtsi" + +/delete-node/ &A35_2; +/delete-node/ &A35_3; + +&thermal_zones { + cpu0-thermal { + cooling-maps { + map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mm-evk.dtsi b/dts/src/arm64/freescale/imx8mm-evk.dtsi index b53104ed89..bd5b365867 100644 --- a/dts/src/arm64/freescale/imx8mm-evk.dtsi +++ b/dts/src/arm64/freescale/imx8mm-evk.dtsi @@ -151,6 +151,28 @@ clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; }; }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; }; &A53_0 { @@ -434,6 +456,16 @@ status = "okay"; }; +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MM_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + &mipi_csi { status = "okay"; @@ -509,6 +541,24 @@ status = "okay"; }; +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", + "pll8k", "pll11k"; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -636,6 +686,18 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 @@ -666,6 +728,13 @@ >; }; + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 diff --git a/dts/src/arm64/freescale/imx8mm-kontron-bl-osm-s.dts b/dts/src/arm64/freescale/imx8mm-kontron-bl-osm-s.dts index 8b16bd6857..33f8d7d197 100644 --- a/dts/src/arm64/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/dts/src/arm64/freescale/imx8mm-kontron-bl-osm-s.dts @@ -25,23 +25,21 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; led1 { label = "led1"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; led2 { label = "led2"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; }; led3 { label = "led3"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; }; }; @@ -52,24 +50,12 @@ reg_rst_eth2: regulator-rst-eth2 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_eth2>; - gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; regulator-name = "rst-usb-eth2"; }; - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_vbus>; - gpio = <&gpio3 25 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "usb1-vbus"; - }; - reg_vdd_5v: regulator-5v { compatible = "regulator-fixed"; regulator-always-on; @@ -80,9 +66,6 @@ }; &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; status = "okay"; can@0 { @@ -91,7 +74,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can>; clocks = <&osc_can>; - interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>; /* * Limit the SPI clock to 15 MHz to prevent issues * with corrupted data due to chip errata. @@ -103,9 +86,6 @@ }; &ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; status = "okay"; eeram@0 { @@ -117,8 +97,8 @@ &fec1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-connection-type = "rgmii-rxid"; + pinctrl-0 = <&pinctrl_enet_rgmii>; + phy-connection-type = "rgmii-id"; phy-handle = <ðphy>; status = "okay"; @@ -127,55 +107,101 @@ #size-cells = <0>; ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-id4f51.e91b"; reg = <0>; - reset-assert-us = <1>; - reset-deassert-us = <15000>; - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; }; }; +/* + * Rename SoM signals according to board usage: + * GPIO_B_0 -> DIO1_OUT + * GPIO_B_1 -> DIO2_OUT + */ &gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>; - gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", - "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; + gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT", + "DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; }; -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5>; - gpio-line-names = "", "", "dio4-in", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; +/* + * Rename SoM signals according to board usage: + * GPIO_B_2 -> DIO3_OUT + * GPIO_B_3 -> DIO4_OUT + */ +&gpio3 { + gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT", + "USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; }; -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; +/* + * Rename SoM signals according to board usage: + * GPIO_B_4 -> DIO1_IN + * GPIO_B_5 -> DIO2_IN + * GPIO_B_6 -> DIO3_IN + * GPIO_B_7 -> DIO4_IN + */ +&gpio4 { + gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN", + "DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; +}; + +&i2c3 { status = "okay"; + + usb-hub@2c { + compatible = "microchip,usb2514b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub>; + reg = <0x2c>; + non-removable-ports = <0>, <3>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + }; }; &pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; +®_usb2_vbus { + status = "disabled"; +}; + +®_usdhc2_vcc { + status = "disabled"; +}; + +®_usdhc3_vcc { + status = "disabled"; +}; + &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; uart-has-rtscts; status = "okay"; }; &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; linux,rs485-enabled-at-boot-time; uart-has-rtscts; status = "okay"; @@ -183,8 +209,6 @@ &usbotg1 { dr_mode = "otg"; - disable-over-current; - vbus-supply = <®_usb1_vbus>; status = "okay"; }; @@ -195,14 +219,17 @@ #size-cells = <0>; status = "okay"; + /* VBUS is controlled by the hub */ + /delete-property/ vbus-supply; + usb1@1 { - compatible = "usb424,9514"; + compatible = "usb424,2514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; usbnet: ethernet@1 { - compatible = "usb424,ec00"; + compatible = "usbb95,772b"; reg = <1>; local-mac-address = [ 00 00 00 00 00 00 ]; }; @@ -210,167 +237,20 @@ }; &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; vmmc-supply = <®_vdd_3v3>; - vqmmc-supply = <®_nvcc_sd>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; status = "okay"; }; &iomuxc { pinctrl_can: cangrp { fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */ - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 - >; - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 - >; - }; - - pinctrl_reg_usb1_vbus: regusb1vbusgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - >; - }; - - pinctrl_usb_eth2: usbeth2grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ >; }; - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + pinctrl_usb_hub: usbhubgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ >; }; }; diff --git a/dts/src/arm64/freescale/imx8mm-kontron-bl.dts b/dts/src/arm64/freescale/imx8mm-kontron-bl.dts index dcec57c203..aab8e24216 100644 --- a/dts/src/arm64/freescale/imx8mm-kontron-bl.dts +++ b/dts/src/arm64/freescale/imx8mm-kontron-bl.dts @@ -279,8 +279,8 @@ pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 >; }; @@ -292,19 +292,19 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 >; }; @@ -316,40 +316,40 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; }; diff --git a/dts/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi b/dts/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi index 6e75ab879b..663ae52b48 100644 --- a/dts/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi +++ b/dts/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2022 Kontron Electronics GmbH */ +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include "imx8mm.dtsi" @@ -28,6 +29,73 @@ chosen { stdout-path = &uart3; }; + + reg_vdd_carrier: regulator-vdd-carrier { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vdd_carrier>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "VDD_CARRIER"; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_vbus>; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB1"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_vbus>; + enable-active-high; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB2"; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>; + enable-active-high; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_A"; + }; + + reg_usdhc3_vcc: regulator-usdhc3-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>; + enable-active-high; + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_B"; + }; }; &A53_0 { @@ -96,6 +164,79 @@ }; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_gpio>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0", + "GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", + "SDIO_A_WP"; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2", + "USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6", + "GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; +}; + +&gpio5 { + gpio-line-names = "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2", + "PWM_1", "PWM_0", "", "", + "", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)", + "SPI_A_SCK", "SPI_A_CS0#", "", "", + "I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA", + "PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO", + "SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX", + "UART_C_RX", "UART_C_TX"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -205,22 +346,86 @@ }; }; + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + address-width = <16>; + pagesize = <32>; + size = <8192>; + }; + rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; - interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; - trickle-diode-disable; + interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>; }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + &uart3 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + vbus-supply = <®_usb1_vbus>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + vbus-supply = <®_usb2_vbus>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -233,6 +438,26 @@ status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + vmmc-supply = <®_usdhc3_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -241,6 +466,12 @@ }; &iomuxc { + pinctrl_csi_mck: csimckgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 /* CAM_MCK */ + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 @@ -250,10 +481,140 @@ >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 /* SPI_A_SDI_(IO0) */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 /* SPI_A_SDO_(IO1) */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 /* SPI_A_SCK */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* SPI_A_CS0# */ + >; + }; + + pinctrl_ecspi2_gpio: ecspi2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* SPI_A_/WP_(IO2) */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* SPI_A_/HOLD_(IO3) */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 /* SPI_B_SDI */ + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 /* SPI_B_SDO */ + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 /* SPI_B_SCK */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* SPI_B_CS0# */ + >; + }; + + pinctrl_enet_rgmii: enetrgmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */ + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */ + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_enet_rmii: enetrmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* GPIO_A_0 */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* GPIO_A_1 */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* GPIO_A_2 */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* GPIO_A_3 */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* GPIO_A_4 */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_A_5 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_A_6 */ + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* GPIO_A_7 */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_B_0 */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* GPIO_B_1 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* GPIO_C_5 */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* GPIO_C_4 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* GPIO_C_0 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* GPIO_C_1 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* GPIO_C_2 */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* GPIO_C_3 */ + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_B_2 */ + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* GPIO_B_3 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* GPIO_C_7 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* GPIO_B_4 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* BOOT_SEL0# */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* BOOT_SEL1# */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* GPIO_B_5 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* GPIO_B_6 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* GPIO_B_7 */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* GPIO_C_6 */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 /* I2C_B_SCL */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 /* I2C_B_SDA */ + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 /* PCIe_SMCLK and I2C_CAM_SCL/CSI_TX_P */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 /* PCIe_SMDAT and I2C_CAM_SDA/CSI_TX_N */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* PCIe_CLKREQ# */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* PCIe_A_PERST# */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* PCIe_WAKE# */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* PCIe_SM_ALERT */ >; }; @@ -263,16 +624,113 @@ >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 /* PWM_0 */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 /* PWM_1 */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x19 /* PWM_2 */ + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* USB_A_EN */ + >; + }; + + pinctrl_reg_usb2_vbus: regusb2vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* USB_B_EN */ + >; + }; + + pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */ + >; + }; + + pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ + >; + }; + + pinctrl_reg_vdd_carrier: regvddcarriergrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* CARRIER_PWR_EN */ + >; + }; + pinctrl_rtc: rtcgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 /* I2S_A_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 /* I2S_A_DATA_OUT */ + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 /* I2S_B_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 /* I2S_B_DATA_OUT */ + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 /* I2S_MCLK */ + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 /* I2S_LRCLK */ + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 /* I2S_BITCLK */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 /* UART_A_RX */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 /* UART_A_TX */ + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 /* UART_A_CTS */ + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 /* UART_A_RTS */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 /* UART_B_RX */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 /* UART_B_TX */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 /* UART_B_CTS */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 /* UART_B_RTS */ + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 /* UART_CON_RX */ + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 /* UART_CON_TX */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x0 /* UART_C_RX */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0 /* UART_C_TX */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 /* USB_A_OC# */ + >; + }; + + pinctrl_usb2: usb2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x19 /* USB_B_OC# */ >; }; @@ -327,6 +785,103 @@ >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* SDIO_A_CD# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x90 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x90 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x90 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x90 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x90 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x90 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x90 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x90 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x90 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x90 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x94 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x94 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x94 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x94 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x94 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x94 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x94 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x94 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x94 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x94 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x96 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x96 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x96 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x96 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x96 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x96 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x96 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x96 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x96 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x96 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_gpio: usdhc3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* SDIO_B_CD# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 diff --git a/dts/src/arm64/freescale/imx8mm-kontron-sl.dtsi b/dts/src/arm64/freescale/imx8mm-kontron-sl.dtsi index 1f8326613e..2076148e08 100644 --- a/dts/src/arm64/freescale/imx8mm-kontron-sl.dtsi +++ b/dts/src/arm64/freescale/imx8mm-kontron-sl.dtsi @@ -237,8 +237,8 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 >; }; diff --git a/dts/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts b/dts/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts index ea6e8b8516..01b632b220 100644 --- a/dts/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/dts/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include <dt-bindings/phy/phy-imx8-pcie.h> + #include "imx8mm-tqma8mqml.dtsi" #include "mba8mx.dtsi" @@ -74,19 +76,23 @@ }; &pcie_phy { - clocks = <&pcie0_refclk>; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcieclk 2>; + clock-names = "ref"; status = "okay"; }; +/* PCIe slot on X36 */ &pcie0 { reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 3>, <&clk IMX8MM_CLK_PCIE1_AUX>; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; + <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; + <&clk IMX8MM_SYS_PLL2_250M>; status = "okay"; }; diff --git a/dts/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi b/dts/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi index 6425773f68..41c966147b 100644 --- a/dts/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi +++ b/dts/src/arm64/freescale/imx8mm-venice-gw71xx.dtsi @@ -47,25 +47,20 @@ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; status = "okay"; }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; }; -/* off-board header */ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio1 { @@ -144,9 +139,10 @@ }; &usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; dr_mode = "otg"; over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; status = "okay"; }; @@ -204,20 +200,13 @@ >; }; - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 - >; - }; - pinctrl_spi2: spi2grp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 >; }; @@ -234,4 +223,11 @@ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 + >; + }; }; diff --git a/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts b/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts index 87b80e2412..5e2cbaf27e 100644 --- a/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts +++ b/dts/src/arm64/freescale/imx8mm-venice-gw7901.dts @@ -285,7 +285,8 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio4 24 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { @@ -294,6 +295,12 @@ spi-max-frequency = <40000000>; status = "okay"; }; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &fec1 { @@ -319,7 +326,7 @@ &gpio4 { gpio-line-names = "", "", "", "", - "", "", "uart3_rs232#", "uart3_rs422#", + "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#", "uart3_rs485#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; @@ -842,6 +849,8 @@ pinctrl_hog: hoggrp { fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ @@ -987,6 +996,7 @@ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 + MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 >; }; diff --git a/dts/src/arm64/freescale/imx8mn-beacon-kit.dts b/dts/src/arm64/freescale/imx8mn-beacon-kit.dts index 35b8d2060c..bbd80896db 100644 --- a/dts/src/arm64/freescale/imx8mn-beacon-kit.dts +++ b/dts/src/arm64/freescale/imx8mn-beacon-kit.dts @@ -99,8 +99,6 @@ }; &lcdif { - assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>; - assigned-clock-rates = <594000000>; status = "okay"; }; diff --git a/dts/src/arm64/freescale/imx8mn-evk.dtsi b/dts/src/arm64/freescale/imx8mn-evk.dtsi index a0e13d3324..269e70f66a 100644 --- a/dts/src/arm64/freescale/imx8mn-evk.dtsi +++ b/dts/src/arm64/freescale/imx8mn-evk.dtsi @@ -110,6 +110,20 @@ spdif-out; spdif-in; }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; }; &easrc { @@ -285,6 +299,16 @@ status = "okay"; }; +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MN_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + &mipi_csi { status = "okay"; @@ -522,6 +546,18 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 diff --git a/dts/src/arm64/freescale/imx8mn-rve-gateway.dts b/dts/src/arm64/freescale/imx8mn-rve-gateway.dts index 1b633bd1eb..ea1855171f 100644 --- a/dts/src/arm64/freescale/imx8mn-rve-gateway.dts +++ b/dts/src/arm64/freescale/imx8mn-rve-gateway.dts @@ -10,7 +10,7 @@ / { model = "RVE gateway"; - compatible = "rve,rve-gateway", "variscite,var-som-mx8mn", "fsl,imx8mn"; + compatible = "rve,gateway", "variscite,var-som-mx8mn", "fsl,imx8mn"; crystal_duart_24m: crystal-duart-24m { compatible = "fixed-clock"; diff --git a/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso b/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso new file mode 100644 index 0000000000..96db07fc9b --- /dev/null +++ b/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +#include "imx8mn-pinfunc.h" + +&{/} { + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "X19"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_connector>; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; +}; + +&rst_usb_hub_hog { + output-low; +}; + +&sel_usb_hub_hog { + output-low; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + /delete-property/ disable-over-current; + over-current-active-low; + usb-role-switch; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&iomuxc { + pinctrl_usb1_connector: usb1-connectorgrp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c0>; + }; +}; diff --git a/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts index c07d59147a..433d8bba44 100644 --- a/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/dts/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -41,7 +41,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0hub_sel>; - sel-usb-hub-hog { + sel_usb_hub_hog: sel-usb-hub-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; output-high; @@ -198,8 +198,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = <MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x84>, - <MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>, - <MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x1C4>; + <MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x84>; }; pinctrl_usdhc2: usdhc2grp { diff --git a/dts/src/arm64/freescale/imx8mn.dtsi b/dts/src/arm64/freescale/imx8mn.dtsi index 136e75c512..932c8b05c7 100644 --- a/dts/src/arm64/freescale/imx8mn.dtsi +++ b/dts/src/arm64/freescale/imx8mn.dtsi @@ -1168,7 +1168,7 @@ <&clk IMX8MN_SYS_PLL1_800M>; assigned-clock-rates = <266000000>, <24000000>, - <594000000>, + <24000000>, <500000000>, <200000000>; #power-domain-cells = <1>; diff --git a/dts/src/arm64/freescale/imx8mp-beacon-som.dtsi b/dts/src/arm64/freescale/imx8mp-beacon-som.dtsi index e5da908047..8be251b693 100644 --- a/dts/src/arm64/freescale/imx8mp-beacon-som.dtsi +++ b/dts/src/arm64/freescale/imx8mp-beacon-som.dtsi @@ -50,6 +50,8 @@ phy-mode = "rgmii-id"; phy-handle = <ðphy0>; snps,force_thresh_dma_mode; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; status = "okay"; mdio { @@ -66,6 +68,71 @@ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; }; &flexspi { @@ -206,6 +273,10 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "nxp,88w8997-bt"; + }; }; &usdhc1 { diff --git a/dts/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts b/dts/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts index 5828c9d782..7e1b58dbe2 100644 --- a/dts/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts +++ b/dts/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/net/qca-ar803x.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mp.dtsi" / { @@ -45,6 +46,19 @@ clock-frequency = <25000000>; }; + clk_pwm4: clock-pwm4 { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + clock-output-names = "codec-pwm4"; + /* + * 1 / 83 ns ~= 12 MHz , but since the PWM input clock is 24 MHz + * and the calculated PWM period is 1 and duty cycle is 50%, the + * result is exactly 12 MHz, which is fine for SGTL5000 MCLK. + */ + pwms = <&pwm4 0 83 0>; + }; + panel: panel { /* Compatible string is filled in by panel board DT Overlay. */ backlight = <&backlight>; @@ -82,6 +96,24 @@ vin-supply = <&buck4>; }; + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SGTL5000-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; + watchdog { /* TPS3813 */ compatible = "linux,wdt-gpio"; pinctrl-names = "default"; @@ -121,7 +153,7 @@ flash@0 { /* W25Q128JVEI */ compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <100000000>; /* Up to 133 MHz */ + spi-max-frequency = <40000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; @@ -288,6 +320,15 @@ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_pwm4>; + VDDA-supply = <&buck4>; + VDDIO-supply = <&buck4>; + }; + usb-hub@2c { compatible = "microchip,usb2514bi"; reg = <0x2c>; @@ -429,6 +470,21 @@ status = "okay"; }; +&pcie_phy { + clocks = <&pcieclk 0>; + clock-names = "ref"; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + fsl,max-link-speed = <3>; + reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_panel_pwm>; @@ -436,6 +492,23 @@ status = "disabled"; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai3 { + #clock-cells = <0>; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + status = "okay"; +}; + /* SD slot */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -785,6 +858,12 @@ >; }; + pinctrl_pwm4: pwm4-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0xd6 + >; + }; + pinctrl_rtc: rtc-grp { fsl,pins = < /* RTC_IRQ# */ @@ -816,7 +895,6 @@ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 - MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 >; }; diff --git a/dts/src/arm64/freescale/imx8mp-evk.dts b/dts/src/arm64/freescale/imx8mp-evk.dts index f87fa5a948..9beba8d6a0 100644 --- a/dts/src/arm64/freescale/imx8mp-evk.dts +++ b/dts/src/arm64/freescale/imx8mp-evk.dts @@ -23,7 +23,7 @@ port { hdmi_connector_in: endpoint { - remote-endpoint = <&adv7533_out>; + remote-endpoint = <&adv7535_out>; }; }; }; @@ -107,6 +107,13 @@ enable-active-high; }; + reg_vext_3v3: regulator-vext-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "wm8960-audio"; @@ -364,7 +371,7 @@ regulator-always-on; }; - BUCK5 { + reg_buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <1950000>; @@ -415,14 +422,16 @@ hdmi@3d { compatible = "adi,adv7535"; - reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; - reg-names = "main", "cec", "edid", "packet"; + reg = <0x3d>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; + avdd-supply = <®_buck5>; + dvdd-supply = <®_buck5>; + pvdd-supply = <®_buck5>; + a2vdd-supply = <®_buck5>; + v3p3-supply = <®_vext_3v3>; + v1p2-supply = <®_buck5>; ports { #address-cells = <1>; @@ -431,7 +440,7 @@ port@0 { reg = <0>; - adv7533_in: endpoint { + adv7535_in: endpoint { remote-endpoint = <&dsi_out>; }; }; @@ -439,7 +448,7 @@ port@1 { reg = <1>; - adv7533_out: endpoint { + adv7535_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; @@ -524,7 +533,7 @@ reg = <1>; dsi_out: endpoint { - remote-endpoint = <&adv7533_in>; + remote-endpoint = <&adv7535_in>; data-lanes = <1 2 3 4>; }; }; diff --git a/dts/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts b/dts/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts index c8640cac3e..00a240484c 100644 --- a/dts/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/dts/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -19,6 +19,30 @@ stdout-path = &uart1; }; + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <11>; + enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + num-interpolated-steps = <2>; + power-supply = <®_lvds1_reg_en>; + pwms = <&pwm3 0 50000 0>; + }; + + panel1_lvds: panel-lvds { + compatible = "edt,etml1010g3dra"; + backlight = <&backlight_lvds>; + power-supply = <®_vcc_3v3_sw>; + + port { + panel1_in: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; + reg_can1_stby: regulator-can1-stby { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -39,6 +63,15 @@ regulator-name = "can2-stby"; }; + reg_lvds1_reg_en: regulator-lvds1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "lvds1_reg_en"; + }; + reg_usb1_vbus: regulator-usb1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -61,6 +94,13 @@ startup-delay-us = <100>; off-on-delay-us = <12000>; }; + + reg_vcc_3v3_sw: regulator-vcc-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &eqos { @@ -135,10 +175,41 @@ }; }; +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; + }; +}; + &snvs_pwrkey { status = "okay"; }; +&pwm3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&rv3028 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + trickle-resistor-ohms = <3000>; +}; + /* debug console */ &uart1 { pinctrl-names = "default"; @@ -239,12 +310,12 @@ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 >; }; @@ -289,16 +360,34 @@ >; }; + pinctrl_lvds1: lvds1grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 >; }; @@ -319,7 +408,7 @@ pinctrl_usdhc2_pins: usdhc2-gpiogrp { fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40 >; }; diff --git a/dts/src/arm64/freescale/imx8mp-phycore-som.dtsi b/dts/src/arm64/freescale/imx8mp-phycore-som.dtsi index c976c3b6cb..e6ffa6a6b6 100644 --- a/dts/src/arm64/freescale/imx8mp-phycore-som.dtsi +++ b/dts/src/arm64/freescale/imx8mp-phycore-som.dtsi @@ -175,7 +175,6 @@ rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; - trickle-resistor-ohms = <3000>; }; }; diff --git a/dts/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi b/dts/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi index 0e8d0f3c7e..e7bf032265 100644 --- a/dts/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi +++ b/dts/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi @@ -63,8 +63,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio4 { @@ -228,6 +235,7 @@ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; diff --git a/dts/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi b/dts/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi index 41c79d2ebd..f24b147447 100644 --- a/dts/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi +++ b/dts/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi @@ -14,6 +14,7 @@ pinctrl-0 = <&pinctrl_usbcon1>; type = "micro"; label = "otg"; + vbus-supply = <®_usb1_vbus>; id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; port { @@ -183,7 +184,6 @@ }; &usb3_phy0 { - vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/dts/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi b/dts/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi index d5c400b355..f5491a608b 100644 --- a/dts/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi +++ b/dts/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi @@ -14,6 +14,7 @@ pinctrl-0 = <&pinctrl_usbcon1>; type = "micro"; label = "otg"; + vbus-supply = <®_usb1_vbus>; id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; port { @@ -202,7 +203,6 @@ }; &usb3_phy0 { - vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/dts/src/arm64/freescale/imx8mp-verdin.dtsi b/dts/src/arm64/freescale/imx8mp-verdin.dtsi index c3305f0d40..faa17cbbe2 100644 --- a/dts/src/arm64/freescale/imx8mp-verdin.dtsi +++ b/dts/src/arm64/freescale/imx8mp-verdin.dtsi @@ -552,7 +552,7 @@ regulator-name = "On-module +V3.3_ADC (LDO4)"; }; - LDO5 { + reg_vdd_sdio: LDO5 { regulator-max-microvolt = <3300000>; regulator-min-microvolt = <1800000>; regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; @@ -885,6 +885,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_vdd_sdio>; }; /* On-module eMMC */ diff --git a/dts/src/arm64/freescale/imx8mp.dtsi b/dts/src/arm64/freescale/imx8mp.dtsi index 39a550c1cd..bfc5c81a5b 100644 --- a/dts/src/arm64/freescale/imx8mp.dtsi +++ b/dts/src/arm64/freescale/imx8mp.dtsi @@ -1636,8 +1636,10 @@ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <500000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; status = "disabled"; @@ -1670,8 +1672,10 @@ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <266000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; status = "disabled"; diff --git a/dts/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts b/dts/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts index b302daca4c..0165f3a259 100644 --- a/dts/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/dts/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -28,18 +28,6 @@ id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie1_refclk: pcie1-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - reg_otg_vbus: regulator-otg-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -103,23 +91,24 @@ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; }; +/* PCIe slot on X36 */ &pcie0 { reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&pcie0_refclk>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcieclk 3>, + <&pcieclk 2>, <&clk IMX8MQ_CLK_PCIE1_AUX>; status = "okay"; }; /* - * miniPCIe, also usable for cards with USB. Therefore configure the reset as + * miniPCIe on X28, also usable for cards with USB. Therefore configure the reset as * static gpio hog. */ &pcie1 { clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&pcie1_refclk>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcieclk 1>, + <&pcieclk 0>, <&clk IMX8MQ_CLK_PCIE2_AUX>; status = "okay"; }; @@ -171,6 +160,7 @@ }; &usb3_phy1 { + vbus-supply = <®_hub_vbus>; status = "okay"; }; diff --git a/dts/src/arm64/freescale/imx8qm-apalis-eval-v1.2.dts b/dts/src/arm64/freescale/imx8qm-apalis-eval-v1.2.dts new file mode 100644 index 0000000000..8466a8204e --- /dev/null +++ b/dts/src/arm64/freescale/imx8qm-apalis-eval-v1.2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-eval-v1.2", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/dts/src/arm64/freescale/imx8qm-apalis-eval.dts b/dts/src/arm64/freescale/imx8qm-apalis-eval.dts index 5ab0921eb5..b0ebf6d054 100644 --- a/dts/src/arm64/freescale/imx8qm-apalis-eval.dts +++ b/dts/src/arm64/freescale/imx8qm-apalis-eval.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx8qm-apalis.dtsi" -#include "imx8-apalis-eval.dtsi" +#include "imx8-apalis-eval-v1.1.dtsi" / { model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board"; diff --git a/dts/src/arm64/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts b/dts/src/arm64/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts new file mode 100644 index 0000000000..92c0ae0c03 --- /dev/null +++ b/dts/src/arm64/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-v1.1-eval-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qm"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + /delete-property/ no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /delete-property/ no-1-8-v; +}; diff --git a/dts/src/arm64/freescale/imx8qm-apalis-v1.1-eval.dts b/dts/src/arm64/freescale/imx8qm-apalis-v1.1-eval.dts index c8ff758315..c998e542f9 100644 --- a/dts/src/arm64/freescale/imx8qm-apalis-v1.1-eval.dts +++ b/dts/src/arm64/freescale/imx8qm-apalis-v1.1-eval.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx8qm-apalis-v1.1.dtsi" -#include "imx8-apalis-eval.dtsi" +#include "imx8-apalis-eval-v1.1.dtsi" / { model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board"; diff --git a/dts/src/arm64/freescale/imx8qm-mek.dts b/dts/src/arm64/freescale/imx8qm-mek.dts index 6d50838ad1..77ac0efdfa 100644 --- a/dts/src/arm64/freescale/imx8qm-mek.dts +++ b/dts/src/arm64/freescale/imx8qm-mek.dts @@ -41,6 +41,18 @@ }; }; +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -104,6 +116,20 @@ }; &iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c + IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c + >; + }; + + pinctrl_i2c1_gpio: i2c1gpio-grp { + fsl,pins = < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c + IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 diff --git a/dts/src/arm64/freescale/imx8qm-ss-conn.dtsi b/dts/src/arm64/freescale/imx8qm-ss-conn.dtsi index ec1639174e..545e175c88 100644 --- a/dts/src/arm64/freescale/imx8qm-ss-conn.dtsi +++ b/dts/src/arm64/freescale/imx8qm-ss-conn.dtsi @@ -6,20 +6,25 @@ &fec1 { compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; }; &fec2 { compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; + iommus = <&smmu 0x12 0x7f80>; }; &usdhc1 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + iommus = <&smmu 0x11 0x7f80>; }; &usdhc2 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + iommus = <&smmu 0x11 0x7f80>; }; &usdhc3 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + iommus = <&smmu 0x11 0x7f80>; }; diff --git a/dts/src/arm64/freescale/imx8qm-ss-dma.dtsi b/dts/src/arm64/freescale/imx8qm-ss-dma.dtsi index 69cb867673..aa9f28c443 100644 --- a/dts/src/arm64/freescale/imx8qm-ss-dma.dtsi +++ b/dts/src/arm64/freescale/imx8qm-ss-dma.dtsi @@ -17,6 +17,32 @@ power-domains = <&pd IMX_SC_R_UART_4>; }; + i2c4: i2c@5a840000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x5a840000 0x4000>; + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&i2c4_lpcg 0>, + <&i2c4_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_4>; + status = "disabled"; + }; + + i2c4_lpcg: clock-controller@5ac40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac40000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "i2c4_lpcg_clk", + "i2c4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_4>; + }; + can1_lpcg: clock-controller@5ace0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ace0000 0x10000>; @@ -96,15 +122,30 @@ status = "okay"; }; +/* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */ &edma3 { + reg = <0x5a9f0000 0x210000>; + dma-channels = <10>; + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd IMX_SC_R_DMA_1_CH0>, - <&pd IMX_SC_R_DMA_1_CH1>, - <&pd IMX_SC_R_DMA_1_CH2>, - <&pd IMX_SC_R_DMA_1_CH3>, - <&pd IMX_SC_R_DMA_1_CH4>, - <&pd IMX_SC_R_DMA_1_CH5>, - <&pd IMX_SC_R_DMA_1_CH6>, - <&pd IMX_SC_R_DMA_1_CH7>; + <&pd IMX_SC_R_DMA_1_CH1>, + <&pd IMX_SC_R_DMA_1_CH2>, + <&pd IMX_SC_R_DMA_1_CH3>, + <&pd IMX_SC_R_DMA_1_CH4>, + <&pd IMX_SC_R_DMA_1_CH5>, + <&pd IMX_SC_R_DMA_1_CH6>, + <&pd IMX_SC_R_DMA_1_CH7>, + <&pd IMX_SC_R_DMA_1_CH8>, + <&pd IMX_SC_R_DMA_1_CH9>; }; &flexcan1 { @@ -112,15 +153,15 @@ }; &flexcan2 { - clocks = <&can1_lpcg 1>, - <&can1_lpcg 0>; + clocks = <&can1_lpcg IMX_LPCG_CLK_4>, + <&can1_lpcg IMX_LPCG_CLK_0>; assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; fsl,clk-source = /bits/ 8 <1>; }; &flexcan3 { - clocks = <&can2_lpcg 1>, - <&can2_lpcg 0>; + clocks = <&can2_lpcg IMX_LPCG_CLK_4>, + <&can2_lpcg IMX_LPCG_CLK_0>; assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; fsl,clk-source = /bits/ 8 <1>; }; diff --git a/dts/src/arm64/freescale/imx8qm.dtsi b/dts/src/arm64/freescale/imx8qm.dtsi index 31744fc1ab..b3d01677b7 100644 --- a/dts/src/arm64/freescale/imx8qm.dtsi +++ b/dts/src/arm64/freescale/imx8qm.dtsi @@ -265,6 +265,47 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ }; + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + system-controller { compatible = "fsl,imx-scu"; mbox-names = "tx0", diff --git a/dts/src/arm64/freescale/imx8qxp-tqma8xqp-mba8xx.dts b/dts/src/arm64/freescale/imx8qxp-tqma8xqp-mba8xx.dts new file mode 100644 index 0000000000..7d2e98bf8b --- /dev/null +++ b/dts/src/arm64/freescale/imx8qxp-tqma8xqp-mba8xx.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "imx8qxp-tqma8xqp.dtsi" +#include "mba8xx.dtsi" + +/ { + model = "TQ-Systems i.MX8QXP TQMa8XQP on MBa8Xx"; + compatible = "tq,imx8qxp-tqma8xqp-mba8xx", "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp"; +}; diff --git a/dts/src/arm64/freescale/imx8qxp-tqma8xqp.dtsi b/dts/src/arm64/freescale/imx8qxp-tqma8xqp.dtsi new file mode 100644 index 0000000000..b14040bf4d --- /dev/null +++ b/dts/src/arm64/freescale/imx8qxp-tqma8xqp.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include "imx8qxp.dtsi" +#include "tqma8xx.dtsi" + +/ { + model = "TQ-Systems i.MX8QXP TQMa8XQP"; + compatible = "tq,imx8qxp-tqma8xqp", "fsl,imx8qxp"; +}; diff --git a/dts/src/arm64/freescale/imx8qxp.dtsi b/dts/src/arm64/freescale/imx8qxp.dtsi index 958267b333..10e16d84c0 100644 --- a/dts/src/arm64/freescale/imx8qxp.dtsi +++ b/dts/src/arm64/freescale/imx8qxp.dtsi @@ -260,6 +260,13 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + xtal32k: clock-xtal32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -310,6 +317,7 @@ /* sorted in register address */ #include "imx8-ss-img.dtsi" #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" diff --git a/dts/src/arm64/freescale/imx8ulp-evk.dts b/dts/src/arm64/freescale/imx8ulp-evk.dts index 69dd8e3102..24bb253b93 100644 --- a/dts/src/arm64/freescale/imx8ulp-evk.dts +++ b/dts/src/arm64/freescale/imx8ulp-evk.dts @@ -37,7 +37,7 @@ no-map; }; - rsc_table: rsc-table@1fff8000{ + rsc_table: rsc-table@1fff8000 { reg = <0 0x1fff8000 0 0x1000>; no-map; }; diff --git a/dts/src/arm64/freescale/imx93-phyboard-segin.dts b/dts/src/arm64/freescale/imx93-phyboard-segin.dts new file mode 100644 index 0000000000..85fb188b05 --- /dev/null +++ b/dts/src/arm64/freescale/imx93-phyboard-segin.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + * + * Product homepage: + * phyBOARD-Segin carrier board is reused for the i.MX93 design. + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ + */ +/dts-v1/; + +#include "imx93-phycore-som.dtsi" + +/{ + model = "PHYTEC phyBOARD-Segin-i.MX93"; + compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", + "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SD"; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + no-1-8-v; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/dts/src/arm64/freescale/imx93-phycore-som.dtsi b/dts/src/arm64/freescale/imx93-phycore-som.dtsi new file mode 100644 index 0000000000..88c2657b50 --- /dev/null +++ b/dts/src/arm64/freescale/imx93-phycore-som.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> + * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + * + * Product homepage: + * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ + */ + +#include <dt-bindings/leds/common.h> + +#include "imx93.dtsi" + +/{ + model = "PHYTEC phyCORE-i.MX93"; + compatible = "phytec,imx93-phycore-som", "fsl,imx93"; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* Ethernet */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>, <50000000>; + status = "okay"; + + mdio: mdio { + clock-frequency = <5000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* Watchdog */ +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e + MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; +}; diff --git a/dts/src/arm64/freescale/imx93-tqma9352.dtsi b/dts/src/arm64/freescale/imx93-tqma9352.dtsi index f6e422dc26..9d2328c185 100644 --- a/dts/src/arm64/freescale/imx93-tqma9352.dtsi +++ b/dts/src/arm64/freescale/imx93-tqma9352.dtsi @@ -122,10 +122,8 @@ /* protectable identification memory (part of M24C64-D @57) */ eeprom@5f { - compatible = "st,24c64", "atmel,24c64"; + compatible = "atmel,24c64d-wl"; reg = <0x5f>; - size = <32>; - pagesize = <32>; vcc-supply = <®_v3v3>; }; diff --git a/dts/src/arm64/freescale/imx93-var-som-symphony.dts b/dts/src/arm64/freescale/imx93-var-som-symphony.dts new file mode 100644 index 0000000000..576d6982a4 --- /dev/null +++ b/dts/src/arm64/freescale/imx93-var-som-symphony.dts @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 NXP + * Copyright 2023 Variscite Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "imx93-var-som.dtsi" + +/{ + model = "Variscite VAR-SOM-MX93 on Symphony evaluation board"; + compatible = "variscite,var-som-mx93-symphony", + "variscite,var-som-mx93", "fsl,imx93"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; + + chosen { + stdout-path = &lpuart1; + }; + + /* + * Needed only for Symphony <= v1.5 + */ + reg_fec_phy: regulator-fec-phy { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ethosu_mem: ethosu-region@88000000 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 0x88000000 0x0 0x8000000>; + }; + + vdev0vring0: vdev0vring0@87ee0000 { + reg = <0 0x87ee0000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@87ee8000 { + reg = <0 0x87ee8000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@87ef0000 { + reg = <0 0x87ef0000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@87ef8000 { + reg = <0 0x87ef8000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@87f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x87f00000 0 0x100000>; + no-map; + }; + + ele_reserved: ele-reserved@87de0000 { + compatible = "shared-dma-pool"; + reg = <0 0x87de0000 0 0x100000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-back { + label = "Back"; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + }; + + key-home { + label = "Home"; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOME>; + }; + + key-menu { + label = "Menu"; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_MENU>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* Use external instead of internal RTC*/ +&bbnsm_rtc { + status = "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + qca,disable-smarteee; + eee-broken-1000t; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1_gpio>; + pinctrl-2 = <&pinctrl_lpi2c1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + /* DS1337 RTC module */ + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&lpi2c5 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + pinctrl-2 = <&pinctrl_lpi2c5_gpio>; + scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + wakeup-source; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* J18.7, J18.9 */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +/* Watchdog */ +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { + fsl,pins = < + MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e + MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; +}; diff --git a/dts/src/arm64/freescale/imx93-var-som.dtsi b/dts/src/arm64/freescale/imx93-var-som.dtsi new file mode 100644 index 0000000000..783938245e --- /dev/null +++ b/dts/src/arm64/freescale/imx93-var-som.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2023 Variscite Ltd. + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/{ + model = "Variscite VAR-SOM-MX93 module"; + compatible = "variscite,var-som-mx93", "fsl,imx93"; + + mmc_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; + + reg_eqos_phy: regulator-eqos-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eqos_phy>; + regulator-name = "eth_phy_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + regulator-always-on; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <1000000>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_reg_eqos_phy: regeqosgrp { + fsl,pins = < + MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; +}; diff --git a/dts/src/arm64/freescale/imx93.dtsi b/dts/src/arm64/freescale/imx93.dtsi index 8f2e7c42ad..601c94e1fa 100644 --- a/dts/src/arm64/freescale/imx93.dtsi +++ b/dts/src/arm64/freescale/imx93.dtsi @@ -294,7 +294,7 @@ status = "disabled"; }; - i3c1: i3c-master@44330000 { + i3c1: i3c@44330000 { compatible = "silvaco,i3c-master-v1"; reg = <0x44330000 0x10000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; @@ -671,7 +671,7 @@ status = "disabled"; }; - i3c2: i3c-master@42520000 { + i3c2: i3c@42520000 { compatible = "silvaco,i3c-master-v1"; reg = <0x42520000 0x10000>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/src/arm64/freescale/mba8mx.dtsi b/dts/src/arm64/freescale/mba8mx.dtsi index e2bc53b8d3..427467df42 100644 --- a/dts/src/arm64/freescale/mba8mx.dtsi +++ b/dts/src/arm64/freescale/mba8mx.dtsi @@ -29,6 +29,12 @@ stdout-path = &uart3; }; + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -100,12 +106,6 @@ }; }; - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - reg_12v: regulator-12v { compatible = "regulator-fixed"; regulator-name = "MBA8MX_12V"; @@ -219,7 +219,7 @@ line-name = "BOOT_CFG_OE#"; }; - rst-usb-hub-hog { + rst_usb_hub_hog: rst-usb-hub-hog { gpio-hog; gpios = <13 0>; output-high; @@ -264,6 +264,13 @@ pagesize = <16>; vcc-supply = <®_vcc_3v3>; }; + + pcieclk: clk@68 { + compatible = "renesas,9fgv0441"; + reg = <0x68>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; }; &i2c3 { diff --git a/dts/src/arm64/freescale/mba8xx.dtsi b/dts/src/arm64/freescale/mba8xx.dtsi new file mode 100644 index 0000000000..276d1683b0 --- /dev/null +++ b/dts/src/arm64/freescale/mba8xx.dtsi @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> + +/ { + adc { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>; + }; + + aliases { + rtc0 = &pcf85063; + rtc1 = &rtc; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bl_lvds>; + pwms = <&adma_pwm 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + chosen { + stdout-path = &lpuart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + autorepeat; + + switch-a { + label = "switcha"; + linux,code = <BTN_0>; + gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>; + }; + + switch-b { + label = "switchb"; + linux,code = <BTN_1>; + gpios = <&lsio_gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&expander 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* TODO LVDS panels */ + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pcie_1v5: regulator-pcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "MBA8XX_PCIE_1V5"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_pcie_1v5>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&lsio_gpio0 30 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1000>; + enable-active-high; + }; + + reg_pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "MBA8XX_PCIE_3V3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_pcie_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1000>; + enable-active-high; + regulator-always-on; + }; + + reg_3v3_mb: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + audio-codec = <&tlv320aic3x04>; + ssi-controller = <&sai1>; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_1v8>; + #io-channel-cells = <1>; + status = "okay"; +}; + +&adma_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_admapwm>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&lsio_gpio3>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&lsio_gpio3>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&i2c1 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + iov-supply = <®_1v8>; + ldoin-supply = <®_3v3>; + }; + + se97b_1c: temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + at24c02_54: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_3v3>; + }; + + expander: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9538>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + vcc-supply = <®_1v8>; + + gpio-line-names = "", "LED_A", + "LED_B", "", + "DSI_EN", "USB_RESET#", + "V_12V_EN", "PCIE_DIS#"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2gpio>; + scl-gpios = <&lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* TODO LDB */ + +&lpspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi3>; + num-cs = <2>; + cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&lsio_gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lsgpio3>; + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "X4_15", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* TODO: Mini-PCIe */ + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + over-current-active-low; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3v3_mb>; + no-1-8-v; + no-sdio; + no-mmc; + status = "okay"; +}; + +&iomuxc { + pinctrl_adc0: adc0grp { + fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x02000060>, + <IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x02000060>, + <IMX8QXP_ADC_IN2_ADMA_ADC_IN2 0x02000060>, + <IMX8QXP_ADC_IN3_ADMA_ADC_IN3 0x02000060>; + }; + + pinctrl_admapwm: admapwmgrp { + fsl,pins = <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000021>; + }; + + pinctrl_bl_lvds: bllvdsgrp { + fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 0x00000021>; + }; + + pinctrl_can0: can0grp { + fsl,pins = <IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX 0x00000021>, + <IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX 0x00000021>; + }; + + pinctrl_can1: can1grp { + fsl,pins = <IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021>, + <IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021>; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins = <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x00000040>, + <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x00000040>; + }; + + pinctrl_ethphy3: ethphy3grp { + fsl,pins = <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x00000040>, + <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x00000040>; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000041>, + <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>, + <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000040>, + <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000040>, + <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000040>, + <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000040>, + <IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000040>, + <IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000040>, + <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>, + <IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>, + <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>, + <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>, + <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>, + <IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000040>, + <IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000040>, + <IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000040>, + <IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000040>, + <IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000040>, + <IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000040>, + <IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000040>, + <IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000040>, + <IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000040>, + <IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000040>, + <IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000040>, + <IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000040>; + }; + + pinctrl_gpiobuttons: gpiobuttonsgrp { + fsl,pins = <IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 0x00000020>, + <IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 0x00000020>; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL 0x06000021>, + <IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA 0x06000021>; + }; + + pinctrl_lpi2c2gpio: lpi2c2gpiogrp { + fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021>, + <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x06000021>; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = <IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020>, + <IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020>; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>, + <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>; + }; + + pinctrl_lsgpio3: lsgpio3grp { + fsl,pins = <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000021>; + }; + + pinctrl_pca9538: pca9538grp { + fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000020>; + }; + + pinctrl_pcieb: pcieagrp { + fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>, + <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>, + <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>; + }; + + pinctrl_reg_pcie_1v5: regpcie1v5grp { + fsl,pins = <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x00000021>; + }; + + pinctrl_reg_pcie_3v3: regpcie3v3grp { + fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000021>; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x06000041>, + <IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000041>, + <IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000041>, + <IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000041>, + <IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000041>; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = <IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI 0x00000041>, + <IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO 0x00000041>, + <IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK 0x00000041>, + <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x00000021>, + <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x00000021>; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x00000041>, + <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x00000041>, + <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x00000041>, + <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021>; + }; + + pinctrl_spi3: spi3grp { + fsl,pins = <IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK 0x00000041>, + <IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI 0x00000041>, + <IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO 0x00000041>, + <IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 0x00000021>, + <IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 0x00000021>; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>, + <IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021>, + <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021>; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, + <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>, + <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>, + <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>, + <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>, + <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>, + <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, + <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, + <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, + <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, + <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, + <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, + <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, + <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, + <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, + <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, + <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, + <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, + <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>; + }; +}; diff --git a/dts/src/arm64/freescale/tqma8xx.dtsi b/dts/src/arm64/freescale/tqma8xx.dtsi new file mode 100644 index 0000000000..d98469a7c4 --- /dev/null +++ b/dts/src/arm64/freescale/tqma8xx.dtsi @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * global autoconfigured region for contiguous allocations + * must not exceed memory size and region + */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x20000000>; + alloc-ranges = <0 0x96000000 0 0x30000000>; + linux,cma-default; + }; + }; +}; + +/* TQMa8Xx only uses industrial grade, reduce trip points accordingly */ +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <100000>; +}; +/* end of temperature grade adjustments */ + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <66000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +/* TODO GPU */ + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1gpio>; + scl-gpios = <&lsio_gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&lsio_gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + se97: temperature-sensor@1b { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + at24c02: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + vcc-supply = <®_3v3>; + }; + + m24c64: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; +}; + +&mu_m0 { + status = "okay"; +}; + +&mu1_m0 { + status = "okay"; +}; + +&thermal_zones { + pmic_thermal: pmic-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vqmmc-supply = <®_1v8>; + vmmc-supply = <®_3v3>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004d + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004d + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004d + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004d + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004d + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004d + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004d + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004d + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004d + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004d + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004d + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004d + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004d + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004d + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004d + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 + IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c1gpio: lpi2c1gpiogrp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 0x06000021 + IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + >; + }; +}; diff --git a/dts/src/arm64/intel/socfpga_agilex5.dtsi b/dts/src/arm64/intel/socfpga_agilex5.dtsi index d66d425e45..1162978329 100644 --- a/dts/src/arm64/intel/socfpga_agilex5.dtsi +++ b/dts/src/arm64/intel/socfpga_agilex5.dtsi @@ -202,7 +202,7 @@ status = "disabled"; }; - i3c0: i3c-master@10da0000 { + i3c0: i3c@10da0000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0x10da0000 0x1000>; #address-cells = <3>; @@ -212,7 +212,7 @@ status = "disabled"; }; - i3c1: i3c-master@10da1000 { + i3c1: i3c@10da1000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0x10da1000 0x1000>; #address-cells = <3>; diff --git a/dts/src/arm64/marvell/ac5-98dx25xx.dtsi b/dts/src/arm64/marvell/ac5-98dx25xx.dtsi index b5e042b8e9..5591939e05 100644 --- a/dts/src/arm64/marvell/ac5-98dx25xx.dtsi +++ b/dts/src/arm64/marvell/ac5-98dx25xx.dtsi @@ -77,7 +77,6 @@ #address-cells = <2>; #size-cells = <2>; ranges; - dma-ranges; internal-regs@7f000000 { #address-cells = <1>; @@ -204,6 +203,30 @@ }; }; + mmc_dma: bus@80500000 { + compatible = "simple-bus"; + ranges; + #address-cells = <0x2>; + #size-cells = <0x2>; + reg = <0x0 0x80500000 0x0 0x100000>; + dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>; + dma-coherent; + + sdhci: mmc@805c0000 { + compatible = "marvell,ac5-sdhci", + "marvell,armada-ap806-sdhci"; + reg = <0x0 0x805c0000 0x0 0x1000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&emmc_clock>, <&cnm_clock>; + clock-names = "core", "axi"; + bus-width = <8>; + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + }; + /* * Dedicated section for devices behind 32bit controllers so we * can configure specific DMA mapping for them @@ -335,5 +358,11 @@ #clock-cells = <0>; clock-frequency = <400000000>; }; + + emmc_clock: emmc-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; }; diff --git a/dts/src/arm64/marvell/ac5-98dx35xx-rd.dts b/dts/src/arm64/marvell/ac5-98dx35xx-rd.dts index f0ebdb84ee..0c973d7a21 100644 --- a/dts/src/arm64/marvell/ac5-98dx35xx-rd.dts +++ b/dts/src/arm64/marvell/ac5-98dx35xx-rd.dts @@ -99,3 +99,7 @@ }; }; }; + +&sdhci { + status = "okay"; +}; diff --git a/dts/src/arm64/marvell/armada-37xx.dtsi b/dts/src/arm64/marvell/armada-37xx.dtsi index e300145ad1..1cc3fa1c35 100644 --- a/dts/src/arm64/marvell/armada-37xx.dtsi +++ b/dts/src/arm64/marvell/armada-37xx.dtsi @@ -431,14 +431,14 @@ crypto: crypto@90000 { compatible = "inside-secure,safexcel-eip97ies"; reg = <0x90000 0x20000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ring0", "ring1", "ring2", + "ring3", "eip", "mem"; clocks = <&nb_periph_clk 15>; }; diff --git a/dts/src/arm64/marvell/armada-ap807.dtsi b/dts/src/arm64/marvell/armada-ap807.dtsi index 4a23f65d47..a3328d05fc 100644 --- a/dts/src/arm64/marvell/armada-ap807.dtsi +++ b/dts/src/arm64/marvell/armada-ap807.dtsi @@ -33,3 +33,6 @@ "marvell,armada-ap806-sdhci"; /* Backward compatibility */ }; +&ap_thermal { + compatible = "marvell,armada-ap807-thermal"; +}; diff --git a/dts/src/arm64/marvell/armada-cp11x.dtsi b/dts/src/arm64/marvell/armada-cp11x.dtsi index 4ec1aae0a3..7e595ac800 100644 --- a/dts/src/arm64/marvell/armada-cp11x.dtsi +++ b/dts/src/arm64/marvell/armada-cp11x.dtsi @@ -511,14 +511,14 @@ CP11X_LABEL(crypto): crypto@800000 { compatible = "inside-secure,safexcel-eip197b"; reg = <0x800000 0x200000>; - interrupts = <87 IRQ_TYPE_LEVEL_HIGH>, - <88 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <88 IRQ_TYPE_LEVEL_HIGH>, <89 IRQ_TYPE_LEVEL_HIGH>, <90 IRQ_TYPE_LEVEL_HIGH>, <91 IRQ_TYPE_LEVEL_HIGH>, - <92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; + <92 IRQ_TYPE_LEVEL_HIGH>, + <87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ring0", "ring1", "ring2", "ring3", + "eip", "mem"; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 26>, <&CP11X_LABEL(clk) 1 17>; diff --git a/dts/src/arm64/mediatek/mt2712-evb.dts b/dts/src/arm64/mediatek/mt2712-evb.dts index fffdb7bbf8..0c38f7b517 100644 --- a/dts/src/arm64/mediatek/mt2712-evb.dts +++ b/dts/src/arm64/mediatek/mt2712-evb.dts @@ -43,12 +43,12 @@ extcon_usb: extcon_iddig { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>; + id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>; }; extcon_usb1: extcon_iddig1 { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; + id-gpios = <&pio 14 GPIO_ACTIVE_HIGH>; }; usb_p0_vbus: regulator-usb-p0-vbus { diff --git a/dts/src/arm64/mediatek/mt2712e.dtsi b/dts/src/arm64/mediatek/mt2712e.dtsi index ed1a9d3194..6d218caa19 100644 --- a/dts/src/arm64/mediatek/mt2712e.dtsi +++ b/dts/src/arm64/mediatek/mt2712e.dtsi @@ -261,7 +261,7 @@ #clock-cells = <1>; }; - syscfg_pctl_a: syscfg_pctl_a@10005000 { + syscfg_pctl_a: syscon@10005000 { compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; }; diff --git a/dts/src/arm64/mediatek/mt6797.dtsi b/dts/src/arm64/mediatek/mt6797.dtsi index c3677d77e0..0e9d11b458 100644 --- a/dts/src/arm64/mediatek/mt6797.dtsi +++ b/dts/src/arm64/mediatek/mt6797.dtsi @@ -117,7 +117,7 @@ #clock-cells = <1>; }; - infrasys: infracfg_ao@10001000 { + infrasys: syscon@10001000 { compatible = "mediatek,mt6797-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; @@ -452,19 +452,19 @@ #clock-cells = <1>; }; - imgsys: imgsys_config@15000000 { + imgsys: syscon@15000000 { compatible = "mediatek,mt6797-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; - vdecsys: vdec_gcon@16000000 { + vdecsys: syscon@16000000 { compatible = "mediatek,mt6797-vdecsys", "syscon"; reg = <0 0x16000000 0 0x10000>; #clock-cells = <1>; }; - vencsys: venc_gcon@17000000 { + vencsys: syscon@17000000 { compatible = "mediatek,mt6797-vencsys", "syscon"; reg = <0 0x17000000 0 0x1000>; #clock-cells = <1>; diff --git a/dts/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts b/dts/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts index a1f42048dc..224bb28966 100644 --- a/dts/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/dts/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts @@ -75,6 +75,7 @@ memory@40000000 { reg = <0 0x40000000 0 0x40000000>; + device_type = "memory"; }; reg_1p8v: regulator-1p8v { @@ -185,6 +186,18 @@ label = "lan3"; }; + port@5 { + reg = <5>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; diff --git a/dts/src/arm64/mediatek/mt7622-rfb1.dts b/dts/src/arm64/mediatek/mt7622-rfb1.dts index 2dc1bdc74e..41629769bd 100644 --- a/dts/src/arm64/mediatek/mt7622-rfb1.dts +++ b/dts/src/arm64/mediatek/mt7622-rfb1.dts @@ -57,6 +57,7 @@ memory@40000000 { reg = <0 0x40000000 0 0x20000000>; + device_type = "memory"; }; reg_1p8v: regulator-1p8v { @@ -117,6 +118,18 @@ }; }; + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + mdio-bus { #address-cells = <1>; #size-cells = <0>; @@ -155,6 +168,18 @@ label = "wan"; }; + port@5 { + reg = <5>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; diff --git a/dts/src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts b/dts/src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts new file mode 100644 index 0000000000..a314c3e05e --- /dev/null +++ b/dts/src/arm64/mediatek/mt7981b-xiaomi-ax3000t.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7981b.dtsi" + +/ { + compatible = "xiaomi,ax3000t", "mediatek,mt7981b"; + model = "Xiaomi AX3000T"; + + memory@40000000 { + reg = <0 0x40000000 0 0x10000000>; + device_type = "memory"; + }; +}; diff --git a/dts/src/arm64/mediatek/mt7981b.dtsi b/dts/src/arm64/mediatek/mt7981b.dtsi new file mode 100644 index 0000000000..4feff3d1c5 --- /dev/null +++ b/dts/src/arm64/mediatek/mt7981b.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +#include <dt-bindings/clock/mediatek,mt7981-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt7981b"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>; /* GICR */ + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + infracfg: clock-controller@10001000 { + compatible = "mediatek,mt7981-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1001b000 { + compatible = "mediatek,mt7981-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1001e000 { + compatible = "mediatek,mt7981-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + pwm@10048000 { + compatible = "mediatek,mt7981-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + #pwm-cells = <2>; + }; + + clock-controller@15000000 { + compatible = "mediatek,mt7981-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/dts/src/arm64/mediatek/mt7986a-acelink-ew-7886cax.dts b/dts/src/arm64/mediatek/mt7986a-acelink-ew-7886cax.dts new file mode 100644 index 0000000000..08b3b08274 --- /dev/null +++ b/dts/src/arm64/mediatek/mt7986a-acelink-ew-7886cax.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +#include "mt7986a.dtsi" + +/ { + compatible = "acelink,ew-7886cax", "mediatek,mt7986a"; + model = "Acelink EW-7886CAX"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + reg = <0 0x40000000 0 0x20000000>; + device_type = "memory"; + }; + + keys { + compatible = "gpio-keys"; + + key-restart { + label = "Reset"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&pio 18 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy6>; + nvmem-cells = <&macaddr>; + nvmem-cell-names = "mac-address"; + }; + + mdio-bus { + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <50000>; + reset-post-delay-us = <20000>; + + #address-cells = <1>; + #size-cells = <0>; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + }; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x100000>; + label = "bootloader"; + read-only; + }; + + partition@100000 { + reg = <0x100000 0x80000>; + label = "u-boot-env"; + }; + + partition@180000 { + compatible = "nvmem-cells"; + reg = <0x180000 0x200000>; + label = "factory"; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr: macaddr@4 { + reg = <0x4 0x6>; + }; + }; + }; + + partition@380000 { + reg = <0x380000 0x200000>; + label = "fip"; + }; + + partition@580000 { + reg = <0x580000 0x4000000>; + label = "ubi"; + }; + }; + }; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + nvmem-cells = <&eeprom>; + nvmem-cell-names = "eeprom"; + status = "okay"; +}; diff --git a/dts/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/dts/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso index 543c13385d..7b97c5c91b 100644 --- a/dts/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +++ b/dts/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -15,7 +15,7 @@ __overlay__ { #address-cells = <1>; #size-cells = <0>; - spi_nand: spi_nand@0 { + spi_nand: flash@0 { compatible = "spi-nand"; reg = <0>; spi-max-frequency = <10000000>; diff --git a/dts/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts b/dts/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts index d06d4af43c..e04b1c0c0e 100644 --- a/dts/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/dts/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -43,7 +43,7 @@ #cooling-cells = <2>; /* cooling level (0, 1, 2) - pwm inverted */ cooling-levels = <255 96 0>; - pwms = <&pwm 0 10000 0>; + pwms = <&pwm 0 10000>; status = "okay"; }; diff --git a/dts/src/arm64/mediatek/mt7986a-rfb.dts b/dts/src/arm64/mediatek/mt7986a-rfb.dts index 3ef371ca25..5d8e3d3f6c 100644 --- a/dts/src/arm64/mediatek/mt7986a-rfb.dts +++ b/dts/src/arm64/mediatek/mt7986a-rfb.dts @@ -65,6 +65,18 @@ }; }; + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + mdio: mdio-bus { #address-cells = <1>; #size-cells = <0>; @@ -237,12 +249,13 @@ pinctrl-0 = <&spi_flash_pins>; cs-gpios = <0>, <0>; status = "okay"; - spi_nand: spi_nand@0 { + + spi_nand: flash@0 { compatible = "spi-nand"; reg = <0>; spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; }; }; @@ -287,6 +300,18 @@ label = "lan4"; }; + port@5 { + reg = <5>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; diff --git a/dts/src/arm64/mediatek/mt7986a.dtsi b/dts/src/arm64/mediatek/mt7986a.dtsi index fc751e0499..b3f416b9a7 100644 --- a/dts/src/arm64/mediatek/mt7986a.dtsi +++ b/dts/src/arm64/mediatek/mt7986a.dtsi @@ -16,49 +16,49 @@ #address-cells = <2>; #size-cells = <2>; - clk40m: oscillator-40m { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; - }; - cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { - device_type = "cpu"; compatible = "arm,cortex-a53"; - enable-method = "psci"; reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; #cooling-cells = <2>; }; cpu1: cpu@1 { - device_type = "cpu"; compatible = "arm,cortex-a53"; - enable-method = "psci"; reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; #cooling-cells = <2>; }; cpu2: cpu@2 { - device_type = "cpu"; compatible = "arm,cortex-a53"; - enable-method = "psci"; reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; #cooling-cells = <2>; }; cpu3: cpu@3 { - device_type = "cpu"; - enable-method = "psci"; compatible = "arm,cortex-a53"; reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; #cooling-cells = <2>; }; }; + clk40m: oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -121,38 +121,30 @@ }; - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; compatible = "simple-bus"; ranges; + #address-cells = <2>; + #size-cells = <2>; gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; reg = <0 0x0c000000 0 0x10000>, /* GICD */ <0 0x0c080000 0 0x80000>, /* GICR */ <0 0x0c400000 0 0x2000>, /* GICC */ <0 0x0c410000 0 0x1000>, /* GICH */ <0 0x0c420000 0 0x2000>; /* GICV */ + interrupt-parent = <&gic>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; }; infracfg: infracfg@10001000 { compatible = "mediatek,mt7986-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; wed_pcie: wed-pcie@10003000 { @@ -202,6 +194,19 @@ #interrupt-cells = <2>; }; + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>; + clock-names = "top", "main", "pwm1", "pwm2"; + status = "disabled"; + }; + sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7986-sgmiisys_0", "syscon"; @@ -234,26 +239,11 @@ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ring0", "ring1", "ring2", "ring3"; clocks = <&infracfg CLK_INFRA_EIP97_CK>; - clock-names = "infra_eip97_ck"; assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; status = "disabled"; }; - pwm: pwm@10048000 { - compatible = "mediatek,mt7986-pwm"; - reg = <0 0x10048000 0 0x1000>; - #clock-cells = <1>; - #pwm-cells = <2>; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>; - clock-names = "top", "main", "pwm1", "pwm2"; - status = "disabled"; - }; - uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; @@ -311,9 +301,9 @@ spi0: spi@1100a000 { compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100a000 0 0x100>; #address-cells = <1>; #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topckgen CLK_TOP_MPLL_D2>, <&topckgen CLK_TOP_SPI_SEL>, @@ -325,9 +315,9 @@ spi1: spi@1100b000 { compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100b000 0 0x100>; #address-cells = <1>; #size-cells = <0>; - reg = <0 0x1100b000 0 0x100>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topckgen CLK_TOP_MPLL_D2>, <&topckgen CLK_TOP_SPIM_MST_SEL>, @@ -337,6 +327,21 @@ status = "disabled"; }; + thermal: thermal@1100c800 { + compatible = "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "therm", "auxadc", "adc_32k"; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; + auxadc: adc@1100d000 { compatible = "mediatek,mt7986-auxadc"; reg = <0 0x1100d000 0 0x1000>; @@ -388,39 +393,23 @@ status = "disabled"; }; - thermal: thermal@1100c800 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "therm", "auxadc", "adc_32k"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - pcie: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; + reg = <0x00 0x11280000 0x00 0x4000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x10000000>; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; - reg = <0x00 0x11280000 0x00 0x4000>; - reg-names = "pcie-mac"; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; bus-range = <0x00 0xff>; - ranges = <0x82000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x10000000>; clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, <&infracfg CLK_INFRA_IPCIE_CK>, <&infracfg CLK_INFRA_IPCIER_CK>, <&infracfg CLK_INFRA_IPCIEB_CK>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; - status = "disabled"; phys = <&pcie_port PHY_TYPE_PCIE>; phy-names = "pcie-phy"; @@ -431,6 +420,8 @@ <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; + status = "disabled"; + pcie_intc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; @@ -441,9 +432,9 @@ pcie_phy: t-phy { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; + ranges; #address-cells = <2>; #size-cells = <2>; - ranges; status = "disabled"; pcie_port: pcie-phy@11c00000 { @@ -468,9 +459,9 @@ usb_phy: t-phy@11e10000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; + ranges = <0 0 0x11e10000 0x1700>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0 0x11e10000 0x1700>; status = "disabled"; u2port0: usb-phy@0 { @@ -498,11 +489,11 @@ }; ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; compatible = "mediatek,mt7986-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -533,20 +524,6 @@ mediatek,wo-ccif = <&wo_ccif1>; }; - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; - }; - - wo_ccif1: syscon@151ad000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; - }; - eth: ethernet@15100000 { compatible = "mediatek,mt7986-eth"; reg = <0 0x15100000 0 0x80000>; @@ -579,26 +556,40 @@ <&topckgen CLK_TOP_SGM_325M_SEL>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, <&apmixedsys CLK_APMIXED_SGMPLL>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; mediatek,ethsys = <ðsys>; mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; mediatek,wed-pcie = <&wed_pcie>; mediatek,wed = <&wed0>, <&wed1>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + }; + + wo_ccif1: syscon@151ad000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + }; + wifi: wifi@18000000 { compatible = "mediatek,mt7986-wmac"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; clock-names = "mcu", "ap2conn"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, @@ -646,4 +637,13 @@ }; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; }; diff --git a/dts/src/arm64/mediatek/mt7986b-rfb.dts b/dts/src/arm64/mediatek/mt7986b-rfb.dts index dde190442e..58f77d9324 100644 --- a/dts/src/arm64/mediatek/mt7986b-rfb.dts +++ b/dts/src/arm64/mediatek/mt7986b-rfb.dts @@ -45,6 +45,18 @@ }; }; + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + mdio: mdio-bus { #address-cells = <1>; #size-cells = <0>; @@ -83,6 +95,18 @@ label = "lan4"; }; + port@5 { + reg = <5>; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; @@ -152,12 +176,13 @@ pinctrl-0 = <&spi_flash_pins>; cs-gpios = <0>, <0>; status = "okay"; - spi_nand: spi_nand@0 { + + spi_nand: flash@0 { compatible = "spi-nand"; reg = <0>; spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; }; }; diff --git a/dts/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts b/dts/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts new file mode 100644 index 0000000000..efc4ad0b08 --- /dev/null +++ b/dts/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7988a.dtsi" + +/ { + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; + model = "Banana Pi BPI-R4"; + chassis-type = "embedded"; +}; diff --git a/dts/src/arm64/mediatek/mt7988a.dtsi b/dts/src/arm64/mediatek/mt7988a.dtsi new file mode 100644 index 0000000000..bba97de4fb --- /dev/null +++ b/dts/src/arm64/mediatek/mt7988a.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt7988a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a73"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a73"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a73"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a73"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + + pmu { + compatible = "arm,cortex-a73-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + clock-controller@10001000 { + compatible = "mediatek,mt7988-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@1001b000 { + compatible = "mediatek,mt7988-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7988-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + clock-controller@1001e000 { + compatible = "mediatek,mt7988-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + clock-controller@11f40000 { + compatible = "mediatek,mt7988-xfi-pll"; + reg = <0 0x11f40000 0 0x1000>; + resets = <&watchdog 16>; + #clock-cells = <1>; + }; + + clock-controller@15000000 { + compatible = "mediatek,mt7988-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock-controller@15031000 { + compatible = "mediatek,mt7988-ethwarp"; + reg = <0 0x15031000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/dts/src/arm64/mediatek/mt8173-elm-hana-rev7.dts b/dts/src/arm64/mediatek/mt8173-elm-hana-rev7.dts index 256f245ac0..1c9fc791bd 100644 --- a/dts/src/arm64/mediatek/mt8173-elm-hana-rev7.dts +++ b/dts/src/arm64/mediatek/mt8173-elm-hana-rev7.dts @@ -14,7 +14,7 @@ &cpu_thermal { trips { - cpu_crit: cpu_crit0 { + cpu_crit: cpu-crit0 { temperature = <100000>; type = "critical"; }; diff --git a/dts/src/arm64/mediatek/mt8173-elm.dtsi b/dts/src/arm64/mediatek/mt8173-elm.dtsi index 8d614ac2c5..6d962d437e 100644 --- a/dts/src/arm64/mediatek/mt8173-elm.dtsi +++ b/dts/src/arm64/mediatek/mt8173-elm.dtsi @@ -1135,7 +1135,7 @@ compatible = "mediatek,mt6397-rtc"; }; - syscfg_pctl_pmic: syscfg_pctl_pmic@c000 { + syscfg_pctl_pmic: syscon@c000 { compatible = "mediatek,mt6397-pctl-pmic-syscfg", "syscon"; reg = <0 0x0000c000 0 0x0108>; @@ -1155,6 +1155,7 @@ spi-max-frequency = <12000000>; interrupts-extended = <&pio 0 IRQ_TYPE_LEVEL_LOW>; google,cros-ec-spi-msg-delay = <500>; + wakeup-source; i2c_tunnel: i2c-tunnel0 { compatible = "google,cros-ec-i2c-tunnel"; diff --git a/dts/src/arm64/mediatek/mt8173-evb.dts b/dts/src/arm64/mediatek/mt8173-evb.dts index 0e5c628d1e..3fab21f59d 100644 --- a/dts/src/arm64/mediatek/mt8173-evb.dts +++ b/dts/src/arm64/mediatek/mt8173-evb.dts @@ -41,7 +41,7 @@ extcon_usb: extcon_iddig { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + id-gpios = <&pio 16 GPIO_ACTIVE_HIGH>; }; usb_p1_vbus: regulator-usb-p1 { diff --git a/dts/src/arm64/mediatek/mt8173.dtsi b/dts/src/arm64/mediatek/mt8173.dtsi index cac4cd0a03..3458be7f7f 100644 --- a/dts/src/arm64/mediatek/mt8173.dtsi +++ b/dts/src/arm64/mediatek/mt8173.dtsi @@ -222,14 +222,14 @@ }; }; - pmu_a53 { + pmu-a53 { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; interrupt-affinity = <&cpu0>, <&cpu1>; }; - pmu_a72 { + pmu-a72 { compatible = "arm,cortex-a72-pmu"; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; @@ -286,7 +286,7 @@ type = "passive"; }; - cpu_crit: cpu_crit0 { + cpu_crit: cpu-crit0 { temperature = <115000>; hysteresis = <2000>; type = "critical"; @@ -318,7 +318,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; - vpu_dma_reserved: vpu_dma_mem_region@b7000000 { + vpu_dma_reserved: vpu-dma-mem@b7000000 { compatible = "shared-dma-pool"; reg = <0 0xb7000000 0 0x500000>; alignment = <0x1000>; @@ -366,7 +366,7 @@ #reset-cells = <1>; }; - syscfg_pctl_a: syscfg_pctl_a@10005000 { + syscfg_pctl_a: syscon@10005000 { compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; }; @@ -590,6 +590,15 @@ reg = <0 0x10206000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + socinfo-data1@40 { + reg = <0x040 0x4>; + }; + + socinfo-data2@44 { + reg = <0x044 0x4>; + }; + thermal_calibration: calib@528 { reg = <0x528 0xc>; }; diff --git a/dts/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi index b6a9830af2..bfb9e42c8a 100644 --- a/dts/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi +++ b/dts/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi @@ -360,6 +360,10 @@ }; &cros_ec { + cbas { + compatible = "google,cros-cbas"; + }; + keyboard-controller { compatible = "google,cros-ec-keyb-switches"; }; diff --git a/dts/src/arm64/mediatek/mt8183-kukui-kodama.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-kodama.dtsi index 306c95166f..5c1bf6a1e4 100644 --- a/dts/src/arm64/mediatek/mt8183-kukui-kodama.dtsi +++ b/dts/src/arm64/mediatek/mt8183-kukui-kodama.dtsi @@ -339,6 +339,10 @@ }; &cros_ec { + cbas { + compatible = "google,cros-cbas"; + }; + keyboard-controller { compatible = "google,cros-ec-keyb-switches"; }; diff --git a/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi b/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi index 382e4c6d71..0f5fa893a7 100644 --- a/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi +++ b/dts/src/arm64/mediatek/mt8183-kukui-krane.dtsi @@ -343,6 +343,10 @@ }; &cros_ec { + cbas { + compatible = "google,cros-cbas"; + }; + keyboard-controller { compatible = "google,cros-ec-keyb-switches"; }; diff --git a/dts/src/arm64/mediatek/mt8183-kukui.dtsi b/dts/src/arm64/mediatek/mt8183-kukui.dtsi index 1b3396b1ce..6bd7424ef6 100644 --- a/dts/src/arm64/mediatek/mt8183-kukui.dtsi +++ b/dts/src/arm64/mediatek/mt8183-kukui.dtsi @@ -924,6 +924,7 @@ interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_odl>; + wakeup-source; i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel"; @@ -937,10 +938,6 @@ google,usb-port-id = <0>; }; - cbas { - compatible = "google,cros-cbas"; - }; - typec { compatible = "google,cros-ec-typec"; #address-cells = <1>; diff --git a/dts/src/arm64/mediatek/mt8183-pumpkin.dts b/dts/src/arm64/mediatek/mt8183-pumpkin.dts index 76449b4cf2..333c516af4 100644 --- a/dts/src/arm64/mediatek/mt8183-pumpkin.dts +++ b/dts/src/arm64/mediatek/mt8183-pumpkin.dts @@ -33,7 +33,7 @@ #size-cells = <2>; ranges; - scp_mem_reserved: scp_mem_region@50000000 { + scp_mem_reserved: scp-mem@50000000 { compatible = "shared-dma-pool"; reg = <0 0x50000000 0 0x2900000>; no-map; diff --git a/dts/src/arm64/mediatek/mt8183.dtsi b/dts/src/arm64/mediatek/mt8183.dtsi index 920ee415ef..93dfbf1302 100644 --- a/dts/src/arm64/mediatek/mt8183.dtsi +++ b/dts/src/arm64/mediatek/mt8183.dtsi @@ -1585,6 +1585,15 @@ reg = <0 0x11f10000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + socinfo-data1@4c { + reg = <0x04c 0x4>; + }; + + socinfo-data2@60 { + reg = <0x060 0x4>; + }; + thermal_calibration: calib@180 { reg = <0x180 0xc>; }; @@ -1955,7 +1964,7 @@ power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; }; - venc_jpg: venc_jpg@17030000 { + venc_jpg: jpeg-encoder@17030000 { compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; reg = <0 0x17030000 0 0x1000>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-krabby.dtsi b/dts/src/arm64/mediatek/mt8186-corsola-krabby.dtsi new file mode 100644 index 0000000000..7c971198fa --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-krabby.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + i2c4 = &i2c4; + }; +}; + +&dsi_out { + remote-endpoint = <&ps8640_in>; +}; + +&i2c0 { + clock-frequency = <400000>; + + edp-bridge@8 { + compatible = "parade,ps8640"; + reg = <0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&ps8640_pins>; + powerdown-gpios = <&pio 96 GPIO_ACTIVE_LOW>; + reset-gpios = <&pio 98 GPIO_ACTIVE_LOW>; + vdd12-supply = <&mt6366_vrf12_reg>; + vdd33-supply = <&mt6366_vcn33_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ps8640_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + ps8640_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&pp3300_disp_x>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&ps8640_out>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + i2c-scl-internal-delay-ns = <10000>; + + touchscreen: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_s3>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <400000>; + status = "okay"; + + proximity@28 { + compatible = "semtech,sx9324"; + reg = <0x28>; + #io-channel-cells = <1>; + interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sar_sensor_pins>; + vdd-supply = <&mt6366_vio18_reg>; + svdd-supply = <&mt6366_vio18_reg>; + }; +}; + +&pio { + i2c4_pins: i2c4-pins { + pins-bus { + pinmux = <PINMUX_GPIO136__FUNC_SDA4>, + <PINMUX_GPIO135__FUNC_SCL4>; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + ps8640_pins: ps8640-pins { + pins-pwrdn-rst { + pinmux = <PINMUX_GPIO96__FUNC_GPIO96>, + <PINMUX_GPIO98__FUNC_GPIO98>; + output-low; + }; + }; + + sar_sensor_pins: sar-sensor-pins { + pins-irq { + pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; + input-enable; + bias-pull-up; + }; + }; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-magneton-sku393216.dts b/dts/src/arm64/mediatek/mt8186-corsola-magneton-sku393216.dts new file mode 100644 index 0000000000..c9673381ad --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-magneton-sku393216.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Magneton board"; + compatible = "google,steelix-sku393219", "google,steelix-sku393216", + "google,steelix", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +&gpio_keys { + status = "disabled"; +}; + +&i2c1 { + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + vdd-supply = <&pp3300_s3>; + post-power-on-delay-ms = <350>; + hid-descr-addr = <0x0001>; + }; +}; + +&touchscreen { + status = "disabled"; +}; + +&usb_c1 { + status = "disabled"; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-magneton-sku393217.dts b/dts/src/arm64/mediatek/mt8186-corsola-magneton-sku393217.dts new file mode 100644 index 0000000000..28e3bbe564 --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-magneton-sku393217.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Magneton board"; + compatible = "google,steelix-sku393220", "google,steelix-sku393217", + "google,steelix", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +&gpio_keys { + status = "disabled"; +}; + +&i2c1 { + touchscreen@40 { + compatible = "hid-over-i2c"; + reg = <0x40>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + vdd-supply = <&pp3300_s3>; + post-power-on-delay-ms = <450>; + hid-descr-addr = <0x0001>; + }; +}; + +&touchscreen { + status = "disabled"; +}; + +&usb_c1 { + status = "disabled"; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-magneton-sku393218.dts b/dts/src/arm64/mediatek/mt8186-corsola-magneton-sku393218.dts new file mode 100644 index 0000000000..332894218f --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-magneton-sku393218.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Magneton board"; + compatible = "google,steelix-sku393221", "google,steelix-sku393218", + "google,steelix", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +&gpio_keys { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; + +&usb_c1 { + status = "disabled"; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-rusty-sku196608.dts b/dts/src/arm64/mediatek/mt8186-corsola-rusty-sku196608.dts new file mode 100644 index 0000000000..731b0d6022 --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-rusty-sku196608.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Rusty board"; + compatible = "google,steelix-sku196609", "google,steelix-sku196608", + "google,steelix", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +&gpio_keys { + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; +}; + +&touchscreen { + status = "disabled"; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-steelix-sku131072.dts b/dts/src/arm64/mediatek/mt8186-corsola-steelix-sku131072.dts new file mode 100644 index 0000000000..eae17bca85 --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-steelix-sku131072.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Steelix board"; + compatible = "google,steelix-sku131072", "google,steelix", + "mediatek,mt8186"; + chassis-type = "convertible"; +}; + +&mt6366codec { + mediatek,dmic-mode = <0>; /* two-wire */ +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-steelix-sku131073.dts b/dts/src/arm64/mediatek/mt8186-corsola-steelix-sku131073.dts new file mode 100644 index 0000000000..a55375b95d --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-steelix-sku131073.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-steelix.dtsi" + +/ { + model = "Google Steelix board"; + compatible = "google,steelix-sku131073", "google,steelix", + "mediatek,mt8186"; + chassis-type = "convertible"; +}; + +&mt6366codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-steelix.dtsi b/dts/src/arm64/mediatek/mt8186-corsola-steelix.dtsi new file mode 100644 index 0000000000..e74e886a00 --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-steelix.dtsi @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/{ + pp1000_edpbrdg: regulator-pp1000-edpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1000_edpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp1000_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 29 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_z2>; + }; + + pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx { + compatible = "regulator-fixed"; + regulator-name = "pp1800_edpbrdg_dx"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp1800_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 30 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6366_vio18_reg>; + }; + + pp3300_edp_dx: regulator-pp3300-edp-dx { + compatible = "regulator-fixed"; + regulator-name = "pp3300_edp_dx"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 31 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_z2>; + }; +}; + +&dsi_out { + remote-endpoint = <&anx7625_in>; +}; + +&i2c0 { + clock-frequency = <400000>; + + anx_bridge: anx7625@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&anx7625_pins>; + enable-gpios = <&pio 96 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&pp1000_edpbrdg>; + vdd18-supply = <&pp1800_edpbrdg_dx>; + vdd33-supply = <&pp3300_edp_dx>; + analogix,lane0-swing = /bits/ 8 <0x70 0x30>; + analogix,lane1-swing = /bits/ 8 <0x70 0x30>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <0 1 2 3>; + }; + }; + + port@1 { + reg = <1>; + + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <&pp3300_disp_x>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&anx7625_out>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + touchscreen: touchscreen@5d { + compatible = "goodix,gt7375p"; + reg = <0x5d>; + interrupts-extended = <&pio 12 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vdd-supply = <&pp3300_s3>; + goodix,no-reset-during-suspend; + }; +}; + +&i2c2 { + i2c-scl-internal-delay-ns = <22000>; + + /* second source component */ + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&pp3300_s3>; + wakeup-source; + }; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x01, 0x04, KEY_MICMUTE) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&pio { + anx7625_pins: anx7625-pins { + pins-int { + pinmux = <PINMUX_GPIO9__FUNC_GPIO9>; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = <PINMUX_GPIO98__FUNC_GPIO98>; + output-low; + }; + + pins-power-en { + pinmux = <PINMUX_GPIO96__FUNC_GPIO96>; + output-low; + }; + }; + + en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins { + pins-vreg-en { + pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; + output-low; + }; + }; + + en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins { + pins-vreg-en { + pinmux = <PINMUX_GPIO30__FUNC_GPIO30>; + output-low; + }; + }; + + en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins { + pins-vreg-en { + pinmux = <PINMUX_GPIO31__FUNC_GPIO31>; + output-low; + }; + }; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-tentacool-sku327681.dts b/dts/src/arm64/mediatek/mt8186-corsola-tentacool-sku327681.dts new file mode 100644 index 0000000000..9bb64353ca --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-tentacool-sku327681.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-krabby.dtsi" + +/ { + model = "Google Tentacool board"; + compatible = "google,tentacruel-sku327681", "google,tentacruel", "mediatek,mt8186"; + chassis-type = "laptop"; +}; + +/* Tentacool omits the pen. */ +&gpio_keys { + status = "disabled"; +}; + +/* Tentacool omits the touchscreen; nothing else is on i2c1. */ +&i2c1 { + status = "disabled"; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +/* Tentacool omits the touchscreen. */ +&touchscreen { + status = "disabled"; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-tentacool-sku327683.dts b/dts/src/arm64/mediatek/mt8186-corsola-tentacool-sku327683.dts new file mode 100644 index 0000000000..c3ae6f9616 --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-tentacool-sku327683.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ + +#include "mt8186-corsola-tentacool-sku327681.dts" + +/ { + compatible = "google,tentacruel-sku327683", "google,tentacruel", "mediatek,mt8186"; +}; + +/* This variant replaces only the trackpad controller. */ +&i2c2 { + /delete-node/ trackpad@15; + + trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_s3>; + wakeup-source; + }; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262144.dts b/dts/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262144.dts new file mode 100644 index 0000000000..26d3451a5e --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262144.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-krabby.dtsi" + +/ { + model = "Google Tentacruel board"; + compatible = "google,tentacruel-sku262147", "google,tentacruel-sku262146", + "google,tentacruel-sku262145", "google,tentacruel-sku262144", + "google,tentacruel", "mediatek,mt8186"; + chassis-type = "convertible"; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262148.dts b/dts/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262148.dts new file mode 100644 index 0000000000..447b57b12b --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola-tentacruel-sku262148.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ + +#include "mt8186-corsola-tentacruel-sku262144.dts" + +/ { + compatible = "google,tentacruel-sku262151", "google,tentacruel-sku262150", + "google,tentacruel-sku262149", "google,tentacruel-sku262148", + "google,tentacruel", "mediatek,mt8186"; +}; + +/* This variant replaces only the trackpad controller. */ +&i2c2 { + /delete-node/ trackpad@15; + + trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_s3>; + wakeup-source; + }; +}; diff --git a/dts/src/arm64/mediatek/mt8186-corsola.dtsi b/dts/src/arm64/mediatek/mt8186-corsola.dtsi new file mode 100644 index 0000000000..3dea28f1d8 --- /dev/null +++ b/dts/src/arm64/mediatek/mt8186-corsola.dtsi @@ -0,0 +1,1681 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8186.dtsi" +#include <dt-bindings/pinctrl/mt8186-pinfunc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/regulator/mediatek,mt6397-regulator.h> + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + /* The size should be filled in by the bootloader. */ + reg = <0 0x40000000 0 0>; + }; + + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 500000>; + power-supply = <&ppvar_sys>; + enable-gpios = <&pio 152 0>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + }; + + bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <0>; + }; + + dmic-codec { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <2>; + wakeup-delay-ms = <50>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pen_eject>; + + pen_insert: pen-insert-switch { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&pio 18 GPIO_ACTIVE_LOW>; + wakeup-event-action = <EV_ACT_DEASSERTED>; + wakeup-source; + linux,code = <SW_PEN_INSERTED>; + linux,input-type = <EV_SW>; + }; + }; + + pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp1800_dpbrdg>; + gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + regulator-name = "pp1800_dpbrdg_dx"; + enable-active-high; + vin-supply = <&mt6366_vio18_reg>; + }; + + pp3300_disp_x: regulator-pp3300-disp-x { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_fixed_pins>; + gpios = <&pio 153 GPIO_ACTIVE_HIGH>; + regulator-name = "pp3300_disp_x"; + enable-active-high; + regulator-boot-on; + vin-supply = <&pp3300_z2>; + }; + + /* system wide LDO 3.3V power rail */ + pp3300_z5: regulator-pp3300-ldo-z5 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_ldo_z5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_s3: regulator-pp3300-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_s3"; + /* automatically sequenced by PMIC EXT_PMIC_EN2 */ + regulator-always-on; + regulator-boot-on; + vin-supply = <&pp3300_z2>; + }; + + /* system wide 3.3V power rail */ + pp3300_z2: regulator-pp3300-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_z2"; + /* EN pin tied to pp4200_z2, which is controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide 4.2V power rail */ + pp4200_z2: regulator-pp4200-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp4200_z2"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_z2: regulator-pp5000-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp5000_z2"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-ppvar-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xA00000>; + no-map; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x10a0000>; + no-map; + }; + }; + + sound: sound { + compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound"; + pinctrl-names = "aud_clk_mosi_off", + "aud_clk_mosi_on", + "aud_clk_miso_off", + "aud_clk_miso_on", + "aud_dat_miso_off", + "aud_dat_miso_on", + "aud_dat_mosi_off", + "aud_dat_mosi_on", + "aud_gpio_i2s0_off", + "aud_gpio_i2s0_on", + "aud_gpio_i2s1_off", + "aud_gpio_i2s1_on", + "aud_gpio_i2s2_off", + "aud_gpio_i2s2_on", + "aud_gpio_i2s3_off", + "aud_gpio_i2s3_on", + "aud_gpio_pcm_off", + "aud_gpio_pcm_on", + "aud_gpio_dmic_sec"; + pinctrl-0 = <&aud_clk_mosi_off>; + pinctrl-1 = <&aud_clk_mosi_on>; + pinctrl-2 = <&aud_clk_miso_off>; + pinctrl-3 = <&aud_clk_miso_on>; + pinctrl-4 = <&aud_dat_miso_off>; + pinctrl-5 = <&aud_dat_miso_on>; + pinctrl-6 = <&aud_dat_mosi_off>; + pinctrl-7 = <&aud_dat_mosi_on>; + pinctrl-8 = <&aud_gpio_i2s0_off>; + pinctrl-9 = <&aud_gpio_i2s0_on>; + pinctrl-10 = <&aud_gpio_i2s1_off>; + pinctrl-11 = <&aud_gpio_i2s1_on>; + pinctrl-12 = <&aud_gpio_i2s2_off>; + pinctrl-13 = <&aud_gpio_i2s2_on>; + pinctrl-14 = <&aud_gpio_i2s3_off>; + pinctrl-15 = <&aud_gpio_i2s3_on>; + pinctrl-16 = <&aud_gpio_pcm_off>; + pinctrl-17 = <&aud_gpio_pcm_on>; + pinctrl-18 = <&aud_gpio_dmic_sec>; + mediatek,adsp = <&adsp>; + mediatek,platform = <&afe>; + + playback-codecs { + sound-dai = <&it6505dptx>, <&rt1019p>; + }; + + headset-codec { + sound-dai = <&rt5682s 0>; + }; + }; + + rt1019p: speaker-codec { + compatible = "realtek,rt1019p"; + pinctrl-names = "default"; + pinctrl-0 = <&rt1019p_pins_default>; + #sound-dai-cells = <0>; + sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; + }; + + usb_p1_vbus: regulator-usb-p1-vbus { + compatible = "regulator-fixed"; + gpio = <&pio 148 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + vin-supply = <&pp5000_z2>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_pin>; + post-power-on-delay-ms = <50>; + reset-gpios = <&pio 54 GPIO_ACTIVE_LOW>; + }; + + wifi_wakeup: wifi-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wakeup_pin>; + + wowlan-event { + label = "Wake on WiFi"; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + status = "okay"; +}; + +&cci { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu0 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu1 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu2 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu3 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu4 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu5 { + proc-supply = <&mt6366_vproc12_reg>; +}; + +&cpu6 { + proc-supply = <&mt6366_vproc11_reg>; +}; + +&cpu7 { + proc-supply = <&mt6366_vproc11_reg>; +}; + +&dpi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dpi_pins_default>; + pinctrl-1 = <&dpi_pins_sleep>; + status = "okay"; +}; + +&dpi_out { + remote-endpoint = <&it6505_in>; +}; + +&dsi0 { + status = "okay"; +}; + +&gic { + mediatek,broken-save-restore-fw; +}; + +&gpu { + mali-supply = <&mt6366_vgpu_reg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <8000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + /* + * Trackpad pin put here to work around second source components + * sharing the pinmux in steelix designs. + */ + pinctrl-0 = <&i2c2_pins>, <&trackpad_pin>; + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <10000>; + status = "okay"; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <&pp3300_s3>; + wakeup-source; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + status = "okay"; + + it6505dptx: dp-bridge@5c { + compatible = "ite,it6505"; + reg = <0x5c>; + interrupts-extended = <&pio 8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&it6505_pins>; + #sound-dai-cells = <0>; + ovdd-supply = <&mt6366_vsim2_reg>; + pwr18-supply = <&pp1800_dpbrdg_dx>; + reset-gpios = <&pio 177 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + it6505_in: endpoint { + link-frequencies = /bits/ 64 <150000000>; + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + status = "okay"; + + rt5682s: codec@1a { + compatible = "realtek,rt5682s"; + reg = <0x1a>; + interrupts-extended = <&pio 17 IRQ_TYPE_EDGE_BOTH>; + #sound-dai-cells = <1>; + AVDD-supply = <&mt6366_vio18_reg>; + DBVDD-supply = <&mt6366_vio18_reg>; + LDO1-IN-supply = <&mt6366_vio18_reg>; + MICVDD-supply = <&pp3300_z2>; + realtek,jd-src = <1>; + }; +}; + +&mfg0 { + domain-supply = <&mt6366_vsram_gpu_reg>; +}; + +&mfg1 { + domain-supply = <&mt6366_vgpu_reg>; +}; + +&mipi_tx0 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + no-sd; + no-sdio; + cap-mmc-hw-reset; + hs400-ds-delay = <0x11814>; + mediatek,hs400-ds-dly3 = <0x14>; + vmmc-supply = <&mt6366_vemc_reg>; + vqmmc-supply = <&mt6366_vio18_reg>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs", "state_eint"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + pinctrl-2 = <&mmc1_pins_eint>; + /delete-property/ interrupts; + interrupt-names = "msdc", "sdio_wakeup"; + interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 87 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr104; + sd-uhs-sdr50; + keep-power-in-suspend; + wakeup-source; + cap-sdio-irq; + no-mmc; + no-sd; + non-removable; + vmmc-supply = <&pp3300_s3>; + vqmmc-supply = <&mt6366_vio18_reg>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; + + bluetooth@2 { + compatible = "mediatek,mt7921s-bluetooth"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins_reset>; + reset-gpios = <&pio 155 GPIO_ACTIVE_LOW>; + }; +}; + +&nor_flash { + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>; + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <39000000>; + }; +}; + +&pio { + /* 185 lines */ + gpio-line-names = "TP", + "TP", + "TP", + "I2S0_HP_DI", + "I2S3_DP_SPKR_DO", + "SAR_INT_ODL", + "BT_WAKE_AP_ODL", + "WIFI_INT_ODL", + "DPBRDG_INT_ODL", + "EDPBRDG_INT_ODL", + "EC_AP_HPD_OD", + "TCHPAD_INT_ODL", + "TCHSCR_INT_1V8_ODL", + "EC_AP_INT_ODL", + "EC_IN_RW_ODL", + "GSC_AP_INT_ODL", + /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ + "AP_FLASH_WP_L", + "HP_INT_ODL", + "PEN_EJECT_OD", + "WCAM_PWDN_L", + "WCAM_RST_L", + "UCAM_SEN_EN", + "UCAM_RST_L", + "LTE_RESET_L", + "LTE_SAR_DETECT_L", + "I2S2_DP_SPK_MCK", + "I2S2_DP_SPKR_BCK", + "I2S2_DP_SPKR_LRCK", + "I2S2_DP_SPKR_DI (TP)", + "EN_PP1000_EDPBRDG", + "EN_PP1800_EDPBRDG", + "EN_PP3300_EDPBRDG", + "UART_GSC_TX_AP_RX", + "UART_AP_TX_GSC_RX", + "UART_DBGCON_TX_ADSP_RX", + "UART_ADSP_TX_DBGCON_RX", + "EN_PP1000_DPBRDG", + "TCHSCR_REPORT_DISABLE", + "EN_PP3300_DPBRDG", + "EN_PP1800_DPBRDG", + "SPI_AP_CLK_EC", + "SPI_AP_CS_EC_L", + "SPI_AP_DO_EC_DI", + "SPI_AP_DI_EC_DO", + "SPI_AP_CLK_GSC", + "SPI_AP_CS_GSC_L", + "SPI_AP_DO_GSC_DI", + "SPI_AP_DI_GSC_DO", + "UART_DBGCON_TX_SCP_RX", + "UART_SCP_TX_DBGCON_RX", + "EN_PP1200_CAM_X", + "EN_PP2800A_VCM_X", + "EN_PP2800A_UCAM_X", + "EN_PP2800A_WCAM_X", + "WLAN_MODULE_RST_L", + "EN_PP1200_UCAM_X", + "I2S1_HP_DO", + "I2S1_HP_BCK", + "I2S1_HP_LRCK", + "I2S1_HP_MCK", + "TCHSCR_RST_1V8_L", + "SPI_AP_CLK_ROM", + "SPI_AP_CS_ROM_L", + "SPI_AP_DO_ROM_DI", + "SPI_AP_DI_ROM_DO", + "NC", + "NC", + "EMMC_STRB", + "EMMC_CLK", + "EMMC_CMD", + "EMMC_RST_L", + "EMMC_DATA0", + "EMMC_DATA1", + "EMMC_DATA2", + "EMMC_DATA3", + "EMMC_DATA4", + "EMMC_DATA5", + "EMMC_DATA6", + "EMMC_DATA7", + "AP_KPCOL0", + "NC", + "NC", + "NC", + "TP", + "SDIO_CLK", + "SDIO_CMD", + "SDIO_DATA0", + "SDIO_DATA1", + "SDIO_DATA2", + "SDIO_DATA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "EDPBRDG_PWREN", + "BL_PWM_1V8", + "EDPBRDG_RST_L", + "MIPI_DPI_CLK", + "MIPI_DPI_VSYNC", + "MIPI_DPI_HSYNC", + "MIPI_DPI_DE", + "MIPI_DPI_D0", + "MIPI_DPI_D1", + "MIPI_DPI_D2", + "MIPI_DPI_D3", + "MIPI_DPI_D4", + "MIPI_DPI_D5", + "MIPI_DPI_D6", + "MIPI_DPI_DA7", + "MIPI_DPI_D8", + "MIPI_DPI_D9", + "MIPI_DPI_D10", + "MIPI_DPI_D11", + "PCM_BT_CLK", + "PCM_BT_SYNC", + "PCM_BT_DI", + "PCM_BT_DO", + "JTAG_TMS_TP", + "JTAG_TCK_TP", + "JTAG_TDI_TP", + "JTAG_TDO_TP", + "JTAG_TRSTN_TP", + "CLK_24M_WCAM", + "CLK_24M_UCAM", + "UCAM_DET_ODL", + "AP_I2C_EDPBRDG_SCL_1V8", + "AP_I2C_EDPBRDG_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_TCHPAD_SCL_1V8", + "AP_I2C_TCHPAD_SDA_1V8", + "AP_I2C_DPBRDG_SCL_1V8", + "AP_I2C_DPBRDG_SDA_1V8", + "AP_I2C_WLAN_SCL_1V8", + "AP_I2C_WLAN_SDA_1V8", + "AP_I2C_AUD_SCL_1V8", + "AP_I2C_AUD_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_UCAM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_WCAM_SCL_1V8", + "AP_I2C_WCAM_SDA_1V8", + "SCP_I2C_SENSOR_SCL_1V8", + "SCP_I2C_SENSOR_SDA_1V8", + "AP_EC_WARM_RST_REQ", + "AP_XHCI_INIT_DONE", + "USB3_HUB_RST_L", + "EN_SPKR", + "BEEP_ON", + "AP_EDP_BKLTEN", + "EN_PP3300_DISP_X", + "EN_PP3300_SDBRDG_X", + "BT_KILL_1V8_L", + "WIFI_KILL_1V8_L", + "PWRAP_SPI0_CSN", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_MI", + "SRCLKENA0", + "SRCLKENA1", + "SCP_VREQ_VAO", + "AP_RTC_CLK32K", + "AP_PMIC_WDTRST_L", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_CLK_MISO", + "AUD_SYNC_MISO", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "NC", + "NC", + "DPBRDG_PWREN", + "DPBRDG_RST_L", + "LTE_W_DISABLE_L", + "LTE_SAR_DETECT_L", + "EN_PP3300_LTE_X", + "LTE_PWR_OFF_L", + "LTE_RESET_L", + "TP", + "TP"; + + aud_clk_mosi_off: aud-clk-mosi-off-pins { + pins-clk-sync { + pinmux = <PINMUX_GPIO166__FUNC_GPIO166>, + <PINMUX_GPIO167__FUNC_GPIO167>; + input-enable; + bias-pull-down; + }; + }; + + aud_clk_mosi_on: aud-clk-mosi-on-pins { + pins-clk-sync { + pinmux = <PINMUX_GPIO166__FUNC_AUD_CLK_MOSI>, + <PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI>; + }; + }; + + aud_clk_miso_off: aud-clk-miso-off-pins { + pins-clk-sync { + pinmux = <PINMUX_GPIO170__FUNC_GPIO170>, + <PINMUX_GPIO171__FUNC_GPIO171>; + input-enable; + bias-pull-down; + }; + }; + + aud_clk_miso_on: aud-clk-miso-on-pins { + pins-clk-sync { + pinmux = <PINMUX_GPIO170__FUNC_AUD_CLK_MISO>, + <PINMUX_GPIO171__FUNC_AUD_SYNC_MISO>; + }; + }; + + aud_dat_mosi_off: aud-dat-mosi-off-pins { + pins-dat { + pinmux = <PINMUX_GPIO168__FUNC_GPIO168>, + <PINMUX_GPIO169__FUNC_GPIO169>; + input-enable; + bias-pull-down; + }; + }; + + aud_dat_mosi_on: aud-dat-mosi-on-pins { + pins-dat { + pinmux = <PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0>, + <PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1>; + }; + }; + + aud_dat_miso_off: aud-dat-miso-off-pins { + pins-dat { + pinmux = <PINMUX_GPIO172__FUNC_GPIO172>, + <PINMUX_GPIO173__FUNC_GPIO173>; + input-enable; + bias-pull-down; + }; + }; + + aud_dat_miso_on: aud-dat-miso-on-pins { + pins-dat { + pinmux = <PINMUX_GPIO172__FUNC_AUD_DAT_MISO0>, + <PINMUX_GPIO173__FUNC_AUD_DAT_MISO1>; + input-schmitt-enable; + bias-disable; + }; + }; + + aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins { + pins-sdata { + pinmux = <PINMUX_GPIO3__FUNC_GPIO3>; + }; + }; + + aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins { + pins-sdata { + pinmux = <PINMUX_GPIO3__FUNC_I2S0_DI>; + }; + }; + + aud_gpio_i2s1_off: aud-gpio-i2s-off-pins { + pins-clk-sdata { + pinmux = <PINMUX_GPIO56__FUNC_GPIO56>, + <PINMUX_GPIO57__FUNC_GPIO57>, + <PINMUX_GPIO58__FUNC_GPIO58>, + <PINMUX_GPIO59__FUNC_GPIO59>; + output-low; + }; + }; + + aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins { + pins-clk-sdata { + pinmux = <PINMUX_GPIO56__FUNC_I2S1_DO>, + <PINMUX_GPIO57__FUNC_I2S1_BCK>, + <PINMUX_GPIO58__FUNC_I2S1_LRCK>, + <PINMUX_GPIO59__FUNC_I2S1_MCK>; + }; + }; + + aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO26__FUNC_GPIO26>, + <PINMUX_GPIO27__FUNC_GPIO27>; + output-low; + }; + }; + + aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins { + pins-clk { + pinmux = <PINMUX_GPIO26__FUNC_I2S2_BCK>, + <PINMUX_GPIO27__FUNC_I2S2_LRCK>; + drive-strength = <4>; + }; + }; + + aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins { + pins-sdata { + pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; + output-low; + }; + }; + + aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins { + pins-sdata { + pinmux = <PINMUX_GPIO4__FUNC_I2S3_DO>; + drive-strength = <4>; + }; + }; + + aud_gpio_pcm_off: aud-gpio-pcm-off-pins { + pins-clk-sdata { + pinmux = <PINMUX_GPIO115__FUNC_GPIO115>, + <PINMUX_GPIO116__FUNC_GPIO116>, + <PINMUX_GPIO117__FUNC_GPIO117>, + <PINMUX_GPIO118__FUNC_GPIO118>; + output-low; + }; + }; + + aud_gpio_pcm_on: aud-gpio-pcm-on-pins { + pins-clk-sdata { + pinmux = <PINMUX_GPIO115__FUNC_PCM_CLK>, + <PINMUX_GPIO116__FUNC_PCM_SYNC>, + <PINMUX_GPIO117__FUNC_PCM_DI>, + <PINMUX_GPIO118__FUNC_PCM_DO>; + }; + }; + + aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins { + pins { + pinmux = <PINMUX_GPIO23__FUNC_GPIO23>; + output-low; + }; + }; + + bt_pins_reset: bt-reset-pins { + pins-bt-reset { + pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; + output-high; + }; + }; + + dpi_pins_sleep: dpi-sleep-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO103__FUNC_GPIO103>, + <PINMUX_GPIO104__FUNC_GPIO104>, + <PINMUX_GPIO105__FUNC_GPIO105>, + <PINMUX_GPIO106__FUNC_GPIO106>, + <PINMUX_GPIO107__FUNC_GPIO107>, + <PINMUX_GPIO108__FUNC_GPIO108>, + <PINMUX_GPIO109__FUNC_GPIO109>, + <PINMUX_GPIO110__FUNC_GPIO110>, + <PINMUX_GPIO111__FUNC_GPIO111>, + <PINMUX_GPIO112__FUNC_GPIO112>, + <PINMUX_GPIO113__FUNC_GPIO113>, + <PINMUX_GPIO114__FUNC_GPIO114>, + <PINMUX_GPIO101__FUNC_GPIO101>, + <PINMUX_GPIO100__FUNC_GPIO100>, + <PINMUX_GPIO102__FUNC_GPIO102>, + <PINMUX_GPIO99__FUNC_GPIO99>; + drive-strength = <10>; + output-low; + }; + }; + + dpi_pins_default: dpi-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>, + <PINMUX_GPIO104__FUNC_DPI_DATA1>, + <PINMUX_GPIO105__FUNC_DPI_DATA2>, + <PINMUX_GPIO106__FUNC_DPI_DATA3>, + <PINMUX_GPIO107__FUNC_DPI_DATA4>, + <PINMUX_GPIO108__FUNC_DPI_DATA5>, + <PINMUX_GPIO109__FUNC_DPI_DATA6>, + <PINMUX_GPIO110__FUNC_DPI_DATA7>, + <PINMUX_GPIO111__FUNC_DPI_DATA8>, + <PINMUX_GPIO112__FUNC_DPI_DATA9>, + <PINMUX_GPIO113__FUNC_DPI_DATA10>, + <PINMUX_GPIO114__FUNC_DPI_DATA11>, + <PINMUX_GPIO101__FUNC_DPI_HSYNC>, + <PINMUX_GPIO100__FUNC_DPI_VSYNC>, + <PINMUX_GPIO102__FUNC_DPI_DE>, + <PINMUX_GPIO99__FUNC_DPI_PCLK>; + drive-strength = <10>; + }; + }; + + ec_ap_int: cros-ec-int-pins { + pins-ec-ap-int-odl { + pinmux = <PINMUX_GPIO13__FUNC_GPIO13>; + input-enable; + }; + }; + + edp_panel_fixed_pins: edp-panel-fixed-pins { + pins-vreg-en { + pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; + output-high; + }; + }; + + en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins { + pins-vreg-en { + pinmux = <PINMUX_GPIO39__FUNC_GPIO39>; + output-low; + }; + }; + + gsc_int: gsc-int-pins { + pins-gsc-ap-int-odl { + pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>, + <PINMUX_GPIO127__FUNC_SCL0>; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux = <PINMUX_GPIO130__FUNC_SDA1>, + <PINMUX_GPIO129__FUNC_SCL1>; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux = <PINMUX_GPIO132__FUNC_SDA2>, + <PINMUX_GPIO131__FUNC_SCL2>; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux = <PINMUX_GPIO134__FUNC_SDA3>, + <PINMUX_GPIO133__FUNC_SCL3>; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + i2c5_pins: i2c5-pins { + pins-bus { + pinmux = <PINMUX_GPIO138__FUNC_SDA5>, + <PINMUX_GPIO137__FUNC_SCL5>; + bias-disable; + drive-strength = <4>; + input-enable; + }; + }; + + it6505_pins: it6505-pins { + pins-hpd { + pinmux = <PINMUX_GPIO10__FUNC_GPIO10>; + input-enable; + bias-pull-up; + }; + + pins-int { + pinmux = <PINMUX_GPIO8__FUNC_GPIO8>; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux = <PINMUX_GPIO177__FUNC_GPIO177>; + output-low; + bias-pull-up; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO69__FUNC_MSDC0_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO69__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO67__FUNC_MSDC0_DSL>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_pins_default: mmc1-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO85__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_pins_uhs: mmc1-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO85__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_pins_eint: mmc1-eint-pins { + pins-dat1 { + pinmux = <PINMUX_GPIO87__FUNC_GPIO87>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + nor_pins_default: nor-default-pins { + pins-clk-dat { + pinmux = <PINMUX_GPIO63__FUNC_SPINOR_IO0>, + <PINMUX_GPIO61__FUNC_SPINOR_CK>, + <PINMUX_GPIO64__FUNC_SPINOR_IO1>; + drive-strength = <6>; + bias-pull-down; + }; + + pins-cs-dat { + pinmux = <PINMUX_GPIO62__FUNC_SPINOR_CS>, + <PINMUX_GPIO65__FUNC_SPINOR_IO2>, + <PINMUX_GPIO66__FUNC_SPINOR_IO3>; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pen_eject: pen-eject-pins { + pins { + pinmux = <PINMUX_GPIO18__FUNC_GPIO18>; + input-enable; + /* External pull-up. */ + bias-disable; + }; + }; + + pwm0_pin: disp-pwm-pins { + pins { + pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM>; + output-high; + }; + }; + + rt1019p_pins_default: rt1019p-default-pins { + pins-sdb { + pinmux = <PINMUX_GPIO150__FUNC_GPIO150>; + output-low; + }; + }; + + scp_pins: scp-default-pins { + pins-scp-uart { + pinmux = <PINMUX_GPIO48__FUNC_TP_URXD2_AO>, + <PINMUX_GPIO49__FUNC_TP_UTXD2_AO>; + }; + }; + + spi1_pins: spi1-pins { + pins-bus { + pinmux = <PINMUX_GPIO40__FUNC_SPI1_CLK_A>, + <PINMUX_GPIO41__FUNC_SPI1_CSB_A>, + <PINMUX_GPIO42__FUNC_SPI1_MO_A>, + <PINMUX_GPIO43__FUNC_SPI1_MI_A>; + bias-disable; + input-enable; + }; + }; + + spi2_pins: spi2-pins { + pins-bus { + pinmux = <PINMUX_GPIO44__FUNC_SPI2_CLK_A>, + <PINMUX_GPIO45__FUNC_GPIO45>, + <PINMUX_GPIO46__FUNC_SPI2_MO_A>, + <PINMUX_GPIO47__FUNC_SPI2_MI_A>; + bias-disable; + input-enable; + }; + }; + + spmi_pins: spmi-pins { + pins-bus { + pinmux = <PINMUX_GPIO183__FUNC_SPMI_SCL>, + <PINMUX_GPIO184__FUNC_SPMI_SDA>; + }; + }; + + touchscreen_pins: touchscreen-pins { + pins-irq { + pinmux = <PINMUX_GPIO12__FUNC_GPIO12>; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux = <PINMUX_GPIO60__FUNC_GPIO60>; + output-high; + }; + + pins-report-sw { + pinmux = <PINMUX_GPIO37__FUNC_GPIO37>; + output-low; + }; + }; + + trackpad_pin: trackpad-default-pins { + pins-int-n { + pinmux = <PINMUX_GPIO11__FUNC_GPIO11>; + input-enable; + bias-disable; /* pulled externally */ + }; + }; + + wifi_enable_pin: wifi-enable-pins { + pins-wifi-enable { + pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; + }; + }; + + wifi_wakeup_pin: wifi-wakeup-pins { + pins-wifi-wakeup { + pinmux = <PINMUX_GPIO7__FUNC_GPIO7>; + input-enable; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +&pwrap { + pmic { + compatible = "mediatek,mt6366", "mediatek,mt6358"; + interrupt-controller; + interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + + mt6366codec: codec { + compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound"; + Avdd-supply = <&mt6366_vaud28_reg>; + mediatek,dmic-mode = <1>; /* one-wire */ + }; + + mt6366_regulators: regulators { + compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator"; + vsys-ldo1-supply = <&pp4200_z2>; + vsys-ldo2-supply = <&pp4200_z2>; + vsys-ldo3-supply = <&pp4200_z2>; + vsys-vcore-supply = <&pp4200_z2>; + vsys-vdram1-supply = <&pp4200_z2>; + vsys-vgpu-supply = <&pp4200_z2>; + vsys-vmodem-supply = <&pp4200_z2>; + vsys-vpa-supply = <&pp4200_z2>; + vsys-vproc11-supply = <&pp4200_z2>; + vsys-vproc12-supply = <&pp4200_z2>; + vsys-vs1-supply = <&pp4200_z2>; + vsys-vs2-supply = <&pp4200_z2>; + vs1-ldo1-supply = <&mt6366_vs1_reg>; + vs2-ldo1-supply = <&mt6366_vdram1_reg>; + vs2-ldo2-supply = <&mt6366_vs2_reg>; + vs2-ldo3-supply = <&mt6366_vs2_reg>; + + vcore { + regulator-name = "pp0750_dvdd_core"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO + MT6397_BUCK_MODE_FORCE_PWM>; + regulator-always-on; + }; + + mt6366_vdram1_reg: vdram1 { + regulator-name = "pp1125_emi_vdd2"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO + MT6397_BUCK_MODE_FORCE_PWM>; + regulator-always-on; + }; + + mt6366_vgpu_reg: vgpu { + /* + * Called "ppvar_dvdd_gpu" in the schematic. + * Called "ppvar_dvdd_vgpu" here to match + * regulator coupling requirements. + */ + regulator-name = "ppvar_dvdd_vgpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO + MT6397_BUCK_MODE_FORCE_PWM>; + regulator-coupled-with = <&mt6366_vsram_gpu_reg>; + regulator-coupled-max-spread = <10000>; + }; + + mt6366_vproc11_reg: vproc11 { + regulator-name = "ppvar_dvdd_proc_bc_mt6366"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO + MT6397_BUCK_MODE_FORCE_PWM>; + regulator-always-on; + }; + + mt6366_vproc12_reg: vproc12 { + regulator-name = "ppvar_dvdd_proc_lc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO + MT6397_BUCK_MODE_FORCE_PWM>; + regulator-always-on; + }; + + mt6366_vs1_reg: vs1 { + regulator-name = "pp2000_vs1"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + mt6366_vs2_reg: vs2 { + regulator-name = "pp1350_vs2"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + va12 { + regulator-name = "pp1200_va12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + mt6366_vaud28_reg: vaud28 { + regulator-name = "pp2800_vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vaux18_reg: vaux18 { + regulator-name = "pp1840_vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1840000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vbif28_reg: vbif28 { + regulator-name = "pp2800_vbif28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vcn18_reg: vcn18 { + regulator-name = "pp1800_vcn18_x"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vcn28_reg: vcn28 { + regulator-name = "pp2800_vcn28_x"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vefuse_reg: vefuse { + regulator-name = "pp1800_vefuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vfe28_reg: vfe28 { + regulator-name = "pp2800_vfe28_x"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vemc_reg: vemc { + regulator-name = "pp3000_vemc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vibr_reg: vibr { + regulator-name = "pp2800_vibr_x"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vio18_reg: vio18 { + regulator-name = "pp1800_vio18_s3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <2700>; + regulator-always-on; + }; + + mt6366_vio28_reg: vio28 { + regulator-name = "pp2800_vio28_x"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6366_vm18_reg: vm18 { + regulator-name = "pp1800_emi_vdd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1840000>; + regulator-enable-ramp-delay = <325>; + regulator-always-on; + }; + + mt6366_vmc_reg: vmc { + regulator-name = "pp3000_vmc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vmddr_reg: vmddr { + regulator-name = "pm0750_emi_vmddr"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <750000>; + regulator-enable-ramp-delay = <325>; + regulator-always-on; + }; + + mt6366_vmch_reg: vmch { + regulator-name = "pp3000_vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6366_vcn33_reg: vcn33 { + regulator-name = "pp3300_vcn33_x"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <270>; + }; + + vdram2 { + regulator-name = "pp0600_emi_vddq"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-enable-ramp-delay = <3300>; + regulator-always-on; + }; + + mt6366_vrf12_reg: vrf12 { + regulator-name = "pp1200_vrf12_x"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <120>; + }; + + mt6366_vrf18_reg: vrf18 { + regulator-name = "pp1800_vrf18_x"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <120>; + }; + + vsim1 { + regulator-name = "pp1860_vsim1_x"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1860000>; + regulator-enable-ramp-delay = <540>; + }; + + mt6366_vsim2_reg: vsim2 { + regulator-name = "pp2760_vsim2_x"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2760000>; + regulator-enable-ramp-delay = <540>; + }; + + mt6366_vsram_gpu_reg: vsram-gpu { + regulator-name = "pp0900_dvdd_sram_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-coupled-with = <&mt6366_vgpu_reg>; + regulator-coupled-max-spread = <10000>; + }; + + mt6366_vsram_others_reg: vsram-others { + regulator-name = "pp0900_dvdd_sram_core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6366_vsram_proc11_reg: vsram-proc11 { + regulator-name = "pp0900_dvdd_sram_bc"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1120000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6366_vsram_proc12_reg: vsram-proc12 { + regulator-name = "pp0900_dvdd_sram_lc"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1120000>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + vusb { + regulator-name = "pp3070_vusb"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3070000>; + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + vxo22 { + regulator-name = "pp2240_vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2240000>; + regulator-enable-ramp-delay = <120>; + /* Feeds DCXO internally */ + regulator-always-on; + }; + }; + + rtc { + compatible = "mediatek,mt6366-rtc", "mediatek,mt6358-rtc"; + }; + }; +}; + +&scp { + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + firmware-name = "mediatek/mt8186/scp.img"; + memory-region = <&scp_mem>; + status = "okay"; + + cros-ec-rpmsg { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + mediatek,pad-select = <0>; + status = "okay"; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_ap_int>; + spi-max-frequency = <1000000>; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + cs-gpios = <&pio 45 GPIO_ACTIVE_LOW>; + mediatek,pad-select = <0>; + status = "okay"; + + tpm@0 { + compatible = "google,cr50"; + reg = <0>; + interrupts-extended = <&pio 15 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gsc_int>; + spi-max-frequency = <1000000>; + }; +}; + +&ssusb0 { + status = "okay"; +}; + +&ssusb1 { + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_host0 { + vbus-supply = <&pp3300_s3>; + status = "okay"; +}; + +&usb_host1 { + vbus-supply = <&usb_p1_vbus>; + status = "okay"; +}; + +&watchdog { + mediatek,reset-by-toprgu; +}; + +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi> diff --git a/dts/src/arm64/mediatek/mt8186.dtsi b/dts/src/arm64/mediatek/mt8186.dtsi index 2fec6fd1c1..4763ed5dc8 100644 --- a/dts/src/arm64/mediatek/mt8186.dtsi +++ b/dts/src/arm64/mediatek/mt8186.dtsi @@ -931,11 +931,17 @@ power-domain@MT8186_POWER_DOMAIN_SSUSB { reg = <MT8186_POWER_DOMAIN_SSUSB>; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>; + clock-names = "sys_ck", "ref_ck"; #power-domain-cells = <0>; }; power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>; + clock-names = "sys_ck", "ref_ck"; #power-domain-cells = <0>; }; @@ -1061,7 +1067,7 @@ reg = <MT8186_POWER_DOMAIN_VENC>; clocks = <&topckgen CLK_TOP_VENC>, <&vencsys CLK_VENC_CKE1_VENC>; - clock-names = "venc0", "larb"; + clock-names = "venc0", "subsys-larb"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; @@ -1530,8 +1536,9 @@ clocks = <&topckgen CLK_TOP_USB_TOP>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, - <&infracfg_ao CLK_INFRA_AO_ICUSB>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; phys = <&u2port0 PHY_TYPE_USB2>; power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; @@ -1595,8 +1602,9 @@ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, - <&clk26m>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; @@ -1672,6 +1680,10 @@ reg = <0x59c 0x4>; bits = <0 3>; }; + + socinfo-data1@7a0 { + reg = <0x7a0 0x4>; + }; }; mipi_tx0: dsi-phy@11cc0000 { @@ -1959,6 +1971,43 @@ power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; }; + video_decoder: video-decoder@16000000 { + compatible = "mediatek,mt8186-vcodec-dec"; + reg = <0 0x16000000 0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>; + mediatek,scp = <&scp>; + + vcodec_core: video-codec@16025000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x16025000 0 0x1000>; + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>, + <&topckgen CLK_TOP_UNIVPLL_D3>; + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; + power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; + }; + }; + larb4: smi@1602e000 { compatible = "mediatek,mt8186-smi-larb"; reg = <0 0x1602e000 0 0x1000>; @@ -1993,6 +2042,40 @@ power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; }; + venc: video-encoder@17020000 { + compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc"; + reg = <0 0x17020000 0 0x2000>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>, + <&iommu_mm IOMMU_PORT_L7_VENC_REC>, + <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>, + <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>, + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>, + <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>; + clocks = <&vencsys CLK_VENC_CKE1_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; + mediatek,scp = <&scp>; + }; + + jpgenc: jpeg-encoder@17030000 { + compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc"; + reg = <0 0x17030000 0 0x10000>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_CKE2_JPGENC>; + clock-names = "jpgenc"; + iommus = <&iommu_mm IOMMU_PORT_L7_JPGENC_Y_RDMA>, + <&iommu_mm IOMMU_PORT_L7_JPGENC_C_RDMA>, + <&iommu_mm IOMMU_PORT_L7_JPGENC_Q_TABLE>, + <&iommu_mm IOMMU_PORT_L7_JPGENC_BSDMA>; + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8186-camsys"; reg = <0 0x1a000000 0 0x1000>; diff --git a/dts/src/arm64/mediatek/mt8192-asurada.dtsi b/dts/src/arm64/mediatek/mt8192-asurada.dtsi index d87aab8d7a..9b738f6a5d 100644 --- a/dts/src/arm64/mediatek/mt8192-asurada.dtsi +++ b/dts/src/arm64/mediatek/mt8192-asurada.dtsi @@ -1332,14 +1332,11 @@ spi-max-frequency = <3000000>; pinctrl-names = "default"; pinctrl-0 = <&cros_ec_int>; + wakeup-source; #address-cells = <1>; #size-cells = <0>; - base_detection: cbas { - compatible = "google,cros-cbas"; - }; - cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; diff --git a/dts/src/arm64/mediatek/mt8192.dtsi b/dts/src/arm64/mediatek/mt8192.dtsi index 6dd32dbfb8..05e401670b 100644 --- a/dts/src/arm64/mediatek/mt8192.dtsi +++ b/dts/src/arm64/mediatek/mt8192.dtsi @@ -1164,6 +1164,14 @@ #address-cells = <1>; #size-cells = <1>; + socinfo-data1@44 { + reg = <0x044 0x4>; + }; + + socinfo-data2@50 { + reg = <0x050 0x4>; + }; + lvts_e_data1: data1@1c0 { reg = <0x1c0 0x58>; }; @@ -1814,7 +1822,7 @@ mediatek,scp = <&scp>; power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; clocks = <&vencsys CLK_VENC_SET1_VENC>; - clock-names = "venc-set1"; + clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; }; diff --git a/dts/src/arm64/mediatek/mt8195-cherry-tomato-r1.dts b/dts/src/arm64/mediatek/mt8195-cherry-tomato-r1.dts index 2d5e8f371b..a82d716f10 100644 --- a/dts/src/arm64/mediatek/mt8195-cherry-tomato-r1.dts +++ b/dts/src/arm64/mediatek/mt8195-cherry-tomato-r1.dts @@ -23,3 +23,7 @@ &ts_10 { status = "okay"; }; + +&watchdog { + /delete-property/ mediatek,disable-extrst; +}; diff --git a/dts/src/arm64/mediatek/mt8195-cherry-tomato-r2.dts b/dts/src/arm64/mediatek/mt8195-cherry-tomato-r2.dts index 2586c32ce6..2fe20e0dad 100644 --- a/dts/src/arm64/mediatek/mt8195-cherry-tomato-r2.dts +++ b/dts/src/arm64/mediatek/mt8195-cherry-tomato-r2.dts @@ -43,3 +43,7 @@ &ts_10 { status = "okay"; }; + +&watchdog { + /delete-property/ mediatek,disable-extrst; +}; diff --git a/dts/src/arm64/mediatek/mt8195-cherry-tomato-r3.dts b/dts/src/arm64/mediatek/mt8195-cherry-tomato-r3.dts index f54f9477b9..dd294ca981 100644 --- a/dts/src/arm64/mediatek/mt8195-cherry-tomato-r3.dts +++ b/dts/src/arm64/mediatek/mt8195-cherry-tomato-r3.dts @@ -44,3 +44,7 @@ &ts_10 { status = "okay"; }; + +&watchdog { + /delete-property/ mediatek,disable-extrst; +}; diff --git a/dts/src/arm64/mediatek/mt8195-cherry.dtsi b/dts/src/arm64/mediatek/mt8195-cherry.dtsi index 3c6079edda..f94c07f8b9 100644 --- a/dts/src/arm64/mediatek/mt8195-cherry.dtsi +++ b/dts/src/arm64/mediatek/mt8195-cherry.dtsi @@ -1149,6 +1149,7 @@ pinctrl-names = "default"; pinctrl-0 = <&cros_ec_int>; spi-max-frequency = <3000000>; + wakeup-source; keyboard-backlight { compatible = "google,cros-kbd-led-backlight"; @@ -1291,11 +1292,32 @@ status = "okay"; }; +/* + * For the USB Type-C ports the role and alternate modes switching is + * done by the EC so we set dr_mode to host to avoid interfering. + */ +&ssusb0 { + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb3 { + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + &xhci0 { status = "okay"; rx-fifo-depth = <3072>; - vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; }; @@ -1309,8 +1331,6 @@ &xhci2 { status = "okay"; - - vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; }; @@ -1319,7 +1339,6 @@ /* MT7921's USB Bluetooth has issues with USB2 LPM */ usb2-lpm-disable; - vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; }; diff --git a/dts/src/arm64/mediatek/mt8195-demo.dts b/dts/src/arm64/mediatek/mt8195-demo.dts index 4127cb84eb..b82f7176b4 100644 --- a/dts/src/arm64/mediatek/mt8195-demo.dts +++ b/dts/src/arm64/mediatek/mt8195-demo.dts @@ -529,8 +529,22 @@ status = "okay"; }; -&xhci0 { +&ssusb0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci0 { vbus-supply = <&otg_vbus_regulator>; status = "okay"; }; @@ -541,11 +555,9 @@ }; &xhci2 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; &xhci3 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; diff --git a/dts/src/arm64/mediatek/mt8195-evb.dts b/dts/src/arm64/mediatek/mt8195-evb.dts index 690dc7717f..341b6e0741 100644 --- a/dts/src/arm64/mediatek/mt8195-evb.dts +++ b/dts/src/arm64/mediatek/mt8195-evb.dts @@ -160,6 +160,18 @@ status = "okay"; }; +&ssusb0 { + status = "okay"; +}; + +&ssusb2 { + status = "okay"; +}; + +&ssusb3 { + status = "okay"; +}; + &xhci0 { status = "okay"; }; diff --git a/dts/src/arm64/mediatek/mt8195.dtsi b/dts/src/arm64/mediatek/mt8195.dtsi index b9101662ce..ea6dc220e1 100644 --- a/dts/src/arm64/mediatek/mt8195.dtsi +++ b/dts/src/arm64/mediatek/mt8195.dtsi @@ -1347,29 +1347,40 @@ }; }; - xhci0: usb@11200000 { - compatible = "mediatek,mt8195-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x1000>, - <0 0x11203e00 0 0x0100>; + ssusb0: usb@11201000 { + compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, - <&topckgen CLK_TOP_SSUSB_XHCI>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x11200000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, <&topckgen CLK_TOP_SSUSB_REF>, - <&apmixedsys CLK_APMIXED_USB1PLL>, - <&clk26m>, <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", - "xhci_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 103>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x400 103>; status = "disabled"; + + xhci0: usb@0 { + compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, + <&topckgen CLK_TOP_SSUSB_XHCI>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&topckgen CLK_TOP_SSUSB_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + status = "disabled"; + }; }; mmc0: mmc@11230000 { @@ -1450,52 +1461,68 @@ status = "disabled"; }; - xhci2: usb@112a0000 { - compatible = "mediatek,mt8195-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x112a0000 0 0x1000>, - <0 0x112a3e00 0 0x0100>; + ssusb2: usb@112a1000 { + compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; + reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; - phys = <&u2port2 PHY_TYPE_USB2>; - assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, - <&topckgen CLK_TOP_SSUSB_XHCI_2P>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x112a0000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, <&topckgen CLK_TOP_SSUSB_P2_REF>, - <&clk26m>, - <&clk26m>, <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", - "xhci_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 105>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port2 PHY_TYPE_USB2>; wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x400 105>; status = "disabled"; + + xhci2: usb@0 { + compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; }; - xhci3: usb@112b0000 { - compatible = "mediatek,mt8195-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x112b0000 0 0x1000>, - <0 0x112b3e00 0 0x0100>; + ssusb3: usb@112b1000 { + compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; + reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; - phys = <&u2port3 PHY_TYPE_USB2>; - assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, - <&topckgen CLK_TOP_SSUSB_XHCI_3P>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x112b0000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, <&topckgen CLK_TOP_SSUSB_P3_REF>, - <&clk26m>, - <&clk26m>, <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", - "xhci_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 106>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port3 PHY_TYPE_USB2>; wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x400 106>; status = "disabled"; + + xhci3: usb@0 { + compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; }; pcie0: pcie@112f0000 { @@ -1701,6 +1728,9 @@ svs_calib_data: svs-calib@580 { reg = <0x580 0x64>; }; + socinfo-data1@7a0 { + reg = <0x7a0 0x4>; + }; }; u3phy2: t-phy@11c40000 { diff --git a/dts/src/arm64/mediatek/mt8395-genio-1200-evk.dts b/dts/src/arm64/mediatek/mt8395-genio-1200-evk.dts index 7fc515a07c..1558649f63 100644 --- a/dts/src/arm64/mediatek/mt8395-genio-1200-evk.dts +++ b/dts/src/arm64/mediatek/mt8395-genio-1200-evk.dts @@ -880,6 +880,21 @@ status = "disabled"; }; +&ssusb0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + &xhci0 { status = "okay"; }; @@ -890,11 +905,9 @@ }; &xhci2 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; &xhci3 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; diff --git a/dts/src/arm64/mediatek/mt8395-radxa-nio-12l.dts b/dts/src/arm64/mediatek/mt8395-radxa-nio-12l.dts new file mode 100644 index 0000000000..e5d9b671a4 --- /dev/null +++ b/dts/src/arm64/mediatek/mt8395-radxa-nio-12l.dts @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Radxa Limited + * Copyright (C) 2024 Collabora Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#include "mt8195.dtsi" +#include "mt6359.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/mt8195-pinfunc.h> +#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/usb/pd.h> + +/ { + model = "Radxa NIO 12L"; + chassis-type = "embedded"; + compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + i2c2 = &i2c4; + i2c3 = &i2c0; + i2c4 = &i2c1; + ethernet0 = ð + serial0 = &uart0; + serial1 = &uart1; + spi0 = &spi1; + spi1 = &spi2; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x1 0x0>; + }; + + wifi_vreg: regulator-wifi-3v3-en { + compatible = "regulator-fixed"; + regulator-name = "wifi_3v3_en"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 67 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_vreg_pins>; + vin-supply = <&vsys>; + }; + + /* system wide switching 5.0V power rail */ + vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_vsys>; + }; + + vsys_buck: regulator-vsys-buck { + compatible = "regulator-fixed"; + regulator-name = "vsys_buck"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_vsys>; + }; + + /* Rail from power-only "TYPE C DC" port */ + vcc5v0_vsys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + reg = <0 0x43200000 0 0xc00000>; + no-map; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible = "shared-dma-pool"; + reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + reg = <0 0x54600000 0x0 0x200000>; + no-map; + }; + + afe_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0x1100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible = "shared-dma-pool"; + reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ + }; + }; +}; + +ð { + phy-mode = "rgmii-rxid"; + phy-handle = <&rgmii_phy>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + mediatek,tx-delay-ps = <2030>; + mediatek,mac-wol; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 20000 100000>; + status = "okay"; + + mdio { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; + }; +}; + +&gpu { + mali-supply = <&mt6315_7_vbuck1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + status = "okay"; + + typec-mux@48 { + compatible = "ite,it5205"; + reg = <0x48>; + + mode-switch; + orientation-switch; + + vcc-supply = <&mt6359_vibr_ldo_reg>; + + port { + it5205_sbu_mux: endpoint { + remote-endpoint = <&typec_con_mux>; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* I2C4 exposed at 39-pins MIPI-LCD connector */ +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + interrupt-controller; + #interrupt-cells = <1>; + pinctrl-0 = <&mt6360_pins>; + + charger { + compatible = "mediatek,mt6360-chg"; + richtek,vinovp-microvolt = <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; + }; + }; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN1-supply = <&vsys_buck>; + LDO_VIN3-supply = <&mt6360_buck2>; + + mt6360_buck1: buck1 { + regulator-name = "emi_vdd2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP + MT6360_OPMODE_ULP>; + regulator-always-on; + }; + + mt6360_buck2: buck2 { + regulator-name = "emi_vddq"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP + MT6360_OPMODE_ULP>; + regulator-always-on; + }; + + mt6360_ldo1: ldo1 { + regulator-name = "ext_lcd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + regulator-always-on; + }; + + mt6360_ldo2: ldo2 { + regulator-name = "panel1_p1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo3: ldo3 { + regulator-name = "vmc_pmu"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo5: ldo5 { + regulator-name = "vmch_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + regulator-always-on; + }; + + mt6360_ldo6: ldo6 { + regulator-name = "mt6360_ldo6"; /* Test point */ + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo7: ldo7 { + regulator-name = "emi_vmddr_en"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + regulator-always-on; + }; + }; + + typec { + compatible = "mediatek,mt6360-tcpc"; + interrupts-extended = <&pio 100 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "PD_IRQB"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <10000000>; + power-role = "dual"; + try-power-role = "sink"; + + source-pdos = <PDO_FIXED(5000, 1000, + PDO_FIXED_DUAL_ROLE | + PDO_FIXED_DATA_SWAP)>; + sink-pdos = <PDO_FIXED(5000, 3000, + PDO_FIXED_DUAL_ROLE | + PDO_FIXED_DATA_SWAP)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_con_hs: endpoint { + remote-endpoint = <&mtu3_hs0_role_sw>; + }; + }; + + port@2 { + reg = <2>; + typec_con_mux: endpoint { + remote-endpoint = <&it5205_sbu_mux>; + }; + }; + }; + }; + }; + }; +}; + +/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */ +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + hs400-ds-delay = <0x14c11>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +/* MMC1 Controller: MicroSD card slot */ +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>, <&mmc1_pins_detect>; + pinctrl-1 = <&mmc1_default_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; +}; + +&mt6359_vaud18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +/* For USB Hub */ +&mt6359_vcamio_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +/* for GPU SRAM */ +&mt6359_vsram_others_ldo_reg { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; +}; + +&pio { + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, + <PINMUX_GPIO86__FUNC_GBE_RXC>, + <PINMUX_GPIO87__FUNC_GBE_RXDV>, + <PINMUX_GPIO88__FUNC_GBE_TXEN>; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, + <PINMUX_GPIO90__FUNC_GBE_MDIO>; + input-enable; + }; + + pins-power { + pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, + <PINMUX_GPIO92__FUNC_GPIO92>; + output-high; + }; + + pins-rst { + pinmux = <PINMUX_GPIO93__FUNC_GPIO93>; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, + <PINMUX_GPIO82__FUNC_GBE_RXD2>, + <PINMUX_GPIO83__FUNC_GBE_RXD1>, + <PINMUX_GPIO84__FUNC_GBE_RXD0>; + }; + + pins-txd { + pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, + <PINMUX_GPIO78__FUNC_GBE_TXD2>, + <PINMUX_GPIO79__FUNC_GBE_TXD1>, + <PINMUX_GPIO80__FUNC_GBE_TXD0>; + drive-strength = <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, + <PINMUX_GPIO86__FUNC_GPIO86>, + <PINMUX_GPIO87__FUNC_GPIO87>, + <PINMUX_GPIO88__FUNC_GPIO88>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, + <PINMUX_GPIO90__FUNC_GPIO90>; + bias-disable; + input-disable; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, + <PINMUX_GPIO82__FUNC_GPIO82>, + <PINMUX_GPIO83__FUNC_GPIO83>, + <PINMUX_GPIO84__FUNC_GPIO84>; + }; + + pins-txd { + pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, + <PINMUX_GPIO78__FUNC_GPIO78>, + <PINMUX_GPIO79__FUNC_GPIO79>, + <PINMUX_GPIO80__FUNC_GPIO80>; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux = <PINMUX_GPIO12__FUNC_SDA2>, + <PINMUX_GPIO13__FUNC_SCL2>; + bias-pull-up = <MTK_PULL_SET_RSEL_111>; + drive-strength = <6>; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux = <PINMUX_GPIO16__FUNC_SDA4>, + <PINMUX_GPIO17__FUNC_SCL4>; + bias-pull-up = <MTK_PULL_SET_RSEL_111>; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = <PINMUX_GPIO25__FUNC_SDA6>, + <PINMUX_GPIO26__FUNC_SCL6>; + bias-pull-up = <MTK_PULL_SET_RSEL_111>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + drive-strength = <6>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + drive-strength = <6>; + input-enable; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + drive-strength = <6>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + drive-strength = <8>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + drive-strength = <8>; + input-enable; + }; + + pins-ds { + pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + drive-strength = <8>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + drive-strength = <8>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + drive-strength = <8>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, + <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + drive-strength = <8>; + input-enable; + }; + }; + + mmc1_pins_detect: mmc1-detect-pins { + pins-insert { + pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; + bias-pull-up; + }; + }; + + mt6360_pins: mt6360-pins { + pins-irq { + pinmux = <PINMUX_GPIO100__FUNC_GPIO100>, + <PINMUX_GPIO101__FUNC_GPIO101>; + input-enable; + bias-pull-up; + }; + }; + + pcie0_default_pins: pcie0-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, + <PINMUX_GPIO20__FUNC_PERSTN>, + <PINMUX_GPIO21__FUNC_CLKREQN>; + bias-pull-up; + }; + }; + + pcie1_default_pins: pcie1-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>, + <PINMUX_GPIO1__FUNC_CLKREQN_1>, + <PINMUX_GPIO2__FUNC_WAKEN_1>; + bias-disable; + }; + }; + + spi1_pins: spi1-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>, + <PINMUX_GPIO137__FUNC_SPIM1_CLK>, + <PINMUX_GPIO138__FUNC_SPIM1_MO>, + <PINMUX_GPIO139__FUNC_SPIM1_MI>; + bias-disable; + }; + }; + + spi2_pins: spi2-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>, + <PINMUX_GPIO141__FUNC_SPIM2_CLK>, + <PINMUX_GPIO142__FUNC_SPIM2_MO>, + <PINMUX_GPIO143__FUNC_SPIM2_MI>; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + pins-bus { + pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, + <PINMUX_GPIO99__FUNC_URXD0>; + }; + }; + + uart1_pins: uart1-pins { + pins-bus { + pinmux = <PINMUX_GPIO102__FUNC_UTXD1>, + <PINMUX_GPIO103__FUNC_URXD1>; + }; + }; + + wifi_vreg_pins: wifi-vreg-pins { + pins-wifi-pmu-en { + pinmux = <PINMUX_GPIO65__FUNC_GPIO65>; + output-high; + }; + + pins-wifi-vreg-en { + pinmux = <PINMUX_GPIO67__FUNC_GPIO67>; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_pins>; + status = "okay"; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&spi1 { + /* Exposed at 40 pin connector */ + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&spi2 { + /* Exposed at 40 pin connector */ + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vgpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + }; + }; + }; +}; + +&uart0 { + /* Exposed at 40 pin connector */ + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + /* Exposed at 40 pin connector */ + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ssusb0 { + role-switch-default-mode = "host"; + usb-role-switch; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; + + port { + mtu3_hs0_role_sw: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&ssusb2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci0 { + vbus-supply = <&otg_vbus_regulator>; + status = "okay"; +}; + +&xhci1 { + /* MT7921's USB Bluetooth has issues with USB2 LPM */ + usb2-lpm-disable; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&vsys>; + status = "okay"; +}; + +&xhci2 { + vbus-supply = <&vsys>; + status = "okay"; +}; diff --git a/dts/src/arm64/nvidia/tegra132-norrin.dts b/dts/src/arm64/nvidia/tegra132-norrin.dts index bbc2e9bef0..14d58859bb 100644 --- a/dts/src/arm64/nvidia/tegra132-norrin.dts +++ b/dts/src/arm64/nvidia/tegra132-norrin.dts @@ -762,6 +762,7 @@ interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/dts/src/arm64/nvidia/tegra194-p2888.dtsi b/dts/src/arm64/nvidia/tegra194-p2888.dtsi index 5b59c1986e..e8b296d9e0 100644 --- a/dts/src/arm64/nvidia/tegra194-p2888.dtsi +++ b/dts/src/arm64/nvidia/tegra194-p2888.dtsi @@ -53,6 +53,56 @@ status = "okay"; }; + i2c@c240000 { + status = "okay"; + + power-sensor@40 { + compatible = "ti,ina3221"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + label = "GPU"; + shunt-resistor-micro-ohms = <5000>; + }; + input@1 { + reg = <0x1>; + label = "CPU"; + shunt-resistor-micro-ohms = <5000>; + }; + input@2 { + reg = <0x2>; + label = "SOC"; + shunt-resistor-micro-ohms = <5000>; + }; + }; + + power-sensor@41 { + compatible = "ti,ina3221"; + reg = <0x41>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + label = "CV"; + shunt-resistor-micro-ohms = <5000>; + }; + input@1 { + reg = <0x1>; + label = "VDDRQ"; + shunt-resistor-micro-ohms = <5000>; + }; + input@2 { + reg = <0x2>; + label = "SYS5V"; + shunt-resistor-micro-ohms = <5000>; + }; + }; + }; + serial@3110000 { status = "okay"; }; diff --git a/dts/src/arm64/nvidia/tegra194-p2972-0000.dts b/dts/src/arm64/nvidia/tegra194-p2972-0000.dts index 64a3398fe7..c32876699a 100644 --- a/dts/src/arm64/nvidia/tegra194-p2972-0000.dts +++ b/dts/src/arm64/nvidia/tegra194-p2972-0000.dts @@ -2062,8 +2062,15 @@ ports { usb2-0 { - mode = "host"; + mode = "otg"; + usb-role-switch; status = "okay"; + + port { + hs_typec_p0: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p0>; + }; + }; }; usb2-1 { @@ -2094,6 +2101,14 @@ }; }; + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-0", "usb3-0"; + }; + usb@3610000 { status = "okay"; @@ -2106,6 +2121,40 @@ phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3"; }; + i2c@c240000 { + typec@8 { + compatible = "cypress,cypd4226"; + reg = <0x08>; + interrupt-parent = <&gpio_aon>; + interrupts = <TEGRA194_AON_GPIO(BB, 2) IRQ_TYPE_LEVEL_LOW>; + firmware-name = "nvidia,jetson-agx-xavier"; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hs_ucsi_ccg_p0: endpoint { + remote-endpoint = <&hs_typec_p0>; + }; + }; + }; + }; + }; + }; + i2c@c250000 { status = "okay"; diff --git a/dts/src/arm64/nvidia/tegra194-p3668.dtsi b/dts/src/arm64/nvidia/tegra194-p3668.dtsi index 58f190b0f8..59860d19f0 100644 --- a/dts/src/arm64/nvidia/tegra194-p3668.dtsi +++ b/dts/src/arm64/nvidia/tegra194-p3668.dtsi @@ -50,6 +50,33 @@ status = "okay"; }; + i2c@c250000 { + status = "okay"; + + power-sensor@40 { + compatible = "ti,ina3221"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + reg = <0x0>; + label = "VDD_IN"; + shunt-resistor-micro-ohms = <5000>; + }; + input@1 { + reg = <0x1>; + label = "VDD_CPU_GPU_CV"; + shunt-resistor-micro-ohms = <5000>; + }; + input@2 { + reg = <0x2>; + label = "VDD_SOC"; + shunt-resistor-micro-ohms = <5000>; + }; + }; + }; + serial@3100000 { status = "okay"; }; diff --git a/dts/src/arm64/nvidia/tegra234-p3701.dtsi b/dts/src/arm64/nvidia/tegra234-p3701.dtsi index db6ef71167..320c8e9b06 100644 --- a/dts/src/arm64/nvidia/tegra234-p3701.dtsi +++ b/dts/src/arm64/nvidia/tegra234-p3701.dtsi @@ -3,6 +3,11 @@ / { compatible = "nvidia,p3701", "nvidia,tegra234"; + aliases { + mmc0 = "/bus@0/mmc@3460000"; + mmc1 = "/bus@0/mmc@3400000"; + }; + bus@0 { aconnect@2900000 { status = "okay"; @@ -12,1970 +17,22 @@ i2s@2901000 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s1_cif: endpoint { - remote-endpoint = <&xbar_i2s1>; - }; - }; - - i2s1_port: port@1 { - reg = <1>; - - i2s1_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; }; i2s@2901100 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s2_cif: endpoint { - remote-endpoint = <&xbar_i2s2>; - }; - }; - - i2s2_port: port@1 { - reg = <1>; - - i2s2_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; }; i2s@2901300 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s4_cif: endpoint { - remote-endpoint = <&xbar_i2s4>; - }; - }; - - i2s4_port: port@1 { - reg = <1>; - - i2s4_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; }; i2s@2901500 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s6_cif: endpoint { - remote-endpoint = <&xbar_i2s6>; - }; - }; - - i2s6_port: port@1 { - reg = <1>; - - i2s6_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; - }; - - sfc@2902000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc1_cif_in: endpoint { - remote-endpoint = <&xbar_sfc1_in>; - }; - }; - - sfc1_out_port: port@1 { - reg = <1>; - - sfc1_cif_out: endpoint { - remote-endpoint = <&xbar_sfc1_out>; - }; - }; - }; - }; - - sfc@2902200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc2_cif_in: endpoint { - remote-endpoint = <&xbar_sfc2_in>; - }; - }; - - sfc2_out_port: port@1 { - reg = <1>; - - sfc2_cif_out: endpoint { - remote-endpoint = <&xbar_sfc2_out>; - }; - }; - }; - }; - - sfc@2902400 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc3_cif_in: endpoint { - remote-endpoint = <&xbar_sfc3_in>; - }; - }; - - sfc3_out_port: port@1 { - reg = <1>; - - sfc3_cif_out: endpoint { - remote-endpoint = <&xbar_sfc3_out>; - }; - }; - }; - }; - - sfc@2902600 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc4_cif_in: endpoint { - remote-endpoint = <&xbar_sfc4_in>; - }; - }; - - sfc4_out_port: port@1 { - reg = <1>; - - sfc4_cif_out: endpoint { - remote-endpoint = <&xbar_sfc4_out>; - }; - }; - }; - }; - - amx@2903000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx1_in1: endpoint { - remote-endpoint = <&xbar_amx1_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx1_in2: endpoint { - remote-endpoint = <&xbar_amx1_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx1_in3: endpoint { - remote-endpoint = <&xbar_amx1_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx1_in4: endpoint { - remote-endpoint = <&xbar_amx1_in4>; - }; - }; - - amx1_out_port: port@4 { - reg = <4>; - - amx1_out: endpoint { - remote-endpoint = <&xbar_amx1_out>; - }; - }; - }; - }; - - amx@2903100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx2_in1: endpoint { - remote-endpoint = <&xbar_amx2_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx2_in2: endpoint { - remote-endpoint = <&xbar_amx2_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx2_in3: endpoint { - remote-endpoint = <&xbar_amx2_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx2_in4: endpoint { - remote-endpoint = <&xbar_amx2_in4>; - }; - }; - - amx2_out_port: port@4 { - reg = <4>; - - amx2_out: endpoint { - remote-endpoint = <&xbar_amx2_out>; - }; - }; - }; - }; - - amx@2903200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx3_in1: endpoint { - remote-endpoint = <&xbar_amx3_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx3_in2: endpoint { - remote-endpoint = <&xbar_amx3_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx3_in3: endpoint { - remote-endpoint = <&xbar_amx3_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx3_in4: endpoint { - remote-endpoint = <&xbar_amx3_in4>; - }; - }; - - amx3_out_port: port@4 { - reg = <4>; - - amx3_out: endpoint { - remote-endpoint = <&xbar_amx3_out>; - }; - }; - }; - }; - - amx@2903300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx4_in1: endpoint { - remote-endpoint = <&xbar_amx4_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx4_in2: endpoint { - remote-endpoint = <&xbar_amx4_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx4_in3: endpoint { - remote-endpoint = <&xbar_amx4_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx4_in4: endpoint { - remote-endpoint = <&xbar_amx4_in4>; - }; - }; - - amx4_out_port: port@4 { - reg = <4>; - - amx4_out: endpoint { - remote-endpoint = <&xbar_amx4_out>; - }; - }; - }; - }; - - adx@2903800 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx1_in: endpoint { - remote-endpoint = <&xbar_adx1_in>; - }; - }; - - adx1_out1_port: port@1 { - reg = <1>; - - adx1_out1: endpoint { - remote-endpoint = <&xbar_adx1_out1>; - }; - }; - - adx1_out2_port: port@2 { - reg = <2>; - - adx1_out2: endpoint { - remote-endpoint = <&xbar_adx1_out2>; - }; - }; - - adx1_out3_port: port@3 { - reg = <3>; - - adx1_out3: endpoint { - remote-endpoint = <&xbar_adx1_out3>; - }; - }; - - adx1_out4_port: port@4 { - reg = <4>; - - adx1_out4: endpoint { - remote-endpoint = <&xbar_adx1_out4>; - }; - }; - }; - }; - - adx@2903900 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx2_in: endpoint { - remote-endpoint = <&xbar_adx2_in>; - }; - }; - - adx2_out1_port: port@1 { - reg = <1>; - - adx2_out1: endpoint { - remote-endpoint = <&xbar_adx2_out1>; - }; - }; - - adx2_out2_port: port@2 { - reg = <2>; - - adx2_out2: endpoint { - remote-endpoint = <&xbar_adx2_out2>; - }; - }; - - adx2_out3_port: port@3 { - reg = <3>; - - adx2_out3: endpoint { - remote-endpoint = <&xbar_adx2_out3>; - }; - }; - - adx2_out4_port: port@4 { - reg = <4>; - - adx2_out4: endpoint { - remote-endpoint = <&xbar_adx2_out4>; - }; - }; - }; - }; - - adx@2903a00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx3_in: endpoint { - remote-endpoint = <&xbar_adx3_in>; - }; - }; - - adx3_out1_port: port@1 { - reg = <1>; - - adx3_out1: endpoint { - remote-endpoint = <&xbar_adx3_out1>; - }; - }; - - adx3_out2_port: port@2 { - reg = <2>; - - adx3_out2: endpoint { - remote-endpoint = <&xbar_adx3_out2>; - }; - }; - - adx3_out3_port: port@3 { - reg = <3>; - - adx3_out3: endpoint { - remote-endpoint = <&xbar_adx3_out3>; - }; - }; - - adx3_out4_port: port@4 { - reg = <4>; - - adx3_out4: endpoint { - remote-endpoint = <&xbar_adx3_out4>; - }; - }; - }; - }; - - adx@2903b00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx4_in: endpoint { - remote-endpoint = <&xbar_adx4_in>; - }; - }; - - adx4_out1_port: port@1 { - reg = <1>; - - adx4_out1: endpoint { - remote-endpoint = <&xbar_adx4_out1>; - }; - }; - - adx4_out2_port: port@2 { - reg = <2>; - - adx4_out2: endpoint { - remote-endpoint = <&xbar_adx4_out2>; - }; - }; - - adx4_out3_port: port@3 { - reg = <3>; - - adx4_out3: endpoint { - remote-endpoint = <&xbar_adx4_out3>; - }; - }; - - adx4_out4_port: port@4 { - reg = <4>; - - adx4_out4: endpoint { - remote-endpoint = <&xbar_adx4_out4>; - }; - }; - }; }; dmic@2904200 { status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic3_cif: endpoint { - remote-endpoint = <&xbar_dmic3>; - }; - }; - - dmic3_port: port@1 { - reg = <1>; - - dmic3_dap: endpoint { - /* placeholder for external codec */ - }; - }; - }; - }; - - processing-engine@2908000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - ope1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_ope1_in_ep>; - }; - }; - - ope1_out_port: port@1 { - reg = <0x1>; - - ope1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_ope1_out_ep>; - }; - }; - }; - }; - - mvc@290a000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in: endpoint { - remote-endpoint = <&xbar_mvc1_in>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out: endpoint { - remote-endpoint = <&xbar_mvc1_out>; - }; - }; - }; - }; - - mvc@290a200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in: endpoint { - remote-endpoint = <&xbar_mvc2_in>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out: endpoint { - remote-endpoint = <&xbar_mvc2_out>; - }; - }; - }; - }; - - amixer@290bb00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - mix_in1: endpoint { - remote-endpoint = <&xbar_mix_in1>; - }; - }; - - port@1 { - reg = <0x1>; - - mix_in2: endpoint { - remote-endpoint = <&xbar_mix_in2>; - }; - }; - - port@2 { - reg = <0x2>; - - mix_in3: endpoint { - remote-endpoint = <&xbar_mix_in3>; - }; - }; - - port@3 { - reg = <0x3>; - - mix_in4: endpoint { - remote-endpoint = <&xbar_mix_in4>; - }; - }; - - port@4 { - reg = <0x4>; - - mix_in5: endpoint { - remote-endpoint = <&xbar_mix_in5>; - }; - }; - - port@5 { - reg = <0x5>; - - mix_in6: endpoint { - remote-endpoint = <&xbar_mix_in6>; - }; - }; - - port@6 { - reg = <0x6>; - - mix_in7: endpoint { - remote-endpoint = <&xbar_mix_in7>; - }; - }; - - port@7 { - reg = <0x7>; - - mix_in8: endpoint { - remote-endpoint = <&xbar_mix_in8>; - }; - }; - - port@8 { - reg = <0x8>; - - mix_in9: endpoint { - remote-endpoint = <&xbar_mix_in9>; - }; - }; - - port@9 { - reg = <0x9>; - - mix_in10: endpoint { - remote-endpoint = <&xbar_mix_in10>; - }; - }; - - mix_out1_port: port@a { - reg = <0xa>; - - mix_out1: endpoint { - remote-endpoint = <&xbar_mix_out1>; - }; - }; - - mix_out2_port: port@b { - reg = <0xb>; - - mix_out2: endpoint { - remote-endpoint = <&xbar_mix_out2>; - }; - }; - - mix_out3_port: port@c { - reg = <0xc>; - - mix_out3: endpoint { - remote-endpoint = <&xbar_mix_out3>; - }; - }; - - mix_out4_port: port@d { - reg = <0xd>; - - mix_out4: endpoint { - remote-endpoint = <&xbar_mix_out4>; - }; - }; - - mix_out5_port: port@e { - reg = <0xe>; - - mix_out5: endpoint { - remote-endpoint = <&xbar_mix_out5>; - }; - }; - }; - }; - - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0: endpoint { - remote-endpoint = <&xbar_admaif0>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1: endpoint { - remote-endpoint = <&xbar_admaif1>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2: endpoint { - remote-endpoint = <&xbar_admaif2>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3: endpoint { - remote-endpoint = <&xbar_admaif3>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4: endpoint { - remote-endpoint = <&xbar_admaif4>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5: endpoint { - remote-endpoint = <&xbar_admaif5>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6: endpoint { - remote-endpoint = <&xbar_admaif6>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7: endpoint { - remote-endpoint = <&xbar_admaif7>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8: endpoint { - remote-endpoint = <&xbar_admaif8>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9: endpoint { - remote-endpoint = <&xbar_admaif9>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10: endpoint { - remote-endpoint = <&xbar_admaif10>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11: endpoint { - remote-endpoint = <&xbar_admaif11>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12: endpoint { - remote-endpoint = <&xbar_admaif12>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13: endpoint { - remote-endpoint = <&xbar_admaif13>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14: endpoint { - remote-endpoint = <&xbar_admaif14>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15: endpoint { - remote-endpoint = <&xbar_admaif15>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16: endpoint { - remote-endpoint = <&xbar_admaif16>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17: endpoint { - remote-endpoint = <&xbar_admaif17>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18: endpoint { - remote-endpoint = <&xbar_admaif18>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19: endpoint { - remote-endpoint = <&xbar_admaif19>; - }; - }; - }; - }; - - asrc@2910000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - asrc_in1_ep: endpoint { - remote-endpoint = <&xbar_asrc_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - asrc_in2_ep: endpoint { - remote-endpoint = <&xbar_asrc_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - asrc_in3_ep: endpoint { - remote-endpoint = <&xbar_asrc_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - asrc_in4_ep: endpoint { - remote-endpoint = <&xbar_asrc_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - asrc_in5_ep: endpoint { - remote-endpoint = <&xbar_asrc_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - asrc_in6_ep: endpoint { - remote-endpoint = <&xbar_asrc_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - asrc_in7_ep: endpoint { - remote-endpoint = <&xbar_asrc_in7_ep>; - }; - }; - - asrc_out1_port: port@7 { - reg = <0x7>; - - asrc_out1_ep: endpoint { - remote-endpoint = <&xbar_asrc_out1_ep>; - }; - }; - - asrc_out2_port: port@8 { - reg = <0x8>; - - asrc_out2_ep: endpoint { - remote-endpoint = <&xbar_asrc_out2_ep>; - }; - }; - - asrc_out3_port: port@9 { - reg = <0x9>; - - asrc_out3_ep: endpoint { - remote-endpoint = <&xbar_asrc_out3_ep>; - }; - }; - - asrc_out4_port: port@a { - reg = <0xa>; - - asrc_out4_ep: endpoint { - remote-endpoint = <&xbar_asrc_out4_ep>; - }; - }; - - asrc_out5_port: port@b { - reg = <0xb>; - - asrc_out5_ep: endpoint { - remote-endpoint = <&xbar_asrc_out5_ep>; - }; - }; - - asrc_out6_port: port@c { - reg = <0xc>; - - asrc_out6_ep: endpoint { - remote-endpoint = <&xbar_asrc_out6_ep>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0: endpoint { - remote-endpoint = <&admaif0>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1: endpoint { - remote-endpoint = <&admaif1>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2: endpoint { - remote-endpoint = <&admaif2>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3: endpoint { - remote-endpoint = <&admaif3>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4: endpoint { - remote-endpoint = <&admaif4>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5: endpoint { - remote-endpoint = <&admaif5>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6: endpoint { - remote-endpoint = <&admaif6>; - }; - }; - - port@7 { - reg = <0x7>; - - xbar_admaif7: endpoint { - remote-endpoint = <&admaif7>; - }; - }; - - port@8 { - reg = <0x8>; - - xbar_admaif8: endpoint { - remote-endpoint = <&admaif8>; - }; - }; - - port@9 { - reg = <0x9>; - - xbar_admaif9: endpoint { - remote-endpoint = <&admaif9>; - }; - }; - - port@a { - reg = <0xa>; - - xbar_admaif10: endpoint { - remote-endpoint = <&admaif10>; - }; - }; - - port@b { - reg = <0xb>; - - xbar_admaif11: endpoint { - remote-endpoint = <&admaif11>; - }; - }; - - port@c { - reg = <0xc>; - - xbar_admaif12: endpoint { - remote-endpoint = <&admaif12>; - }; - }; - - port@d { - reg = <0xd>; - - xbar_admaif13: endpoint { - remote-endpoint = <&admaif13>; - }; - }; - - port@e { - reg = <0xe>; - - xbar_admaif14: endpoint { - remote-endpoint = <&admaif14>; - }; - }; - - port@f { - reg = <0xf>; - - xbar_admaif15: endpoint { - remote-endpoint = <&admaif15>; - }; - }; - - port@10 { - reg = <0x10>; - - xbar_admaif16: endpoint { - remote-endpoint = <&admaif16>; - }; - }; - - port@11 { - reg = <0x11>; - - xbar_admaif17: endpoint { - remote-endpoint = <&admaif17>; - }; - }; - - port@12 { - reg = <0x12>; - - xbar_admaif18: endpoint { - remote-endpoint = <&admaif18>; - }; - }; - - port@13 { - reg = <0x13>; - - xbar_admaif19: endpoint { - remote-endpoint = <&admaif19>; - }; - }; - - xbar_i2s1_port: port@14 { - reg = <0x14>; - - xbar_i2s1: endpoint { - remote-endpoint = <&i2s1_cif>; - }; - }; - - xbar_i2s2_port: port@15 { - reg = <0x15>; - - xbar_i2s2: endpoint { - remote-endpoint = <&i2s2_cif>; - }; - }; - - xbar_i2s4_port: port@17 { - reg = <0x17>; - - xbar_i2s4: endpoint { - remote-endpoint = <&i2s4_cif>; - }; - }; - - xbar_i2s6_port: port@19 { - reg = <0x19>; - - xbar_i2s6: endpoint { - remote-endpoint = <&i2s6_cif>; - }; - }; - - xbar_dmic3_port: port@1c { - reg = <0x1c>; - - xbar_dmic3: endpoint { - remote-endpoint = <&dmic3_cif>; - }; - }; - - xbar_sfc1_in_port: port@20 { - reg = <0x20>; - - xbar_sfc1_in: endpoint { - remote-endpoint = <&sfc1_cif_in>; - }; - }; - - port@21 { - reg = <0x21>; - - xbar_sfc1_out: endpoint { - remote-endpoint = <&sfc1_cif_out>; - }; - }; - - xbar_sfc2_in_port: port@22 { - reg = <0x22>; - - xbar_sfc2_in: endpoint { - remote-endpoint = <&sfc2_cif_in>; - }; - }; - - port@23 { - reg = <0x23>; - - xbar_sfc2_out: endpoint { - remote-endpoint = <&sfc2_cif_out>; - }; - }; - - xbar_sfc3_in_port: port@24 { - reg = <0x24>; - - xbar_sfc3_in: endpoint { - remote-endpoint = <&sfc3_cif_in>; - }; - }; - - port@25 { - reg = <0x25>; - - xbar_sfc3_out: endpoint { - remote-endpoint = <&sfc3_cif_out>; - }; - }; - - xbar_sfc4_in_port: port@26 { - reg = <0x26>; - - xbar_sfc4_in: endpoint { - remote-endpoint = <&sfc4_cif_in>; - }; - }; - - port@27 { - reg = <0x27>; - - xbar_sfc4_out: endpoint { - remote-endpoint = <&sfc4_cif_out>; - }; - }; - - xbar_mvc1_in_port: port@28 { - reg = <0x28>; - - xbar_mvc1_in: endpoint { - remote-endpoint = <&mvc1_cif_in>; - }; - }; - - port@29 { - reg = <0x29>; - - xbar_mvc1_out: endpoint { - remote-endpoint = <&mvc1_cif_out>; - }; - }; - - xbar_mvc2_in_port: port@2a { - reg = <0x2a>; - - xbar_mvc2_in: endpoint { - remote-endpoint = <&mvc2_cif_in>; - }; - }; - - port@2b { - reg = <0x2b>; - - xbar_mvc2_out: endpoint { - remote-endpoint = <&mvc2_cif_out>; - }; - }; - - xbar_amx1_in1_port: port@2c { - reg = <0x2c>; - - xbar_amx1_in1: endpoint { - remote-endpoint = <&amx1_in1>; - }; - }; - - xbar_amx1_in2_port: port@2d { - reg = <0x2d>; - - xbar_amx1_in2: endpoint { - remote-endpoint = <&amx1_in2>; - }; - }; - - xbar_amx1_in3_port: port@2e { - reg = <0x2e>; - - xbar_amx1_in3: endpoint { - remote-endpoint = <&amx1_in3>; - }; - }; - - xbar_amx1_in4_port: port@2f { - reg = <0x2f>; - - xbar_amx1_in4: endpoint { - remote-endpoint = <&amx1_in4>; - }; - }; - - port@30 { - reg = <0x30>; - - xbar_amx1_out: endpoint { - remote-endpoint = <&amx1_out>; - }; - }; - - xbar_amx2_in1_port: port@31 { - reg = <0x31>; - - xbar_amx2_in1: endpoint { - remote-endpoint = <&amx2_in1>; - }; - }; - - xbar_amx2_in2_port: port@32 { - reg = <0x32>; - - xbar_amx2_in2: endpoint { - remote-endpoint = <&amx2_in2>; - }; - }; - - xbar_amx2_in3_port: port@33 { - reg = <0x33>; - - xbar_amx2_in3: endpoint { - remote-endpoint = <&amx2_in3>; - }; - }; - - xbar_amx2_in4_port: port@34 { - reg = <0x34>; - - xbar_amx2_in4: endpoint { - remote-endpoint = <&amx2_in4>; - }; - }; - - port@35 { - reg = <0x35>; - - xbar_amx2_out: endpoint { - remote-endpoint = <&amx2_out>; - }; - }; - - xbar_amx3_in1_port: port@36 { - reg = <0x36>; - - xbar_amx3_in1: endpoint { - remote-endpoint = <&amx3_in1>; - }; - }; - - xbar_amx3_in2_port: port@37 { - reg = <0x37>; - - xbar_amx3_in2: endpoint { - remote-endpoint = <&amx3_in2>; - }; - }; - - xbar_amx3_in3_port: port@38 { - reg = <0x38>; - - xbar_amx3_in3: endpoint { - remote-endpoint = <&amx3_in3>; - }; - }; - - xbar_amx3_in4_port: port@39 { - reg = <0x39>; - - xbar_amx3_in4: endpoint { - remote-endpoint = <&amx3_in4>; - }; - }; - - port@3a { - reg = <0x3a>; - - xbar_amx3_out: endpoint { - remote-endpoint = <&amx3_out>; - }; - }; - - xbar_amx4_in1_port: port@3b { - reg = <0x3b>; - - xbar_amx4_in1: endpoint { - remote-endpoint = <&amx4_in1>; - }; - }; - - xbar_amx4_in2_port: port@3c { - reg = <0x3c>; - - xbar_amx4_in2: endpoint { - remote-endpoint = <&amx4_in2>; - }; - }; - - xbar_amx4_in3_port: port@3d { - reg = <0x3d>; - - xbar_amx4_in3: endpoint { - remote-endpoint = <&amx4_in3>; - }; - }; - - xbar_amx4_in4_port: port@3e { - reg = <0x3e>; - - xbar_amx4_in4: endpoint { - remote-endpoint = <&amx4_in4>; - }; - }; - - port@3f { - reg = <0x3f>; - - xbar_amx4_out: endpoint { - remote-endpoint = <&amx4_out>; - }; - }; - - xbar_adx1_in_port: port@40 { - reg = <0x40>; - - xbar_adx1_in: endpoint { - remote-endpoint = <&adx1_in>; - }; - }; - - port@41 { - reg = <0x41>; - - xbar_adx1_out1: endpoint { - remote-endpoint = <&adx1_out1>; - }; - }; - - port@42 { - reg = <0x42>; - - xbar_adx1_out2: endpoint { - remote-endpoint = <&adx1_out2>; - }; - }; - - port@43 { - reg = <0x43>; - - xbar_adx1_out3: endpoint { - remote-endpoint = <&adx1_out3>; - }; - }; - - port@44 { - reg = <0x44>; - - xbar_adx1_out4: endpoint { - remote-endpoint = <&adx1_out4>; - }; - }; - - xbar_adx2_in_port: port@45 { - reg = <0x45>; - - xbar_adx2_in: endpoint { - remote-endpoint = <&adx2_in>; - }; - }; - - port@46 { - reg = <0x46>; - - xbar_adx2_out1: endpoint { - remote-endpoint = <&adx2_out1>; - }; - }; - - port@47 { - reg = <0x47>; - - xbar_adx2_out2: endpoint { - remote-endpoint = <&adx2_out2>; - }; - }; - - port@48 { - reg = <0x48>; - - xbar_adx2_out3: endpoint { - remote-endpoint = <&adx2_out3>; - }; - }; - - port@49 { - reg = <0x49>; - - xbar_adx2_out4: endpoint { - remote-endpoint = <&adx2_out4>; - }; - }; - - xbar_adx3_in_port: port@4a { - reg = <0x4a>; - - xbar_adx3_in: endpoint { - remote-endpoint = <&adx3_in>; - }; - }; - - port@4b { - reg = <0x4b>; - - xbar_adx3_out1: endpoint { - remote-endpoint = <&adx3_out1>; - }; - }; - - port@4c { - reg = <0x4c>; - - xbar_adx3_out2: endpoint { - remote-endpoint = <&adx3_out2>; - }; - }; - - port@4d { - reg = <0x4d>; - - xbar_adx3_out3: endpoint { - remote-endpoint = <&adx3_out3>; - }; - }; - - port@4e { - reg = <0x4e>; - - xbar_adx3_out4: endpoint { - remote-endpoint = <&adx3_out4>; - }; - }; - - xbar_adx4_in_port: port@4f { - reg = <0x4f>; - - xbar_adx4_in: endpoint { - remote-endpoint = <&adx4_in>; - }; - }; - - port@50 { - reg = <0x50>; - - xbar_adx4_out1: endpoint { - remote-endpoint = <&adx4_out1>; - }; - }; - - port@51 { - reg = <0x51>; - - xbar_adx4_out2: endpoint { - remote-endpoint = <&adx4_out2>; - }; - }; - - port@52 { - reg = <0x52>; - - xbar_adx4_out3: endpoint { - remote-endpoint = <&adx4_out3>; - }; - }; - - port@53 { - reg = <0x53>; - - xbar_adx4_out4: endpoint { - remote-endpoint = <&adx4_out4>; - }; - }; - - xbar_mix_in1_port: port@54 { - reg = <0x54>; - - xbar_mix_in1: endpoint { - remote-endpoint = <&mix_in1>; - }; - }; - - xbar_mix_in2_port: port@55 { - reg = <0x55>; - - xbar_mix_in2: endpoint { - remote-endpoint = <&mix_in2>; - }; - }; - - xbar_mix_in3_port: port@56 { - reg = <0x56>; - - xbar_mix_in3: endpoint { - remote-endpoint = <&mix_in3>; - }; - }; - - xbar_mix_in4_port: port@57 { - reg = <0x57>; - - xbar_mix_in4: endpoint { - remote-endpoint = <&mix_in4>; - }; - }; - - xbar_mix_in5_port: port@58 { - reg = <0x58>; - - xbar_mix_in5: endpoint { - remote-endpoint = <&mix_in5>; - }; - }; - - xbar_mix_in6_port: port@59 { - reg = <0x59>; - - xbar_mix_in6: endpoint { - remote-endpoint = <&mix_in6>; - }; - }; - - xbar_mix_in7_port: port@5a { - reg = <0x5a>; - - xbar_mix_in7: endpoint { - remote-endpoint = <&mix_in7>; - }; - }; - - xbar_mix_in8_port: port@5b { - reg = <0x5b>; - - xbar_mix_in8: endpoint { - remote-endpoint = <&mix_in8>; - }; - }; - - xbar_mix_in9_port: port@5c { - reg = <0x5c>; - - xbar_mix_in9: endpoint { - remote-endpoint = <&mix_in9>; - }; - }; - - xbar_mix_in10_port: port@5d { - reg = <0x5d>; - - xbar_mix_in10: endpoint { - remote-endpoint = <&mix_in10>; - }; - }; - - port@5e { - reg = <0x5e>; - - xbar_mix_out1: endpoint { - remote-endpoint = <&mix_out1>; - }; - }; - - port@5f { - reg = <0x5f>; - - xbar_mix_out2: endpoint { - remote-endpoint = <&mix_out2>; - }; - }; - - port@60 { - reg = <0x60>; - - xbar_mix_out3: endpoint { - remote-endpoint = <&mix_out3>; - }; - }; - - port@61 { - reg = <0x61>; - - xbar_mix_out4: endpoint { - remote-endpoint = <&mix_out4>; - }; - }; - - port@62 { - reg = <0x62>; - - xbar_mix_out5: endpoint { - remote-endpoint = <&mix_out5>; - }; - }; - - xbar_asrc_in1_port: port@63 { - reg = <0x63>; - - xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; - }; - }; - - port@64 { - reg = <0x64>; - - xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; - }; - }; - - xbar_asrc_in2_port: port@65 { - reg = <0x65>; - - xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; - }; - }; - - port@66 { - reg = <0x66>; - - xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; - }; - }; - - xbar_asrc_in3_port: port@67 { - reg = <0x67>; - - xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; - }; - }; - - port@68 { - reg = <0x68>; - - xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; - }; - }; - - xbar_asrc_in4_port: port@69 { - reg = <0x69>; - - xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; - }; - }; - - port@6a { - reg = <0x6a>; - - xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; - }; - }; - - xbar_asrc_in5_port: port@6b { - reg = <0x6b>; - - xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; - }; - }; - - port@6c { - reg = <0x6c>; - - xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; - }; - }; - - xbar_asrc_in6_port: port@6d { - reg = <0x6d>; - - xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; - }; - }; - - port@6e { - reg = <0x6e>; - - xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; - }; - }; - - xbar_asrc_in7_port: port@6f { - reg = <0x6f>; - - xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; - }; - }; - - xbar_ope1_in_port: port@70 { - reg = <0x70>; - - xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; - }; - }; - - port@71 { - reg = <0x71>; - - xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; - }; - }; }; }; diff --git a/dts/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts b/dts/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts index 81a82933e3..69db584253 100644 --- a/dts/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/dts/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -12,7 +12,6 @@ compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234"; aliases { - mmc3 = "/bus@0/mmc@3460000"; serial0 = &tcu; serial1 = &uarta; }; diff --git a/dts/src/arm64/nvidia/tegra234-p3767-0000.dtsi b/dts/src/arm64/nvidia/tegra234-p3767-0000.dtsi deleted file mode 100644 index baf4f69e41..0000000000 --- a/dts/src/arm64/nvidia/tegra234-p3767-0000.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "tegra234-p3767.dtsi" - -/ { - compatible = "nvidia,p3767-0000", "nvidia,tegra234"; - model = "NVIDIA Jetson Orin NX"; - - bus@0 { - hda@3510000 { - nvidia,model = "NVIDIA Jetson Orin NX HDA"; - }; - }; -}; diff --git a/dts/src/arm64/nvidia/tegra234-p3767-0005.dtsi b/dts/src/arm64/nvidia/tegra234-p3767-0005.dtsi deleted file mode 100644 index 232fa95ef4..0000000000 --- a/dts/src/arm64/nvidia/tegra234-p3767-0005.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "tegra234-p3767.dtsi" - -/ { - compatible = "nvidia,p3767-0005", "nvidia,tegra234"; - model = "NVIDIA Jetson Orin Nano"; - - bus@0 { - hda@3510000 { - nvidia,model = "NVIDIA Jetson Orin Nano HDA"; - }; - }; -}; diff --git a/dts/src/arm64/nvidia/tegra234-p3767.dtsi b/dts/src/arm64/nvidia/tegra234-p3767.dtsi index 59c14ded5e..84db7132e8 100644 --- a/dts/src/arm64/nvidia/tegra234-p3767.dtsi +++ b/dts/src/arm64/nvidia/tegra234-p3767.dtsi @@ -5,7 +5,35 @@ / { compatible = "nvidia,p3767", "nvidia,tegra234"; + aliases { + mmc0 = "/bus@0/mmc@3400000"; + }; + bus@0 { + aconnect@2900000 { + status = "okay"; + + ahub@2900800 { + status = "okay"; + + i2s@2901100 { + status = "okay"; + }; + + i2s@2901300 { + status = "okay"; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + i2c@3160000 { status = "okay"; @@ -127,6 +155,64 @@ vin-supply = <&vdd_5v0_sys>; }; + sound { + compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* XBAR Ports */ + <&xbar_i2s2_port>, <&xbar_i2s4_port>, + <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, + <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, + <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, + <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, + <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, + <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, + <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, + <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, + <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, + <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, + <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, + <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, + <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, + <&xbar_mix_in1_port>, <&xbar_mix_in2_port>, + <&xbar_mix_in3_port>, <&xbar_mix_in4_port>, + <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, + <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, + <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, + /* HW accelerators */ + <&sfc1_out_port>, <&sfc2_out_port>, + <&sfc3_out_port>, <&sfc4_out_port>, + <&mvc1_out_port>, <&mvc2_out_port>, + <&amx1_out_port>, <&amx2_out_port>, + <&amx3_out_port>, <&amx4_out_port>, + <&adx1_out1_port>, <&adx1_out2_port>, + <&adx1_out3_port>, <&adx1_out4_port>, + <&adx2_out1_port>, <&adx2_out2_port>, + <&adx2_out3_port>, <&adx2_out4_port>, + <&adx3_out1_port>, <&adx3_out2_port>, + <&adx3_out3_port>, <&adx3_out4_port>, + <&adx4_out1_port>, <&adx4_out2_port>, + <&adx4_out3_port>, <&adx4_out4_port>, + <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, + <&mix_out4_port>, <&mix_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, + /* BE I/O Ports */ + <&i2s2_port>, <&i2s4_port>; + }; + thermal-zones { tj-thermal { polling-delay = <1000>; diff --git a/dts/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts b/dts/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts index 61b0e69d3d..1607ee1421 100644 --- a/dts/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts +++ b/dts/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts @@ -4,7 +4,7 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/input/gpio-keys.h> -#include "tegra234-p3767-0000.dtsi" +#include "tegra234-p3767.dtsi" #include "tegra234-p3768-0000.dtsi" / { @@ -37,7 +37,6 @@ hda@3510000 { nvidia,model = "NVIDIA Jetson Orin NX HDA"; - status = "okay"; }; padctl@3520000 { @@ -85,6 +84,10 @@ enable-active-high; }; + sound { + label = "NVIDIA Jetson Orin NX APE"; + }; + thermal-zones { tj-thermal { cooling-maps { diff --git a/dts/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts b/dts/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts index 9e9bb9ca8b..dc2d4bef1e 100644 --- a/dts/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts +++ b/dts/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts @@ -4,17 +4,27 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/input/gpio-keys.h> -#include "tegra234-p3767-0005.dtsi" +#include "tegra234-p3767.dtsi" #include "tegra234-p3768-0000.dtsi" / { compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234"; model = "NVIDIA Jetson Orin Nano Developer Kit"; + bus@0 { + hda@3510000 { + nvidia,model = "NVIDIA Jetson Orin Nano HDA"; + }; + }; + pwm-fan { cooling-levels = <0 88 187 255>; }; + sound { + label = "NVIDIA Jetson Orin Nano APE"; + }; + thermal-zones { tj-thermal { cooling-maps { diff --git a/dts/src/arm64/nvidia/tegra234-sim-vdk.dts b/dts/src/arm64/nvidia/tegra234-sim-vdk.dts index 9f3e9f30c3..292e28376e 100644 --- a/dts/src/arm64/nvidia/tegra234-sim-vdk.dts +++ b/dts/src/arm64/nvidia/tegra234-sim-vdk.dts @@ -8,7 +8,6 @@ compatible = "nvidia,tegra234-vdk", "nvidia,tegra234"; aliases { - mmc3 = "/bus@0/mmc@3460000"; serial0 = &uarta; }; diff --git a/dts/src/arm64/nvidia/tegra234.dtsi b/dts/src/arm64/nvidia/tegra234.dtsi index d1bd328892..78cbfdd98d 100644 --- a/dts/src/arm64/nvidia/tegra234.dtsi +++ b/dts/src/arm64/nvidia/tegra234.dtsi @@ -200,6 +200,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S1"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif: endpoint { + remote-endpoint = <&xbar_i2s1>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s2: i2s@2901100 { @@ -214,6 +236,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S2"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s2_cif: endpoint { + remote-endpoint = <&xbar_i2s2>; + }; + }; + + i2s2_port: port@1 { + reg = <1>; + + i2s2_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s3: i2s@2901200 { @@ -228,6 +272,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S3"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif: endpoint { + remote-endpoint = <&xbar_i2s3>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s4: i2s@2901300 { @@ -242,6 +308,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S4"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s4_cif: endpoint { + remote-endpoint = <&xbar_i2s4>; + }; + }; + + i2s4_port: port@1 { + reg = <1>; + + i2s4_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s5: i2s@2901400 { @@ -256,6 +344,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S5"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s5_cif: endpoint { + remote-endpoint = <&xbar_i2s5>; + }; + }; + + i2s5_port: port@1 { + reg = <1>; + + i2s5_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_i2s6: i2s@2901500 { @@ -270,6 +380,28 @@ assigned-clock-rates = <1536000>; sound-name-prefix = "I2S6"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s6_cif: endpoint { + remote-endpoint = <&xbar_i2s6>; + }; + }; + + i2s6_port: port@1 { + reg = <1>; + + i2s6_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; }; tegra_sfc1: sfc@2902000 { @@ -277,7 +409,27 @@ "nvidia,tegra210-sfc"; reg = <0x0 0x2902000 0x0 0x200>; sound-name-prefix = "SFC1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in: endpoint { + remote-endpoint = <&xbar_sfc1_in>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out: endpoint { + remote-endpoint = <&xbar_sfc1_out>; + }; + }; + }; }; tegra_sfc2: sfc@2902200 { @@ -285,7 +437,27 @@ "nvidia,tegra210-sfc"; reg = <0x0 0x2902200 0x0 0x200>; sound-name-prefix = "SFC2"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in: endpoint { + remote-endpoint = <&xbar_sfc2_in>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out: endpoint { + remote-endpoint = <&xbar_sfc2_out>; + }; + }; + }; }; tegra_sfc3: sfc@2902400 { @@ -293,7 +465,27 @@ "nvidia,tegra210-sfc"; reg = <0x0 0x2902400 0x0 0x200>; sound-name-prefix = "SFC3"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in: endpoint { + remote-endpoint = <&xbar_sfc3_in>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out: endpoint { + remote-endpoint = <&xbar_sfc3_out>; + }; + }; + }; }; tegra_sfc4: sfc@2902600 { @@ -301,7 +493,27 @@ "nvidia,tegra210-sfc"; reg = <0x0 0x2902600 0x0 0x200>; sound-name-prefix = "SFC4"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in: endpoint { + remote-endpoint = <&xbar_sfc4_in>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out: endpoint { + remote-endpoint = <&xbar_sfc4_out>; + }; + }; + }; }; tegra_amx1: amx@2903000 { @@ -309,7 +521,51 @@ "nvidia,tegra194-amx"; reg = <0x0 0x2903000 0x0 0x100>; sound-name-prefix = "AMX1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1: endpoint { + remote-endpoint = <&xbar_amx1_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2: endpoint { + remote-endpoint = <&xbar_amx1_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3: endpoint { + remote-endpoint = <&xbar_amx1_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4: endpoint { + remote-endpoint = <&xbar_amx1_in4>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out: endpoint { + remote-endpoint = <&xbar_amx1_out>; + }; + }; + }; }; tegra_amx2: amx@2903100 { @@ -317,7 +573,51 @@ "nvidia,tegra194-amx"; reg = <0x0 0x2903100 0x0 0x100>; sound-name-prefix = "AMX2"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1: endpoint { + remote-endpoint = <&xbar_amx2_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2: endpoint { + remote-endpoint = <&xbar_amx2_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx2_in3: endpoint { + remote-endpoint = <&xbar_amx2_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx2_in4: endpoint { + remote-endpoint = <&xbar_amx2_in4>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out: endpoint { + remote-endpoint = <&xbar_amx2_out>; + }; + }; + }; }; tegra_amx3: amx@2903200 { @@ -325,7 +625,51 @@ "nvidia,tegra194-amx"; reg = <0x0 0x2903200 0x0 0x100>; sound-name-prefix = "AMX3"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1: endpoint { + remote-endpoint = <&xbar_amx3_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2: endpoint { + remote-endpoint = <&xbar_amx3_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3: endpoint { + remote-endpoint = <&xbar_amx3_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4: endpoint { + remote-endpoint = <&xbar_amx3_in4>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out: endpoint { + remote-endpoint = <&xbar_amx3_out>; + }; + }; + }; }; tegra_amx4: amx@2903300 { @@ -333,7 +677,51 @@ "nvidia,tegra194-amx"; reg = <0x0 0x2903300 0x0 0x100>; sound-name-prefix = "AMX4"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1: endpoint { + remote-endpoint = <&xbar_amx4_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2: endpoint { + remote-endpoint = <&xbar_amx4_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3: endpoint { + remote-endpoint = <&xbar_amx4_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4: endpoint { + remote-endpoint = <&xbar_amx4_in4>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out: endpoint { + remote-endpoint = <&xbar_amx4_out>; + }; + }; + }; }; tegra_adx1: adx@2903800 { @@ -341,7 +729,51 @@ "nvidia,tegra210-adx"; reg = <0x0 0x2903800 0x0 0x100>; sound-name-prefix = "ADX1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in: endpoint { + remote-endpoint = <&xbar_adx1_in>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1: endpoint { + remote-endpoint = <&xbar_adx1_out1>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2: endpoint { + remote-endpoint = <&xbar_adx1_out2>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3: endpoint { + remote-endpoint = <&xbar_adx1_out3>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4: endpoint { + remote-endpoint = <&xbar_adx1_out4>; + }; + }; + }; }; tegra_adx2: adx@2903900 { @@ -349,7 +781,51 @@ "nvidia,tegra210-adx"; reg = <0x0 0x2903900 0x0 0x100>; sound-name-prefix = "ADX2"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in: endpoint { + remote-endpoint = <&xbar_adx2_in>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1: endpoint { + remote-endpoint = <&xbar_adx2_out1>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2: endpoint { + remote-endpoint = <&xbar_adx2_out2>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3: endpoint { + remote-endpoint = <&xbar_adx2_out3>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4: endpoint { + remote-endpoint = <&xbar_adx2_out4>; + }; + }; + }; }; tegra_adx3: adx@2903a00 { @@ -357,7 +833,51 @@ "nvidia,tegra210-adx"; reg = <0x0 0x2903a00 0x0 0x100>; sound-name-prefix = "ADX3"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in: endpoint { + remote-endpoint = <&xbar_adx3_in>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1: endpoint { + remote-endpoint = <&xbar_adx3_out1>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2: endpoint { + remote-endpoint = <&xbar_adx3_out2>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3: endpoint { + remote-endpoint = <&xbar_adx3_out3>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4: endpoint { + remote-endpoint = <&xbar_adx3_out4>; + }; + }; + }; }; tegra_adx4: adx@2903b00 { @@ -365,7 +885,51 @@ "nvidia,tegra210-adx"; reg = <0x0 0x2903b00 0x0 0x100>; sound-name-prefix = "ADX4"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in: endpoint { + remote-endpoint = <&xbar_adx4_in>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1: endpoint { + remote-endpoint = <&xbar_adx4_out1>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2: endpoint { + remote-endpoint = <&xbar_adx4_out2>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3: endpoint { + remote-endpoint = <&xbar_adx4_out3>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4: endpoint { + remote-endpoint = <&xbar_adx4_out4>; + }; + }; + }; }; @@ -380,6 +944,27 @@ assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC1"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif: endpoint { + remote-endpoint = <&xbar_dmic1>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dmic2: dmic@2904100 { @@ -393,6 +978,27 @@ assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC2"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif: endpoint { + remote-endpoint = <&xbar_dmic2>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dmic3: dmic@2904200 { @@ -406,6 +1012,27 @@ assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC3"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif: endpoint { + remote-endpoint = <&xbar_dmic3>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dmic4: dmic@2904300 { @@ -419,6 +1046,27 @@ assigned-clock-rates = <3072000>; sound-name-prefix = "DMIC4"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic4_cif: endpoint { + remote-endpoint = <&xbar_dmic4>; + }; + }; + + dmic4_port: port@1 { + reg = <1>; + + dmic4_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dspk1: dspk@2905000 { @@ -432,6 +1080,27 @@ assigned-clock-rates = <12288000>; sound-name-prefix = "DSPK1"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif: endpoint { + remote-endpoint = <&xbar_dspk1>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_dspk2: dspk@2905100 { @@ -445,6 +1114,27 @@ assigned-clock-rates = <12288000>; sound-name-prefix = "DSPK2"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk2_cif: endpoint { + remote-endpoint = <&xbar_dspk2>; + }; + }; + + dspk2_port: port@1 { + reg = <1>; + + dspk2_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; }; tegra_ope1: processing-engine@2908000 { @@ -452,7 +1142,6 @@ "nvidia,tegra210-ope"; reg = <0x0 0x2908000 0x0 0x100>; sound-name-prefix = "OPE1"; - status = "disabled"; #address-cells = <2>; #size-cells = <2>; @@ -469,6 +1158,29 @@ "nvidia,tegra210-mbdrc"; reg = <0x0 0x2908200 0x0 0x200>; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = + <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = + <&xbar_ope1_out_ep>; + }; + }; + }; }; tegra_mvc1: mvc@290a000 { @@ -476,7 +1188,27 @@ "nvidia,tegra210-mvc"; reg = <0x0 0x290a000 0x0 0x200>; sound-name-prefix = "MVC1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in: endpoint { + remote-endpoint = <&xbar_mvc1_in>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out: endpoint { + remote-endpoint = <&xbar_mvc1_out>; + }; + }; + }; }; tegra_mvc2: mvc@290a200 { @@ -484,7 +1216,27 @@ "nvidia,tegra210-mvc"; reg = <0x0 0x290a200 0x0 0x200>; sound-name-prefix = "MVC2"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in: endpoint { + remote-endpoint = <&xbar_mvc2_in>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out: endpoint { + remote-endpoint = <&xbar_mvc2_out>; + }; + }; + }; }; tegra_amixer: amixer@290bb00 { @@ -492,7 +1244,131 @@ "nvidia,tegra210-amixer"; reg = <0x0 0x290bb00 0x0 0x800>; sound-name-prefix = "MIXER1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mix_in1: endpoint { + remote-endpoint = <&xbar_mix_in1>; + }; + }; + + port@1 { + reg = <0x1>; + + mix_in2: endpoint { + remote-endpoint = <&xbar_mix_in2>; + }; + }; + + port@2 { + reg = <0x2>; + + mix_in3: endpoint { + remote-endpoint = <&xbar_mix_in3>; + }; + }; + + port@3 { + reg = <0x3>; + + mix_in4: endpoint { + remote-endpoint = <&xbar_mix_in4>; + }; + }; + + port@4 { + reg = <0x4>; + + mix_in5: endpoint { + remote-endpoint = <&xbar_mix_in5>; + }; + }; + + port@5 { + reg = <0x5>; + + mix_in6: endpoint { + remote-endpoint = <&xbar_mix_in6>; + }; + }; + + port@6 { + reg = <0x6>; + + mix_in7: endpoint { + remote-endpoint = <&xbar_mix_in7>; + }; + }; + + port@7 { + reg = <0x7>; + + mix_in8: endpoint { + remote-endpoint = <&xbar_mix_in8>; + }; + }; + + port@8 { + reg = <0x8>; + + mix_in9: endpoint { + remote-endpoint = <&xbar_mix_in9>; + }; + }; + + port@9 { + reg = <0x9>; + + mix_in10: endpoint { + remote-endpoint = <&xbar_mix_in10>; + }; + }; + + mix_out1_port: port@a { + reg = <0xa>; + + mix_out1: endpoint { + remote-endpoint = <&xbar_mix_out1>; + }; + }; + + mix_out2_port: port@b { + reg = <0xb>; + + mix_out2: endpoint { + remote-endpoint = <&xbar_mix_out2>; + }; + }; + + mix_out3_port: port@c { + reg = <0xc>; + + mix_out3: endpoint { + remote-endpoint = <&xbar_mix_out3>; + }; + }; + + mix_out4_port: port@d { + reg = <0xd>; + + mix_out4: endpoint { + remote-endpoint = <&xbar_mix_out4>; + }; + }; + + mix_out5_port: port@e { + reg = <0xe>; + + mix_out5: endpoint { + remote-endpoint = <&xbar_mix_out5>; + }; + }; + }; }; tegra_admaif: admaif@290f000 { @@ -543,7 +1419,171 @@ <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; interconnect-names = "dma-mem", "write"; iommus = <&smmu_niso0 TEGRA234_SID_APE>; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0: endpoint { + remote-endpoint = <&xbar_admaif0>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1: endpoint { + remote-endpoint = <&xbar_admaif1>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2: endpoint { + remote-endpoint = <&xbar_admaif2>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3: endpoint { + remote-endpoint = <&xbar_admaif3>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4: endpoint { + remote-endpoint = <&xbar_admaif4>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5: endpoint { + remote-endpoint = <&xbar_admaif5>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6: endpoint { + remote-endpoint = <&xbar_admaif6>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7: endpoint { + remote-endpoint = <&xbar_admaif7>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8: endpoint { + remote-endpoint = <&xbar_admaif8>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9: endpoint { + remote-endpoint = <&xbar_admaif9>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10: endpoint { + remote-endpoint = <&xbar_admaif10>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11: endpoint { + remote-endpoint = <&xbar_admaif11>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12: endpoint { + remote-endpoint = <&xbar_admaif12>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13: endpoint { + remote-endpoint = <&xbar_admaif13>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14: endpoint { + remote-endpoint = <&xbar_admaif14>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15: endpoint { + remote-endpoint = <&xbar_admaif15>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16: endpoint { + remote-endpoint = <&xbar_admaif16>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17: endpoint { + remote-endpoint = <&xbar_admaif17>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18: endpoint { + remote-endpoint = <&xbar_admaif18>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19: endpoint { + remote-endpoint = <&xbar_admaif19>; + }; + }; + }; }; tegra_asrc: asrc@2910000 { @@ -551,7 +1591,1045 @@ "nvidia,tegra186-asrc"; reg = <0x0 0x2910000 0x0 0x2000>; sound-name-prefix = "ASRC1"; - status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out6_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint = <&admaif0>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint = <&admaif1>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint = <&admaif2>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint = <&admaif3>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint = <&admaif4>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint = <&admaif5>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint = <&admaif6>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint = <&admaif7>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint = <&admaif8>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint = <&admaif9>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint = <&admaif10>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint = <&admaif11>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint = <&admaif12>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint = <&admaif13>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint = <&admaif14>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint = <&admaif15>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint = <&admaif16>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint = <&admaif17>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint = <&admaif18>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint = <&admaif19>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1: endpoint { + remote-endpoint = <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@15 { + reg = <0x15>; + + xbar_i2s2: endpoint { + remote-endpoint = <&i2s2_cif>; + }; + }; + + xbar_i2s3_port: port@16 { + reg = <0x16>; + + xbar_i2s3: endpoint { + remote-endpoint = <&i2s3_cif>; + }; + }; + + xbar_i2s4_port: port@17 { + reg = <0x17>; + + xbar_i2s4: endpoint { + remote-endpoint = <&i2s4_cif>; + }; + }; + + xbar_i2s5_port: port@18 { + reg = <0x18>; + + xbar_i2s5: endpoint { + remote-endpoint = <&i2s5_cif>; + }; + }; + + xbar_i2s6_port: port@19 { + reg = <0x19>; + + xbar_i2s6: endpoint { + remote-endpoint = <&i2s6_cif>; + }; + }; + + xbar_dmic1_port: port@1a { + reg = <0x1a>; + + xbar_dmic1: endpoint { + remote-endpoint = <&dmic1_cif>; + }; + }; + + xbar_dmic2_port: port@1b { + reg = <0x1b>; + + xbar_dmic2: endpoint { + remote-endpoint = <&dmic2_cif>; + }; + }; + + xbar_dmic3_port: port@1c { + reg = <0x1c>; + + xbar_dmic3: endpoint { + remote-endpoint = <&dmic3_cif>; + }; + }; + + xbar_dmic4_port: port@1d { + reg = <0x1d>; + + xbar_dmic4: endpoint { + remote-endpoint = <&dmic4_cif>; + }; + }; + + xbar_dspk1_port: port@1e { + reg = <0x1e>; + + xbar_dspk1: endpoint { + remote-endpoint = <&dspk1_cif>; + }; + }; + + xbar_dspk2_port: port@1f { + reg = <0x1f>; + + xbar_dspk2: endpoint { + remote-endpoint = <&dspk2_cif>; + }; + }; + + xbar_sfc1_in_port: port@20 { + reg = <0x20>; + + xbar_sfc1_in: endpoint { + remote-endpoint = <&sfc1_cif_in>; + }; + }; + + port@21 { + reg = <0x21>; + + xbar_sfc1_out: endpoint { + remote-endpoint = <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@22 { + reg = <0x22>; + + xbar_sfc2_in: endpoint { + remote-endpoint = <&sfc2_cif_in>; + }; + }; + + port@23 { + reg = <0x23>; + + xbar_sfc2_out: endpoint { + remote-endpoint = <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@24 { + reg = <0x24>; + + xbar_sfc3_in: endpoint { + remote-endpoint = <&sfc3_cif_in>; + }; + }; + + port@25 { + reg = <0x25>; + + xbar_sfc3_out: endpoint { + remote-endpoint = <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@26 { + reg = <0x26>; + + xbar_sfc4_in: endpoint { + remote-endpoint = <&sfc4_cif_in>; + }; + }; + + port@27 { + reg = <0x27>; + + xbar_sfc4_out: endpoint { + remote-endpoint = <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in: endpoint { + remote-endpoint = <&mvc1_cif_in>; + }; + }; + + port@29 { + reg = <0x29>; + + xbar_mvc1_out: endpoint { + remote-endpoint = <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@2a { + reg = <0x2a>; + + xbar_mvc2_in: endpoint { + remote-endpoint = <&mvc2_cif_in>; + }; + }; + + port@2b { + reg = <0x2b>; + + xbar_mvc2_out: endpoint { + remote-endpoint = <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1: endpoint { + remote-endpoint = <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2: endpoint { + remote-endpoint = <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@2e { + reg = <0x2e>; + + xbar_amx1_in3: endpoint { + remote-endpoint = <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@2f { + reg = <0x2f>; + + xbar_amx1_in4: endpoint { + remote-endpoint = <&amx1_in4>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_amx1_out: endpoint { + remote-endpoint = <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@31 { + reg = <0x31>; + + xbar_amx2_in1: endpoint { + remote-endpoint = <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@32 { + reg = <0x32>; + + xbar_amx2_in2: endpoint { + remote-endpoint = <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@33 { + reg = <0x33>; + + xbar_amx2_in3: endpoint { + remote-endpoint = <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@34 { + reg = <0x34>; + + xbar_amx2_in4: endpoint { + remote-endpoint = <&amx2_in4>; + }; + }; + + port@35 { + reg = <0x35>; + + xbar_amx2_out: endpoint { + remote-endpoint = <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@36 { + reg = <0x36>; + + xbar_amx3_in1: endpoint { + remote-endpoint = <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@37 { + reg = <0x37>; + + xbar_amx3_in2: endpoint { + remote-endpoint = <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@38 { + reg = <0x38>; + + xbar_amx3_in3: endpoint { + remote-endpoint = <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@39 { + reg = <0x39>; + + xbar_amx3_in4: endpoint { + remote-endpoint = <&amx3_in4>; + }; + }; + + port@3a { + reg = <0x3a>; + + xbar_amx3_out: endpoint { + remote-endpoint = <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@3b { + reg = <0x3b>; + + xbar_amx4_in1: endpoint { + remote-endpoint = <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@3c { + reg = <0x3c>; + + xbar_amx4_in2: endpoint { + remote-endpoint = <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@3d { + reg = <0x3d>; + + xbar_amx4_in3: endpoint { + remote-endpoint = <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@3e { + reg = <0x3e>; + + xbar_amx4_in4: endpoint { + remote-endpoint = <&amx4_in4>; + }; + }; + + port@3f { + reg = <0x3f>; + + xbar_amx4_out: endpoint { + remote-endpoint = <&amx4_out>; + }; + }; + + xbar_adx1_in_port: port@40 { + reg = <0x40>; + + xbar_adx1_in: endpoint { + remote-endpoint = <&adx1_in>; + }; + }; + + port@41 { + reg = <0x41>; + + xbar_adx1_out1: endpoint { + remote-endpoint = <&adx1_out1>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_adx1_out2: endpoint { + remote-endpoint = <&adx1_out2>; + }; + }; + + port@43 { + reg = <0x43>; + + xbar_adx1_out3: endpoint { + remote-endpoint = <&adx1_out3>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_adx1_out4: endpoint { + remote-endpoint = <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@45 { + reg = <0x45>; + + xbar_adx2_in: endpoint { + remote-endpoint = <&adx2_in>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1: endpoint { + remote-endpoint = <&adx2_out1>; + }; + }; + + port@47 { + reg = <0x47>; + + xbar_adx2_out2: endpoint { + remote-endpoint = <&adx2_out2>; + }; + }; + + port@48 { + reg = <0x48>; + + xbar_adx2_out3: endpoint { + remote-endpoint = <&adx2_out3>; + }; + }; + + port@49 { + reg = <0x49>; + + xbar_adx2_out4: endpoint { + remote-endpoint = <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@4a { + reg = <0x4a>; + + xbar_adx3_in: endpoint { + remote-endpoint = <&adx3_in>; + }; + }; + + port@4b { + reg = <0x4b>; + + xbar_adx3_out1: endpoint { + remote-endpoint = <&adx3_out1>; + }; + }; + + port@4c { + reg = <0x4c>; + + xbar_adx3_out2: endpoint { + remote-endpoint = <&adx3_out2>; + }; + }; + + port@4d { + reg = <0x4d>; + + xbar_adx3_out3: endpoint { + remote-endpoint = <&adx3_out3>; + }; + }; + + port@4e { + reg = <0x4e>; + + xbar_adx3_out4: endpoint { + remote-endpoint = <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@4f { + reg = <0x4f>; + + xbar_adx4_in: endpoint { + remote-endpoint = <&adx4_in>; + }; + }; + + port@50 { + reg = <0x50>; + + xbar_adx4_out1: endpoint { + remote-endpoint = <&adx4_out1>; + }; + }; + + port@51 { + reg = <0x51>; + + xbar_adx4_out2: endpoint { + remote-endpoint = <&adx4_out2>; + }; + }; + + port@52 { + reg = <0x52>; + + xbar_adx4_out3: endpoint { + remote-endpoint = <&adx4_out3>; + }; + }; + + port@53 { + reg = <0x53>; + + xbar_adx4_out4: endpoint { + remote-endpoint = <&adx4_out4>; + }; + }; + + xbar_mix_in1_port: port@54 { + reg = <0x54>; + + xbar_mix_in1: endpoint { + remote-endpoint = <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@55 { + reg = <0x55>; + + xbar_mix_in2: endpoint { + remote-endpoint = <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@56 { + reg = <0x56>; + + xbar_mix_in3: endpoint { + remote-endpoint = <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@57 { + reg = <0x57>; + + xbar_mix_in4: endpoint { + remote-endpoint = <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@58 { + reg = <0x58>; + + xbar_mix_in5: endpoint { + remote-endpoint = <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@59 { + reg = <0x59>; + + xbar_mix_in6: endpoint { + remote-endpoint = <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@5a { + reg = <0x5a>; + + xbar_mix_in7: endpoint { + remote-endpoint = <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@5b { + reg = <0x5b>; + + xbar_mix_in8: endpoint { + remote-endpoint = <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@5c { + reg = <0x5c>; + + xbar_mix_in9: endpoint { + remote-endpoint = <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@5d { + reg = <0x5d>; + + xbar_mix_in10: endpoint { + remote-endpoint = <&mix_in10>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_mix_out1: endpoint { + remote-endpoint = <&mix_out1>; + }; + }; + + port@5f { + reg = <0x5f>; + + xbar_mix_out2: endpoint { + remote-endpoint = <&mix_out2>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_mix_out3: endpoint { + remote-endpoint = <&mix_out3>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_mix_out4: endpoint { + remote-endpoint = <&mix_out4>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_mix_out5: endpoint { + remote-endpoint = <&mix_out5>; + }; + }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; }; }; @@ -1461,6 +3539,14 @@ iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; status = "disabled"; + + snps,axi-config = <&mgbe0_axi_setup>; + + mgbe0_axi_setup: stmmac-axi-config { + snps,blen = <256 128 64 32>; + snps,rd_osr_lmt = <63>; + snps,wr_osr_lmt = <63>; + }; }; ethernet@6900000 { @@ -1495,6 +3581,14 @@ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; status = "disabled"; + + snps,axi-config = <&mgbe1_axi_setup>; + + mgbe1_axi_setup: stmmac-axi-config { + snps,blen = <256 128 64 32>; + snps,rd_osr_lmt = <63>; + snps,wr_osr_lmt = <63>; + }; }; ethernet@6a00000 { @@ -1529,6 +3623,14 @@ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; status = "disabled"; + + snps,axi-config = <&mgbe2_axi_setup>; + + mgbe2_axi_setup: stmmac-axi-config { + snps,blen = <256 128 64 32>; + snps,rd_osr_lmt = <63>; + snps,wr_osr_lmt = <63>; + }; }; ethernet@6b00000 { diff --git a/dts/src/arm64/qcom/apq8016-sbc-d3-camera-mezzanine.dts b/dts/src/arm64/qcom/apq8016-sbc-d3-camera-mezzanine.dts index c08b4be5cc..f9cbf8c1d6 100644 --- a/dts/src/arm64/qcom/apq8016-sbc-d3-camera-mezzanine.dts +++ b/dts/src/arm64/qcom/apq8016-sbc-d3-camera-mezzanine.dts @@ -9,7 +9,7 @@ #include "apq8016-sbc.dts" / { - camera_vdddo_1v8: camera-vdddo-1v8 { + camera_vdddo_1v8: regulator-camera-vdddo { compatible = "regulator-fixed"; regulator-name = "camera_vdddo"; regulator-min-microvolt = <1800000>; @@ -17,7 +17,7 @@ regulator-always-on; }; - camera_vdda_2v8: camera-vdda-2v8 { + camera_vdda_2v8: regulator-camera-vdda { compatible = "regulator-fixed"; regulator-name = "camera_vdda"; regulator-min-microvolt = <2800000>; @@ -25,7 +25,7 @@ regulator-always-on; }; - camera_vddd_1v5: camera-vddd-1v5 { + camera_vddd_1v5: regulator-camera-vddd { compatible = "regulator-fixed"; regulator-name = "camera_vddd"; regulator-min-microvolt = <1500000>; @@ -53,7 +53,7 @@ }; &cci_i2c0 { - camera_rear@3b { + camera@3b { compatible = "ovti,ov5640"; reg = <0x3b>; diff --git a/dts/src/arm64/qcom/ipq5332.dtsi b/dts/src/arm64/qcom/ipq5332.dtsi index 42e2e48b2b..770d9c2fb4 100644 --- a/dts/src/arm64/qcom/ipq5332.dtsi +++ b/dts/src/arm64/qcom/ipq5332.dtsi @@ -320,8 +320,12 @@ compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; reg = <0x08af8800 0x400>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>, + <GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; clocks = <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_SNOC_USB_CLK>, diff --git a/dts/src/arm64/qcom/ipq6018.dtsi b/dts/src/arm64/qcom/ipq6018.dtsi index 61c8fd49c9..4e29adea57 100644 --- a/dts/src/arm64/qcom/ipq6018.dtsi +++ b/dts/src/arm64/qcom/ipq6018.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,gcc-ipq6018.h> #include <dt-bindings/reset/qcom,gcc-ipq6018.h> #include <dt-bindings/clock/qcom,apss-ipq.h> +#include <dt-bindings/thermal/thermal.h> / { #address-cells = <2>; @@ -43,6 +44,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -55,6 +57,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -67,6 +70,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -79,6 +83,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq6018_s2>; + #cooling-cells = <2>; }; L2_0: l2-cache { @@ -330,6 +335,16 @@ clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens"; + reg = <0x0 0x004a9000 0x0 0x1000>, + <0x0 0x004a8000 0x0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + cryptobam: dma-controller@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x00704000 0x0 0x20000>; @@ -418,6 +433,12 @@ <&gcc GCC_USB1_MOCK_UTMI_CLK>; assigned-clock-rates = <133330000>, <24000000>; + + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy"; + resets = <&gcc GCC_USB1_BCR>; status = "disabled"; @@ -578,6 +599,21 @@ status = "disabled"; }; + blsp1_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x078ba000 0x0 0x600>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp_dma 22>, <&blsp_dma 23>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07984000 0x0 0x1a000>; @@ -630,6 +666,13 @@ <133330000>, <24000000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + resets = <&gcc GCC_USB0_BCR>; status = "disabled"; @@ -867,6 +910,122 @@ }; }; + thermal-zones { + nss-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 4>; + + trips { + nss-top-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nss-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 5>; + + trips { + nss-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wcss-phya0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 7>; + + trips { + wcss-phya0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wcss-phya1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 8>; + + trips { + wcss-phya1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 13>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_alert: cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + lpass-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 14>; + + trips { + lpass-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddrss-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 15>; + + trips { + ddrss-top-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/dts/src/arm64/qcom/ipq8074.dtsi b/dts/src/arm64/qcom/ipq8074.dtsi index 26441447c8..e5b89753aa 100644 --- a/dts/src/arm64/qcom/ipq8074.dtsi +++ b/dts/src/arm64/qcom/ipq8074.dtsi @@ -252,6 +252,8 @@ clocks = <&gcc GCC_MDIO_AHB_CLK>; clock-names = "gcc_mdio_ahb_clk"; + clock-frequency = <6250000>; + status = "disabled"; }; @@ -627,6 +629,13 @@ <133330000>, <19200000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + power-domains = <&gcc USB0_GDSC>; resets = <&gcc GCC_USB0_BCR>; @@ -669,6 +678,13 @@ <133330000>, <19200000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + power-domains = <&gcc USB1_GDSC>; resets = <&gcc GCC_USB1_BCR>; diff --git a/dts/src/arm64/qcom/ipq9574.dtsi b/dts/src/arm64/qcom/ipq9574.dtsi index 5f83ee42a7..7f2e5cbf3b 100644 --- a/dts/src/arm64/qcom/ipq9574.dtsi +++ b/dts/src/arm64/qcom/ipq9574.dtsi @@ -321,8 +321,10 @@ sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x07804000 0x1000>, <0x07805000 0x1000>; - reg-names = "hc", "cqhci"; + reg = <0x07804000 0x1000>, + <0x07805000 0x1000>, + <0x07808000 0x2000>; + reg-names = "hc", "cqhci", "ice"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -330,9 +332,11 @@ clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board_clk>; - clock-names = "iface", "core", "xo"; + <&xo_board_clk>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; non-removable; + supports-cqe; status = "disabled"; }; diff --git a/dts/src/arm64/qcom/msm8216-samsung-fortuna3g.dts b/dts/src/arm64/qcom/msm8216-samsung-fortuna3g.dts new file mode 100644 index 0000000000..366914be7d --- /dev/null +++ b/dts/src/arm64/qcom/msm8216-samsung-fortuna3g.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-fortuna-common.dtsi" + +/ { + model = "Samsung Galaxy Grand Prime (SM-G530H)"; + compatible = "samsung,fortuna3g", "qcom,msm8916"; + chassis-type = "handset"; +}; diff --git a/dts/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi b/dts/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi new file mode 100644 index 0000000000..c2800ad2dd --- /dev/null +++ b/dts/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85a00000 { + reg = <0x0 0x85a00000 0x0 0x600000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + button-home { + label = "Home"; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + }; + }; + + haptic { + compatible = "regulator-haptic"; + haptic-supply = <®_motor_vdd>; + min-microvolt = <3300000>; + max-microvolt = <3300000>; + }; + + reg_motor_vdd: regulator-motor-vdd { + compatible = "regulator-fixed"; + regulator-name = "motor_vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&motor_en_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c1 { + status = "okay"; + + muic: extcon@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&muic_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c4 { + status = "okay"; + + fuel-gauge@35 { + compatible = "richtek,rt5033-battery"; + reg = <0x35>; + + interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&fg_alert_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_uart2 { + status = "okay"; +}; + +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x5000000>; +}; + +&pm8916_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&sound { + model = "msm8916-1mic"; + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; +}; + +&venus { + status = "okay"; +}; + +&venus_mem { + status = "okay"; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +&tlmm { + fg_alert_default: fg-alert-default-state { + pins = "gpio121"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio109"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + motor_en_default: motor-en-default-state { + pins = "gpio72"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + muic_int_default: muic-int-default-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/dts/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts b/dts/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts new file mode 100644 index 0000000000..9d65fa58ba --- /dev/null +++ b/dts/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-fortuna-common.dtsi" + +/ { + model = "Samsung Galaxy Grand Prime (SM-G530W)"; + compatible = "samsung,gprimeltecan", "qcom,msm8916"; + chassis-type = "handset"; + + reserved-memory { + /* Firmware for gprimeltecan needs more space */ + /delete-node/ tz-apps@85a00000; + + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; +}; + +&mpss_mem { + /* Firmware for gprimeltecan needs more space */ + reg = <0x0 0x86800000 0x0 0x5400000>; +}; diff --git a/dts/src/arm64/qcom/msm8916-samsung-grandprimelte.dts b/dts/src/arm64/qcom/msm8916-samsung-grandprimelte.dts new file mode 100644 index 0000000000..a66ce4b135 --- /dev/null +++ b/dts/src/arm64/qcom/msm8916-samsung-grandprimelte.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-fortuna-common.dtsi" + +/ { + model = "Samsung Galaxy Grand Prime (SM-G530FZ)"; + compatible = "samsung,grandprimelte", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&mpss_mem { + /* Firmware for grandprimelte needs more space */ + reg = <0x0 0x86800000 0x0 0x5400000>; +}; diff --git a/dts/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi b/dts/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi new file mode 100644 index 0000000000..42843771ae --- /dev/null +++ b/dts/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-samsung-fortuna-common.dtsi" + +/* SM5504 MUIC instead of SM5502 */ +/delete-node/ &muic; + +&blsp_i2c1 { + muic: extcon@14 { + compatible = "siliconmitus,sm5504-muic"; + reg = <0x14>; + interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&muic_int_default>; + pinctrl-names = "default"; + }; +}; diff --git a/dts/src/arm64/qcom/msm8916-samsung-rossa.dts b/dts/src/arm64/qcom/msm8916-samsung-rossa.dts new file mode 100644 index 0000000000..ebaa13c6b0 --- /dev/null +++ b/dts/src/arm64/qcom/msm8916-samsung-rossa.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-rossa-common.dtsi" + +/ { + model = "Samsung Galaxy Core Prime LTE"; + compatible = "samsung,rossa", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&mpss_mem { + /* Firmware for rossa needs more space */ + reg = <0x0 0x86800000 0x0 0x5800000>; +}; diff --git a/dts/src/arm64/qcom/msm8916.dtsi b/dts/src/arm64/qcom/msm8916.dtsi index e423c57ddd..cedff4166b 100644 --- a/dts/src/arm64/qcom/msm8916.dtsi +++ b/dts/src/arm64/qcom/msm8916.dtsi @@ -1785,6 +1785,8 @@ power-domains = <&gcc OXILI_GDSC>; operating-points-v2 = <&gpu_opp_table>; iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + #cooling-cells = <2>; + status = "disabled"; gpu_opp_table: opp-table { @@ -2688,6 +2690,13 @@ thermal-sensors = <&tsens 2>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { gpu_alert0: trip-point0 { temperature = <75000>; diff --git a/dts/src/arm64/qcom/msm8939.dtsi b/dts/src/arm64/qcom/msm8939.dtsi index 82d85ff610..dd45975682 100644 --- a/dts/src/arm64/qcom/msm8939.dtsi +++ b/dts/src/arm64/qcom/msm8939.dtsi @@ -1427,6 +1427,8 @@ power-domains = <&gcc OXILI_GDSC>; operating-points-v2 = <&opp_table>; iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + #cooling-cells = <2>; + status = "disabled"; opp_table: opp-table { @@ -2456,6 +2458,13 @@ thermal-sensors = <&tsens 3>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { gpu_alert0: trip-point0 { temperature = <75000>; @@ -2463,7 +2472,7 @@ type = "passive"; }; - gpu_crit: gpu_crit { + gpu_crit: gpu-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; diff --git a/dts/src/arm64/qcom/msm8953.dtsi b/dts/src/arm64/qcom/msm8953.dtsi index ad2f8cf9c9..f1011bb641 100644 --- a/dts/src/arm64/qcom/msm8953.dtsi +++ b/dts/src/arm64/qcom/msm8953.dtsi @@ -859,6 +859,8 @@ "vsync", "core"; + resets = <&gcc GCC_MDSS_BCR>; + #address-cells = <1>; #size-cells = <1>; ranges; @@ -1044,6 +1046,125 @@ }; }; + gpu: gpu@1c00000 { + compatible = "qcom,adreno-506.0", "qcom,adreno"; + reg = <0x01c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GCC_OXILI_TIMER_CLK>, + <&gcc GCC_OXILI_AON_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "rbbmtimer", + "alwayson"; + power-domains = <&gcc OXILI_GX_GDSC>; + + iommus = <&gpu_iommu 0>; + operating-points-v2 = <&gpu_opp_table>; + + #cooling-cells = <2>; + + status = "disabled"; + + zap-shader { + memory-region = <&zap_shader_region>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-133300000 { + opp-hz = /bits/ 64 <133300000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-510000000 { + opp-hz = /bits/ 64 <510000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_nom_plus>; + }; + + /* + * This opp is only available on msm8953 and + * sdm632, the max for sdm450 is 600MHz. + */ + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + gpu_iommu: iommu@1c48000 { + compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2"; + ranges = <0 0x01c48000 0x8000>; + + clocks = <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>; + clock-names = "iface", "bus"; + + power-domains = <&gcc OXILI_CX_GDSC>; + + qcom,iommu-secure-id = <18>; + + #address-cells = <1>; + #iommu-cells = <1>; + #size-cells = <1>; + + /* gfx3d_user */ + iommu-ctx@0 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x0000 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* gfx3d_secure */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + apps_iommu: iommu@1e20000 { compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; ranges = <0 0x01e20000 0x20000>; @@ -1160,9 +1281,12 @@ #size-cells = <1>; ranges; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, @@ -2012,6 +2136,33 @@ }; }; }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 15>; + + trips { + gpu_alert: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; }; timer { diff --git a/dts/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi b/dts/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi index cbc84459a5..10cd244dea 100644 --- a/dts/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/dts/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi @@ -377,7 +377,7 @@ &blsp2_i2c1 { status = "okay"; - sideinteraction: ad7147_captouch@2c { + sideinteraction: touch@2c { compatible = "ad,ad7147_captouch"; reg = <0x2c>; diff --git a/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi b/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi index 9dbde79f26..0163d41f95 100644 --- a/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/dts/src/arm64/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -79,7 +79,7 @@ pmsg-size = <0x80000>; }; - fb_region: fb_region@40000000 { + fb_region: fb@40000000 { reg = <0 0x40000000 0 0x1000000>; no-map; }; diff --git a/dts/src/arm64/qcom/msm8994.dtsi b/dts/src/arm64/qcom/msm8994.dtsi index 8295bf1b21..695e541832 100644 --- a/dts/src/arm64/qcom/msm8994.dtsi +++ b/dts/src/arm64/qcom/msm8994.dtsi @@ -233,7 +233,7 @@ #size-cells = <2>; ranges; - dfps_data_mem: dfps_data_mem@3400000 { + dfps_data_mem: dfps-data@3400000 { reg = <0 0x03400000 0 0x1000>; no-map; }; @@ -243,7 +243,7 @@ no-map; }; - smem_mem: smem_region@6a00000 { + smem_mem: smem@6a00000 { reg = <0 0x06a00000 0 0x200000>; no-map; }; diff --git a/dts/src/arm64/qcom/msm8996.dtsi b/dts/src/arm64/qcom/msm8996.dtsi index ee6f87c828..1601e46549 100644 --- a/dts/src/arm64/qcom/msm8996.dtsi +++ b/dts/src/arm64/qcom/msm8996.dtsi @@ -756,12 +756,12 @@ #address-cells = <1>; #size-cells = <1>; - qusb2p_hstx_trim: hstx_trim@24e { + qusb2p_hstx_trim: hstx-trim@24e { reg = <0x24e 0x2>; bits = <5 4>; }; - qusb2s_hstx_trim: hstx_trim@24f { + qusb2s_hstx_trim: hstx-trim@24f { reg = <0x24f 0x1>; bits = <1 4>; }; @@ -2077,7 +2077,7 @@ <0 0>, <0 0>, <150000000 300000000>, - <0 0>, + <75000000 150000000>, <0 0>, <0 0>, <0 0>, @@ -2096,8 +2096,8 @@ compatible = "qcom,msm8996-qmp-ufs-phy"; reg = <0x00627000 0x1000>; - clocks = <&gcc GCC_UFS_CLKREF_CLK>; - clock-names = "ref"; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref", "qref"; resets = <&ufshc 0>; reset-names = "ufsphy"; @@ -3381,8 +3381,12 @@ #size-cells = <1>; ranges; - interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq"; clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, <&gcc GCC_USB20_MASTER_CLK>, diff --git a/dts/src/arm64/qcom/msm8998.dtsi b/dts/src/arm64/qcom/msm8998.dtsi index 2793cc22d3..4dfe2d09ac 100644 --- a/dts/src/arm64/qcom/msm8998.dtsi +++ b/dts/src/arm64/qcom/msm8998.dtsi @@ -1047,12 +1047,12 @@ compatible = "qcom,msm8998-qmp-ufs-phy"; reg = <0x01da7000 0x1000>; - clock-names = - "ref", - "ref_aux"; - clocks = - <&gcc GCC_UFS_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_AUX_CLK>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>, + <&gcc GCC_UFS_PHY_AUX_CLK>, + <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; reset-names = "ufsphy"; resets = <&ufshc 0>; @@ -1072,6 +1072,11 @@ reg = <0x01f60000 0x20000>; }; + tcsr_regs_2: syscon@1fc0000 { + compatible = "qcom,msm8998-tcsr", "syscon"; + reg = <0x01fc0000 0x26000>; + }; + tlmm: pinctrl@3400000 { compatible = "qcom,msm8998-pinctrl"; reg = <0x03400000 0xc00000>; @@ -2132,9 +2137,12 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; - interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; power-domains = <&gcc USB_30_GDSC>; @@ -2174,6 +2182,8 @@ reset-names = "phy", "phy_phy"; + qcom,tcsr-reg = <&tcsr_regs_2 0xb244>; + status = "disabled"; }; diff --git a/dts/src/arm64/qcom/pm2250.dtsi b/dts/src/arm64/qcom/pm4125.dtsi index 5f1d15db5c..cf8c822e80 100644 --- a/dts/src/arm64/qcom/pm2250.dtsi +++ b/dts/src/arm64/qcom/pm4125.dtsi @@ -19,7 +19,7 @@ compatible = "qcom,pm8916-pon"; reg = <0x800>; - pm2250_pwrkey: pwrkey { + pm4125_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; interrupts-extended = <&spmi_bus 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; linux,code = <KEY_POWER>; @@ -27,7 +27,7 @@ bias-pull-up; }; - pm2250_resin: resin { + pm4125_resin: resin { compatible = "qcom,pm8941-resin"; interrupts-extended = <&spmi_bus 0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; @@ -36,6 +36,36 @@ }; }; + pm4125_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pm4125-vbus-reg", "qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pm4125_typec: typec@1500 { + compatible = "qcom,pm4125-typec", "qcom,pmi632-typec"; + reg = <0x1500>; + interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x07 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect"; + vdd-vbus-supply = <&pm4125_vbus>; + + status = "disabled"; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>, <0x6100>; @@ -43,11 +73,11 @@ interrupts-extended = <&spmi_bus 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; - pm2250_gpios: gpio@c000 { + pm4125_gpios: gpio@c000 { compatible = "qcom,pm2250-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm2250_gpios 0 0 10>; + gpio-ranges = <&pm4125_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/dts/src/arm64/qcom/pm6150.dtsi b/dts/src/arm64/qcom/pm6150.dtsi index ddbaf7280b..11158c2bd5 100644 --- a/dts/src/arm64/qcom/pm6150.dtsi +++ b/dts/src/arm64/qcom/pm6150.dtsi @@ -63,6 +63,52 @@ }; }; + pm6150_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pm6150-vbus-reg, + qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pm6150_typec: typec@1500 { + compatible = "qcom,pm6150-typec, + qcom,pm8150b-typec"; + reg = <0x1500>, <0x1700>; + interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x07 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x01 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x03 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x06 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x07 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect", + "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + status = "disabled"; + }; + pm6150_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; diff --git a/dts/src/arm64/qcom/pmi632.dtsi b/dts/src/arm64/qcom/pmi632.dtsi index 4eb79e0ce4..94d53b1cf6 100644 --- a/dts/src/arm64/qcom/pmi632.dtsi +++ b/dts/src/arm64/qcom/pmi632.dtsi @@ -45,6 +45,36 @@ #address-cells = <1>; #size-cells = <0>; + pmi632_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pmi632-vbus-reg", "qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pmi632_typec: typec@1500 { + compatible = "qcom,pmi632-typec"; + reg = <0x1500>; + interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x07 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect"; + vdd-vbus-supply = <&pmi632_vbus>; + + status = "disabled"; + }; + pmi632_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; @@ -127,6 +157,11 @@ status = "disabled"; }; + pmi632_pbs_client3: pbs@7400 { + compatible = "qcom,pmi632-pbs", "qcom,pbs"; + reg = <0x7400>; + }; + pmi632_sdam_7: nvram@b600 { compatible = "qcom,spmi-sdam"; reg = <0xb600>; @@ -155,6 +190,10 @@ pmi632_lpg: pwm { compatible = "qcom,pmi632-lpg"; + nvmem = <&pmi632_sdam_7>; + nvmem-names = "lpg_chan_sdam"; + qcom,pbs = <&pmi632_pbs_client3>; + #address-cells = <1>; #size-cells = <0>; #pwm-cells = <2>; diff --git a/dts/src/arm64/qcom/qcm2290.dtsi b/dts/src/arm64/qcom/qcm2290.dtsi index 0911fb08ed..89beac833d 100644 --- a/dts/src/arm64/qcom/qcm2290.dtsi +++ b/dts/src/arm64/qcom/qcm2290.dtsi @@ -442,6 +442,11 @@ #hwlock-cells = <1>; }; + tcsr_regs: syscon@3c0000 { + compatible = "qcom,qcm2290-tcsr", "syscon"; + reg = <0x0 0x003c0000 0x0 0x40000>; + }; + tlmm: pinctrl@500000 { compatible = "qcom,qcm2290-tlmm"; reg = <0x0 0x00500000 0x0 0x300000>; @@ -690,6 +695,8 @@ #phy-cells = <0>; + qcom,tcsr-reg = <&tcsr_regs 0xb244>; + status = "disabled"; }; diff --git a/dts/src/arm64/qcom/qcm6490-fairphone-fp5.dts b/dts/src/arm64/qcom/qcm6490-fairphone-fp5.dts index 176898c9db..4ff9fc24e5 100644 --- a/dts/src/arm64/qcom/qcm6490-fairphone-fp5.dts +++ b/dts/src/arm64/qcom/qcm6490-fairphone-fp5.dts @@ -71,6 +71,41 @@ }; }; + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + reserved-memory { cont_splash_mem: cont-splash@e1000000 { reg = <0x0 0xe1000000 0x0 0x2300000>; @@ -82,6 +117,11 @@ no-map; }; + removed_mem: removed@c0000000 { + reg = <0x0 0xc0000000 0x0 0x5100000>; + no-map; + }; + rmtfs_mem: memory@f8500000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0xf8500000 0x0 0x600000>; @@ -886,7 +926,16 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { @@ -915,6 +964,11 @@ status = "okay"; }; +&venus { + firmware-name = "qcom/qcm6490/fairphone5/venus.mbn"; + status = "okay"; +}; + &wifi { qcom,ath11k-calibration-variant = "Fairphone_5"; status = "okay"; diff --git a/dts/src/arm64/qcom/qcm6490-idp.dts b/dts/src/arm64/qcom/qcm6490-idp.dts index 03e97e27d1..e4bfad50a6 100644 --- a/dts/src/arm64/qcom/qcm6490-idp.dts +++ b/dts/src/arm64/qcom/qcm6490-idp.dts @@ -5,8 +5,14 @@ /dts-v1/; +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sc7280.dtsi" +#include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" @@ -109,7 +115,7 @@ no-map; }; - trusted_apps_mem: trusted_apps@c1800000 { + trusted_apps_mem: trusted-apps@c1800000 { reg = <0x0 0xc1800000 0x0 0x1c00000>; no-map; }; @@ -123,8 +129,8 @@ vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <4350000>; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; }; }; @@ -415,6 +421,33 @@ }; }; +&pm8350c_pwm { + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_RED>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + }; + }; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/dts/src/arm64/qcom/qcs404.dtsi b/dts/src/arm64/qcom/qcs404.dtsi index 2f2eeaf2e9..a05d0234f7 100644 --- a/dts/src/arm64/qcom/qcs404.dtsi +++ b/dts/src/arm64/qcom/qcs404.dtsi @@ -675,6 +675,14 @@ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; + + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "qusb2_phy"; + status = "disabled"; usb3_dwc3: usb@7580000 { @@ -704,6 +712,14 @@ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; assigned-clock-rates = <19200000>, <133333333>; + + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "qusb2_phy"; + status = "disabled"; usb@78c0000 { diff --git a/dts/src/arm64/qcom/qcs6490-rb3gen2.dts b/dts/src/arm64/qcom/qcs6490-rb3gen2.dts index 8bb7d13d85..97824c769b 100644 --- a/dts/src/arm64/qcom/qcs6490-rb3gen2.dts +++ b/dts/src/arm64/qcom/qcs6490-rb3gen2.dts @@ -110,7 +110,7 @@ no-map; }; - trusted_apps_mem: trusted_apps@c1800000 { + trusted_apps_mem: trusted-apps@c1800000 { reg = <0x0 0xc1800000 0x0 0x1c00000>; no-map; }; @@ -124,8 +124,8 @@ vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <4350000>; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; }; }; @@ -413,6 +413,23 @@ }; }; +&gcc { + protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, + <GCC_MSS_CFG_AHB_CLK>, + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, + <GCC_MSS_OFFLINE_AXI_CLK>, + <GCC_MSS_Q6SS_BOOT_CLK_SRC>, + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <GCC_MSS_SNOC_AXI_CLK>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_SEC_CTRL_CLK_SRC>, + <GCC_WPSS_AHB_BDG_MST_CLK>, + <GCC_WPSS_AHB_CLK>, + <GCC_WPSS_RSCP_CLK>; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/dts/src/arm64/qcom/qrb2210-rb1.dts b/dts/src/arm64/qcom/qrb2210-rb1.dts index aa53b6af6d..6e9dd0312a 100644 --- a/dts/src/arm64/qcom/qrb2210-rb1.dts +++ b/dts/src/arm64/qcom/qrb2210-rb1.dts @@ -7,7 +7,7 @@ #include <dt-bindings/leds/common.h> #include "qcm2290.dtsi" -#include "pm2250.dtsi" +#include "pm4125.dtsi" / { model = "Qualcomm Technologies, Inc. Robotics RB1"; @@ -177,6 +177,24 @@ }; }; +&CPU_PD0 { + /delete-property/ power-domains; +}; + +&CPU_PD1 { + /delete-property/ power-domains; +}; + +&CPU_PD2 { + /delete-property/ power-domains; +}; + +&CPU_PD3 { + /delete-property/ power-domains; +}; + +/delete-node/ &CLUSTER_PD; + &gpi_dma0 { status = "okay"; }; @@ -226,7 +244,7 @@ }; &mdss_dsi0 { - vdda-supply = <&pm2250_l5>; + vdda-supply = <&pm4125_l5>; status = "okay"; }; @@ -239,7 +257,7 @@ status = "okay"; }; -&pm2250_resin { +&pm4125_resin { linux,code = <KEY_VOLUMEDOWN>; status = "okay"; }; @@ -263,23 +281,23 @@ compatible = "qcom,rpm-pm2250-regulators"; vdd_s3-supply = <&vph_pwr>; vdd_s4-supply = <&vph_pwr>; - vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm2250_s3>; + vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm4125_s3>; vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>; - vdd_l13_l14_l15_l16-supply = <&pm2250_s4>; + vdd_l13_l14_l15_l16-supply = <&pm4125_s4>; /* * S1 - VDD_APC * S2 - VDD_CX */ - pm2250_s3: s3 { + pm4125_s3: s3 { /* 0.4V-1.6625V -> 1.3V (Power tree requirements) */ regulator-min-microvolt = <1352000>; regulator-max-microvolt = <1352000>; regulator-boot-on; }; - pm2250_s4: s4 { + pm4125_s4: s4 { /* 1.2V-2.35V -> 2.05V (Power tree requirements) */ regulator-min-microvolt = <2072000>; regulator-max-microvolt = <2072000>; @@ -288,7 +306,7 @@ /* L1 - VDD_MX */ - pm2250_l2: l2 { + pm4125_l2: l2 { /* LPDDR4X VDD2 */ regulator-min-microvolt = <1136000>; regulator-max-microvolt = <1136000>; @@ -296,7 +314,7 @@ regulator-boot-on; }; - pm2250_l3: l3 { + pm4125_l3: l3 { /* LPDDR4X VDDQ */ regulator-min-microvolt = <616000>; regulator-max-microvolt = <616000>; @@ -304,14 +322,14 @@ regulator-boot-on; }; - pm2250_l4: l4 { + pm4125_l4: l4 { /* max = 3.05V -> max = 2.7 to disable 3V signaling (SDHCI2) */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2700000>; regulator-allow-set-load; }; - pm2250_l5: l5 { + pm4125_l5: l5 { /* CSI/DSI */ regulator-min-microvolt = <1232000>; regulator-max-microvolt = <1232000>; @@ -319,7 +337,7 @@ regulator-boot-on; }; - pm2250_l6: l6 { + pm4125_l6: l6 { /* DRAM PLL */ regulator-min-microvolt = <928000>; regulator-max-microvolt = <928000>; @@ -327,7 +345,7 @@ regulator-boot-on; }; - pm2250_l7: l7 { + pm4125_l7: l7 { /* Wi-Fi CX/MX */ regulator-min-microvolt = <664000>; regulator-max-microvolt = <664000>; @@ -338,20 +356,20 @@ * L9 - VDD_LPI_MX */ - pm2250_l10: l10 { + pm4125_l10: l10 { /* Wi-Fi RFA */ regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; }; - pm2250_l11: l11 { + pm4125_l11: l11 { /* GPS RF1 */ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; }; - pm2250_l12: l12 { + pm4125_l12: l12 { /* USB PHYs */ regulator-min-microvolt = <928000>; regulator-max-microvolt = <928000>; @@ -359,7 +377,7 @@ regulator-boot-on; }; - pm2250_l13: l13 { + pm4125_l13: l13 { /* USB/QFPROM/PLLs */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -367,7 +385,7 @@ regulator-boot-on; }; - pm2250_l14: l14 { + pm4125_l14: l14 { /* SDHCI1 VQMMC */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -376,7 +394,7 @@ regulator-always-on; }; - pm2250_l15: l15 { + pm4125_l15: l15 { /* WCD/DSI/BT VDDIO */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -385,38 +403,38 @@ regulator-boot-on; }; - pm2250_l16: l16 { + pm4125_l16: l16 { /* GPS RF2 */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; }; - pm2250_l17: l17 { + pm4125_l17: l17 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; - pm2250_l18: l18 { + pm4125_l18: l18 { /* VDD_PXn */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - pm2250_l19: l19 { + pm4125_l19: l19 { /* VDD_PXn */ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - pm2250_l20: l20 { + pm4125_l20: l20 { /* SDHCI1 VMMC */ regulator-min-microvolt = <2400000>; regulator-max-microvolt = <3600000>; regulator-allow-set-load; }; - pm2250_l21: l21 { + pm4125_l21: l21 { /* SDHCI2 VMMC */ regulator-min-microvolt = <2960000>; regulator-max-microvolt = <3300000>; @@ -424,7 +442,7 @@ regulator-boot-on; }; - pm2250_l22: l22 { + pm4125_l22: l22 { /* Wi-Fi */ regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3312000>; @@ -433,8 +451,8 @@ }; &sdhc_1 { - vmmc-supply = <&pm2250_l20>; - vqmmc-supply = <&pm2250_l14>; + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; pinctrl-names = "default", "sleep"; @@ -446,8 +464,8 @@ }; &sdhc_2 { - vmmc-supply = <&pm2250_l21>; - vqmmc-supply = <&pm2250_l4>; + vmmc-supply = <&pm4125_l21>; + vqmmc-supply = <&pm4125_l4>; cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; pinctrl-0 = <&sdc2_state_on &sd_det_in_on>; pinctrl-1 = <&sdc2_state_off &sd_det_in_off>; @@ -518,8 +536,8 @@ }; &usb_qmpphy { - vdda-phy-supply = <&pm2250_l12>; - vdda-pll-supply = <&pm2250_l13>; + vdda-phy-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; status = "okay"; }; @@ -528,17 +546,17 @@ }; &usb_hsphy { - vdd-supply = <&pm2250_l12>; - vdda-pll-supply = <&pm2250_l13>; - vdda-phy-dpdm-supply = <&pm2250_l21>; + vdd-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + vdda-phy-dpdm-supply = <&pm4125_l21>; status = "okay"; }; &wifi { - vdd-0.8-cx-mx-supply = <&pm2250_l7>; - vdd-1.8-xo-supply = <&pm2250_l13>; - vdd-1.3-rfa-supply = <&pm2250_l10>; - vdd-3.3-ch0-supply = <&pm2250_l22>; + vdd-0.8-cx-mx-supply = <&pm4125_l7>; + vdd-1.8-xo-supply = <&pm4125_l13>; + vdd-1.3-rfa-supply = <&pm4125_l10>; + vdd-3.3-ch0-supply = <&pm4125_l22>; qcom,ath10k-calibration-variant = "Thundercomm_RB1"; status = "okay"; }; diff --git a/dts/src/arm64/qcom/qrb4210-rb2.dts b/dts/src/arm64/qcom/qrb4210-rb2.dts index 7c19f874fa..696d6d43c5 100644 --- a/dts/src/arm64/qcom/qrb4210-rb2.dts +++ b/dts/src/arm64/qcom/qrb4210-rb2.dts @@ -6,8 +6,10 @@ /dts-v1/; #include <dt-bindings/leds/common.h> +#include <dt-bindings/usb/pd.h> #include "sm4250.dtsi" #include "pm6125.dtsi" +#include "pmi632.dtsi" / { model = "Qualcomm Technologies, Inc. QRB4210 RB2"; @@ -256,6 +258,46 @@ }; }; +&pmi632_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pmi632_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + pmi632_ss_in: endpoint { + remote-endpoint = <&usb_qmpphy_out>; + }; + }; + }; + }; +}; + +&pmi632_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; @@ -607,8 +649,8 @@ status = "okay"; }; -&usb_dwc3 { - maximum-speed = "super-speed"; +&usb_dwc3_hs { + remote-endpoint = <&pmi632_hs_in>; }; &usb_hsphy { @@ -626,6 +668,10 @@ status = "okay"; }; +&usb_qmpphy_out { + remote-endpoint = <&pmi632_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>; vdd-1.8-xo-supply = <&vreg_l16a_1p3>; diff --git a/dts/src/arm64/qcom/sa8295p-adp.dts b/dts/src/arm64/qcom/sa8295p-adp.dts index fd253942e5..78e933c42c 100644 --- a/dts/src/arm64/qcom/sa8295p-adp.dts +++ b/dts/src/arm64/qcom/sa8295p-adp.dts @@ -108,6 +108,13 @@ }; }; }; + + reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + }; }; &apps_rsc { @@ -266,6 +273,48 @@ status = "okay"; }; +&i2c12 { + pinctrl-0 = <&qup1_i2c4_state>; + pinctrl-names = "default"; + + status = "okay"; + + vdd_gfx: regulator@39 { + compatible = "maxim,max20411"; + reg = <0x39>; + + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + + enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&max20411_en>; + pinctrl-names = "default"; + }; +}; + +&gpucc { + vdd-gfx-supply = <&vdd_gfx>; + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sa8295p/a690_zap.mbn"; + }; +}; + +&gpu_smmu { + status = "okay"; +}; + &mdss0 { status = "okay"; }; @@ -476,6 +525,10 @@ status = "okay"; }; +&qup1 { + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -636,6 +689,14 @@ /* PINCTRL */ +&pmm8540a_gpios { + max20411_en: max20411-en-state { + pins = "gpio2"; + function = "normal"; + output-enable; + }; +}; + &tlmm { pcie2a_default: pcie2a-default-state { clkreq-n-pins { @@ -728,4 +789,11 @@ bias-pull-up; }; }; + + qup1_i2c4_state: qup1-i2c4-state { + pins = "gpio0", "gpio1"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; }; diff --git a/dts/src/arm64/qcom/sa8540p-ride.dts b/dts/src/arm64/qcom/sa8540p-ride.dts index b04f72ec09..177b9dad6f 100644 --- a/dts/src/arm64/qcom/sa8540p-ride.dts +++ b/dts/src/arm64/qcom/sa8540p-ride.dts @@ -376,14 +376,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; - status = "okay"; + status = "disabled"; }; &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; - status = "okay"; + status = "disabled"; }; &pcie3a { diff --git a/dts/src/arm64/qcom/sa8540p.dtsi b/dts/src/arm64/qcom/sa8540p.dtsi index 96b2c59ad0..23888029cc 100644 --- a/dts/src/arm64/qcom/sa8540p.dtsi +++ b/dts/src/arm64/qcom/sa8540p.dtsi @@ -168,6 +168,9 @@ }; &gpucc { + /* SA8295P and SA8540P doesn't provide gfx.lvl */ + /delete-property/ power-domains; + status = "disabled"; }; diff --git a/dts/src/arm64/qcom/sa8775p.dtsi b/dts/src/arm64/qcom/sa8775p.dtsi index a7eaca33d3..231cea1f0f 100644 --- a/dts/src/arm64/qcom/sa8775p.dtsi +++ b/dts/src/arm64/qcom/sa8775p.dtsi @@ -356,13 +356,18 @@ no-map; }; + ddr_training_checksum: ddr-training-checksum@908c0000 { + reg = <0x0 0x908c0000 0x0 0x1000>; + no-map; + }; + reserved_mem: reserved@908f0000 { - reg = <0x0 0x908f0000 0x0 0xf000>; + reg = <0x0 0x908f0000 0x0 0xe000>; no-map; }; - secdata_apss_mem: secdata-apss@908ff000 { - reg = <0x0 0x908ff000 0x0 0x1000>; + secdata_apss_mem: secdata-apss@908fe000 { + reg = <0x0 0x908fe000 0x0 0x2000>; no-map; }; @@ -373,8 +378,43 @@ hwlocks = <&tcsr_mutex 3>; }; - cpucp_fw_mem: cpucp-fw@90b00000 { - reg = <0x0 0x90b00000 0x0 0x100000>; + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg = <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg = <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg = <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + + aoss_backup_mem: aoss-backup@91b00000 { + reg = <0x0 0x91b00000 0x0 0x40000>; + no-map; + }; + + cpucp_backup_mem: cpucp-backup@91b40000 { + reg = <0x0 0x91b40000 0x0 0x40000>; + no-map; + }; + + tz_config_backup_mem: tz-config-backup@91b80000 { + reg = <0x0 0x91b80000 0x0 0x10000>; + no-map; + }; + + ddr_training_data_mem: ddr-training-data@91b90000 { + reg = <0x0 0x91b90000 0x0 0x10000>; + no-map; + }; + + cdt_data_backup_mem: cdt-data-backup@91ba0000 { + reg = <0x0 0x91ba0000 0x0 0x1000>; no-map; }; @@ -433,13 +473,43 @@ no-map; }; + audio_mdf_mem: audio-mdf-region@ae000000 { + reg = <0x0 0xae000000 0x0 0x1000000>; + no-map; + }; + + firmware_mem: firmware-region@b0000000 { + reg = <0x0 0xb0000000 0x0 0x800000>; + no-map; + }; + hyptz_reserved_mem: hyptz-reserved@beb00000 { reg = <0x0 0xbeb00000 0x0 0x11500000>; no-map; }; - tz_stat_mem: tz-stat@d0000000 { - reg = <0x0 0xd0000000 0x0 0x100000>; + scmi_mem: scmi-region@d0000000 { + reg = <0x0 0xd0000000 0x0 0x40000>; + no-map; + }; + + firmware_logs_mem: firmware-logs@d0040000 { + reg = <0x0 0xd0040000 0x0 0x10000>; + no-map; + }; + + firmware_audio_mem: firmware-audio@d0050000 { + reg = <0x0 0xd0050000 0x0 0x4000>; + no-map; + }; + + firmware_reserved_mem: firmware-reserved@d0054000 { + reg = <0x0 0xd0054000 0x0 0x9c000>; + no-map; + }; + + firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { + reg = <0x0 0xd00f0000 0x0 0x10000>; no-map; }; @@ -453,8 +523,23 @@ no-map; }; - trusted_apps_mem: trusted-apps@d1800000 { - reg = <0x0 0xd1800000 0x0 0x3900000>; + deepsleep_backup_mem: deepsleep-backup@d1800000 { + reg = <0x0 0xd1800000 0x0 0x100000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg = <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + + tz_stat_mem: tz-stat@db100000 { + reg = <0x0 0xdb100000 0x0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@db200000 { + reg = <0x0 0xdb200000 0x0 0x100000>; no-map; }; }; @@ -1615,10 +1700,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -1702,10 +1789,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 7 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -1765,9 +1854,11 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -2394,8 +2485,9 @@ <0x0 0x23016000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; + interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "sfty"; clocks = <&gcc GCC_EMAC1_AXI_CLK>, <&gcc GCC_EMAC1_SLV_AHB_CLK>, @@ -2427,8 +2519,9 @@ <0x0 0x23056000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; + interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "sfty"; clocks = <&gcc GCC_EMAC0_AXI_CLK>, <&gcc GCC_EMAC0_SLV_AHB_CLK>, diff --git a/dts/src/arm64/qcom/sc7180-trogdor.dtsi b/dts/src/arm64/qcom/sc7180-trogdor.dtsi index 46aaeba286..5260c63db0 100644 --- a/dts/src/arm64/qcom/sc7180-trogdor.dtsi +++ b/dts/src/arm64/qcom/sc7180-trogdor.dtsi @@ -649,6 +649,7 @@ ap_ec_spi: &spi6 { pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; @@ -943,6 +944,8 @@ ap_spi_fp: &spi10 { vddrf-supply = <&pp1300_l2c>; vddch0-supply = <&pp3300_l10c>; max-speed = <3200000>; + + qcom,local-bd-address-broken; }; }; diff --git a/dts/src/arm64/qcom/sc7180.dtsi b/dts/src/arm64/qcom/sc7180.dtsi index 4dcaa15cae..2b481e20ae 100644 --- a/dts/src/arm64/qcom/sc7180.dtsi +++ b/dts/src/arm64/qcom/sc7180.dtsi @@ -817,7 +817,7 @@ bits = <1 3>; }; - gpu_speed_bin: gpu_speed_bin@1d2 { + gpu_speed_bin: gpu-speed-bin@1d2 { reg = <0x1d2 0x2>; bits = <5 8>; }; @@ -1532,6 +1532,76 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sc7180-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xa0 0x0>; + + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ice = <&ice>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sc7180-qmp-ufs-phy", + "qcom,sm7150-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1000>; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + #phy-cells = <0>; + status = "disabled"; + }; + + ice: crypto@1d90000 { + compatible = "qcom,sc7180-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + ipa: ipa@1e40000 { compatible = "qcom,sc7180-ipa"; @@ -2964,12 +3034,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; diff --git a/dts/src/arm64/qcom/sc7280-chrome-common.dtsi b/dts/src/arm64/qcom/sc7280-chrome-common.dtsi index c4d00a81da..cecb3e89f7 100644 --- a/dts/src/arm64/qcom/sc7280-chrome-common.dtsi +++ b/dts/src/arm64/qcom/sc7280-chrome-common.dtsi @@ -18,6 +18,7 @@ */ /delete-node/ &cdsp_mem; +/delete-node/ &domain_idle_states; /delete-node/ &gpu_zap_mem; /delete-node/ &gpu_zap_shader; /delete-node/ &hyp_mem; @@ -26,6 +27,18 @@ /delete-node/ &sec_apps_mem; / { + cpus { + domain_idle_states: domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x40003444>; + entry-latency-us = <2752>; + exit-latency-us = <6562>; + min-residency-us = <9926>; + }; + }; + }; + reserved-memory { camera_mem: memory@8ad00000 { reg = <0x0 0x8ad00000 0x0 0x500000>; @@ -39,6 +52,10 @@ }; }; +&CLUSTER_PD { + domain-idle-states = <&CLUSTER_SLEEP_0>; +}; + &lpass_aon { status = "okay"; }; @@ -119,6 +136,17 @@ dma-coherent; }; +&venus { + iommus = <&apps_smmu 0x2180 0x20>, + <&apps_smmu 0x2184 0x20>; + + status = "okay"; + + video-firmware { + iommus = <&apps_smmu 0x21a2 0x0>; + }; +}; + &watchdog { status = "okay"; }; diff --git a/dts/src/arm64/qcom/sc7280-herobrine.dtsi b/dts/src/arm64/qcom/sc7280-herobrine.dtsi index 9ea6636125..2ba4ea60cb 100644 --- a/dts/src/arm64/qcom/sc7280-herobrine.dtsi +++ b/dts/src/arm64/qcom/sc7280-herobrine.dtsi @@ -548,6 +548,7 @@ ap_ec_spi: &spi10 { pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/dts/src/arm64/qcom/sc7280-idp-ec-h1.dtsi b/dts/src/arm64/qcom/sc7280-idp-ec-h1.dtsi index ebae545c58..fbfac7534d 100644 --- a/dts/src/arm64/qcom/sc7280-idp-ec-h1.dtsi +++ b/dts/src/arm64/qcom/sc7280-idp-ec-h1.dtsi @@ -19,6 +19,7 @@ ap_ec_spi: &spi10 { pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/dts/src/arm64/qcom/sc7280.dtsi b/dts/src/arm64/qcom/sc7280.dtsi index 83b5b76ba1..7e7f0f0fb4 100644 --- a/dts/src/arm64/qcom/sc7280.dtsi +++ b/dts/src/arm64/qcom/sc7280.dtsi @@ -202,6 +202,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_0>; operating-points-v2 = <&cpu0_opp_table>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -229,6 +231,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_100>; operating-points-v2 = <&cpu0_opp_table>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -251,6 +255,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_200>; operating-points-v2 = <&cpu0_opp_table>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -273,6 +279,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_300>; operating-points-v2 = <&cpu0_opp_table>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -295,6 +303,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_400>; operating-points-v2 = <&cpu4_opp_table>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -317,6 +327,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_500>; operating-points-v2 = <&cpu4_opp_table>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -339,6 +351,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_600>; operating-points-v2 = <&cpu4_opp_table>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <520>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -361,6 +375,8 @@ power-domain-names = "psci"; next-level-cache = <&L2_700>; operating-points-v2 = <&cpu7_opp_table>; + capacity-dmips-mhz = <1985>; + dynamic-power-coefficient = <552>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 2>; @@ -453,15 +469,29 @@ }; }; - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + domain_idle_states: domain-idle-states { + CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x40003444>; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001344>; entry-latency-us = <3263>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + }; + + CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b344>; + entry-latency-us = <3638>; exit-latency-us = <6562>; - min-residency-us = <9926>; - local-timer-stop; + min-residency-us = <9826>; }; }; }; @@ -872,7 +902,7 @@ CLUSTER_PD: power-domain-cluster { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; + domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &CLUSTER_SLEEP_LLCC_OFF>; }; }; @@ -966,7 +996,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@1e9 { + gpu_speed_bin: gpu-speed-bin@1e9 { reg = <0x1e9 0x2>; bits = <5 8>; }; @@ -2178,8 +2208,16 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, @@ -2345,6 +2383,8 @@ <&apps_smmu 0x4e6 0x0011>; qcom,ee = <0>; qcom,controlled-remotely; + num-channels = <16>; + qcom,num-ees = <4>; }; crypto: crypto@1dfa000 { @@ -2648,6 +2688,31 @@ status = "disabled"; }; + slimbam: dma-controller@3a84000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0 0x03a84000 0 0x20000>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,controlled-remotely; + num-channels = <31>; + qcom,ee = <1>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x1826 0x0>; + status = "disabled"; + }; + + slim: slim-ngd@3ac0000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0 0x03ac0000 0 0x2c000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x1826 0x0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + lpass_hm: clock-controller@3c00000 { compatible = "qcom,sc7280-lpasshm"; reg = <0 0x03c00000 0 0x28>; @@ -3582,10 +3647,12 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", + interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -4035,11 +4102,13 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", + interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -4065,6 +4134,25 @@ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; }; @@ -4091,10 +4179,11 @@ <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "cpu-cfg", "video-mem"; - iommus = <&apps_smmu 0x2180 0x20>, - <&apps_smmu 0x2184 0x20>; + iommus = <&apps_smmu 0x2180 0x20>; memory-region = <&video_mem>; + status = "disabled"; + video-decoder { compatible = "venus-decoder"; }; @@ -4103,10 +4192,6 @@ compatible = "venus-encoder"; }; - video-firmware { - iommus = <&apps_smmu 0x21a2 0x0>; - }; - venus_opp_table: opp-table { compatible = "operating-points-v2"; diff --git a/dts/src/arm64/qcom/sc8180x.dtsi b/dts/src/arm64/qcom/sc8180x.dtsi index 0430d99091..32afc78d5b 100644 --- a/dts/src/arm64/qcom/sc8180x.dtsi +++ b/dts/src/arm64/qcom/sc8180x.dtsi @@ -290,7 +290,7 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <241>; + entry-latency-us = <2411>; exit-latency-us = <1461>; min-residency-us = <4488>; local-timer-stop; @@ -298,7 +298,15 @@ }; domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <3300>; + exit-latency-us = <3300>; + min-residency-us = <6000>; + }; + + CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100a344>; entry-latency-us = <3263>; @@ -582,7 +590,7 @@ CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; + domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; }; }; @@ -782,6 +790,7 @@ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + power-domains = <&rpmhpd SC8180X_CX>; }; qupv3_id_0: geniqup@8c0000 { @@ -1708,8 +1717,22 @@ ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1805,8 +1828,22 @@ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1903,8 +1940,22 @@ ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; - interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2001,8 +2052,22 @@ ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; - interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2131,9 +2196,11 @@ reg = <0 0x01d87000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_EN>; clock-names = "ref", - "ref_aux"; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -2173,6 +2240,8 @@ interconnect-names = "gfx-mem"; qcom,gmu = <&gmu>; + #cooling-cells = <2>; + status = "disabled"; gpu_opp_table: opp-table { @@ -2692,9 +2761,15 @@ interrupt-controller; #interrupt-cells = <1>; - interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, - <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; iommus = <&apps_smmu 0x800 0x420>; @@ -2723,10 +2798,8 @@ "rot", "lut"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC8180X_MMCX>; @@ -3184,7 +3257,7 @@ <&dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "aux", "cfg_ahb"; - power-domains = <&dispcc MDSS_GDSC>; + power-domains = <&rpmhpd SC8180X_MX>; #clock-cells = <1>; #phy-cells = <0>; @@ -3210,6 +3283,7 @@ "edp_phy_pll_link_clk", "edp_phy_pll_vco_div_clk"; power-domains = <&rpmhpd SC8180X_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -3248,7 +3322,7 @@ aoss_qmp: power-controller@c300000 { compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x100000>; + reg = <0x0 0x0c300000 0x0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 0>; @@ -3256,6 +3330,11 @@ #power-domain-cells = <1>; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x0001100>, @@ -3880,8 +3959,15 @@ thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -4030,8 +4116,15 @@ thermal-sensors = <&tsens1 11>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/dts/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/dts/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index eb657e5449..15ae94c160 100644 --- a/dts/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/dts/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -6,10 +6,8 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h> -#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> -#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> @@ -855,27 +853,6 @@ }; &pmk8280_vadc { - status = "okay"; - - channel@3 { - reg = <PMK8350_ADC7_DIE_TEMP>; - qcom,pre-scaling = <1 1>; - label = "pmk8350_die_temp"; - }; - - channel@44 { - reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; - qcom,hw-settle-time = <200>; - qcom,ratiometric; - label = "pmk8350_xo_therm"; - }; - - channel@103 { - reg = <PM8350_ADC7_DIE_TEMP(1)>; - qcom,pre-scaling = <1 1>; - label = "pmc8280_1_die_temp"; - }; - channel@144 { reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>; qcom,hw-settle-time = <200>; @@ -904,12 +881,6 @@ label = "sys_therm4"; }; - channel@303 { - reg = <PM8350_ADC7_DIE_TEMP(3)>; - qcom,pre-scaling = <1 1>; - label = "pmc8280_2_die_temp"; - }; - channel@344 { reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>; qcom,hw-settle-time = <200>; @@ -937,12 +908,6 @@ qcom,ratiometric; label = "sys_therm8"; }; - - channel@403 { - reg = <PMR735A_ADC7_DIE_TEMP>; - qcom,pre-scaling = <1 1>; - label = "pmr735a_die_temp"; - }; }; &qup0 { @@ -1204,7 +1169,7 @@ }; &vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic02_default>; + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; vdd-micb-supply = <&vreg_s10b>; diff --git a/dts/src/arm64/qcom/sc8280xp-pmics.dtsi b/dts/src/arm64/qcom/sc8280xp-pmics.dtsi index 80ee12ded4..945de77911 100644 --- a/dts/src/arm64/qcom/sc8280xp-pmics.dtsi +++ b/dts/src/arm64/qcom/sc8280xp-pmics.dtsi @@ -3,6 +3,9 @@ * Copyright (c) 2022, Linaro Limited */ +#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/spmi/spmi.h> @@ -84,7 +87,37 @@ #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; - status = "disabled"; + + channel@3 { + reg = <PMK8350_ADC7_DIE_TEMP>; + qcom,pre-scaling = <1 1>; + label = "pmk8350_die_temp"; + }; + + channel@44 { + reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "pmk8350_xo_therm"; + }; + + channel@103 { + reg = <PM8350_ADC7_DIE_TEMP(1)>; + qcom,pre-scaling = <1 1>; + label = "pmc8280_1_die_temp"; + }; + + channel@303 { + reg = <PM8350_ADC7_DIE_TEMP(3)>; + qcom,pre-scaling = <1 1>; + label = "pmc8280_2_die_temp"; + }; + + channel@403 { + reg = <PMR735A_ADC7_DIE_TEMP>; + qcom,pre-scaling = <1 1>; + label = "pmr735a_die_temp"; + }; }; pmk8280_adc_tm: adc-tm@3400 { @@ -126,6 +159,8 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; interrupts-extended = <&spmi_bus 0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmk8280_vadc PM8350_ADC7_DIE_TEMP(1)>; + io-channel-names = "thermal"; #thermal-sensor-cells = <0>; }; @@ -178,6 +213,8 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmk8280_vadc PM8350_ADC7_DIE_TEMP(3)>; + io-channel-names = "thermal"; #thermal-sensor-cells = <0>; }; diff --git a/dts/src/arm64/qcom/sc8280xp.dtsi b/dts/src/arm64/qcom/sc8280xp.dtsi index febf28356f..a5b1948130 100644 --- a/dts/src/arm64/qcom/sc8280xp.dtsi +++ b/dts/src/arm64/qcom/sc8280xp.dtsi @@ -2257,9 +2257,12 @@ compatible = "qcom,sc8280xp-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; - clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_CARD_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_PHY_GDSC>; @@ -2319,9 +2322,12 @@ compatible = "qcom,sc8280xp-qmp-ufs-phy"; reg = <0 0x01da7000 0 0x1000>; - clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, - <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, + <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_CARD_GDSC>; @@ -2978,7 +2984,7 @@ }; }; - dmic02_default: dmic02-default-state { + dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -2994,7 +3000,7 @@ }; }; - dmic02_sleep: dmic02-sleep-state { + dmic23_sleep: dmic23-sleep-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -3451,6 +3457,404 @@ }; }; + cci0: cci@ac4a000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4a000 0 0x1000>; + + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4b000 0 0x1000>; + + interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci2: cci@ac4c000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4c000 0 0x1000>; + + interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_2_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci2_default>; + pinctrl-1 = <&cci2_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci3: cci@ac4d000 { + compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4d000 0 0x1000>; + + interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_3_CLK>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci"; + + power-domains = <&camcc TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci3_default>; + pinctrl-1 = <&cci3_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci3_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci3_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: camss@ac5a000 { + compatible = "qcom,sc8280xp-camss"; + + reg = <0 0x0ac5a000 0 0x2000>, + <0 0x0ac5c000 0 0x2000>, + <0 0x0ac65000 0 0x2000>, + <0 0x0ac67000 0 0x2000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb3000 0 0x1000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbd000 0 0x4000>, + <0 0x0acc1000 0 0x1000>, + <0 0x0acc4000 0 0x4000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0accb000 0 0x4000>, + <0 0x0accf000 0 0x1000>, + <0 0x0acd2000 0 0x4000>, + <0 0x0acd6000 0 0x1000>, + <0 0x0acd9000 0 0x4000>, + <0 0x0acdd000 0 0x1000>, + <0 0x0ace0000 0 0x4000>, + <0 0x0ace4000 0 0x1000>; + reg-names = "csiphy2", + "csiphy3", + "csiphy0", + "csiphy1", + "vfe0", + "csid0", + "vfe1", + "csid1", + "vfe2", + "csid2", + "vfe_lite0", + "csid0_lite", + "vfe_lite1", + "csid1_lite", + "vfe_lite2", + "csid2_lite", + "vfe_lite3", + "csid3_lite", + "vfe3", + "csid3"; + + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csid1_lite", + "vfe_lite1", + "csiphy3", + "csid0", + "vfe0", + "csid1", + "vfe1", + "csid0_lite", + "vfe_lite0", + "csiphy0", + "csiphy1", + "csiphy2", + "csid2", + "vfe2", + "csid3_lite", + "csid2_lite", + "vfe_lite3", + "vfe_lite2", + "csid3", + "vfe3"; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc IFE_3_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "ife3", + "top"; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_3_AXI_CLK>, + <&camcc CAMCC_IFE_3_CLK>, + <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_3_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_0_CLK>, + <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_1_CLK>, + <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_2_CLK>, + <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_3_CLK>, + <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe3_axi", + "vfe3", + "vfe3_cphy_rx", + "vfe3_csid", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid", + "vfe_lite2", + "vfe_lite2_cphy_rx", + "vfe_lite2_csid", + "vfe_lite3", + "vfe_lite3_cphy_rx", + "vfe_lite3_csid", + "gcc_axi_hf", + "gcc_axi_sf"; + + iommus = <&apps_smmu 0x2000 0x4e0>, + <&apps_smmu 0x2020 0x4e0>, + <&apps_smmu 0x2040 0x4e0>, + <&apps_smmu 0x2060 0x4e0>, + <&apps_smmu 0x2080 0x4e0>, + <&apps_smmu 0x20e0 0x4e0>, + <&apps_smmu 0x20c0 0x4e0>, + <&apps_smmu 0x20a0 0x4e0>, + <&apps_smmu 0x2400 0x4e0>, + <&apps_smmu 0x2420 0x4e0>, + <&apps_smmu 0x2440 0x4e0>, + <&apps_smmu 0x2460 0x4e0>, + <&apps_smmu 0x2480 0x4e0>, + <&apps_smmu 0x24e0 0x4e0>, + <&apps_smmu 0x24c0 0x4e0>, + <&apps_smmu 0x24a0 0x4e0>; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "cam_ahb", + "cam_hf_mnoc", + "cam_sf_mnoc", + "cam_sf_icp_mnoc"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc8280xp-camcc"; reg = <0 0x0ad00000 0 0x20000>; @@ -4011,6 +4415,28 @@ interrupt-controller; }; + tsens2: thermal-sensor@c251000 { + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg = <0 0x0c251000 0 0x1ff>, + <0 0x0c224000 0 0x8>; + #qcom,sensors = <11>; + interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c252000 { + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg = <0 0x0c252000 0 0x1ff>, + <0 0x0c225000 0 0x8>; + #qcom,sensors = <5>; + interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + tsens0: thermal-sensor@c263000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ @@ -4076,6 +4502,150 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 230>; wakeup-parent = <&pdc>; + + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio113", "gpio114"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio115", "gpio116"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins = "gpio113", "gpio114"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins = "gpio115", "gpio116"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio10","gpio11"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins = "gpio123","gpio124"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins = "gpio10","gpio11"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* cci_i2c_sda3, cci_i2c_scl3 */ + pins = "gpio123","gpio124"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci2_default: cci2-default-state { + cci2_i2c0_default: cci2-i2c0-default-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins = "gpio117","gpio118"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci2_i2c1_default: cci2-i2c1-default-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins = "gpio12","gpio13"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci2_sleep: cci2-sleep-state { + cci2_i2c0_sleep: cci2-i2c0-sleep-pins { + /* cci_i2c_sda4, cci_i2c_scl4 */ + pins = "gpio117","gpio118"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_i2c1_sleep: cci2-i2c1-sleep-pins { + /* cci_i2c_sda5, cci_i2c_scl5 */ + pins = "gpio12","gpio13"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci3_default: cci3-default-state { + cci3_i2c0_default: cci3-i2c0-default-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins = "gpio145","gpio146"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci3_i2c1_default: cci3-i2c1-default-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins = "gpio164","gpio165"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + cci3_sleep: cci3-sleep-state { + cci3_i2c0_sleep: cci3-i2c0-sleep-pins { + /* cci_i2c_sda6, cci_i2c_scl6 */ + pins = "gpio145","gpio146"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci3_i2c1_sleep: cci3-i2c1-sleep-pins { + /* cci_i2c_sda7, cci_i2c_scl7 */ + pins = "gpio164","gpio165"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; apps_smmu: iommu@15000000 { @@ -5212,6 +5782,21 @@ }; }; + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens2 2>; + + trips { + gpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + mem-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/dts/src/arm64/qcom/sda660-inforce-ifc6560.dts b/dts/src/arm64/qcom/sda660-inforce-ifc6560.dts index 2ed39d402d..702ab49bbc 100644 --- a/dts/src/arm64/qcom/sda660-inforce-ifc6560.dts +++ b/dts/src/arm64/qcom/sda660-inforce-ifc6560.dts @@ -461,3 +461,8 @@ dr_mode = "peripheral"; extcon = <&extcon_usb>; }; + +&usb3_qmpphy { + vdda-phy-supply = <&vreg_l1b_0p925>; + status = "okay"; +}; diff --git a/dts/src/arm64/qcom/sdm450-motorola-ali.dts b/dts/src/arm64/qcom/sdm450-motorola-ali.dts index 362be5719d..e27f3c5d5b 100644 --- a/dts/src/arm64/qcom/sdm450-motorola-ali.dts +++ b/dts/src/arm64/qcom/sdm450-motorola-ali.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include "msm8953.dtsi" +#include "sdm450.dtsi" #include "pm8953.dtsi" #include "pmi8950.dtsi" diff --git a/dts/src/arm64/qcom/sdm450.dtsi b/dts/src/arm64/qcom/sdm450.dtsi new file mode 100644 index 0000000000..b222aeb459 --- /dev/null +++ b/dts/src/arm64/qcom/sdm450.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (c) 2023, Luca Weiss <luca@z3ntu.xyz> */ + +#include "msm8953.dtsi" + +&gpu_opp_table { + /delete-node/ opp-650000000; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_turbo>; + }; +}; diff --git a/dts/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi b/dts/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi index 87d0293c72..819a5f8825 100644 --- a/dts/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi +++ b/dts/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi @@ -241,6 +241,16 @@ }; }; +&pm660l_wled { + status = "okay"; + + qcom,switching-freq = <800>; + qcom,ovp-millivolt = <29600>; + qcom,current-boost-limit = <970>; + qcom,current-limit-microamp = <17500>; + qcom,num-strings = <2>; +}; + &pon_pwrkey { status = "okay"; }; @@ -658,10 +668,16 @@ }; &usb3 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; }; &usb3_dwc3 { + maximum-speed = "high-speed"; + phys = <&qusb2phy0>; + phy-names = "usb2-phy"; + dr_mode = "peripheral"; extcon = <&extcon_usb>; }; diff --git a/dts/src/arm64/qcom/sdm630.dtsi b/dts/src/arm64/qcom/sdm630.dtsi index 513fe5e76b..f5921b80ef 100644 --- a/dts/src/arm64/qcom/sdm630.dtsi +++ b/dts/src/arm64/qcom/sdm630.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/soc/qcom,apr.h> / { @@ -1100,6 +1101,7 @@ interconnect-names = "gfx-mem"; operating-points-v2 = <&gpu_sdm630_opp_table>; + #cooling-cells = <2>; status = "disabled"; @@ -1281,12 +1283,16 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; - interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB_30_GDSC>; - qcom,select-utmi-as-pipe-clk; resets = <&gcc GCC_USB_30_BCR>; @@ -1297,17 +1303,38 @@ snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - /* - * SDM630 technically supports USB3 but I - * haven't seen any devices making use of it. - */ - maximum-speed = "high-speed"; - phys = <&qusb2phy0>; - phy-names = "usb2-phy"; + phys = <&qusb2phy0>, <&usb3_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; snps,hird-threshold = /bits/ 8 <0>; }; }; + usb3_qmpphy: phy@c010000 { + compatible = "qcom,sdm660-qmp-usb3-phy"; + reg = <0x0c010000 0x1000>; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3_phy_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; + + status = "disabled"; + }; + qusb2phy0: phy@c012000 { compatible = "qcom,sdm660-qusb2-phy"; reg = <0x0c012000 0x180>; @@ -1463,8 +1490,12 @@ <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <60000000>; - interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq"; qcom,select-utmi-as-pipe-clk; @@ -2551,6 +2582,13 @@ thermal-sensors = <&tsens 8>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { gpu_alert0: trip-point0 { temperature = <90000>; diff --git a/dts/src/arm64/qcom/sdm632.dtsi b/dts/src/arm64/qcom/sdm632.dtsi index 645b9f6a80..95b025ea26 100644 --- a/dts/src/arm64/qcom/sdm632.dtsi +++ b/dts/src/arm64/qcom/sdm632.dtsi @@ -79,3 +79,11 @@ compatible = "qcom,kryo250"; capacity-dmips-mhz = <1980>; }; + +&gpu_opp_table { + opp-725000000 { + opp-hz = /bits/ 64 <725000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_turbo>; + }; +}; diff --git a/dts/src/arm64/qcom/sdm660-xiaomi-lavender.dts b/dts/src/arm64/qcom/sdm660-xiaomi-lavender.dts index 3c47410ba9..7167f75bce 100644 --- a/dts/src/arm64/qcom/sdm660-xiaomi-lavender.dts +++ b/dts/src/arm64/qcom/sdm660-xiaomi-lavender.dts @@ -413,10 +413,16 @@ }; &usb3 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; }; &usb3_dwc3 { + maximum-speed = "high-speed"; + phys = <&qusb2phy0>; + phy-names = "usb2-phy"; + dr_mode = "peripheral"; extcon = <&extcon_usb>; }; diff --git a/dts/src/arm64/qcom/sdm670.dtsi b/dts/src/arm64/qcom/sdm670.dtsi index 4d7b77a231..80e81c4233 100644 --- a/dts/src/arm64/qcom/sdm670.dtsi +++ b/dts/src/arm64/qcom/sdm670.dtsi @@ -1320,12 +1320,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; diff --git a/dts/src/arm64/qcom/sdm845-cheza.dtsi b/dts/src/arm64/qcom/sdm845-cheza.dtsi index 0ab5e8f53a..e8276db9ea 100644 --- a/dts/src/arm64/qcom/sdm845-cheza.dtsi +++ b/dts/src/arm64/qcom/sdm845-cheza.dtsi @@ -852,6 +852,7 @@ ap_ts_i2c: &i2c14 { pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/dts/src/arm64/qcom/sdm845-db845c.dts b/dts/src/arm64/qcom/sdm845-db845c.dts index ab62204565..1f51732819 100644 --- a/dts/src/arm64/qcom/sdm845-db845c.dts +++ b/dts/src/arm64/qcom/sdm845-db845c.dts @@ -580,7 +580,7 @@ &pcie0 { status = "okay"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>; vddpe-3v3-supply = <&pcie0_3p3v_dual>; diff --git a/dts/src/arm64/qcom/sdm845-oneplus-common.dtsi b/dts/src/arm64/qcom/sdm845-oneplus-common.dtsi index e821103d49..46e25c5382 100644 --- a/dts/src/arm64/qcom/sdm845-oneplus-common.dtsi +++ b/dts/src/arm64/qcom/sdm845-oneplus-common.dtsi @@ -508,13 +508,13 @@ }; &q6afedai { - qi2s@22 { - reg = <22>; + dai@22 { + reg = <QUATERNARY_MI2S_RX>; qcom,sd-lines = <1>; }; - qi2s@23 { - reg = <23>; + dai@23 { + reg = <QUATERNARY_MI2S_TX>; qcom,sd-lines = <0>; }; }; diff --git a/dts/src/arm64/qcom/sdm845-shift-axolotl.dts b/dts/src/arm64/qcom/sdm845-shift-axolotl.dts index fbb8655653..486ce175e6 100644 --- a/dts/src/arm64/qcom/sdm845-shift-axolotl.dts +++ b/dts/src/arm64/qcom/sdm845-shift-axolotl.dts @@ -60,7 +60,7 @@ }; reserved-memory { - framebuffer_region@9d400000 { + framebuffer@9d400000 { reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; no-map; }; diff --git a/dts/src/arm64/qcom/sdm845.dtsi b/dts/src/arm64/qcom/sdm845.dtsi index c224482435..2f20be99ee 100644 --- a/dts/src/arm64/qcom/sdm845.dtsi +++ b/dts/src/arm64/qcom/sdm845.dtsi @@ -2639,10 +2639,12 @@ compatible = "qcom,sdm845-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -3366,8 +3368,8 @@ qcom,qmp = <&aoss_qmp>; - power-domains = <&rpmhpd SDM845_CX>, - <&rpmhpd SDM845_MX>; + power-domains = <&rpmhpd SDM845_LCX>, + <&rpmhpd SDM845_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; @@ -4058,12 +4060,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -4109,12 +4115,16 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, - <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; @@ -4760,6 +4770,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; @@ -5568,7 +5579,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster0_crit: cluster0_crit { + cluster0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -5588,7 +5599,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster1_crit: cluster1_crit { + cluster1_crit: cluster1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -5602,8 +5613,15 @@ thermal-sensors = <&tsens0 11>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu1_alert0: trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -5617,8 +5635,15 @@ thermal-sensors = <&tsens0 12>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu2_alert0: trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/dts/src/arm64/qcom/sm4450.dtsi b/dts/src/arm64/qcom/sm4450.dtsi index 3e7ae3bebb..603c962661 100644 --- a/dts/src/arm64/qcom/sm4450.dtsi +++ b/dts/src/arm64/qcom/sm4450.dtsi @@ -17,7 +17,7 @@ chosen { }; - clocks{ + clocks { xo_board: xo-board { compatible = "fixed-clock"; clock-frequency = <76800000>; diff --git a/dts/src/arm64/qcom/sm6115.dtsi b/dts/src/arm64/qcom/sm6115.dtsi index f9849b8bef..aca0a87092 100644 --- a/dts/src/arm64/qcom/sm6115.dtsi +++ b/dts/src/arm64/qcom/sm6115.dtsi @@ -14,6 +14,7 @@ #include <dt-bindings/interconnect/qcom,sm6115.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -614,6 +615,11 @@ #hwlock-cells = <1>; }; + tcsr_regs: syscon@3c0000 { + compatible = "qcom,sm6115-tcsr", "syscon"; + reg = <0x0 0x003c0000 0x0 0x40000>; + }; + tlmm: pinctrl@500000 { compatible = "qcom,sm6115-tlmm"; reg = <0x0 0x00500000 0x0 0x400000>, @@ -878,8 +884,31 @@ clock-output-names = "usb3_phy_pipe_clk_src"; #phy-cells = <0>; + orientation-switch; + + qcom,tcsr-reg = <&tcsr_regs 0xb244>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; }; system_noc: interconnect@1880000 { @@ -1194,8 +1223,12 @@ compatible = "qcom,sm6115-qmp-ufs-phy"; reg = <0x0 0x04807000 0x0 0x1000>; - clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1589,9 +1622,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; - interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq", + "ss_phy_irq"; resets = <&gcc GCC_USB30_PRIM_BCR>; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; @@ -1603,7 +1641,6 @@ interconnect-names = "usb-ddr", "apps-usb"; - qcom,select-utmi-as-pipe-clk; status = "disabled"; usb_dwc3: usb@4e00000 { @@ -1618,6 +1655,28 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_qmpphy_usb_ss_in>; + }; + }; + }; }; }; @@ -1649,6 +1708,7 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; status = "disabled"; @@ -3088,7 +3148,7 @@ type = "passive"; }; - cpu4_crit: cpu_crit { + cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3114,7 +3174,7 @@ type = "passive"; }; - cpu5_crit: cpu_crit { + cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3140,7 +3200,7 @@ type = "passive"; }; - cpu6_crit: cpu_crit { + cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3166,7 +3226,7 @@ type = "passive"; }; - cpu7_crit: cpu_crit { + cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3192,7 +3252,7 @@ type = "passive"; }; - cpu45_crit: cpu_crit { + cpu45_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3218,7 +3278,7 @@ type = "passive"; }; - cpu67_crit: cpu_crit { + cpu67_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3244,7 +3304,7 @@ type = "passive"; }; - cpu0123_crit: cpu_crit { + cpu0123_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3297,8 +3357,15 @@ polling-delay = <0>; thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu_alert0: trip-point0 { temperature = <115000>; hysteresis = <5000>; type = "passive"; @@ -3307,7 +3374,7 @@ trip-point1 { temperature = <125000>; hysteresis = <1000>; - type = "passive"; + type = "critical"; }; }; }; diff --git a/dts/src/arm64/qcom/sm6125.dtsi b/dts/src/arm64/qcom/sm6125.dtsi index 1dd3a4056e..98ab083560 100644 --- a/dts/src/arm64/qcom/sm6125.dtsi +++ b/dts/src/arm64/qcom/sm6125.dtsi @@ -812,10 +812,12 @@ compatible = "qcom,sm6125-qmp-ufs-phy"; reg = <0x04807000 0xdb8>; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux"; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1185,9 +1187,14 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; - interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; qcom,select-utmi-as-pipe-clk; diff --git a/dts/src/arm64/qcom/sm6350.dtsi b/dts/src/arm64/qcom/sm6350.dtsi index 43cffe8e12..24bcec3366 100644 --- a/dts/src/arm64/qcom/sm6350.dtsi +++ b/dts/src/arm64/qcom/sm6350.dtsi @@ -19,6 +19,7 @@ #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -1189,10 +1190,12 @@ compatible = "qcom,sm6350-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1325,10 +1328,11 @@ qcom,gmu = <&gmu>; nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; @@ -1439,8 +1443,6 @@ operating-points-v2 = <&gmu_opp_table>; - status = "disabled"; - gmu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -1830,12 +1832,15 @@ "mock_utmi"; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -1966,6 +1971,13 @@ interrupt-controller; #interrupt-cells = <1>; + interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; @@ -2698,6 +2710,569 @@ }; }; + thermal-zones { + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + audio-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 2>; + + trips { + audio-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu5_alert0>; + cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-left-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_left_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6-left-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_left_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-right-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu6_right_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6-right-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_right_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-left-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu7_left_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7-left-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_left_alert0>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-right-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu7_right_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7-right-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_right_alert0>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpuss0-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpuss1-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cwlan-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 1>; + + trips { + cwlan-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 3>; + + trips { + ddr-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 13>; + + trips { + gpuss0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 14>; + + trips { + gpuss1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss1-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + modem-core0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 6>; + + trips { + modem-core0-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem-core1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 7>; + + trips { + modem-core1-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem-scl-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 9>; + + trips { + modem-scl-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem-vec-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 8>; + + trips { + modem-vec-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 10>; + + trips { + npu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6-hvx-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 11>; + + trips { + video-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; clock-frequency = <19200000>; diff --git a/dts/src/arm64/qcom/sm6375.dtsi b/dts/src/arm64/qcom/sm6375.dtsi index 7ac8bf26dd..4386f8a9c6 100644 --- a/dts/src/arm64/qcom/sm6375.dtsi +++ b/dts/src/arm64/qcom/sm6375.dtsi @@ -1431,13 +1431,15 @@ assigned-clock-rates = <19200000>, <133333333>; interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, - <&mpm 12 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <&mpm 94 IRQ_TYPE_EDGE_BOTH>, <&mpm 93 IRQ_TYPE_EDGE_BOTH>, - <&mpm 94 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; diff --git a/dts/src/arm64/qcom/sm7125-xiaomi-common.dtsi b/dts/src/arm64/qcom/sm7125-xiaomi-common.dtsi index e55cd83c19..29289fa41b 100644 --- a/dts/src/arm64/qcom/sm7125-xiaomi-common.dtsi +++ b/dts/src/arm64/qcom/sm7125-xiaomi-common.dtsi @@ -152,6 +152,9 @@ regulator-min-microvolt = <824000>; regulator-max-microvolt = <928000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; vreg_l5a_2p7: ldo5 { @@ -188,6 +191,9 @@ regulator-min-microvolt = <1696000>; regulator-max-microvolt = <1952000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; vreg_l13a_1p8: ldo13 { @@ -230,6 +236,9 @@ regulator-min-microvolt = <2696000>; regulator-max-microvolt = <3304000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; }; @@ -258,6 +267,9 @@ regulator-min-microvolt = <1144000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; vreg_l4c_1p8: ldo4 { @@ -398,6 +410,20 @@ }; }; +&ufs_mem_hc { + vcc-supply = <&vreg_l19a_3p0>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l12a_1p8>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a_0p88>; + vdda-pll-supply = <&vreg_l3c_1p23>; + status = "okay"; +}; + &usb_1 { qcom,select-utmi-as-pipe-clk; status = "okay"; diff --git a/dts/src/arm64/qcom/sm7125-xiaomi-curtana.dts b/dts/src/arm64/qcom/sm7125-xiaomi-curtana.dts new file mode 100644 index 0000000000..12f517a849 --- /dev/null +++ b/dts/src/arm64/qcom/sm7125-xiaomi-curtana.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Joe Mason <buddyjojo06@outlook.com> + */ + +/dts-v1/; + +#include "sm7125-xiaomi-common.dtsi" + +/ { + model = "Xiaomi Redmi Note 9S"; + compatible = "xiaomi,curtana", "qcom,sm7125"; + + /* required for bootloader to select correct board */ + qcom,board-id = <0x20022 1>; +}; diff --git a/dts/src/arm64/qcom/sm7225-fairphone-fp4.dts b/dts/src/arm64/qcom/sm7225-fairphone-fp4.dts index ade6198055..bc67e8c1fe 100644 --- a/dts/src/arm64/qcom/sm7225-fairphone-fp4.dts +++ b/dts/src/arm64/qcom/sm7225-fairphone-fp4.dts @@ -68,6 +68,14 @@ }; }; + /* Dummy regulator until PM6150L has LCDB VSP/VSN support */ + lcdb_dummy: regulator-lcdb-dummy { + compatible = "regulator-fixed"; + regulator-name = "lcdb_dummy"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + }; + reserved-memory { /* * The rmtfs memory region in downstream is 'dynamically allocated' @@ -116,7 +124,7 @@ }; &adsp { - firmware-name = "qcom/sm7225/fairphone4/adsp.mdt"; + firmware-name = "qcom/sm7225/fairphone4/adsp.mbn"; status = "okay"; }; @@ -361,7 +369,7 @@ }; &cdsp { - firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt"; + firmware-name = "qcom/sm7225/fairphone4/cdsp.mbn"; status = "okay"; }; @@ -373,6 +381,14 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sm7225/fairphone4/a615_zap.mbn"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -400,12 +416,49 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&pil_ipa_fw_mem>; - firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mdt"; + firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mbn"; + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l22a>; + status = "okay"; + + panel@0 { + compatible = "djn,9a-3r063-1102b"; + reg = <0>; + + backlight = <&pm6150l_wled>; + reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>; + + vdd1-supply = <&vreg_l1e>; + vsn-supply = <&lcdb_dummy>; + vsp-supply = <&lcdb_dummy>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l18a>; status = "okay"; }; &mpss { - firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; + firmware-name = "qcom/sm7225/fairphone4/modem.mbn"; status = "okay"; }; diff --git a/dts/src/arm64/qcom/sm8150.dtsi b/dts/src/arm64/qcom/sm8150.dtsi index 761a6757dc..a35c0852b5 100644 --- a/dts/src/arm64/qcom/sm8150.dtsi +++ b/dts/src/arm64/qcom/sm8150.dtsi @@ -967,7 +967,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@133 { + gpu_speed_bin: gpu-speed-bin@133 { reg = <0x133 0x1>; bits = <5 3>; }; @@ -1843,8 +1843,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1858,14 +1872,16 @@ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", - "tbu"; + "tbu", + "ref"; iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, <0x100 &apps_smmu 0x1d81 0x1>; @@ -1879,7 +1895,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; - enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -1934,8 +1950,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1949,14 +1979,16 @@ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", - "tbu"; + "tbu", + "ref"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; @@ -2063,10 +2095,12 @@ compatible = "qcom,sm8150-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + "ref_aux", + "qref"; power-domains = <&gcc UFS_PHY_GDSC>; @@ -2198,6 +2232,7 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; status = "disabled"; @@ -2428,7 +2463,7 @@ bias-disable; }; - qup_spi6_default: qup-spi6_default-state { + qup_spi6_default: qup-spi6-default-state { pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "qup6"; drive-strength = <6>; @@ -2442,7 +2477,7 @@ bias-disable; }; - qup_spi7_default: qup-spi7_default-state { + qup_spi7_default: qup-spi7-default-state { pins = "gpio98", "gpio99", "gpio100", "gpio101"; function = "qup7"; drive-strength = <6>; @@ -3573,12 +3608,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -3645,12 +3684,16 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, - <&pdc 11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; @@ -5067,7 +5110,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster0_crit: cluster0_crit { + cluster0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -5087,7 +5130,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster1_crit: cluster1_crit { + cluster1_crit: cluster1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -5101,8 +5144,15 @@ thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu1_alert0: trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -5281,8 +5331,15 @@ thermal-sensors = <&tsens1 11>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu2_alert0: trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/dts/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi b/dts/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi index 946365f15a..6f54f50a70 100644 --- a/dts/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/dts/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com> + * Copyright (c) 2022-2024 Jianhua Lu <lujianhua000@gmail.com> */ #include <dt-bindings/arm/qcom,ids.h> @@ -551,6 +551,7 @@ vddio-supply = <&vreg_l14a_1p88>; reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; backlight = <&backlight>; + rotation = <90>; status = "disabled"; diff --git a/dts/src/arm64/qcom/sm8250.dtsi b/dts/src/arm64/qcom/sm8250.dtsi index 760501c130..39bd8f0eba 100644 --- a/dts/src/arm64/qcom/sm8250.dtsi +++ b/dts/src/arm64/qcom/sm8250.dtsi @@ -975,7 +975,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@19b { + gpu_speed_bin: gpu-speed-bin@19b { reg = <0x19b 0x1>; bits = <5 3>; }; @@ -2152,8 +2152,14 @@ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2248,8 +2254,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2349,8 +2369,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2506,10 +2540,12 @@ compatible = "qcom,sm8250-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; - clock-names = "ref", - "ref_aux"; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_1X_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -2888,6 +2924,7 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; status = "disabled"; @@ -4128,14 +4165,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; wakeup-source; @@ -4197,14 +4236,16 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; wakeup-source; @@ -6757,7 +6798,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster0_crit: cluster0_crit { + cluster0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -6777,7 +6818,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster1_crit: cluster1_crit { + cluster1_crit: cluster1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -6791,8 +6832,15 @@ thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu1_alert0: trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -6926,8 +6974,15 @@ thermal-sensors = <&tsens1 8>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu2_alert0: trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/dts/src/arm64/qcom/sm8350.dtsi b/dts/src/arm64/qcom/sm8350.dtsi index e78c83a897..a5e7dbbd8c 100644 --- a/dts/src/arm64/qcom/sm8350.dtsi +++ b/dts/src/arm64/qcom/sm8350.dtsi @@ -1526,8 +1526,14 @@ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1611,8 +1617,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1726,10 +1746,12 @@ compatible = "qcom,sm8350-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; - clock-names = "ref", - "ref_aux"; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_1_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1847,6 +1869,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; status = "disabled"; @@ -2312,14 +2335,16 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -2385,14 +2410,16 @@ <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; @@ -4165,7 +4192,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster0_crit: cluster0_crit { + cluster0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4185,7 +4212,7 @@ hysteresis = <2000>; type = "hot"; }; - cluster1_crit: cluster1_crit { + cluster1_crit: cluster1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4214,8 +4241,15 @@ thermal-sensors = <&tsens1 1>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu1_alert0: trip-point0 { + gpu_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <1000>; type = "hot"; @@ -4229,8 +4263,15 @@ thermal-sensors = <&tsens1 2>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu2_alert0: trip-point0 { + gpu_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <1000>; type = "hot"; diff --git a/dts/src/arm64/qcom/sm8450-hdk.dts b/dts/src/arm64/qcom/sm8450-hdk.dts index a20d5d76af..0786cff07b 100644 --- a/dts/src/arm64/qcom/sm8450-hdk.dts +++ b/dts/src/arm64/qcom/sm8450-hdk.dts @@ -938,8 +938,8 @@ "TX DMIC3", "MIC BIAS1", "TX SWR_INPUT0", "ADC1_OUTPUT", "TX SWR_INPUT1", "ADC2_OUTPUT", - "TX SWR_INPUT2", "ADC3_OUTPUT", - "TX SWR_INPUT3", "ADC4_OUTPUT"; + "TX SWR_INPUT0", "ADC3_OUTPUT", + "TX SWR_INPUT1", "ADC4_OUTPUT"; wcd-playback-dai-link { link-name = "WCD Playback"; @@ -1147,7 +1147,7 @@ }; &vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic02_default>; + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; vdd-micb-supply = <&vreg_s10b_1p8>; qcom,dmic-sample-rate = <600000>; diff --git a/dts/src/arm64/qcom/sm8450.dtsi b/dts/src/arm64/qcom/sm8450.dtsi index 01e4dfc4ba..b86be34a91 100644 --- a/dts/src/arm64/qcom/sm8450.dtsi +++ b/dts/src/arm64/qcom/sm8450.dtsi @@ -1028,6 +1028,12 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart20_default>; interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; status = "disabled"; }; @@ -1420,6 +1426,12 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; status = "disabled"; }; }; @@ -1772,8 +1784,22 @@ msi-map = <0x0 &gic_its 0x5981 0x1>, <0x100 &gic_its 0x5980 0x1>; msi-map-mask = <0xff00>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1881,8 +1907,22 @@ msi-map = <0x0 &gic_its 0x5a01 0x1>, <0x100 &gic_its 0x5a00 0x1>; msi-map-mask = <0xff00>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2038,6 +2078,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; status = "disabled"; @@ -3934,7 +3975,7 @@ }; }; - dmic02_default: dmic02-default-state { + dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -4485,13 +4526,15 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -4890,6 +4933,13 @@ polling-delay = <0>; thermal-sensors = <&tsens0 14>; + cooling-maps { + map0 { + trip = <&gpu_top_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -4909,7 +4959,7 @@ type = "passive"; }; - gpu0_tj_cfg: tj-cfg { + gpu_top_alert0: trip-point0 { temperature = <95000>; hysteresis = <5000>; type = "passive"; @@ -4922,6 +4972,13 @@ polling-delay = <0>; thermal-sensors = <&tsens0 15>; + cooling-maps { + map0 { + trip = <&gpu_bottom_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -4941,7 +4998,7 @@ type = "passive"; }; - gpu1_tj_cfg: tj-cfg { + gpu_bottom_alert0: trip-point0 { temperature = <95000>; hysteresis = <5000>; type = "passive"; diff --git a/dts/src/arm64/qcom/sm8550-hdk.dts b/dts/src/arm64/qcom/sm8550-hdk.dts new file mode 100644 index 0000000000..12d60a0ee0 --- /dev/null +++ b/dts/src/arm64/qcom/sm8550-hdk.dts @@ -0,0 +1,1306 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d_a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8550 HDK"; + compatible = "qcom,sm8550-hdk", "qcom,sm8550"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart7; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_out: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; + gpios = <&tlmm 159 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + led-1 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; + gpios = <&tlmm 160 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + + led-2 { + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_ORANGE>; + gpios = <&tlmm 162 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + lt9611_1v2: regulator-lt9611-1v2 { + compatible = "regulator-fixed"; + + regulator-name = "LT9611_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&vph_pwr>; + gpio = <&tlmm 152 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "LT9611_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_bob_3v3>; + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_bob_3v3: regulator-vreg-bob-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_BOB_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_pwr>; + }; + + sound { + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + model = "SM8550-HDK"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC5", "MIC BIAS4", + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT1", "ADC4_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p25>; + vdd-l12-supply = <&vreg_s6g_1p86>; + vdd-l15-supply = <&vreg_s6g_1p86>; + vdd-l17-supply = <&vreg_bob2>; + + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + qcom,pmic-id = "c"; + + vreg_l3c_0p9: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + /* ldo2 supplies SM8550 VDD_LPI_MX */ + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + qcom,pmic-id = "e"; + + vreg_s4e_0p95: smps4 { + regulator-name = "vreg_s4e_0p95"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5e_1p08: smps5 { + regulator-name = "vreg_s5e_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + vdd-s4-supply = <&vph_pwr>; + + qcom,pmic-id = "f"; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name = "vreg_l3f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "g"; + + vreg_s1g_1p25: smps1 { + regulator-name = "vreg_s1g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2g_0p85: smps2 { + regulator-name = "vreg_s2g_0p85"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3g_0p8: smps3 { + regulator-name = "vreg_s3g_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4g_1p25: smps4 { + regulator-name = "vreg_s4g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5g_0p85: smps5 { + regulator-name = "vreg_s5g_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6g_1p86: smps6 { + regulator-name = "vreg_s6g_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6g_1p86>; + vdd-l6-supply = <&vreg_s6g_1p86>; + vdd-l7-supply = <&vreg_bob1>; + + qcom,pmic-id = "m"; + + vreg_l1m_1p056: ldo1 { + regulator-name = "vreg_l1m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6m_1p8: ldo6 { + regulator-name = "vreg_l6m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6g_1p86>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + qcom,pmic-id = "n"; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2n_1p1: ldo2 { + regulator-name = "vreg_l2n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3n_2p8: ldo3 { + regulator-name = "vreg_l3n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4n_2p8: ldo4 { + regulator-name = "vreg_l4n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5n_1p8: ldo5 { + regulator-name = "vreg_l5n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6n_3p3: ldo6 { + regulator-name = "vreg_l6n_3p3"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7n_2p96: ldo7 { + regulator-name = "vreg_l7n_2p96"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 8 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + }; +}; + +&i2c_hub_2 { + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sm8550/ipa_fws.mbn"; + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; + }; +}; + +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + data-lanes = <0 1>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; + + status = "okay"; +}; + +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source = <1>; /* 1.8 V */ + }; + + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +/* The RGB signals are routed to 3 separate LEDs on the HDK8550 */ +&pm8550_pwm { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + default-state = "off"; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + default-state = "off"; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8550/modem.mbn", + "qcom/sm8550/modem_dtb.mbn"; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + bus-width = <4>; + no-sdio; + no-mmc; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + + powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + + powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + + /* + * WCD9385 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9385 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9385 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9385 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9385 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + + /* + * WCD9385 TX Port 1 (ADC1,2) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9385 TX Port 2 (ADC3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9385 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9385 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges = <32 8>; + + bt_default: bt-default-state { + bt-en-pins { + pins = "gpio81"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins = "gpio82"; + function = "gpio"; + bias-pull-down; + }; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio8"; + function = "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio7"; + function = "gpio"; + output-high; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&uart7 { + status = "okay"; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_s4e_0p95>; + vdddig-supply = <&vreg_s4e_0p95>; + vddrfa0p8-supply = <&vreg_s4e_0p95>; + vddrfa1p2-supply = <&vreg_s4g_1p25>; + vddrfa1p9-supply = <&vreg_s6g_1p86>; + + max-speed = <3200000>; + + enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bt_default>; + pinctrl-names = "default"; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vdd-hba-supply = <&vreg_l3g_1p2>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p88>; + + orientation-switch; + + status = "okay"; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/dts/src/arm64/qcom/sm8550-mtp.dts b/dts/src/arm64/qcom/sm8550-mtp.dts index c1135ad5fa..3d4ad5aac7 100644 --- a/dts/src/arm64/qcom/sm8550-mtp.dts +++ b/dts/src/arm64/qcom/sm8550-mtp.dts @@ -106,14 +106,21 @@ "SpkrRight IN", "WSA_SPK2 OUT", "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", "VA DMIC0", "MIC BIAS1", "VA DMIC1", "MIC BIAS1", "VA DMIC2", "MIC BIAS3", "TX DMIC0", "MIC BIAS1", "TX DMIC1", "MIC BIAS2", "TX DMIC2", "MIC BIAS3", - "TX SWR_ADC1", "ADC2_OUTPUT"; + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT0", "ADC3_OUTPUT", + "TX SWR_INPUT1", "ADC4_OUTPUT"; wcd-playback-dai-link { link-name = "WCD Playback"; @@ -874,7 +881,7 @@ wcd_tx: codec@0,3 { compatible = "sdw20217010d00"; reg = <0 3>; - qcom,tx-port-mapping = <1 1 2 3>; + qcom,tx-port-mapping = <2 2 3 4>; }; }; diff --git a/dts/src/arm64/qcom/sm8550-qrd.dts b/dts/src/arm64/qcom/sm8550-qrd.dts index d401d63e5c..92f0150174 100644 --- a/dts/src/arm64/qcom/sm8550-qrd.dts +++ b/dts/src/arm64/qcom/sm8550-qrd.dts @@ -124,14 +124,21 @@ "SpkrRight IN", "WSA_SPK2 OUT", "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", "VA DMIC0", "MIC BIAS1", "VA DMIC1", "MIC BIAS1", "VA DMIC2", "MIC BIAS3", "TX DMIC0", "MIC BIAS1", "TX DMIC1", "MIC BIAS2", "TX DMIC2", "MIC BIAS3", - "TX SWR_ADC1", "ADC2_OUTPUT"; + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT0", "ADC3_OUTPUT", + "TX SWR_INPUT1", "ADC4_OUTPUT"; wcd-playback-dai-link { link-name = "WCD Playback"; @@ -724,6 +731,10 @@ <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; @@ -960,6 +971,30 @@ }; }; +&spi4 { + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vreg_l14b_3p2>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_irq>, <&ts_reset>; + }; +}; + &swr1 { status = "okay"; @@ -978,7 +1013,7 @@ wcd_tx: codec@0,3 { compatible = "sdw20217010d00"; reg = <0 3>; - qcom,tx-port-mapping = <1 1 2 3>; + qcom,tx-port-mapping = <2 2 3 4>; }; }; @@ -1028,6 +1063,20 @@ bias-pull-down; }; + ts_irq: ts-irq-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_reset: ts-reset-state { + pins = "gpio24"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio108"; function = "gpio"; diff --git a/dts/src/arm64/qcom/sm8550.dtsi b/dts/src/arm64/qcom/sm8550.dtsi index ee1ba5a8c8..3904348075 100644 --- a/dts/src/arm64/qcom/sm8550.dtsi +++ b/dts/src/arm64/qcom/sm8550.dtsi @@ -1713,9 +1713,22 @@ linux,pci-domain = <0>; num-lanes = <2>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1742,6 +1755,9 @@ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + /* Entries are reversed due to the unusual ITS DeviceID encoding */ + msi-map = <0x0 &gic_its 0x1401 0x1>, + <0x100 &gic_its 0x1400 0x1>; iommu-map = <0x0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; @@ -1804,9 +1820,22 @@ linux,pci-domain = <1>; num-lanes = <2>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1838,6 +1867,9 @@ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + /* Entries are reversed due to the unusual ITS DeviceID encoding */ + msi-map = <0x0 &gic_its 0x1481 0x1>, + <0x100 &gic_its 0x1480 0x1>; iommu-map = <0x0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; @@ -1907,9 +1939,12 @@ ufs_mem_phy: phy@1d80000 { compatible = "qcom,sm8550-qmp-ufs-phy"; reg = <0x0 0x01d80000 0x0 0x2000>; - clocks = <&tcsr TCSR_UFS_CLKREF_EN>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_MEM_PHY_GDSC>; @@ -1940,6 +1975,7 @@ iommus = <&apps_smmu 0x60 0x0>; dma-coherent; + operating-points-v2 = <&ufs_opp_table>; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; @@ -1960,18 +1996,49 @@ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <100000000 403000000>, - <0 0>, - <0 0>, - <0 0>; qcom,ice = <&ice>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ice: crypto@1d88000 { @@ -2012,6 +2079,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; status = "disabled"; @@ -2507,7 +2575,7 @@ }; }; - dmic02_default: dmic02-default-state { + dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -3133,13 +3201,15 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; @@ -3248,7 +3318,7 @@ spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c400000 0 0x3000>, - <0 0x0c500000 0 0x4000000>, + <0 0x0c500000 0 0x400000>, <0 0x0c440000 0 0x80000>, <0 0x0c4c0000 0 0x20000>, <0 0x0c42d000 0 0x4000>; @@ -4254,6 +4324,7 @@ reg = <3>; iommus = <&apps_smmu 0x1003 0x80>, <&apps_smmu 0x1063 0x0>; + dma-coherent; }; compute-cb@4 { @@ -4261,6 +4332,7 @@ reg = <4>; iommus = <&apps_smmu 0x1004 0x80>, <&apps_smmu 0x1064 0x0>; + dma-coherent; }; compute-cb@5 { @@ -4268,6 +4340,7 @@ reg = <5>; iommus = <&apps_smmu 0x1005 0x80>, <&apps_smmu 0x1065 0x0>; + dma-coherent; }; compute-cb@6 { @@ -4275,6 +4348,7 @@ reg = <6>; iommus = <&apps_smmu 0x1006 0x80>, <&apps_smmu 0x1066 0x0>; + dma-coherent; }; compute-cb@7 { @@ -4282,6 +4356,7 @@ reg = <7>; iommus = <&apps_smmu 0x1007 0x80>, <&apps_smmu 0x1067 0x0>; + dma-coherent; }; }; @@ -4388,6 +4463,7 @@ iommus = <&apps_smmu 0x1961 0x0>, <&apps_smmu 0x0c01 0x20>, <&apps_smmu 0x19c1 0x10>; + dma-coherent; }; compute-cb@2 { @@ -4396,6 +4472,7 @@ iommus = <&apps_smmu 0x1962 0x0>, <&apps_smmu 0x0c02 0x20>, <&apps_smmu 0x19c2 0x10>; + dma-coherent; }; compute-cb@3 { @@ -4404,6 +4481,7 @@ iommus = <&apps_smmu 0x1963 0x0>, <&apps_smmu 0x0c03 0x20>, <&apps_smmu 0x19c3 0x10>; + dma-coherent; }; compute-cb@4 { @@ -4412,6 +4490,7 @@ iommus = <&apps_smmu 0x1964 0x0>, <&apps_smmu 0x0c04 0x20>, <&apps_smmu 0x19c4 0x10>; + dma-coherent; }; compute-cb@5 { @@ -4420,6 +4499,7 @@ iommus = <&apps_smmu 0x1965 0x0>, <&apps_smmu 0x0c05 0x20>, <&apps_smmu 0x19c5 0x10>; + dma-coherent; }; compute-cb@6 { @@ -4428,6 +4508,7 @@ iommus = <&apps_smmu 0x1966 0x0>, <&apps_smmu 0x0c06 0x20>, <&apps_smmu 0x19c6 0x10>; + dma-coherent; }; compute-cb@7 { @@ -4436,6 +4517,7 @@ iommus = <&apps_smmu 0x1967 0x0>, <&apps_smmu 0x0c07 0x20>, <&apps_smmu 0x19c7 0x10>; + dma-coherent; }; compute-cb@8 { @@ -4444,6 +4526,7 @@ iommus = <&apps_smmu 0x1968 0x0>, <&apps_smmu 0x0c08 0x20>, <&apps_smmu 0x19c8 0x10>; + dma-coherent; }; /* note: secure cb9 in downstream */ @@ -5304,6 +5387,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 1>; + cooling-maps { + map0 { + trip = <&gpu0_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5336,6 +5426,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 2>; + cooling-maps { + map0 { + trip = <&gpu1_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5368,6 +5465,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 3>; + cooling-maps { + map0 { + trip = <&gpu2_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5400,6 +5504,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 4>; + cooling-maps { + map0 { + trip = <&gpu3_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5432,6 +5543,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 5>; + cooling-maps { + map0 { + trip = <&gpu4_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5464,6 +5582,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 6>; + cooling-maps { + map0 { + trip = <&gpu5_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5496,6 +5621,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 7>; + cooling-maps { + map0 { + trip = <&gpu6_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; @@ -5528,6 +5660,13 @@ polling-delay = <0>; thermal-sensors = <&tsens2 8>; + cooling-maps { + map0 { + trip = <&gpu7_junction_config>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { thermal-engine-config { temperature = <125000>; diff --git a/dts/src/arm64/qcom/sm8650-mtp.dts b/dts/src/arm64/qcom/sm8650-mtp.dts index be133a3d5c..4450273f96 100644 --- a/dts/src/arm64/qcom/sm8650-mtp.dts +++ b/dts/src/arm64/qcom/sm8650-mtp.dts @@ -66,6 +66,29 @@ }; }; + sound { + compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model = "SM8650-MTP"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT"; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -428,6 +451,138 @@ RPMH_REGULATOR_MODE_HPM>; }; }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6c_1p8>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p1: ldo1 { + regulator-name = "vreg_l1m_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7m_2p96: ldo7 { + regulator-name = "vreg_l7m_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "n"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_s6c_1p8>; + vdd-l5-supply = <&vreg_bob2>; + vdd-l6-supply = <&vreg_bob2>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2n_1p056: ldo2 { + regulator-name = "vreg_l2n_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; }; &dispcc { diff --git a/dts/src/arm64/qcom/sm8650-qrd.dts b/dts/src/arm64/qcom/sm8650-qrd.dts index b9151c2ddf..b07cac2e5b 100644 --- a/dts/src/arm64/qcom/sm8650-qrd.dts +++ b/dts/src/arm64/qcom/sm8650-qrd.dts @@ -77,9 +77,83 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&redriver_ss_out>; }; }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&wcd_usbss_sbu_mux>; + }; + }; + }; + }; + }; + + sound { + compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model = "SM8650-QRD"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT2", "ADC3_OUTPUT", + "TX SWR_INPUT3", "ADC4_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; }; }; }; @@ -94,6 +168,41 @@ regulator-always-on; regulator-boot-on; }; + + wcd939x: audio-codec { + compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + + mode-switch; + orientation-switch; + + port { + wcd_codec_headset_in: endpoint { + remote-endpoint = <&wcd_usbss_headset_out>; + }; + }; + }; }; &apps_rsc { @@ -436,6 +545,138 @@ RPMH_REGULATOR_MODE_HPM>; }; }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6c_1p8>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p1: ldo1 { + regulator-name = "vreg_l1m_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7m_2p96: ldo7 { + regulator-name = "vreg_l7m_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "n"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_s6c_1p8>; + vdd-l5-supply = <&vreg_bob2>; + vdd-l6-supply = <&vreg_bob2>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2n_1p056: ldo2 { + regulator-name = "vreg_l2n_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; }; &dispcc { @@ -446,6 +687,78 @@ status = "okay"; }; +&i2c3 { + status = "okay"; + + wcd_usbss: typec-mux@e { + compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg = <0xe>; + + vdd-supply = <&vreg_l15b_1p8>; + reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + + port@1 { + reg = <1>; + + wcd_usbss_headset_out: endpoint { + remote-endpoint = <&wcd_codec_headset_in>; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_ss_in: endpoint { + data-lanes = <3 2 1 0>; + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; +}; + &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; @@ -453,6 +766,16 @@ status = "okay"; }; +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + &mdss { status = "okay"; }; @@ -495,6 +818,15 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + &mdss_mdp { status = "okay"; }; @@ -600,6 +932,11 @@ status = "okay"; }; +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up = <2200>; +}; + &qupv3_id_0 { status = "okay"; }; @@ -657,6 +994,74 @@ }; }; +&swr0 { + status = "okay"; + + /* WSA8845, Speaker Left */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&lpass_tlmm 21 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + }; + + /* WSA8845, Speaker Right */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + &tlmm { /* Reserved I/Os for NFC */ gpio-reserved-ranges = <32 8>, <74 1>; @@ -704,6 +1109,14 @@ bias-pull-down; }; + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + ts_irq: ts-irq-state { pins = "gpio161"; function = "gpio"; @@ -718,6 +1131,14 @@ drive-strength = <8>; bias-pull-up; }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart14 { @@ -787,7 +1208,7 @@ }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -803,9 +1224,23 @@ vdda-phy-supply = <&vreg_l3i_1p2>; vdda-pll-supply = <&vreg_l3g_0p91>; + orientation-switch; + status = "okay"; }; +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + &xo_board { clock-frequency = <76800000>; }; diff --git a/dts/src/arm64/qcom/sm8650.dtsi b/dts/src/arm64/qcom/sm8650.dtsi index 2df77123a8..ba72d8f384 100644 --- a/dts/src/arm64/qcom/sm8650.dtsi +++ b/dts/src/arm64/qcom/sm8650.dtsi @@ -525,6 +525,11 @@ no-map; }; + qlink_logging_mem: qlink-logging@84800000 { + reg = <0 0x84800000 0 0x200000>; + no-map; + }; + mpss_dsm_mem: mpss-dsm@86b00000 { reg = <0 0x86b00000 0 0x4900000>; no-map; @@ -1228,7 +1233,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; @@ -1250,7 +1255,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; @@ -2213,8 +2218,22 @@ <0 0x60100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2255,6 +2274,11 @@ interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; + /* Entries are reversed due to the unusual ITS DeviceID encoding */ + msi-map = <0x0 &gic_its 0x1401 0x1>, + <0x100 &gic_its 0x1400 0x1>; + msi-map-mask = <0xff00>; + linux,pci-domain = <0>; num-lanes = <2>; bus-range = <0 0xff>; @@ -2317,8 +2341,22 @@ "atu", "config"; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2364,6 +2402,11 @@ interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; + /* Entries are reversed due to the unusual ITS DeviceID encoding */ + msi-map = <0x0 &gic_its 0x1481 0x1>, + <0x100 &gic_its 0x1480 0x1>; + msi-map-mask = <0xff00>; + linux,pci-domain = <1>; num-lanes = <2>; bus-range = <0 0xff>; @@ -2448,10 +2491,12 @@ compatible = "qcom,sm8650-qmp-ufs-phy"; reg = <0 0x01d80000 0 0x2000>; - clocks = <&tcsr TCSR_UFS_CLKREF_EN>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; clock-names = "ref", - "ref_aux"; + "ref_aux", + "qref"; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -2627,7 +2672,8 @@ "mss"; memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, - <&mpss_dsm_mem>, <&mpss_dsm_mem_2>; + <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, + <&qlink_logging_mem>; qcom,qmp = <&aoss_qmp>; @@ -2919,7 +2965,7 @@ }; }; - dmic02_default: dmic02-default-state { + dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; @@ -3703,7 +3749,7 @@ spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c400000 0 0x3000>, - <0 0x0c500000 0 0x4000000>, + <0 0x0c500000 0 0x400000>, <0 0x0c440000 0 0x80000>, <0 0x0c4c0000 0 0x20000>, <0 0x0c42d000 0 0x4000>; @@ -4808,6 +4854,7 @@ iommus = <&apps_smmu 0x1003 0x80>, <&apps_smmu 0x1043 0x20>; + dma-coherent; }; compute-cb@4 { @@ -4816,6 +4863,7 @@ iommus = <&apps_smmu 0x1004 0x80>, <&apps_smmu 0x1044 0x20>; + dma-coherent; }; compute-cb@5 { @@ -4824,6 +4872,7 @@ iommus = <&apps_smmu 0x1005 0x80>, <&apps_smmu 0x1045 0x20>; + dma-coherent; }; compute-cb@6 { @@ -4832,6 +4881,7 @@ iommus = <&apps_smmu 0x1006 0x80>, <&apps_smmu 0x1046 0x20>; + dma-coherent; }; compute-cb@7 { @@ -4841,6 +4891,7 @@ iommus = <&apps_smmu 0x1007 0x40>, <&apps_smmu 0x1067 0x0>, <&apps_smmu 0x1087 0x0>; + dma-coherent; }; }; @@ -4961,6 +5012,7 @@ iommus = <&apps_smmu 0x1961 0x0>, <&apps_smmu 0x0c01 0x20>, <&apps_smmu 0x19c1 0x0>; + dma-coherent; }; compute-cb@2 { @@ -4970,6 +5022,7 @@ iommus = <&apps_smmu 0x1962 0x0>, <&apps_smmu 0x0c02 0x20>, <&apps_smmu 0x19c2 0x0>; + dma-coherent; }; compute-cb@3 { @@ -4979,6 +5032,7 @@ iommus = <&apps_smmu 0x1963 0x0>, <&apps_smmu 0x0c03 0x20>, <&apps_smmu 0x19c3 0x0>; + dma-coherent; }; compute-cb@4 { @@ -4988,6 +5042,7 @@ iommus = <&apps_smmu 0x1964 0x0>, <&apps_smmu 0x0c04 0x20>, <&apps_smmu 0x19c4 0x0>; + dma-coherent; }; compute-cb@5 { @@ -4997,6 +5052,7 @@ iommus = <&apps_smmu 0x1965 0x0>, <&apps_smmu 0x0c05 0x20>, <&apps_smmu 0x19c5 0x0>; + dma-coherent; }; compute-cb@6 { @@ -5006,6 +5062,7 @@ iommus = <&apps_smmu 0x1966 0x0>, <&apps_smmu 0x0c06 0x20>, <&apps_smmu 0x19c6 0x0>; + dma-coherent; }; compute-cb@7 { @@ -5015,6 +5072,7 @@ iommus = <&apps_smmu 0x1967 0x0>, <&apps_smmu 0x0c07 0x20>, <&apps_smmu 0x19c7 0x0>; + dma-coherent; }; compute-cb@8 { @@ -5024,6 +5082,7 @@ iommus = <&apps_smmu 0x1968 0x0>, <&apps_smmu 0x0c08 0x20>, <&apps_smmu 0x19c8 0x0>; + dma-coherent; }; }; }; diff --git a/dts/src/arm64/qcom/x1e80100-crd.dts b/dts/src/arm64/qcom/x1e80100-crd.dts index 7532d8eca2..6a0a54532e 100644 --- a/dts/src/arm64/qcom/x1e80100-crd.dts +++ b/dts/src/arm64/qcom/x1e80100-crd.dts @@ -18,10 +18,124 @@ serial0 = &uart21; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-CRD"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TwitterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TwitterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -401,10 +515,251 @@ }; }; +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + &qupv3_2 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + /* pinctrl in left_woofer node because of sharing the GPIO*/ + powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TwitterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + +&swr3 { + status = "okay"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + /* pinctrl in right_woofer node because of sharing the GPIO*/ + powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TwitterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -416,9 +771,104 @@ drive-strength = <16>; bias-disable; }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart21 { compatible = "qcom,geni-debug-uart"; status = "okay"; }; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; diff --git a/dts/src/arm64/qcom/x1e80100-qcp.dts b/dts/src/arm64/qcom/x1e80100-qcp.dts index a37ad9475c..e76d29053d 100644 --- a/dts/src/arm64/qcom/x1e80100-qcp.dts +++ b/dts/src/arm64/qcom/x1e80100-qcp.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "x1e80100.dtsi" @@ -31,6 +32,23 @@ regulator-always-on; regulator-boot-on; }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; }; &apps_rsc { @@ -243,7 +261,7 @@ qcom,pmic-id = "e"; vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vph_pwr>; + vdd-l3-supply = <&vreg_s5j_1p2>; vreg_l2e_0p8: ldo2 { regulator-name = "vreg_l2e_0p8"; @@ -349,7 +367,7 @@ qcom,pmic-id = "j"; vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vph_pwr>; + vdd-l2-supply = <&vreg_s5j_1p2>; vdd-l3-supply = <&vreg_s1f_0p7>; vdd-s5-supply = <&vph_pwr>; @@ -383,17 +401,170 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + &qupv3_2 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; &uart21 { compatible = "qcom,geni-debug-uart"; status = "okay"; }; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; diff --git a/dts/src/arm64/qcom/x1e80100.dtsi b/dts/src/arm64/qcom/x1e80100.dtsi index 6f75fc342c..8e517f7618 100644 --- a/dts/src/arm64/qcom/x1e80100.dtsi +++ b/dts/src/arm64/qcom/x1e80100.dtsi @@ -4,14 +4,20 @@ */ #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> #include <dt-bindings/clock/qcom,x1e80100-gcc.h> +#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> / { interrupt-parent = <&intc>; @@ -395,16 +401,24 @@ CLUSTER_PD0: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; + power-domains = <&SYSTEM_PD>; }; CLUSTER_PD1: power-domain-cpu-cluster1 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; + power-domains = <&SYSTEM_PD>; }; CLUSTER_PD2: power-domain-cpu-cluster2 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; + power-domains = <&SYSTEM_PD>; + }; + + SYSTEM_PD: power-domain-system { + #power-domain-cells = <0>; + /* TODO: system-wide idle states */ }; }; @@ -662,6 +676,58 @@ }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -677,13 +743,13 @@ clocks = <&bi_tcxo_div2>, <&sleep_clk>, <0>, + <&pcie4_phy>, <0>, + <&pcie6a_phy>, <0>, - <0>, - <0>, - <0>, - <0>, - <0>; + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; @@ -691,6 +757,17 @@ #power-domain-cells = <1>; }; + ipcc: mailbox@408000 { + compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; @@ -1139,7 +1216,7 @@ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; @@ -2428,6 +2505,126 @@ }; }; + usb_1_ss0_hsphy: phy@fd3000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x00fd3000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_1_ss0_qmpphy: phy@fd5000 { + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; + reg = <0 0x00fd5000 0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&gcc GCC_USB_0_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1_ss1_hsphy: phy@fd9000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x00fd9000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status = "disabled"; + }; + + usb_1_ss1_qmpphy: phy@fda000 { + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; + reg = <0 0x00fda000 0 0x4000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&gcc GCC_USB_1_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1_ss2_hsphy: phy@fde000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x00fde000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; + + status = "disabled"; + }; + + usb_1_ss2_qmpphy: phy@fdf000 { + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; + reg = <0 0x00fdf000 0 0x4000>; + + clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&gcc GCC_USB_2_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_TERT_BCR>, + <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,x1e80100-cnoc-main"; reg = <0 0x1500000 0 0x14400>; @@ -2536,12 +2733,258 @@ #interconnect-cells = <2>; }; + pcie6a: pci@1bf8000 { + device_type = "pci"; + compatible = "qcom,pcie-x1e80100"; + reg = <0 0x01bf8000 0 0x3000>, + <0 0x70000000 0 0xf1d>, + <0 0x70000f20 0 0xa8>, + <0 0x70001000 0 0x1000>, + <0 0x70100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, + <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; + bus-range = <0 0xff>; + + dma-coherent; + + linux,pci-domain = <7>; + num-lanes = <2>; + + interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, + <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_6A_BCR>, + <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_6A_GDSC>; + + phys = <&pcie6a_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie6a_phy: phy@1bfc000 { + compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; + reg = <0 0x01bfc000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, + <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_6A_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_6A_PHY_BCR>, + <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie6a_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie4: pci@1c08000 { + device_type = "pci"; + compatible = "qcom,pcie-x1e80100"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x7c000000 0 0xf1d>, + <0 0x7c000f40 0 0xa8>, + <0 0x7c001000 0 0x1000>, + <0 0x7c100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, + <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <5>; + num-lanes = <2>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_4_BCR>, + <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_4_GDSC>; + + phys = <&pcie4_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie4_phy: phy@1c0e000 { + compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_4_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_4_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie4_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; #hwlock-cells = <1>; }; + tcsr: clock-controller@1fc0000 { + compatible = "qcom,x1e80100-tcsr", "syscon"; + reg = <0 0x01fc0000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + gem_noc: interconnect@26400000 { compatible = "qcom,x1e80100-gem-noc"; reg = <0 0x26400000 0 0x311200>; @@ -2560,6 +3003,331 @@ #interconnect-cells = <2>; }; + lpass_wsa2macro: codec@6aa0000 { + compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0 0x06aa0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + #sound-dai-cells = <1>; + sound-name-prefix = "WSA2"; + }; + + swr3: soundwire@6ab0000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06ab0000 0 0x10000>; + clocks = <&lpass_wsa2macro>; + clock-names = "iface"; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + label = "WSA2"; + + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; + reg = <0 0x06ac0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr1: soundwire@6ad0000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06ad0000 0 0x10000>; + clocks = <&lpass_rxmacro>; + clock-names = "iface"; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + label = "RX"; + + pinctrl-0 = <&rx_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <1>; + qcom,dout-ports = <11>; + + qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_txmacro: codec@6ae0000 { + compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; + reg = <0 0x06ae0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0 0x06b00000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + sound-name-prefix = "WSA"; + }; + + swr0: soundwire@6b10000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06b10000 0 0x10000>; + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + label = "WSA"; + + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + swr2: soundwire@6d30000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06d30000 0 0x10000>; + clocks = <&lpass_txmacro>; + clock-names = "iface"; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core", "wakeup"; + label = "TX"; + + pinctrl-0 = <&tx_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <1>; + + qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_vamacro: codec@6d44000 { + compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; + reg = <0 0x06d44000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@6e80000 { + compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; + reg = <0 0x06e80000 0 0x20000>, + <0 0x07250000 0 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,x1e80100-lpass-ag-noc"; reg = <0 0x7e40000 0 0xE080>; @@ -2587,6 +3355,849 @@ #interconnect-cells = <2>; }; + usb_2_hsphy: phy@88e0000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x088e0000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; + + status = "disabled"; + }; + + usb_1_ss2: usb@a0f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a0f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_SLEEP_CLK>, + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 58 IRQ_TYPE_EDGE_BOTH>, + <&pdc 57 IRQ_TYPE_EDGE_BOTH>, + <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_TERT_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_TERT_BCR>; + + interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_ss2_dwc3: usb@a000000 { + compatible = "snps,dwc3"; + reg = <0 0x0a000000 0 0xcd00>; + + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&apps_smmu 0x14a0 0x0>; + + phys = <&usb_1_ss2_hsphy>, + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + + dma-coherent; + + port { + usb_1_ss2_role_switch: endpoint { + }; + }; + }; + }; + + usb_2: usb@a2f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a2f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 50 IRQ_TYPE_EDGE_BOTH>, + <&pdc 49 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + power-domains = <&gcc GCC_USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + + interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_2_dwc3: usb@a200000 { + compatible = "snps,dwc3"; + reg = <0 0x0a200000 0 0xcd00>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x14e0 0x0>; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + + port { + usb_2_role_switch: endpoint { + }; + }; + }; + }; + + usb_1_ss0: usb@a6f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 61 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_ss0_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&apps_smmu 0x1420 0x0>; + + phys = <&usb_1_ss0_hsphy>, + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + + dma-coherent; + + port { + usb_1_ss0_role_switch: endpoint { + }; + }; + }; + }; + + usb_1_ss1: usb@a8f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 60 IRQ_TYPE_EDGE_BOTH>, + <&pdc 11 IRQ_TYPE_EDGE_BOTH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_ss1_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&apps_smmu 0x1460 0x0>; + + phys = <&usb_1_ss1_hsphy>, + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + + dma-coherent; + + port { + usb_1_ss1_role_switch: endpoint { + }; + }; + }; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,x1e80100-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,x1e80100-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&mdss_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@ae98000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xae98000 0 0x200>, + <0 0xae98200 0 0x200>, + <0 0xae98400 0 0x600>, + <0 0xae99000 0 0x400>, + <0 0xae99400 0 0x400>; + + interrupts-extended = <&mdss 13>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp1_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + }; + }; + }; + + mdss_dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp2: displayport-controller@ae9a000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9b000 0 0x400>, + <0 0xae9b400 0 0x400>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp2_phy 0>, + <&mdss_dp2_phy 1>; + + operating-points-v2 = <&mdss_dp2_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp2_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp3: displayport-controller@aea0000 { + compatible = "qcom,x1e80100-dp"; + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0x600>, + <0 0xaea1000 0 0x400>, + <0 0xaea1400 0 0x400>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp3_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + + link-frequencies = /bits/ 64 <8100000000>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + }; + + mdss_dp2_phy: phy@aec2a00 { + compatible = "qcom,x1e80100-dp-phy"; + reg = <0 0x0aec2a00 0 0x19c>, + <0 0x0aec2200 0 0xec>, + <0 0x0aec2600 0 0xec>, + <0 0x0aec2000 0 0x1c8>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp3_phy: phy@aec5a00 { + compatible = "qcom,x1e80100-dp-phy"; + reg = <0 0x0aec5a00 0 0x19c>, + <0 0x0aec5200 0 0xec>, + <0 0x0aec5600 0 0xec>, + <0 0x0aec5000 0 0x1c8>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,x1e80100-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp2_phy 0>, /* dp2 */ + <&mdss_dp2_phy 1>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,x1e80100-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; @@ -2599,6 +4210,18 @@ interrupt-controller; }; + aoss_qmp: power-management@c300000 { + compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + tlmm: pinctrl@f100000 { compatible = "qcom,x1e80100-tlmm"; reg = <0 0x0f100000 0 0xf00000>; @@ -3170,7 +4793,7 @@ /* TX, RX */ pins = "gpio86", "gpio87"; function = "qup2_se5"; - drive-strength= <2>; + drive-strength = <2>; bias-disable; }; }; @@ -3315,7 +4938,6 @@ <0 0x17510000 0 0x10000>, <0 0x17520000 0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; - qcom,drv-count = <3>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, @@ -3326,6 +4948,7 @@ <WAKE_TCS 2>, <CONTROL_TCS 0>; label = "apps_rsc"; + power-domains = <&SYSTEM_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; @@ -3514,6 +5137,144 @@ "llcc_broadcast_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; }; + + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,x1e80100-adsp-pas"; + reg = <0 0x30000000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&adspslpi_mem>, + <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1061 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,x1e80100-cdsp-pas"; + reg = <0 0x32300000 0 0x1400000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&cdsp_mem>, + <&q6_cdsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + }; + }; }; timer { diff --git a/dts/src/arm64/renesas/r8a774a1.dtsi b/dts/src/arm64/renesas/r8a774a1.dtsi index 95b0a1f6de..a8a44fe5e8 100644 --- a/dts/src/arm64/renesas/r8a774a1.dtsi +++ b/dts/src/arm64/renesas/r8a774a1.dtsi @@ -529,6 +529,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -541,7 +542,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -554,7 +557,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -568,6 +573,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -581,6 +587,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a774b1.dtsi b/dts/src/arm64/renesas/r8a774b1.dtsi index 786660fcde..4fff511e99 100644 --- a/dts/src/arm64/renesas/r8a774b1.dtsi +++ b/dts/src/arm64/renesas/r8a774b1.dtsi @@ -413,6 +413,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -425,7 +426,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -438,7 +441,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -452,6 +457,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -465,6 +471,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a774c0.dtsi b/dts/src/arm64/renesas/r8a774c0.dtsi index eed94ffed7..1ef43d78c3 100644 --- a/dts/src/arm64/renesas/r8a774c0.dtsi +++ b/dts/src/arm64/renesas/r8a774c0.dtsi @@ -384,6 +384,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -396,7 +397,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -409,7 +412,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -423,6 +428,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -436,6 +442,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a774e1.dtsi b/dts/src/arm64/renesas/r8a774e1.dtsi index 175e5d296d..be55ae8394 100644 --- a/dts/src/arm64/renesas/r8a774e1.dtsi +++ b/dts/src/arm64/renesas/r8a774e1.dtsi @@ -593,6 +593,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -605,7 +606,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -618,7 +621,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -632,6 +637,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -645,6 +651,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a77951.dtsi b/dts/src/arm64/renesas/r8a77951.dtsi index a4260d9291..bea4edd17d 100644 --- a/dts/src/arm64/renesas/r8a77951.dtsi +++ b/dts/src/arm64/renesas/r8a77951.dtsi @@ -614,6 +614,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -626,7 +627,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -639,7 +642,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -653,6 +658,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -666,6 +672,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a77960.dtsi b/dts/src/arm64/renesas/r8a77960.dtsi index a631ead171..7846fea8e4 100644 --- a/dts/src/arm64/renesas/r8a77960.dtsi +++ b/dts/src/arm64/renesas/r8a77960.dtsi @@ -578,6 +578,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -590,7 +591,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -603,7 +606,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -617,6 +622,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -630,6 +636,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a77961.dtsi b/dts/src/arm64/renesas/r8a77961.dtsi index 7254912a24..58f9286a5a 100644 --- a/dts/src/arm64/renesas/r8a77961.dtsi +++ b/dts/src/arm64/renesas/r8a77961.dtsi @@ -578,6 +578,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -590,7 +591,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -603,7 +606,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -617,6 +622,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -630,6 +636,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a77965.dtsi b/dts/src/arm64/renesas/r8a77965.dtsi index e57b902706..692940662d 100644 --- a/dts/src/arm64/renesas/r8a77965.dtsi +++ b/dts/src/arm64/renesas/r8a77965.dtsi @@ -449,6 +449,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -461,7 +462,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -474,7 +477,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -488,6 +493,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -501,6 +507,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a77970.dtsi b/dts/src/arm64/renesas/r8a77970.dtsi index ed6e2e47c6..d2d3cecc76 100644 --- a/dts/src/arm64/renesas/r8a77970.dtsi +++ b/dts/src/arm64/renesas/r8a77970.dtsi @@ -328,6 +328,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -340,7 +341,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -353,7 +356,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -367,6 +372,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -380,6 +386,7 @@ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a77980.dtsi b/dts/src/arm64/renesas/r8a77980.dtsi index 5ed2daaca1..c0ba110c74 100644 --- a/dts/src/arm64/renesas/r8a77980.dtsi +++ b/dts/src/arm64/renesas/r8a77980.dtsi @@ -357,6 +357,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -369,7 +370,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -382,7 +385,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -395,7 +400,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -408,7 +415,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a77990.dtsi b/dts/src/arm64/renesas/r8a77990.dtsi index 8c2b283423..37063e3f4e 100644 --- a/dts/src/arm64/renesas/r8a77990.dtsi +++ b/dts/src/arm64/renesas/r8a77990.dtsi @@ -415,6 +415,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -427,7 +428,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -440,7 +443,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -454,6 +459,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -467,6 +473,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a77995.dtsi b/dts/src/arm64/renesas/r8a77995.dtsi index 8cf6473c63..89990dd8eb 100644 --- a/dts/src/arm64/renesas/r8a77995.dtsi +++ b/dts/src/arm64/renesas/r8a77995.dtsi @@ -336,6 +336,7 @@ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -348,7 +349,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -361,7 +364,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -375,6 +380,7 @@ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -388,6 +394,7 @@ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a779a0.dtsi b/dts/src/arm64/renesas/r8a779a0.dtsi index 4e67a03564..cfa70b441e 100644 --- a/dts/src/arm64/renesas/r8a779a0.dtsi +++ b/dts/src/arm64/renesas/r8a779a0.dtsi @@ -370,6 +370,7 @@ interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -382,7 +383,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -395,7 +398,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -408,7 +413,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -421,7 +428,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -658,7 +667,7 @@ avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779a0", "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6800000 0 0x800>; + reg = <0 0xe6800000 0 0x1000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, @@ -706,7 +715,7 @@ avb1: ethernet@e6810000 { compatible = "renesas,etheravb-r8a779a0", "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6810000 0 0x800>; + reg = <0 0xe6810000 0 0x1000>; interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/src/arm64/renesas/r8a779f0.dtsi b/dts/src/arm64/renesas/r8a779f0.dtsi index 7fb4989cce..72cf30341f 100644 --- a/dts/src/arm64/renesas/r8a779f0.dtsi +++ b/dts/src/arm64/renesas/r8a779f0.dtsi @@ -501,6 +501,7 @@ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -513,7 +514,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -526,7 +529,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -539,7 +544,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -552,7 +559,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dts b/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dts new file mode 100644 index 0000000000..c8b1bb50a8 --- /dev/null +++ b/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the standalone R-Car V4H White Hawk CPU board + * + * Copyright (C) 2023 Glider bv + */ + +/dts-v1/; +#include "r8a779g0-white-hawk-cpu.dtsi" + +/ { + model = "Renesas White Hawk CPU board based on r8a779g0"; +}; diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi b/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi index 913f70fe6c..b1fe1aedc2 100644 --- a/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/dts/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -1,378 +1,14 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the White Hawk CPU board + * Device Tree Source for the R-Car V4H White Hawk CPU board * * Copyright (C) 2022 Renesas Electronics Corp. */ #include "r8a779g0.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> +#include "white-hawk-cpu-common.dtsi" / { model = "Renesas White Hawk CPU board"; compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; - - aliases { - ethernet0 = &avb0; - serial0 = &hscif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:921600n8"; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&keys_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = <KEY_1>; - label = "SW47"; - wakeup-source; - debounce-interval = <20>; - }; - - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = <KEY_2>; - label = "SW48"; - wakeup-source; - debounce-interval = <20>; - }; - - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = <KEY_3>; - label = "SW49"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - }; - - led-2 { - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - }; - - led-3 { - gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x1 0x00000000>; - }; - - mini-dp-con { - compatible = "dp-connector"; - label = "CN5"; - type = "mini"; - - port { - mini_dp_con_in: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - - reg_1p2v: regulator-1p2v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sn65dsi86_refclk: clk-x6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; -}; - -&avb0 { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio7>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - }; -}; - -&dsi0 { - status = "okay"; - - ports { - port@1 { - dsi0_out: endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&du { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander_a: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "cpu-board"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - bridge@2c { - compatible = "ti,sn65dsi86"; - reg = <0x2c>; - - clocks = <&sn65dsi86_refclk>; - clock-names = "refclk"; - - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - - vccio-supply = <®_1p8v>; - vpll-supply = <®_1p8v>; - vcca-supply = <®_1p2v>; - vcc-supply = <®_1p2v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - remote-endpoint = <&mini_dp_con_in>; - }; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb0_pins: avb0 { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", - "avb0_txcrefclk"; - function = "avb0"; - }; - - pins_mdio { - groups = "avb0_mdio"; - drive-strength = <21>; - }; - - pins_mii { - groups = "avb0_rgmii"; - drive-strength = <21>; - }; - - }; - hscif0_pins: hscif0 { - groups = "hscif0_data"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - keys_pins: keys { - pins = "GP_5_0", "GP_5_1", "GP_5_2"; - bias-pull-up; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - reg = <0x0 0x1200000>; - read-only; - }; - user@1200000 { - reg = <0x1200000 0x2e00000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <24000000>; }; diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk.dts b/dts/src/arm64/renesas/r8a779g0-white-hawk.dts index eff1ef6e2c..784d4e8b20 100644 --- a/dts/src/arm64/renesas/r8a779g0-white-hawk.dts +++ b/dts/src/arm64/renesas/r8a779g0-white-hawk.dts @@ -1,69 +1,15 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the White Hawk CPU and BreakOut boards + * Device Tree Source for the R-Car V4H White Hawk CPU and BreakOut boards * * Copyright (C) 2022 Renesas Electronics Corp. */ /dts-v1/; #include "r8a779g0-white-hawk-cpu.dtsi" -#include "r8a779g0-white-hawk-csi-dsi.dtsi" -#include "r8a779g0-white-hawk-ethernet.dtsi" +#include "white-hawk-common.dtsi" / { model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0"; - - can_transceiver0: can-phy0 { - compatible = "nxp,tjr1443"; - #phy-cells = <0>; - enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - max-bitrate = <5000000>; - }; -}; - -&can_clk { - clock-frequency = <40000000>; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; - - channel0 { - status = "okay"; - phys = <&can_transceiver0>; - }; - - channel1 { - status = "okay"; - }; -}; - -&i2c0 { - eeprom@51 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "breakout-board"; - reg = <0x51>; - pagesize = <8>; - }; -}; - -&pfc { - can_clk_pins: can-clk { - groups = "can_clk"; - function = "can_clk"; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data"; - function = "canfd0"; - }; - - canfd1_pins: canfd1 { - groups = "canfd1_data"; - function = "canfd1"; - }; }; diff --git a/dts/src/arm64/renesas/r8a779g0.dtsi b/dts/src/arm64/renesas/r8a779g0.dtsi index d3d25e077c..9bc542bc61 100644 --- a/dts/src/arm64/renesas/r8a779g0.dtsi +++ b/dts/src/arm64/renesas/r8a779g0.dtsi @@ -161,11 +161,6 @@ }; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; @@ -185,13 +180,24 @@ interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; - /* External SCIF clock - to be overridden by boards that provide it */ + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clocks - to be overridden by boards that provide them */ scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; + scif_clk2: scif2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -479,6 +485,7 @@ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -491,7 +498,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -504,7 +513,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -517,7 +528,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -530,7 +543,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -681,7 +696,7 @@ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 516>, <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; + <&scif_clk2>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x35>, <&dmac0 0x34>, <&dmac1 0x35>, <&dmac1 0x34>; @@ -761,7 +776,7 @@ avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779g0", "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6800000 0 0x800>; + reg = <0 0xe6800000 0 0x1000>; interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, @@ -808,7 +823,7 @@ avb1: ethernet@e6810000 { compatible = "renesas,etheravb-r8a779g0", "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6810000 0 0x800>; + reg = <0 0xe6810000 0 0x1000>; interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, @@ -1057,7 +1072,7 @@ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 705>, <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; + <&scif_clk2>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>, <&dmac1 0x59>, <&dmac1 0x58>; @@ -1777,6 +1792,37 @@ }; }; + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779g0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 706>, + <&cpg CPG_CORE R8A779G0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + iommus = <&ipmmu_ds0 32>; + status = "disabled"; + }; + + rpc: spi@ee200000 { + compatible = "renesas,r8a779g0-rpc-if", + "renesas,rcar-gen4-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ipmmu_rt0: iommu@ee480000 { compatible = "renesas,ipmmu-r8a779g0", "renesas,rcar-gen4-ipmmu-vmsa"; @@ -1886,37 +1932,6 @@ #iommu-cells = <1>; }; - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a779g0", - "renesas,rcar-gen4-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 706>, - <&cpg CPG_CORE R8A779G0_CLK_SD0H>; - clock-names = "core", "clkh"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 706>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds0 32>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a779g0-rpc-if", - "renesas,rcar-gen4-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 629>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; diff --git a/dts/src/arm64/renesas/r8a779g2-white-hawk-single.dts b/dts/src/arm64/renesas/r8a779g2-white-hawk-single.dts new file mode 100644 index 0000000000..2f79e5a612 --- /dev/null +++ b/dts/src/arm64/renesas/r8a779g2-white-hawk-single.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H ES2.0 White Hawk Single board + * + * Copyright (C) 2023 Glider bv + */ + +/dts-v1/; +#include "r8a779g2.dtsi" +#include "white-hawk-cpu-common.dtsi" +#include "white-hawk-common.dtsi" + +/ { + model = "Renesas White Hawk Single board based on r8a779g2"; + compatible = "renesas,white-hawk-single", "renesas,r8a779g2", + "renesas,r8a779g0"; +}; + +&hscif0 { + uart-has-rtscts; +}; + +&hscif0_pins { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; +}; diff --git a/dts/src/arm64/renesas/r8a779g2.dtsi b/dts/src/arm64/renesas/r8a779g2.dtsi new file mode 100644 index 0000000000..e08f531843 --- /dev/null +++ b/dts/src/arm64/renesas/r8a779g2.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H (R8A779G2) SoC + * + * Copyright (C) 2023 Glider bv + */ + +#include "r8a779g0.dtsi" + +/ { + compatible = "renesas,r8a779g2", "renesas,r8a779g0"; +}; diff --git a/dts/src/arm64/renesas/r8a779h0-gray-hawk-single.dts b/dts/src/arm64/renesas/r8a779h0-gray-hawk-single.dts new file mode 100644 index 0000000000..bc8616a56c --- /dev/null +++ b/dts/src/arm64/renesas/r8a779h0-gray-hawk-single.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4M Gray Hawk Single board + * + * Copyright (C) 2023 Renesas Electronics Corp. + * Copyright (C) 2024 Glider bv + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> + +#include "r8a779h0.dtsi" + +/ { + model = "Renesas Gray Hawk Single board based on r8a779h0"; + compatible = "renesas,gray-hawk-single", "renesas,r8a779h0"; + + aliases { + serial0 = &hscif0; + ethernet0 = &avb0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:921600n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x1 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; + + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; + + eeprom@52 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "csi-dsi-sub-board-id"; + reg = <0x52>; + pagesize = <8>; + }; + + eeprom@53 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "ethernet-sub-board-id"; + reg = <0x53>; + pagesize = <8>; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0x1200000>; + read-only; + }; + user@1200000 { + reg = <0x1200000 0x2e00000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/dts/src/arm64/renesas/r8a779h0.dtsi b/dts/src/arm64/renesas/r8a779h0.dtsi new file mode 100644 index 0000000000..1188572918 --- /dev/null +++ b/dts/src/arm64/renesas/r8a779h0.dtsi @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4M (R8A779H0) SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/renesas,r8a779h0-sysc.h> + +/ { + compatible = "renesas,r8a779h0"; + #address-cells = <2>; + #size-cells = <2>; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a76_0>; + }; + core1 { + cpu = <&a76_1>; + }; + core2 { + cpu = <&a76_2>; + }; + core3 { + cpu = <&a76_3>; + }; + }; + }; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_1: cpu@100 { + compatible = "arm,cortex-a76"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_2: cpu@200 { + compatible = "arm,cortex-a76"; + reg = <0x200>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_3: cpu@300 { + compatible = "arm,cortex-a76"; + reg = <0x300>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; + operating-points-v2 = <&cluster0_opp>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; + + L3_CA76: cache-controller { + compatible = "cache"; + power-domains = <&sysc R8A779H0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; + }; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779h0-wdt", + "renesas,rcar-gen4-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a779h0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, + <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, + <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; + }; + + gpio0: gpio@e6050180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050180 0 0x54>; + interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 19>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + }; + + gpio1: gpio@e6050980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050980 0 0x54>; + interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + }; + + gpio2: gpio@e6058180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058180 0 0x54>; + interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 20>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + }; + + gpio3: gpio@e6058980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058980 0 0x54>; + interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + }; + + gpio4: gpio@e6060180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060180 0 0x54>; + interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 25>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + gpio5: gpio@e6060980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060980 0 0x54>; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + gpio6: gpio@e6061180 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061180 0 0x54>; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + gpio7: gpio@e6061980 { + compatible = "renesas,gpio-r8a779h0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061980 0 0x54>; + interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 21>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779h0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779h0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779h0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779h0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + dmas = <&dmac1 0x97>, <&dmac1 0x96>, + <&dmac2 0x97>, <&dmac2 0x96>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + avb0: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a779h0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6800000 0 0x1000>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 211>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 211>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb1: ethernet@e6810000 { + compatible = "renesas,etheravb-r8a779h0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6810000 0 0x1000>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 212>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 212>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb2: ethernet@e6820000 { + compatible = "renesas,etheravb-r8a779h0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6820000 0 0x1000>; + interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 213>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 213>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac1: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779h0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779h0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779h0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 706>, + <&cpg CPG_CORE R8A779H0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + status = "disabled"; + }; + + rpc: spi@ee200000 { + compatible = "renesas,r8a779h0-rpc-if", + "renesas,rcar-gen4-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/dts/src/arm64/renesas/r9a07g043u.dtsi b/dts/src/arm64/renesas/r9a07g043u.dtsi index 2ab231572d..964b0a475e 100644 --- a/dts/src/arm64/renesas/r9a07g043u.dtsi +++ b/dts/src/arm64/renesas/r9a07g043u.dtsi @@ -61,6 +61,75 @@ &soc { interrupt-parent = <&gic>; + cru: video@10830000 { + compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru"; + reg = <0 0x10830000 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>, + <&cpg CPG_MOD R9A07G043_CRU_PCLK>, + <&cpg CPG_MOD R9A07G043_CRU_ACLK>; + clock-names = "video", "apb", "axi"; + interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(168) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(169) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + resets = <&cpg R9A07G043_CRU_PRESETN>, + <&cpg R9A07G043_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi2cru>; + }; + }; + }; + }; + + csi2: csi2@10830400 { + compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2"; + reg = <0 0x10830400 0 0xfc00>; + interrupts = <SOC_PERIPHERAL_IRQ(166) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>, + <&cpg CPG_MOD R9A07G043_CRU_VCLK>, + <&cpg CPG_MOD R9A07G043_CRU_PCLK>; + clock-names = "system", "video", "apb"; + resets = <&cpg R9A07G043_CRU_PRESETN>, + <&cpg R9A07G043_CRU_CMN_RSTB>; + reset-names = "presetn", "cmn-rstb"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2cru: endpoint@0 { + reg = <0>; + remote-endpoint = <&crucsi2>; + }; + }; + }; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc"; @@ -109,7 +178,13 @@ <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>, <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>, <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>, - <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>; + <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>; interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", "irq4", "irq5", "irq6", "irq7", @@ -121,7 +196,9 @@ "tint20", "tint21", "tint22", "tint23", "tint24", "tint25", "tint26", "tint27", "tint28", "tint29", "tint30", "tint31", - "bus-err"; + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, <&cpg CPG_MOD R9A07G043_IA55_PCLK>; clock-names = "clk", "pclk"; diff --git a/dts/src/arm64/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso b/dts/src/arm64/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso new file mode 100644 index 0000000000..b41bb4b31a --- /dev/null +++ b/dts/src/arm64/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/G2UL SMARC EVK with OV5645 camera + * connected to CSI and CRU enabled. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +#define OV5645_PARENT_I2C i2c0 +#include "rz-smarc-cru-csi-ov5645.dtsi" + +&ov5645 { + enable-gpios = <&pinctrl RZG2L_GPIO(4, 4) GPIO_ACTIVE_HIGH>; + reset-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>; +}; diff --git a/dts/src/arm64/renesas/r9a07g044.dtsi b/dts/src/arm64/renesas/r9a07g044.dtsi index 66f68fc2b2..9f00b75d2b 100644 --- a/dts/src/arm64/renesas/r9a07g044.dtsi +++ b/dts/src/arm64/renesas/r9a07g044.dtsi @@ -793,6 +793,22 @@ reset-names = "rst", "arst", "prst"; power-domains = <&cpg>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; }; vspd: vsp@10870000 { @@ -820,6 +836,36 @@ resets = <&cpg R9A07G044_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g044-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -905,7 +951,27 @@ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, <&cpg CPG_MOD R9A07G044_IA55_PCLK>; clock-names = "clk", "pclk"; diff --git a/dts/src/arm64/renesas/r9a07g054.dtsi b/dts/src/arm64/renesas/r9a07g054.dtsi index 1f1d481dc7..53d8905f36 100644 --- a/dts/src/arm64/renesas/r9a07g054.dtsi +++ b/dts/src/arm64/renesas/r9a07g054.dtsi @@ -798,6 +798,22 @@ reset-names = "rst", "arst", "prst"; power-domains = <&cpg>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; }; vspd: vsp@10870000 { @@ -826,6 +842,37 @@ resets = <&cpg R9A07G054_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g054-du", + "renesas,r9a07g044-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g054-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -912,7 +959,27 @@ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>, <&cpg CPG_MOD R9A07G054_IA55_PCLK>; clock-names = "clk", "pclk"; diff --git a/dts/src/arm64/renesas/r9a08g045.dtsi b/dts/src/arm64/renesas/r9a08g045.dtsi index 5facfad961..f5f3f4f4c8 100644 --- a/dts/src/arm64/renesas/r9a08g045.dtsi +++ b/dts/src/arm64/renesas/r9a08g045.dtsi @@ -42,6 +42,11 @@ clock-frequency = <0>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -152,7 +157,10 @@ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", "irq4", "irq5", "irq6", "irq7", @@ -164,7 +172,8 @@ "tint20", "tint21", "tint22", "tint23", "tint24", "tint25", "tint26", "tint27", "tint28", "tint29", "tint30", "tint31", - "bus-err"; + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0"; clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, <&cpg CPG_MOD R9A08G045_IA55_PCLK>; clock-names = "clk", "pclk"; @@ -264,6 +273,20 @@ <0x0 0x12440000 0 0x60000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G045_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G045_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { diff --git a/dts/src/arm64/renesas/rzg2l-smarc.dtsi b/dts/src/arm64/renesas/rzg2l-smarc.dtsi index 37807f1bda..887dffe149 100644 --- a/dts/src/arm64/renesas/rzg2l-smarc.dtsi +++ b/dts/src/arm64/renesas/rzg2l-smarc.dtsi @@ -40,17 +40,7 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - }; - }; - port@1 { - reg = <1>; dsi0_out: endpoint { data-lanes = <1 2 3 4>; remote-endpoint = <&adv7535_in>; @@ -59,6 +49,10 @@ }; }; +&du { + status = "okay"; +}; + &i2c1 { adv7535: hdmi@3d { compatible = "adi,adv7535"; diff --git a/dts/src/arm64/renesas/rzg2lc-smarc.dtsi b/dts/src/arm64/renesas/rzg2lc-smarc.dtsi index 859bc8745e..f21508640b 100644 --- a/dts/src/arm64/renesas/rzg2lc-smarc.dtsi +++ b/dts/src/arm64/renesas/rzg2lc-smarc.dtsi @@ -56,17 +56,7 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - }; - }; - port@1 { - reg = <1>; dsi0_out: endpoint { data-lanes = <1 2 3 4>; remote-endpoint = <&adv7535_in>; @@ -75,6 +65,10 @@ }; }; +&du { + status = "okay"; +}; + &i2c1 { adv7535: hdmi@3d { compatible = "adi,adv7535"; diff --git a/dts/src/arm64/renesas/rzg3s-smarc-som.dtsi b/dts/src/arm64/renesas/rzg3s-smarc-som.dtsi index f062d4ad78..acac4666ae 100644 --- a/dts/src/arm64/renesas/rzg3s-smarc-som.dtsi +++ b/dts/src/arm64/renesas/rzg3s-smarc-som.dtsi @@ -193,12 +193,14 @@ #endif &pinctrl { +#if SW_CONFIG3 == SW_ON eth0-phy-irq-hog { gpio-hog; gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>; input; line-name = "eth0-phy-irq"; }; +#endif eth0_pins: eth0 { txc { @@ -234,12 +236,14 @@ }; }; +#if SW_CONFIG3 == SW_ON eth1-phy-irq-hog { gpio-hog; gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>; input; line-name = "eth1-phy-irq"; }; +#endif eth1_pins: eth1 { txc { @@ -336,3 +340,8 @@ }; }; }; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/dts/src/arm64/renesas/rzg3s-smarc.dtsi b/dts/src/arm64/renesas/rzg3s-smarc.dtsi index 2145201372..deb2ad37bb 100644 --- a/dts/src/arm64/renesas/rzg3s-smarc.dtsi +++ b/dts/src/arm64/renesas/rzg3s-smarc.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> / { @@ -14,6 +15,37 @@ mmc1 = &sdhi1; }; + keys { + compatible = "gpio-keys"; + + key-1 { + interrupts = <RZG2L_GPIO(18, 0) IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pinctrl>; + linux,code = <KEY_1>; + label = "USER_SW1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + interrupts = <RZG2L_GPIO(0, 1) IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pinctrl>; + linux,code = <KEY_2>; + label = "USER_SW2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts = <RZG2L_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pinctrl>; + linux,code = <KEY_3>; + label = "USER_SW3"; + wakeup-source; + debounce-interval = <20>; + }; + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; @@ -35,6 +67,27 @@ }; &pinctrl { + key-1-gpio-hog { + gpio-hog; + gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>; + input; + line-name = "key-1-gpio-irq"; + }; + + key-2-gpio-hog { + gpio-hog; + gpios = <RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>; + input; + line-name = "key-2-gpio-irq"; + }; + + key-3-gpio-hog { + gpio-hog; + gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_LOW>; + input; + line-name = "key-3-gpio-irq"; + }; + scif0_pins: scif0 { pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */ <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */ diff --git a/dts/src/arm64/renesas/ulcb-kf.dtsi b/dts/src/arm64/renesas/ulcb-kf.dtsi index 50de17e4fb..431b37bf56 100644 --- a/dts/src/arm64/renesas/ulcb-kf.dtsi +++ b/dts/src/arm64/renesas/ulcb-kf.dtsi @@ -32,39 +32,40 @@ }; }; - accel_3v3: regulator-acc-3v3 { + reg_t1p8v: regulator-t1p8v { compatible = "regulator-fixed"; - regulator-name = "accel-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_1v8: regulator-hdmi-1v8 { - compatible = "regulator-fixed"; - regulator-name = "hdmi-1v8"; + regulator-name = "T1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; - hdmi_3v3: regulator-hdmi-3v3 { + pcie_1v5: regulator-pcie-1v5 { compatible = "regulator-fixed"; - regulator-name = "hdmi-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "pcie-1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio_exp_77 15 GPIO_ACTIVE_HIGH>; + enable-active-high; }; - snd_3p3v: regulator-snd_3p3v { + pcie_3v3: regulator-pcie-3v3 { compatible = "regulator-fixed"; - regulator-name = "snd-3.3v"; + regulator-name = "pcie-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = <&gpio_exp_77 14 GPIO_ACTIVE_HIGH>; + enable-active-high; }; - snd_vcc5v: regulator-snd_vcc5v { + reg_5v: regulator-5v { compatible = "regulator-fixed"; - regulator-name = "snd-vcc5v"; + regulator-name = "fixed-5V"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; }; wlan_en: regulator-wlan_en { @@ -157,11 +158,11 @@ pd-gpios = <&gpio_exp_75 5 GPIO_ACTIVE_LOW>; - avdd-supply = <&hdmi_1v8>; - dvdd-supply = <&hdmi_1v8>; - pvdd-supply = <&hdmi_1v8>; - dvdd-3v-supply = <&hdmi_3v3>; - bgvdd-supply = <&hdmi_1v8>; + avdd-supply = <®_t1p8v>; + dvdd-supply = <®_t1p8v>; + pvdd-supply = <®_t1p8v>; + dvdd-3v-supply = <®_3p3v>; + bgvdd-supply = <®_t1p8v>; adi,input-depth = <8>; adi,input-colorspace = "rgb"; @@ -198,8 +199,8 @@ compatible = "st,lsm9ds0-imu"; reg = <0x1d>; - vdd-supply = <&accel_3v3>; - vddio-supply = <&accel_3v3>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; pcm3168a: audio-codec@44 { @@ -209,20 +210,20 @@ clocks = <&clksndsel>; clock-names = "scki"; - VDD1-supply = <&snd_3p3v>; - VDD2-supply = <&snd_3p3v>; - VCCAD1-supply = <&snd_vcc5v>; - VCCAD2-supply = <&snd_vcc5v>; - VCCDA1-supply = <&snd_vcc5v>; - VCCDA2-supply = <&snd_vcc5v>; + VDD1-supply = <®_3p3v>; + VDD2-supply = <®_3p3v>; + VCCAD1-supply = <®_5v>; + VCCAD2-supply = <®_5v>; + VCCDA1-supply = <®_5v>; + VCCDA2-supply = <®_5v>; }; gyroscope@6b { compatible = "st,lsm9ds0-gyro"; reg = <0x6b>; - vdd-supply = <&accel_3v3>; - vddio-supply = <&accel_3v3>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; }; @@ -348,6 +349,9 @@ &pciec1 { status = "okay"; + + vpcie1v5-supply = <&pcie_1v5>; + vpcie3v3-supply = <&pcie_3v3>; }; &pfc { @@ -417,6 +421,13 @@ pinctrl-names = "default"; status = "okay"; + + gnss { + compatible = "u-blox,neo-m8"; + reset-gpios = <&gpio_exp_75 6 GPIO_ACTIVE_LOW>; + vcc-supply = <®_3p3v>; + current-speed = <9600>; + }; }; &sdhi3 { diff --git a/dts/src/arm64/renesas/white-hawk-common.dtsi b/dts/src/arm64/renesas/white-hawk-common.dtsi new file mode 100644 index 0000000000..c99086edad --- /dev/null +++ b/dts/src/arm64/renesas/white-hawk-common.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the common parts shared by the White Hawk BreakOut + * and White Hawk Single boards + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include "white-hawk-csi-dsi.dtsi" +#include "white-hawk-ethernet.dtsi" + +/ { + can_transceiver0: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + max-bitrate = <5000000>; + }; +}; + +&can_clk { + clock-frequency = <40000000>; +}; + +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; + + channel0 { + status = "okay"; + phys = <&can_transceiver0>; + }; + + channel1 { + status = "okay"; + }; +}; + +&i2c0 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; +}; + +&pfc { + can_clk_pins: can-clk { + groups = "can_clk"; + function = "can_clk"; + }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; +}; diff --git a/dts/src/arm64/renesas/white-hawk-cpu-common.dtsi b/dts/src/arm64/renesas/white-hawk-cpu-common.dtsi new file mode 100644 index 0000000000..8ac17370ff --- /dev/null +++ b/dts/src/arm64/renesas/white-hawk-cpu-common.dtsi @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the common parts shared by the White Hawk CPU and + * White Hawk Single boards + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + aliases { + ethernet0 = &avb0; + serial0 = &hscif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:921600n8"; + }; + + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_1>; + label = "SW47"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_2>; + label = "SW48"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + label = "SW49"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + led-2 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led-3 { + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; + + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; +}; + +&dsi0 { + status = "okay"; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander_a: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + keys_pins: keys { + pins = "GP_5_0", "GP_5_1", "GP_5_2"; + bias-pull-up; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0x1200000>; + read-only; + }; + user@1200000 { + reg = <0x1200000 0x2e00000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk-csi-dsi.dtsi b/dts/src/arm64/renesas/white-hawk-csi-dsi.dtsi index f8537f7ea4..3006b0a64f 100644 --- a/dts/src/arm64/renesas/r8a779g0-white-hawk-csi-dsi.dtsi +++ b/dts/src/arm64/renesas/white-hawk-csi-dsi.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board + * Device Tree Source for the White Hawk CSI/DSI sub-board * * Copyright (C) 2022 Glider bv */ diff --git a/dts/src/arm64/renesas/r8a779g0-white-hawk-ethernet.dtsi b/dts/src/arm64/renesas/white-hawk-ethernet.dtsi index 4f411f95c6..a218fda337 100644 --- a/dts/src/arm64/renesas/r8a779g0-white-hawk-ethernet.dtsi +++ b/dts/src/arm64/renesas/white-hawk-ethernet.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) + * Device Tree Source for the White Hawk RAVB/Ethernet(1000Base-T1) * sub-board * * Copyright (C) 2022 Glider bv diff --git a/dts/src/arm64/rockchip/px30-ringneck-haikou.dts b/dts/src/arm64/rockchip/px30-ringneck-haikou.dts index 16798eb770..ae398acdcf 100644 --- a/dts/src/arm64/rockchip/px30-ringneck-haikou.dts +++ b/dts/src/arm64/rockchip/px30-ringneck-haikou.dts @@ -227,6 +227,7 @@ &uart5 { pinctrl-0 = <&uart5_xfer>; + rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/dts/src/arm64/rockchip/px30-ringneck.dtsi b/dts/src/arm64/rockchip/px30-ringneck.dtsi index 1239775583..bb1aea82e6 100644 --- a/dts/src/arm64/rockchip/px30-ringneck.dtsi +++ b/dts/src/arm64/rockchip/px30-ringneck.dtsi @@ -347,6 +347,12 @@ }; }; +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8>; status = "okay"; diff --git a/dts/src/arm64/rockchip/rk3328-rock-pi-e.dts b/dts/src/arm64/rockchip/rk3328-rock-pi-e.dts index 3cda6c627b..f09d60bbe6 100644 --- a/dts/src/arm64/rockchip/rk3328-rock-pi-e.dts +++ b/dts/src/arm64/rockchip/rk3328-rock-pi-e.dts @@ -148,7 +148,7 @@ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; clock_in_out = "input"; - phy-handle = <&rtl8211e>; + phy-handle = <&rtl8211>; phy-mode = "rgmii"; phy-supply = <&vcc_io>; pinctrl-names = "default"; @@ -165,7 +165,7 @@ #address-cells = <1>; #size-cells = <0>; - rtl8211e: ethernet-phy@1 { + rtl8211: ethernet-phy@1 { reg = <1>; pinctrl-0 = <ð_phy_int_pin>, <ð_phy_reset_pin>; pinctrl-names = "default"; diff --git a/dts/src/arm64/rockchip/rk3328.dtsi b/dts/src/arm64/rockchip/rk3328.dtsi index 7b4c15c4a9..b6f045069e 100644 --- a/dts/src/arm64/rockchip/rk3328.dtsi +++ b/dts/src/arm64/rockchip/rk3328.dtsi @@ -744,11 +744,20 @@ status = "disabled"; ports { - hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + hdmi_in_vop: endpoint { remote-endpoint = <&vop_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/dts/src/arm64/rockchip/rk3399-kobol-helios64.dts b/dts/src/arm64/rockchip/rk3399-kobol-helios64.dts index 9e3aec4440..dfb2a0bdea 100644 --- a/dts/src/arm64/rockchip/rk3399-kobol-helios64.dts +++ b/dts/src/arm64/rockchip/rk3399-kobol-helios64.dts @@ -22,9 +22,6 @@ ethernet0 = &gmac; mmc0 = &sdmmc; mmc1 = &sdhci; - spi1 = &spi1; - spi2 = &spi2; - spi5 = &spi5; }; avdd_0v9_s0: avdd-0v9-s0 { diff --git a/dts/src/arm64/rockchip/rk3399-orangepi.dts b/dts/src/arm64/rockchip/rk3399-orangepi.dts index e7551449e7..e26e2d8627 100644 --- a/dts/src/arm64/rockchip/rk3399-orangepi.dts +++ b/dts/src/arm64/rockchip/rk3399-orangepi.dts @@ -14,7 +14,7 @@ / { model = "Orange Pi RK3399 Board"; - compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399"; + compatible = "xunlong,rk3399-orangepi", "rockchip,rk3399"; aliases { ethernet0 = &gmac; diff --git a/dts/src/arm64/rockchip/rk3399-puma-haikou.dts b/dts/src/arm64/rockchip/rk3399-puma-haikou.dts index 18a98c4648..2c3984a880 100644 --- a/dts/src/arm64/rockchip/rk3399-puma-haikou.dts +++ b/dts/src/arm64/rockchip/rk3399-puma-haikou.dts @@ -273,11 +273,12 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + pinctrl-0 = <&uart0_xfer>; status = "okay"; }; &uart2 { + rts-gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/dts/src/arm64/rockchip/rk3399-rock-pi-4a.dts b/dts/src/arm64/rockchip/rk3399-rock-pi-4a.dts index d5df8939a6..c68f45849c 100644 --- a/dts/src/arm64/rockchip/rk3399-rock-pi-4a.dts +++ b/dts/src/arm64/rockchip/rk3399-rock-pi-4a.dts @@ -19,6 +19,6 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <10000000>; + spi-max-frequency = <108000000>; }; }; diff --git a/dts/src/arm64/rockchip/rk3399-rock-pi-4b.dts b/dts/src/arm64/rockchip/rk3399-rock-pi-4b.dts index bee6d75883..6ea3180e57 100644 --- a/dts/src/arm64/rockchip/rk3399-rock-pi-4b.dts +++ b/dts/src/arm64/rockchip/rk3399-rock-pi-4b.dts @@ -37,7 +37,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <10000000>; + spi-max-frequency = <108000000>; }; }; diff --git a/dts/src/arm64/rockchip/rk3399-rock-pi-4c.dts b/dts/src/arm64/rockchip/rk3399-rock-pi-4c.dts index de2ebe4cb4..5274938bf1 100644 --- a/dts/src/arm64/rockchip/rk3399-rock-pi-4c.dts +++ b/dts/src/arm64/rockchip/rk3399-rock-pi-4c.dts @@ -49,7 +49,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <10000000>; + spi-max-frequency = <108000000>; }; }; diff --git a/dts/src/arm64/rockchip/rk3399.dtsi b/dts/src/arm64/rockchip/rk3399.dtsi index 6e12c5a920..9d5f5b083e 100644 --- a/dts/src/arm64/rockchip/rk3399.dtsi +++ b/dts/src/arm64/rockchip/rk3399.dtsi @@ -38,6 +38,12 @@ serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; }; cpus { @@ -45,7 +51,7 @@ #size-cells = <0>; cpu-map { - cluster0 { + cluster0 { /* Cortex-A53 */ core0 { cpu = <&cpu_l0>; }; @@ -60,7 +66,7 @@ }; }; - cluster1 { + cluster1 { /* Cortex-A72 */ core0 { cpu = <&cpu_b0>; }; @@ -80,6 +86,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l1: cpu@1 { @@ -92,6 +105,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l2: cpu@2 { @@ -104,6 +124,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l3: cpu@3 { @@ -116,6 +143,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_b0: cpu@100 { @@ -128,6 +162,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b>; thermal-idle { #cooling-cells = <2>; @@ -146,6 +187,13 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b>; thermal-idle { #cooling-cells = <2>; @@ -154,6 +202,24 @@ }; }; + l2_cache_l: l2-cache-cluster0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + idle-states { entry-method = "psci"; @@ -1956,6 +2022,7 @@ hdmi: hdmi@ff940000 { compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; + reg-io-width = <4>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, @@ -1964,13 +2031,16 @@ <&cru PLL_VPLL>; clock-names = "iahb", "isfr", "cec", "grf", "ref"; power-domains = <&power RK3399_PD_HDCP>; - reg-io-width = <4>; rockchip,grf = <&grf>; #sound-dai-cells = <0>; status = "disabled"; ports { - hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -1983,6 +2053,10 @@ remote-endpoint = <&vopl_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/dts/src/arm64/rockchip/rk3566-anbernic-rg-arc-d.dts b/dts/src/arm64/rockchip/rk3566-anbernic-rg-arc-d.dts new file mode 100644 index 0000000000..ab83e8a616 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3566-anbernic-rg-arc-d.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3566-anbernic-rg-arc.dtsi" + +/ { + model = "Anbernic RG ARC-D"; + compatible = "anbernic,rg-arc-d", "rockchip,rk3566"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + mmc3 = &sdmmc2; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2m1_xfer>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@14 { + compatible = "goodix,gt927"; + reg = <0x14>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PB1 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-y; + touchscreen-size-x = <640>; + touchscreen-size-y = <480>; + }; +}; + +&pinctrl { + touchscreen { + touch_int: touch_int { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, + <&emmc_datastrobe>, <&emmc_rstnout>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; diff --git a/dts/src/arm64/rockchip/rk3566-anbernic-rg-arc-s.dts b/dts/src/arm64/rockchip/rk3566-anbernic-rg-arc-s.dts new file mode 100644 index 0000000000..6264a8c78d --- /dev/null +++ b/dts/src/arm64/rockchip/rk3566-anbernic-rg-arc-s.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3566-anbernic-rg-arc.dtsi" + +/ { + model = "Anbernic RG ARC-S"; + compatible = "anbernic,rg-arc-s", "rockchip,rk3566"; + + aliases { + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + mmc3 = &sdmmc2; + }; +}; diff --git a/dts/src/arm64/rockchip/rk3566-anbernic-rg-arc.dtsi b/dts/src/arm64/rockchip/rk3566-anbernic-rg-arc.dtsi new file mode 100644 index 0000000000..a4a60e4a53 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3566-anbernic-rg-arc.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3566-anbernic-rgxx3.dtsi" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_sys>; + pwms = <&pwm4 0 25000 0>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3472000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <117000>; + voltage-max-design-microvolt = <4172000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>, + <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>, + <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>, + <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>, + <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>, + <3400000 0>; + }; + + /* Channels reversed for both headphones and speakers. */ + sound { + compatible = "simple-audio-card"; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,aux-devs = <&spk_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amp OUTL", + "Internal Speakers", "Speaker Amp OUTR", + "Speaker Amp INL", "HPOL", + "Speaker Amp INR", "HPOR"; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + }; + + spk_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spk_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Speaker Amp"; + }; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <128000000>; +}; + +&dsi_dphy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + dsi0_in: port@0 { + reg = <0>; + dsi0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi0>; + }; + }; + + dsi0_out: port@1 { + reg = <1>; + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel: panel@0 { + compatible = "anbernic,rg-arc-panel", "sitronix,st7701"; + reg = <0>; + backlight = <&backlight>; + IOVCC-supply = <&vcc3v3_lcd0_n>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rotation = <90>; + VCC-supply = <&vcc3v3_lcd0_n>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +/* + * Device uses a non-standard six button layout for a gamepad with X, + * Y, and Z on the top row of buttons and A, B, and C under the bottom + * row. + */ +&gpio_keys_control { + button-a { + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; + label = "A"; + linux,code = <BTN_A>; + }; + + button-b { + gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + label = "B"; + linux,code = <BTN_B>; + }; + + button-c { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + label = "C"; + linux,code = <BTN_C>; + }; + + button-left { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-r1 { + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + label = "TR"; + linux,code = <BTN_TR>; + }; + + button-r2 { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = <BTN_TR2>; + }; + + button-right { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-x { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + label = "X"; + linux,code = <BTN_X>; + }; + + button-y { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + label = "Y"; + linux,code = <BTN_Y>; + }; + + button-z { + gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + label = "Z"; + linux,code = <BTN_Z>; + }; +}; + +&pinctrl { + audio-amplifier { + spk_amp_enable_h: spk-amp-enable-h { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-lcd { + lcd_rst: lcd-rst { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = + <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&rk817 { + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; +}; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = <ROCKCHIP_VOP2_EP_MIPI0>; + remote-endpoint = <&dsi0_in_vp1>; + }; +}; diff --git a/dts/src/arm64/rockchip/rk3566-anbernic-rg353x.dtsi b/dts/src/arm64/rockchip/rk3566-anbernic-rg353x.dtsi index 2a2821f4c5..63a18ff36c 100644 --- a/dts/src/arm64/rockchip/rk3566-anbernic-rg353x.dtsi +++ b/dts/src/arm64/rockchip/rk3566-anbernic-rg353x.dtsi @@ -8,11 +8,73 @@ #include "rk3566-anbernic-rgxx3.dtsi" / { + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_en>; + pinctrl-names = "default"; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = <ABS_X>; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = <ABS_RX>; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = <ABS_Y>; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = <ABS_RY>; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "right_x", "left_y", "right_y"; + #io-channel-cells = <1>; + io-channels = <&saradc 3>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + backlight: backlight { compatible = "pwm-backlight"; power-supply = <&vcc_sys>; pwms = <&pwm4 0 25000 0>; }; + + gpio_mux: mux-controller { + compatible = "gpio-mux"; + mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, + <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + #mux-control-cells = <0>; + }; }; &cru { @@ -83,6 +145,18 @@ linux,code = <BTN_DPAD_RIGHT>; }; + button-thumbl { + gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + label = "THUMBL"; + linux,code = <BTN_THUMBL>; + }; + + button-thumbr { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + label = "THUMBR"; + linux,code = <BTN_THUMBR>; + }; + button-y { gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; label = "WEST"; diff --git a/dts/src/arm64/rockchip/rk3566-anbernic-rg503.dts b/dts/src/arm64/rockchip/rk3566-anbernic-rg503.dts index c763c7f3b1..94e6dd61a2 100644 --- a/dts/src/arm64/rockchip/rk3566-anbernic-rg503.dts +++ b/dts/src/arm64/rockchip/rk3566-anbernic-rg503.dts @@ -17,6 +17,61 @@ mmc2 = &sdmmc2; }; + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_en>; + pinctrl-names = "default"; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = <ABS_X>; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = <ABS_RX>; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = <ABS_Y>; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = <ABS_RY>; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "right_x", "left_y", "right_y"; + #io-channel-cells = <1>; + io-channels = <&saradc 3>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + battery: battery { compatible = "simple-battery"; charge-full-design-microamp-hours = <3472000>; @@ -36,6 +91,13 @@ <3400000 0>; }; + gpio_mux: mux-controller { + compatible = "gpio-mux"; + mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, + <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + #mux-control-cells = <0>; + }; + gpio_spi: spi { compatible = "spi-gpio"; pinctrl-names = "default"; @@ -174,6 +236,18 @@ linux,code = <BTN_DPAD_RIGHT>; }; + button-thumbl { + gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + label = "THUMBL"; + linux,code = <BTN_THUMBL>; + }; + + button-thumbr { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + label = "THUMBR"; + linux,code = <BTN_THUMBR>; + }; + button-y { gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; label = "WEST"; diff --git a/dts/src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi b/dts/src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi index 8cbf3d9a4f..18b8c2e7be 100644 --- a/dts/src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi +++ b/dts/src/arm64/rockchip/rk3566-anbernic-rgxx3.dtsi @@ -14,51 +14,6 @@ stdout-path = "serial2:1500000n8"; }; - adc-joystick { - compatible = "adc-joystick"; - io-channels = <&adc_mux 0>, - <&adc_mux 1>, - <&adc_mux 2>, - <&adc_mux 3>; - pinctrl-0 = <&joy_mux_en>; - pinctrl-names = "default"; - poll-interval = <60>; - #address-cells = <1>; - #size-cells = <0>; - - axis@0 { - reg = <0>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <1023 15>; - linux,code = <ABS_X>; - }; - - axis@1 { - reg = <1>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <15 1023>; - linux,code = <ABS_RX>; - }; - - axis@2 { - reg = <2>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <15 1023>; - linux,code = <ABS_Y>; - }; - - axis@3 { - reg = <3>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <1023 15>; - linux,code = <ABS_RY>; - }; - }; - adc_keys: adc-keys { compatible = "adc-keys"; io-channels = <&saradc 0>; @@ -77,16 +32,6 @@ }; }; - adc_mux: adc-mux { - compatible = "io-channel-mux"; - channels = "left_x", "right_x", "left_y", "right_y"; - #io-channel-cells = <1>; - io-channels = <&saradc 3>; - io-channel-names = "parent"; - mux-controls = <&gpio_mux>; - settle-time-us = <100>; - }; - gpio_keys_control: gpio-keys-control { compatible = "gpio-keys"; pinctrl-0 = <&btn_pins_ctrl>; @@ -128,18 +73,6 @@ linux,code = <BTN_START>; }; - button-thumbl { - gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - label = "THUMBL"; - linux,code = <BTN_THUMBL>; - }; - - button-thumbr { - gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; - label = "THUMBR"; - linux,code = <BTN_THUMBR>; - }; - button-up { gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; label = "DPAD-UP"; @@ -172,13 +105,6 @@ }; }; - gpio_mux: mux-controller { - compatible = "gpio-mux"; - mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, - <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - #mux-control-cells = <0>; - }; - hdmi-con { compatible = "hdmi-connector"; ddc-i2c-bus = <&i2c5>; diff --git a/dts/src/arm64/rockchip/rk3566-pinetab2-v0.1.dts b/dts/src/arm64/rockchip/rk3566-pinetab2-v0.1.dts new file mode 100644 index 0000000000..5fe6ca5da9 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3566-pinetab2-v0.1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v0.1"; + compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc3v3_sys>; +}; diff --git a/dts/src/arm64/rockchip/rk3566-pinetab2-v2.0.dts b/dts/src/arm64/rockchip/rk3566-pinetab2-v2.0.dts new file mode 100644 index 0000000000..9349541cbb --- /dev/null +++ b/dts/src/arm64/rockchip/rk3566-pinetab2-v2.0.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v2.0"; + compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&gpio_keys { + pinctrl-0 = <&kb_id_det>, <&hall_int_l>; + + event-hall-sensor { + debounce-interval = <20>; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + label = "Hall Sensor"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + wakeup-event-action = <EV_ACT_DEASSERTED>; + wakeup-source; + }; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall { + hall_int_l: hall-int-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc_sys>; +}; diff --git a/dts/src/arm64/rockchip/rk3566-pinetab2.dtsi b/dts/src/arm64/rockchip/rk3566-pinetab2.dtsi new file mode 100644 index 0000000000..db40281eaf --- /dev/null +++ b/dts/src/arm64/rockchip/rk3566-pinetab2.dtsi @@ -0,0 +1,943 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> +#include "rk3566.dtsi" + +/ { + chassis-type = "tablet"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <25>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <297500>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <1750>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = <20 220>; + num-interpolated-steps = <200>; + default-brightness-level = <100>; + power-supply = <&vcc_sys>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <6000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4300000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>, + <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>, + <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>, + <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>, + <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>, + <3400000 0>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&kb_id_det>; + + tablet-mode-switch { + debounce-interval = <20>; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + label = "Tablet Mode"; + linux,input-type = <EV_SW>; + linux,code = <SW_TABLET_MODE>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + led-0 { + compatible = "regulator-led"; + vled-supply = <&vcc5v0_flashled>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_FLASH; + }; + + rk817-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_l>; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + + simple-audio-card,routing = + "MICR", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amplifier OUTL", + "Internal Speakers", "Speaker Amplifier OUTR", + "Speaker Amplifier INL", "HPOL", + "Speaker Amplifier INR", "HPOR"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + simple-audio-card,aux-devs = <&speaker_amp>; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + }; + + speaker_amp: speaker-amplifier { + compatible = "simple-audio-amplifier"; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctl>; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Speaker Amplifier"; + VCC-supply = <&vcc_bat>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_sd: vcc3v3-sd-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_flashled: vcc5v0-flashled-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led_en_h>; + regulator-name = "vcc5v0_flashled"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host0: vcc5v0-usb-host0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren1_h>; + regulator-name = "vcc5v0_usb_host0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host2: vcc5v0-usb-host2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren2_h>; + regulator-name = "vcc5v0_usb_host2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc_bat: vcc-bat-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_bat"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_bat>; + }; + + vdd1v2_dvp: vdd1v2-dvp-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd1v2_dvp"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; +}; + +&csi_dphy { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + clock-master; + #address-cells = <1>; + #size-cells = <0>; + + lcd: panel@0 { + compatible = "boe,th101mb31ig002-28a"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + rotation = <90>; + power-supply = <&vcc_3v3>; + + port@0 { + panel_in_dsi: endpoint@0 { + remote-endpoint = <&dsi0_out_con>; + }; + }; + }; +}; + +&dsi0_in { + dsi0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_con: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; +}; + +&dsi_dphy0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9_p>; + avdd-1v8-supply = <&vcc_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v_midu>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_0v9_p: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9_p"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_midu: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbus: OTG_SWITCH { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>; + AVDD28-supply = <&vcc3v3_pmu>; + VDDIO-supply = <&vcca1v8_pmu>; + irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; + + vcm@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + vcc-supply = <&vcc1v8_dvp>; + }; + + camera@36 { + compatible = "ovti,ov5648"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>; + + clocks = <&cru CLK_CIF_OUT>; + assigned-clocks = <&cru CLK_CIF_OUT>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vcc2v8_dvp>; + dvdd-supply = <&vdd1v2_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + + port { + endpoint { + data-lanes = <1 2>; + remote-endpoint = <0>; + link-frequencies = /bits/ 64 <210000000 168000000>; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + accelerometer@18 { + compatible = "silan,sc7a20"; + reg = <0x18>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int_l>; + st,drdy-int-pin = <1>; + vdd-supply = <&vcc_1v8>; + vddio-supply = <&vcc_1v8>; + mount-matrix = "1", "0", "0", + "0", "0", "1", + "0", "1", "0"; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&pinctrl { + camerab { + camerab_pdn_l: camerab-pdn-l { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camerab_rst_l: camerab-rst-l { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cameraf { + cameraf_pdn_l: cameraf-pdn-l { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cameraf_rst_l: cameraf-rst-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_led_en_h: flash-led-en-h { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + gsensor { + gsensor_int_l: gsensor-int-l { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + kb { + kb_id_det: kb-id-det { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_pwren_h: lcd-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_det_l: hp-det-l { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + spk_ctl: spk-ctl { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp { + tp_int_l_pmuio2: tp-int-l-pmuio2 { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + tp_rst_l_pmuio2: tp-rst-l-pmuio2 { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usbcc_int_l: usbcc-int-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren1_h: usb-host-pwren1-h { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren2_h: usb-host-pwren2-h { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + host_wake_wl: host-wake-wl { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 + &emmc_clk + &emmc_cmd + &emmc_datastrobe + &emmc_rstnout>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 + &sdmmc0_clk + &sdmmc0_cmd + &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 + &sdmmc1_cmd + &sdmmc1_clk>; + sd-uhs-sdr104; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_dual_io_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host0>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host2>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = <ROCKCHIP_VOP2_EP_MIPI0>; + remote-endpoint = <&dsi0_in_vp1>; + }; +}; diff --git a/dts/src/arm64/rockchip/rk3566-powkiddy-rgb10max3.dts b/dts/src/arm64/rockchip/rk3566-powkiddy-rgb10max3.dts new file mode 100644 index 0000000000..e5a474e681 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3566-powkiddy-rgb10max3.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3566-powkiddy-rk2023.dtsi" + +/ { + model = "Powkiddy RGB10MAX3"; + compatible = "powkiddy,rgb10max3", "rockchip,rk3566"; +}; + +&bluetooth { + compatible = "realtek,rtl8723ds-bt"; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <126400000>; +}; + +&dsi0 { + panel: panel@0 { + compatible = "powkiddy,rgb10max3-panel"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc3v3_lcd0_n>; + pinctrl-0 = <&lcd_rst>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + rotation = <270>; + vcc-supply = <&vcc3v3_lcd0_n>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&green_led { + default-state = "on"; + function = LED_FUNCTION_POWER; +}; + +&i2c0 { + vdd_cpu: regulator@40 { + compatible = "fcs,fan53555"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&leds { + amber_led: led-2 { + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_CHARGING; + max-brightness = <255>; + pwms = <&pwm0 0 25000 0>; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&red_led { + default-state = "off"; + function = LED_FUNCTION_STATUS; +}; diff --git a/dts/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts b/dts/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts index 0ac64f043b..1f567a14ac 100644 --- a/dts/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts +++ b/dts/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts @@ -37,3 +37,21 @@ }; }; }; + +&i2c0 { + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; diff --git a/dts/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts b/dts/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts index ba32d0793d..bc9933d9e2 100644 --- a/dts/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts +++ b/dts/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts @@ -36,3 +36,21 @@ }; }; }; + +&i2c0 { + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; diff --git a/dts/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi b/dts/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi index 0fa8f06f94..3ab751a01c 100644 --- a/dts/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi +++ b/dts/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi @@ -614,22 +614,6 @@ rockchip,sleep-filter-current-microamp = <100000>; }; }; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1390000>; - regulator-name = "vdd_cpu"; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc_sys>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; }; &i2c5 { @@ -805,7 +789,7 @@ uart-has-rtscts; status = "okay"; - bluetooth { + bluetooth: bluetooth { compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; diff --git a/dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts b/dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts index f9127ddfbb..7b5f3904ef 100644 --- a/dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts +++ b/dts/src/arm64/rockchip/rk3568-bpi-r2-pro.dts @@ -13,7 +13,7 @@ / { model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; - compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; + compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568"; aliases { ethernet0 = &gmac0; diff --git a/dts/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/src/arm64/rockchip/rk3568-qnap-ts433.dts new file mode 100644 index 0000000000..6a99816600 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3568-qnap-ts433.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Uwe Kleine-König + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "rk3568.dtsi" + +/ { + model = "Qnap TS-433-4G NAS System 4-Bay"; + compatible = "qnap,ts433", "rockchip,rk3568"; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + rx_delay = <0x2f>; + tx_delay = <0x3c>; + status = "okay"; +}; + +&i2c0 { + pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + + rtc@51 { + compatible = "microcrystal,rv8263"; + reg = <0x51>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x1 { + /* The downstream dts has: rockchip,bifurcation, XXX: find out what this is about */ + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + status = "okay"; +}; + +/* + * Pins available on CN3 connector at TTL voltage level (3V3). + * ,_ _. + * |1234| 1=TX 2=VCC + * `----' 3=RX 4=GND + */ +&uart2 { + status = "okay"; +}; diff --git a/dts/src/arm64/rockchip/rk356x.dtsi b/dts/src/arm64/rockchip/rk356x.dtsi index c19c0f1b37..92f96ec013 100644 --- a/dts/src/arm64/rockchip/rk356x.dtsi +++ b/dts/src/arm64/rockchip/rk356x.dtsi @@ -597,6 +597,7 @@ compatible = "rockchip,rk3568-vpu"; reg = <0x0 0xfdea0000 0x0 0x800>; interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vdpu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "hclk"; iommus = <&vdpu_mmu>; @@ -1123,7 +1124,7 @@ dmas = <&dmac1 4>, <&dmac1 5>; dma-names = "tx", "rx"; resets = <&cru SRST_M_I2S2_2CH>; - reset-names = "m"; + reset-names = "tx-m"; rockchip,grf = <&grf>; pinctrl-names = "default"; pinctrl-0 = <&i2s2m0_sclktx diff --git a/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi new file mode 100644 index 0000000000..c0d4a15323 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + aliases { + mmc0 = &sdhci; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_user: led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pinctrl { + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts index be6a4f4f90..46d5e21d4d 100644 --- a/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts +++ b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts @@ -6,18 +6,10 @@ /dts-v1/; #include "rk3588.dtsi" #include "rk3588-edgeble-neu6a.dtsi" +#include "rk3588-edgeble-neu6a-io.dtsi" / { model = "Edgeble Neu6A IO Board"; compatible = "edgeble,neural-compute-module-6a-io", "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; }; diff --git a/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi new file mode 100644 index 0000000000..963e880ccc --- /dev/null +++ b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie3x2: vcc3v3-pcie3x2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_vcc3v3_en>; + regulator-name = "vcc3v3_pcie3x2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_vcc3v3_en>; + regulator-name = "vcc3v3_pcie3x4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +/* ETH */ +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */ + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +/* B-Key and E-Key */ +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie3x2>; + status = "okay"; +}; + +/* M-Key */ +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_rst>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie3x4>; + status = "okay"; +}; + +&pinctrl { + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en { + rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_rst: pcie3x4-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* FAN */ +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* RS232 */ +&uart6 { + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* RS485 */ +&uart7 { + pinctrl-0 = <&uart7m2_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB hub, which is powered by vcc5v0_sys */ + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-wifi.dtso b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-wifi.dtso new file mode 100644 index 0000000000..e9a3855e87 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a-wifi.dtso @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + * + * DT-overlay for Edgeble On-SoM WiFi6/BT M.2 1216 modules, + * - AW-XM548NF + * - Intel 8260D2W + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +&{/} { + vcc3v3_pcie2x1l1: vcc3v3-pcie2x1l1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; /* WIFI_3V3_EN */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_vcc3v3_en>; + regulator-name = "vcc3v3_pcie2x1l1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +/* WiFi6 */ +&pcie2x1l1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; /* PCIE20_2_WIFI_PERSTn */ + vpcie3v3-supply = <&vcc3v3_pcie2x1l1>; + status = "okay"; +}; + +&pinctrl { + pcie2 { + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_vcc3v3_en: pcie2-1-vcc-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/dts/src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi index 727580aaa1..4c76a00b41 100644 --- a/dts/src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi +++ b/dts/src/arm64/rockchip/rk3588-edgeble-neu6a.dtsi @@ -3,29 +3,8 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ +#include "rk3588-edgeble-neu6a-common.dtsi" + / { compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; }; diff --git a/dts/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts b/dts/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts index 070baeb634..0d6f1be69a 100644 --- a/dts/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts +++ b/dts/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts @@ -6,84 +6,10 @@ /dts-v1/; #include "rk3588j.dtsi" #include "rk3588-edgeble-neu6b.dtsi" +#include "rk3588-edgeble-neu6a-io.dtsi" / { model = "Edgeble Neu6B IO Board"; compatible = "edgeble,neural-compute-module-6a-io", "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -/* FAN */ -&pwm2 { - pinctrl-0 = <&pwm2m1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - no-sdio; - no-mmc; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -/* RS232 */ -&uart6 { - pinctrl-0 = <&uart6m0_xfer>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* RS485 */ -&uart7 { - pinctrl-0 = <&uart7m2_xfer>; - pinctrl-names = "default"; - status = "okay"; }; diff --git a/dts/src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi b/dts/src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi index 017559bba3..c4634bc09f 100644 --- a/dts/src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi +++ b/dts/src/arm64/rockchip/rk3588-edgeble-neu6b.dtsi @@ -3,387 +3,8 @@ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. */ +#include "rk3588-edgeble-neu6a-common.dtsi" + / { compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; }; diff --git a/dts/src/arm64/rockchip/rk3588-nanopc-t6.dts b/dts/src/arm64/rockchip/rk3588-nanopc-t6.dts index 997b516c25..ad8e36a339 100644 --- a/dts/src/arm64/rockchip/rk3588-nanopc-t6.dts +++ b/dts/src/arm64/rockchip/rk3588-nanopc-t6.dts @@ -159,6 +159,29 @@ regulator-max-microvolt = <3300000>; vin-supply = <&vcc5v0_sys>; }; + + vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vdd_4g_3v3: vdd-4g-3v3-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pin_4g_lte_pwren>; + regulator-name = "vdd_4g_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; }; &combphy0_ps { @@ -504,6 +527,10 @@ }; usb { + pin_4g_lte_pwren: 4g-lte-pwren { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + typec5v_pwren: typec5v-pwren { rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -539,11 +566,12 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; no-mmc; no-sdio; sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; + vmmc-supply = <&vcc3v3_sd_s0>; vqmmc-supply = <&vccio_sd_s0>; status = "okay"; }; @@ -884,6 +912,7 @@ }; &u2phy2_host { + phy-supply = <&vdd_4g_3v3>; status = "okay"; }; diff --git a/dts/src/arm64/rockchip/rk3588-orangepi-5-plus.dts b/dts/src/arm64/rockchip/rk3588-orangepi-5-plus.dts index 3e660ff6cd..1b606ea5b6 100644 --- a/dts/src/arm64/rockchip/rk3588-orangepi-5-plus.dts +++ b/dts/src/arm64/rockchip/rk3588-orangepi-5-plus.dts @@ -444,7 +444,6 @@ &sdmmc { bus-width = <4>; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <150000000>; no-sdio; diff --git a/dts/src/arm64/rockchip/rk3588-quartzpro64.dts b/dts/src/arm64/rockchip/rk3588-quartzpro64.dts index 87a0abf95f..67414d72e2 100644 --- a/dts/src/arm64/rockchip/rk3588-quartzpro64.dts +++ b/dts/src/arm64/rockchip/rk3588-quartzpro64.dts @@ -429,7 +429,6 @@ &sdmmc { bus-width = <4>; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <150000000>; no-sdio; diff --git a/dts/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/src/arm64/rockchip/rk3588-rock-5b.dts index a0e303c3a1..1fe8b2a0ed 100644 --- a/dts/src/arm64/rockchip/rk3588-rock-5b.dts +++ b/dts/src/arm64/rockchip/rk3588-rock-5b.dts @@ -58,6 +58,13 @@ #cooling-cells = <2>; }; + rfkill { + compatible = "rfkill-gpio"; + label = "rfkill-pcie-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -371,7 +378,6 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; sd-uhs-sdr104; vmmc-supply = <&vcc_3v3_s3>; diff --git a/dts/src/arm64/rockchip/rk3588-tiger-haikou.dts b/dts/src/arm64/rockchip/rk3588-tiger-haikou.dts new file mode 100644 index 0000000000..d672198c6b --- /dev/null +++ b/dts/src/arm64/rockchip/rk3588-tiger-haikou.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include "rk3588-tiger.dtsi" + +/ { + model = "Theobroma Systems RK3588-Q7 SoM on Haikou devkit"; + compatible = "tsd,rk3588-tiger-haikou", "tsd,rk3588-tiger", "rockchip,rk3588"; + + aliases { + ethernet0 = &gmac0; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&haikou_keys_pin>; + + button-batlow-n { + label = "BATLOW#"; + linux,code = <KEY_BATTERY>; + gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + }; + + button-slp-btn-n { + label = "SLP_BTN#"; + linux,code = <KEY_SLEEP>; + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + button-wake-n { + label = "WAKE#"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-lid-btn-n { + label = "LID_BTN#"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + }; + + i2s3-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Haikou,I2S-codec"; + simple-audio-card,mclk-fs = <512>; + simple-audio-card,frame-master = <&sgtl5000_codec>; + simple-audio-card,bitclock-master = <&sgtl5000_codec>; + + sgtl5000_codec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + }; + + sgtl5000_clk: sgtl5000-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_low_noise: vcc3v3-low-noise-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_low_noise"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_baseboard: vcc5v0-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vddd_audio_1v6: vddd-audio-1v6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vddd_audio_1v6"; + regulator-boot-on; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; + pagesize = <8>; + size = <128>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sgtl5000_clk>; + #sound-dai-cells = <0>; + VDDA-supply = <&vcc3v3_low_noise>; + VDDIO-supply = <&vcc3v3_baseboard>; + VDDD-supply = <&vddd_audio_1v6>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2s3_2ch { + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + vpcie3v3-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&pinctrl { + haikou { + haikou_keys_pin: haikou-keys-pin { + rockchip,pins = + /* BATLOW# */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + /* SLP_BTN# */ + <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, + /* WAKE# */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, + /* LID_BTN */ + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdmmc { + /* while the same pin, sdmmc_det does not detect card changes */ + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m2_xfer>; + status = "okay"; +}; + +&uart5 { + rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* host0 on Q7_USB_P2, lower usb3 port */ +&usb_host0_ehci { + status = "okay"; +}; + +/* host0 on Q7_USB_P2, lower usb3 port */ +&usb_host0_ohci { + status = "okay"; +}; + +/* host1 on Q7_USB_P3, usb2 port */ +&usb_host1_ehci { + status = "okay"; +}; + +/* host1 on Q7_USB_P3, usb2 port */ +&usb_host1_ohci { + status = "okay"; +}; + +/* host2 on Q7_USB_P2, lower usb3 port */ +&usb_host2_xhci { + status = "okay"; +}; diff --git a/dts/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/src/arm64/rockchip/rk3588-tiger.dtsi new file mode 100644 index 0000000000..1eb2543a5f --- /dev/null +++ b/dts/src/arm64/rockchip/rk3588-tiger.dtsi @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + compatible = "tsd,rk3588-tiger", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + rtc0 = &rtc_twi; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&module_led_pin>; + + /* Named LED1 on the board */ + led-1 { + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + color = <LED_COLOR_ID_AMBER>; + }; + }; + + /* + * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE + * clock generator. + * The clock output is gated via the OE pin on the clock generator. + * This is modeled as a fixed-clock plus a gpio-gate-clock. + */ + pcie_refclk_gen: pcie-refclk-gen-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + pcie_refclk: pcie-refclk-clock { + compatible = "gpio-gate-clock"; + clocks = <&pcie_refclk_gen>; + #clock-cells = <0>; + enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v2_s3: vcc-1v2-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v2_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_baseboard>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_1v2_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_rx_bus2 + &gmac0_tx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + ð0_pins + ð_reset>; + tx_delay = <0x10>; + rx_delay = <0x10>; + snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 100000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1m0_xfer>; +}; + +&i2c1m0_xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB5 9 &pcfg_pull_none_drv_level_0>, + /* i2c1_sda_m0 */ + <0 RK_PB6 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c2 { + pinctrl-0 = <&i2c2m3_xfer>; + status = "okay"; +}; + +&i2c2m3_xfer { + rockchip,pins = + /* i2c2_scl_m3 */ + <1 RK_PC5 9 &pcfg_pull_none_drv_level_0>, + /* i2c2_sda_m3 */ + <1 RK_PC4 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c3 { + pinctrl-0 = <&i2c3m0_xfer>; +}; + +&i2c4 { + pinctrl-0 = <&i2c4m4_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c5 { + pinctrl-0 = <&i2c5m1_xfer>; +}; + +&i2c5m1_xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <4 RK_PB6 9 &pcfg_pull_none_drv_level_0>, + /* i2c5_sda_m1 */ + <4 RK_PB7 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c6 { + /* + * Mule-ATtiny can handle up to Fast mode Plus (1MHz) on I2C bus, + * but SOC can handle only up to (400kHz). + */ + clock-frequency = <400000>; + status = "okay"; + + fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c6m0_xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <0 RK_PD0 9 &pcfg_pull_none_drv_level_0>, + /* i2c6_sda_m0 */ + <0 RK_PC7 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c7 { + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c7m0_xfer { + rockchip,pins = + /* i2c7_scl_m0 */ + <1 RK_PD0 9 &pcfg_pull_none_drv_level_0>, + /* i2c7_sda_m0 */ + <1 RK_PD1 9 &pcfg_pull_none_drv_level_0>; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@6 { + /* KSZ9031 or KSZ9131 */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x6>; + clocks = <&cru REFCLKO25M_ETH0_OUT>; + }; +}; + +&pcie3x4 { + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + eth_reset: eth-reset { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + module_led_pin: module-led-pin { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-pwrseq = <&emmc_pwrseq>; + no-sdio; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; + supports-cqe; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <150000000>; + vqmmc-supply = <&vccio_sd_s0>; +}; + +&spi0 { + pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vcc_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-name = "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-name = "vdda_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-name = "vcca_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdda_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdda_0v75_s0: nldo-reg3 { + regulator-name = "vdda_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-name = "vdda_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +/* Mule-ATtiny UPDI */ +&uart4 { + pinctrl-0 = <&uart4m2_xfer>; + status = "okay"; +}; diff --git a/dts/src/arm64/rockchip/rk3588-toybrick-x0.dts b/dts/src/arm64/rockchip/rk3588-toybrick-x0.dts new file mode 100644 index 0000000000..9090c5c99f --- /dev/null +++ b/dts/src/arm64/rockchip/rk3588-toybrick-x0.dts @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + model = "Rockchip Toybrick TB-RK3588X Board"; + compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "Escape"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/dts/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/dts/src/arm64/rockchip/rk3588s-indiedroid-nova.dts index 3c22788868..ce8119cbb8 100644 --- a/dts/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +++ b/dts/src/arm64/rockchip/rk3588s-indiedroid-nova.dts @@ -141,6 +141,10 @@ status = "okay"; }; +&combphy2_psu { + status = "okay"; +}; + &cpu_l0 { cpu-supply = <&vdd_cpu_lit_s0>; }; @@ -842,3 +846,7 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/dts/src/arm64/rockchip/rk3588s-nanopi-r6c.dts b/dts/src/arm64/rockchip/rk3588s-nanopi-r6c.dts new file mode 100644 index 0000000000..497bbb5707 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3588s-nanopi-r6c.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588s-nanopi-r6s.dts" + +/ { + model = "FriendlyElec NanoPi R6C"; + compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s"; +}; + +&lan2_led { + label = "user_led"; +}; diff --git a/dts/src/arm64/rockchip/rk3588s-nanopi-r6s.dts b/dts/src/arm64/rockchip/rk3588s-nanopi-r6s.dts new file mode 100644 index 0000000000..4fa644ae51 --- /dev/null +++ b/dts/src/arm64/rockchip/rk3588s-nanopi-r6s.dts @@ -0,0 +1,764 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "rk3588s.dtsi" + +/ { + model = "FriendlyElec NanoPi R6S"; + compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Maskrom"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <1800>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button-user { + label = "User"; + linux,code = <BTN_1>; + gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + }; + + leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + label = "sys_led"; + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-1 { + label = "wan_led"; + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan1_led: led-2 { + label = "lan1_led"; + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-3 { + label = "lan2_led"; + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s0: vcc-3v3-s0-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vcc5v0_usb_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_host_20: vcc5v0-host-20-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + tx_delay = <0x42>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs200-1_8v; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + avdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "avdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "avdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/dts/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/src/arm64/rockchip/rk3588s-rock-5a.dts index 2002fd0221..00afb90d4e 100644 --- a/dts/src/arm64/rockchip/rk3588s-rock-5a.dts +++ b/dts/src/arm64/rockchip/rk3588s-rock-5a.dts @@ -366,7 +366,6 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <150000000>; no-sdio; diff --git a/dts/src/arm64/rockchip/rk3588s.dtsi b/dts/src/arm64/rockchip/rk3588s.dtsi index 36b1b7acfe..87b83c87bd 100644 --- a/dts/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/src/arm64/rockchip/rk3588s.dtsi @@ -519,6 +519,7 @@ vo1_grf: syscon@fd5a8000 { compatible = "rockchip,rk3588-vo-grf", "syscon"; reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <&cru PCLK_VO1GRF>; }; php_grf: syscon@fd5b0000 { @@ -586,6 +587,11 @@ }; }; + hdptxphy0_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + }; + ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; @@ -1704,7 +1710,6 @@ dmas = <&dmac1 0>, <&dmac1 1>; dma-names = "tx", "rx"; power-domains = <&power RK3588_PD_AUDIO>; - rockchip,trcm-sync-tx-only; pinctrl-names = "default"; pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk @@ -1725,7 +1730,6 @@ dmas = <&dmac1 2>, <&dmac1 3>; dma-names = "tx", "rx"; power-domains = <&power RK3588_PD_AUDIO>; - rockchip,trcm-sync-tx-only; pinctrl-names = "default"; pinctrl-0 = <&i2s3_lrck &i2s3_sclk @@ -2360,6 +2364,22 @@ #dma-cells = <1>; }; + hdptxphy_hdmi0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy0_grf>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/dts/src/arm64/st/stm32mp251.dtsi b/dts/src/arm64/st/stm32mp251.dtsi index 96859d098e..5dd4f3580a 100644 --- a/dts/src/arm64/st/stm32mp251.dtsi +++ b/dts/src/arm64/st/stm32mp251.dtsi @@ -52,6 +52,18 @@ compatible = "fixed-clock"; clock-frequency = <200000000>; }; + + ck_icn_p_vdec: ck-icn-p-vdec { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_p_venc: ck-icn-p-venc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; firmware { diff --git a/dts/src/arm64/st/stm32mp255.dtsi b/dts/src/arm64/st/stm32mp255.dtsi index e6fa596211..17f197c5b2 100644 --- a/dts/src/arm64/st/stm32mp255.dtsi +++ b/dts/src/arm64/st/stm32mp255.dtsi @@ -6,4 +6,21 @@ #include "stm32mp253.dtsi" / { + soc@0 { + rifsc: rifsc-bus@42080000 { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_icn_p_vdec>; + }; + + venc: venc@480e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x480e0000 0x800>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_icn_ls_mcu>; + }; + }; + }; }; diff --git a/dts/src/arm64/tesla/fsd.dtsi b/dts/src/arm64/tesla/fsd.dtsi index aaffb50b8b..047a83cee6 100644 --- a/dts/src/arm64/tesla/fsd.dtsi +++ b/dts/src/arm64/tesla/fsd.dtsi @@ -601,6 +601,7 @@ clocks = <&clock_peric PERIC_PCLK_UART0>, <&clock_peric PERIC_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; status = "disabled"; }; @@ -613,6 +614,7 @@ clocks = <&clock_peric PERIC_PCLK_UART1>, <&clock_peric PERIC_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; status = "disabled"; }; diff --git a/dts/src/arm64/ti/k3-am62-lp-sk.dts b/dts/src/arm64/ti/k3-am62-lp-sk.dts index 5e6feb8cd1..c4149059a4 100644 --- a/dts/src/arm64/ti/k3-am62-lp-sk.dts +++ b/dts/src/arm64/ti/k3-am62-lp-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM62x LP SK: https://www.ti.com/tool/SK-AM62-LP * - * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am62-main.dtsi b/dts/src/arm64/ti/k3-am62-main.dtsi index 464b7565d0..e9cffca073 100644 --- a/dts/src/arm64/ti/k3-am62-main.dtsi +++ b/dts/src/arm64/ti/k3-am62-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -42,9 +42,8 @@ }; }; - main_conf: syscon@100000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; + main_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x00100000 0x20000>; @@ -559,10 +558,9 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 6>; assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,trm-icp = <0x2>; - bus-width = <8>; ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; @@ -580,7 +578,8 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -592,8 +591,6 @@ ti,itap-del-sel-sd-hs = <0x1>; ti,itap-del-sel-sdr12 = <0xa>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; - bus-width = <4>; status = "disabled"; }; @@ -604,7 +601,8 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0x0>; @@ -616,7 +614,6 @@ ti,itap-del-sel-sd-hs = <0xa>; ti,itap-del-sel-sdr12 = <0xa>; ti,itap-del-sel-sdr25 = <0x1>; - ti,clkbuf-sel = <0x7>; status = "disabled"; }; @@ -640,6 +637,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -663,6 +662,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -779,9 +780,10 @@ <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&dss_vp1_clk>, diff --git a/dts/src/arm64/ti/k3-am62-mcu.dtsi b/dts/src/arm64/ti/k3-am62-mcu.dtsi index 0e0b234581..e66d486ef1 100644 --- a/dts/src/arm64/ti/k3-am62-mcu.dtsi +++ b/dts/src/arm64/ti/k3-am62-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/dts/src/arm64/ti/k3-am62-phycore-som.dtsi b/dts/src/arm64/ti/k3-am62-phycore-som.dtsi index aa43e7407e..43488cc8bc 100644 --- a/dts/src/arm64/ti/k3-am62-phycore-som.dtsi +++ b/dts/src/arm64/ti/k3-am62-phycore-som.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> * * Product homepage: @@ -317,7 +317,6 @@ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; non-removable; status = "okay"; diff --git a/dts/src/arm64/ti/k3-am62-thermal.dtsi b/dts/src/arm64/ti/k3-am62-thermal.dtsi index a358757e26..12ba833002 100644 --- a/dts/src/arm64/ti/k3-am62-thermal.dtsi +++ b/dts/src/arm64/ti/k3-am62-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/dts/src/arm64/ti/k3-am62-verdin-dahlia.dtsi b/dts/src/arm64/ti/k3-am62-verdin-dahlia.dtsi index bf6d27e70b..6c4cec8728 100644 --- a/dts/src/arm64/ti/k3-am62-verdin-dahlia.dtsi +++ b/dts/src/arm64/ti/k3-am62-verdin-dahlia.dtsi @@ -185,7 +185,6 @@ /* Verdin SD_1 */ &sdhci1 { - ti,driver-strength-ohm = <33>; status = "okay"; }; diff --git a/dts/src/arm64/ti/k3-am62-verdin-dev.dtsi b/dts/src/arm64/ti/k3-am62-verdin-dev.dtsi index 680071688d..be62648e78 100644 --- a/dts/src/arm64/ti/k3-am62-verdin-dev.dtsi +++ b/dts/src/arm64/ti/k3-am62-verdin-dev.dtsi @@ -206,7 +206,6 @@ /* Verdin SD_1 */ &sdhci1 { - ti,driver-strength-ohm = <33>; status = "okay"; }; diff --git a/dts/src/arm64/ti/k3-am62-verdin-mallow.dtsi b/dts/src/arm64/ti/k3-am62-verdin-mallow.dtsi index 17b93534f6..77b1beb638 100644 --- a/dts/src/arm64/ti/k3-am62-verdin-mallow.dtsi +++ b/dts/src/arm64/ti/k3-am62-verdin-mallow.dtsi @@ -127,6 +127,16 @@ <&pinctrl_qspi1_cs2_gpio>; cs-gpios = <0>, <&main_gpio0 12 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; + interrupt-parent = <&main_gpio1>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; }; /* Verdin UART_3 */ diff --git a/dts/src/arm64/ti/k3-am62-verdin-wifi.dtsi b/dts/src/arm64/ti/k3-am62-verdin-wifi.dtsi index a6808b10c7..4768ef42c4 100644 --- a/dts/src/arm64/ti/k3-am62-verdin-wifi.dtsi +++ b/dts/src/arm64/ti/k3-am62-verdin-wifi.dtsi @@ -26,7 +26,6 @@ mmc-pwrseq = <&wifi_pwrseq>; non-removable; ti,fails-without-test-cd; - ti,driver-strength-ohm = <50>; vmmc-supply = <®_3v3>; status = "okay"; }; diff --git a/dts/src/arm64/ti/k3-am62-verdin.dtsi b/dts/src/arm64/ti/k3-am62-verdin.dtsi index 6a06724b6d..e8d8857ad5 100644 --- a/dts/src/arm64/ti/k3-am62-verdin.dtsi +++ b/dts/src/arm64/ti/k3-am62-verdin.dtsi @@ -42,6 +42,22 @@ usb1 = &usb1; }; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_id>; + id-gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb0_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb0_ep>; + }; + }; + }; + verdin_gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -151,6 +167,18 @@ vin-supply = <®_sd_3v3_1v8>; }; + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_en>; + enable-active-high; + /* Verdin USB_1_EN (SODIMM 155) */ + gpio = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_1_EN"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -436,6 +464,13 @@ >; }; + /* Verdin USB_1_EN */ + pinctrl_usb0_en: main-gpio1-50-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0254, PIN_INPUT, 7) /* (C20) USB0_DRVVBUS.GPIO1_50 */ /* SODIMM 155 */ + >; + }; + /* On-module I2C - PMIC_I2C */ pinctrl_i2c0: main-i2c0-default-pins { pinctrl-single,pins = < @@ -660,13 +695,6 @@ >; }; - /* Verdin USB_1 */ - pinctrl_usb0: main-usb0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ - >; - }; - /* Verdin USB_2 */ pinctrl_usb1: main-usb1-default-pins { pinctrl-single,pins = < @@ -1013,7 +1041,7 @@ "", "", "SODIMM_17", - "", /* 50 */ + "SODIMM_155", /* 50 */ "", "", "", @@ -1118,7 +1146,7 @@ regulator-always-on; regulator-boot-on; regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; + regulator-min-microvolt = <750000>; regulator-name = "+VDD_CORE (PMIC BUCK1)"; }; @@ -1407,7 +1435,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0>; non-removable; - ti,driver-strength-ohm = <50>; status = "okay"; }; @@ -1416,7 +1443,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1>; disable-wp; - ti,driver-strength-ohm = <50>; vmmc-supply = <®_sdhc1_vmmc>; vqmmc-supply = <®_sdhc1_vqmmc>; status = "disabled"; @@ -1428,11 +1454,16 @@ status = "disabled"; }; -/* TODO: role swich using ID pin */ &usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>; + adp-disable; + usb-role-switch; status = "disabled"; + + port { + usb0_ep: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; }; /* Verdin USB_2 */ diff --git a/dts/src/arm64/ti/k3-am62-wakeup.dtsi b/dts/src/arm64/ti/k3-am62-wakeup.dtsi index fef76f52a5..23ce1bfda8 100644 --- a/dts/src/arm64/ti/k3-am62-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-am62-wakeup.dtsi @@ -1,10 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/bus/ti-sysc.h> + &cbass_wakeup { wkup_conf: syscon@43000000 { bootph-all; @@ -21,14 +23,34 @@ }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x00 0x2b300050 0x00 0x4>, + <0x00 0x2b300054 0x00 0x4>, + <0x00 0x2b300058 0x00 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x0 0x100>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { diff --git a/dts/src/arm64/ti/k3-am62.dtsi b/dts/src/arm64/ti/k3-am62.dtsi index f1e15206e1..f0781f2bea 100644 --- a/dts/src/arm64/ti/k3-am62.dtsi +++ b/dts/src/arm64/ti/k3-am62.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62 SoC Family * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/dts/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso b/dts/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso index 5e80ca7033..3b4643b7d1 100644 --- a/dts/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso +++ b/dts/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso b/dts/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso index 5e1cbbc27c..81a2763d43 100644 --- a/dts/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso +++ b/dts/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Technexion TEVI-OV5640-*-RPI - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am625-beagleplay.dts b/dts/src/arm64/ti/k3-am625-beagleplay.dts index eadbdd9ffe..a34e0df2ab 100644 --- a/dts/src/arm64/ti/k3-am625-beagleplay.dts +++ b/dts/src/arm64/ti/k3-am625-beagleplay.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * https://beagleplay.org/ * - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation */ /dts-v1/; @@ -29,7 +29,6 @@ i2c3 = &main_i2c3; i2c4 = &wkup_i2c0; i2c5 = &mcu_i2c0; - mdio-gpio0 = &mdio0; mmc0 = &sdhci0; mmc1 = &sdhci1; mmc2 = &sdhci2; @@ -231,27 +230,6 @@ }; }; - /* Workaround for errata i2329 - just use mdio bitbang */ - mdio0: mdio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio0_pins_default>; - gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */ - <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - }; - - cpsw3g_phy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <25>; - reset-deassert-us = <60000>; /* T2 */ - }; - }; }; &main_pmx0 { @@ -312,8 +290,8 @@ mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ - AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ + AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ >; }; @@ -573,11 +551,13 @@ }; &usbss0 { + bootph-all; ti,vbus-divider; status = "okay"; }; &usb0 { + bootph-all; dr_mode = "peripheral"; }; @@ -611,8 +591,20 @@ }; &cpsw3g_mdio { - /* Workaround for errata i2329 - Use mdio bitbang */ - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <25>; + reset-deassert-us = <60000>; /* T2 */ + }; }; &main_gpio0 { @@ -827,7 +819,6 @@ bootph-all; pinctrl-names = "default"; pinctrl-0 = <&emmc_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; status = "okay"; }; @@ -840,7 +831,6 @@ vmmc-supply = <&vdd_3v3_sd>; vqmmc-supply = <&vdd_sd_dv>; - ti,driver-strength-ohm = <50>; disable-wp; cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; cd-debounce-delay-ms = <100>; @@ -852,12 +842,10 @@ vmmc-supply = <&wlan_en>; pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; - bus-width = <4>; non-removable; ti,fails-without-test-cd; cap-power-off-card; keep-power-in-suspend; - ti,driver-strength-ohm = <50>; assigned-clocks = <&k3_clks 157 158>; assigned-clock-parents = <&k3_clks 157 160>; #address-cells = <1>; diff --git a/dts/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts b/dts/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts index 4bc0134c98..a83a904978 100644 --- a/dts/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/dts/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> * * Product homepage: @@ -222,6 +222,7 @@ cpsw3g_phy3: ethernet-phy@3 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <3>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; @@ -333,7 +334,6 @@ vqmmc-supply = <&vddshv5_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; no-1-8-v; status = "okay"; diff --git a/dts/src/arm64/ti/k3-am625-sk.dts b/dts/src/arm64/ti/k3-am625-sk.dts index b18092497c..ae81ebb39d 100644 --- a/dts/src/arm64/ti/k3-am625-sk.dts +++ b/dts/src/arm64/ti/k3-am625-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM625 SK: https://www.ti.com/lit/zip/sprr448 * - * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am625.dtsi b/dts/src/arm64/ti/k3-am625.dtsi index 4193c2b3ee..4014add632 100644 --- a/dts/src/arm64/ti/k3-am625.dtsi +++ b/dts/src/arm64/ti/k3-am625.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC family in Quad core configuration * * TRM: https://www.ti.com/lit/pdf/spruiv7 * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am62a-main.dtsi b/dts/src/arm64/ti/k3-am62a-main.dtsi index f0b8c9ab14..aa1e057082 100644 --- a/dts/src/arm64/ti/k3-am62a-main.dtsi +++ b/dts/src/arm64/ti/k3-am62a-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family Main Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -42,9 +42,8 @@ }; }; - main_conf: syscon@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x20000>; + main_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x20000>; @@ -536,6 +535,24 @@ status = "disabled"; }; + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + bus-width = <8>; + mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-hs200 = <0x6>; + status = "disabled"; + }; + sdhci1: mmc@fa00000 { compatible = "ti,am62-sdhci"; reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; @@ -543,7 +560,8 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; @@ -555,8 +573,30 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - ti,clkbuf-sel = <0x7>; + no-1-8-v; + status = "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; no-1-8-v; status = "disabled"; }; @@ -985,4 +1025,30 @@ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + dss: dss@30200000 { + compatible = "ti,am62a7-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; diff --git a/dts/src/arm64/ti/k3-am62a-mcu.dtsi b/dts/src/arm64/ti/k3-am62a-mcu.dtsi index a6d16a9408..8c36e56f41 100644 --- a/dts/src/arm64/ti/k3-am62a-mcu.dtsi +++ b/dts/src/arm64/ti/k3-am62a-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM625 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/dts/src/arm64/ti/k3-am62a-thermal.dtsi b/dts/src/arm64/ti/k3-am62a-thermal.dtsi index 85ce545633..c7486fb2a5 100644 --- a/dts/src/arm64/ti/k3-am62a-thermal.dtsi +++ b/dts/src/arm64/ti/k3-am62a-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/dts/src/arm64/ti/k3-am62a-wakeup.dtsi b/dts/src/arm64/ti/k3-am62a-wakeup.dtsi index 4e8279fa01..f7bec48470 100644 --- a/dts/src/arm64/ti/k3-am62a-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-am62a-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { diff --git a/dts/src/arm64/ti/k3-am62a.dtsi b/dts/src/arm64/ti/k3-am62a.dtsi index 61a210ecd5..b1b8846002 100644 --- a/dts/src/arm64/ti/k3-am62a.dtsi +++ b/dts/src/arm64/ti/k3-am62a.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A SoC Family * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/dts/src/arm64/ti/k3-am62a7-sk.dts b/dts/src/arm64/ti/k3-am62a7-sk.dts index 7b71425862..f241637a56 100644 --- a/dts/src/arm64/ti/k3-am62a7-sk.dts +++ b/dts/src/arm64/ti/k3-am62a7-sk.dts @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * AM62A SK: https://www.ti.com/lit/zip/sprr459 * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -20,6 +20,7 @@ serial0 = &wkup_uart0; serial2 = &main_uart0; serial3 = &main_uart1; + mmc0 = &sdhci0; mmc1 = &sdhci1; }; @@ -132,6 +133,18 @@ clock-frequency = <12288000>; }; + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + codec_audio: sound { compatible = "simple-audio-card"; simple-audio-card,name = "AM62Ax-SKEVM"; @@ -181,6 +194,39 @@ }; &main_pmx0 { + main_dss0_pins_default: main-dss0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */ + AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */ + AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */ + AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */ + AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */ + AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */ + AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */ + AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */ + AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */ + AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */ + AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */ + AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */ + AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */ + AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */ + AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */ + AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */ + AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */ + AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */ + AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */ + AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */ + AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */ + AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */ + AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */ + AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */ + AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */ + AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ @@ -218,6 +264,22 @@ >; }; + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */ + AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ @@ -466,6 +528,36 @@ "CSI_EN", "AUTO_100M_1000M_CONFIG", "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST"; }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_i2c2 { @@ -475,13 +567,21 @@ clock-frequency = <400000>; }; +&sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; +}; + &sdhci1 { /* SD/MMC */ status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -583,3 +683,20 @@ tx-num-evt = <32>; rx-num-evt = <32>; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; diff --git a/dts/src/arm64/ti/k3-am62a7.dtsi b/dts/src/arm64/ti/k3-am62a7.dtsi index 58f1c43edc..f86a23404e 100644 --- a/dts/src/arm64/ti/k3-am62a7.dtsi +++ b/dts/src/arm64/ti/k3-am62a7.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62A7 SoC family in Quad core configuration * * TRM: https://www.ti.com/lit/zip/spruj16 * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am62p-main.dtsi b/dts/src/arm64/ti/k3-am62p-main.dtsi index 4c51bae06b..7337a9e135 100644 --- a/dts/src/arm64/ti/k3-am62p-main.dtsi +++ b/dts/src/arm64/ti/k3-am62p-main.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P main domain peripherals - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_main { @@ -158,6 +158,43 @@ }; }; + dmss_csi: bus@4e000000 { + compatible = "simple-bus"; + ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ti,sci-dev-id = <198>; + + inta_main_dmss_csi: interrupt-controller@4e400000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x4e400000 0x00 0x8000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <200>; + ti,interrupt-ranges = <0 237 8>; + ti,unmapped-event-sources = <&main_bcdma_csi>; + }; + + main_bcdma_csi: dma-controller@4e230000 { + compatible = "ti,am62a-dmss-bcdma-csirx"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x8000>, + <0x00 0x4e100000 0x00 0x10000>; + reg-names = "gcfg", "rchanrt", "ringrt"; + #dma-cells = <3>; + msi-parent = <&inta_main_dmss_csi>; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <199>; + ti,sci-rm-range-rchan = <0x21>; + }; + }; + dmsc: system-controller@44043000 { compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -534,7 +571,21 @@ clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 2>; assigned-clock-parents = <&k3_clks 57 4>; - ti,otap-del-sel-legacy = <0x0>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + ti,clkbuf-sel = <0x7>; + ti,strobe-sel = <0x77>; + ti,trm-icp = <0x8>; + ti,otap-del-sel-legacy = <0x1>; + ti,otap-del-sel-mmc-hs = <0x1>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; status = "disabled"; }; @@ -545,7 +596,19 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -556,7 +619,19 @@ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -891,4 +966,73 @@ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30102000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5000 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30101000 0x00 0x1000>; + clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30110000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vpu: video-codec@30210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x30210000 0x00 0x10000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 204 2>; + power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + }; }; diff --git a/dts/src/arm64/ti/k3-am62p-mcu.dtsi b/dts/src/arm64/ti/k3-am62p-mcu.dtsi index c4b0b91d70..b973b550eb 100644 --- a/dts/src/arm64/ti/k3-am62p-mcu.dtsi +++ b/dts/src/arm64/ti/k3-am62p-mcu.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P MCU domain peripherals - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { @@ -187,6 +187,8 @@ ranges = <0x79000000 0x00 0x79000000 0x8000>, <0x79020000 0x00 0x79020000 0x8000>; power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + mcu_r5fss0_core0: r5f@79000000 { compatible = "ti,am62-r5f"; reg = <0x79000000 0x00008000>, diff --git a/dts/src/arm64/ti/k3-am62p-thermal.dtsi b/dts/src/arm64/ti/k3-am62p-thermal.dtsi index 85ce545633..c7486fb2a5 100644 --- a/dts/src/arm64/ti/k3-am62p-thermal.dtsi +++ b/dts/src/arm64/ti/k3-am62p-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/dts/src/arm64/ti/k3-am62p-wakeup.dtsi b/dts/src/arm64/ti/k3-am62p-wakeup.dtsi index 19f42b3939..a84756c336 100644 --- a/dts/src/arm64/ti/k3-am62p-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-am62p-wakeup.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P wakeup domain peripherals - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { @@ -78,6 +78,7 @@ ranges = <0x78000000 0x00 0x78000000 0x8000>, <0x78100000 0x00 0x78100000 0x8000>; power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; wkup_r5fss0_core0: r5f@78000000 { compatible = "ti,am62-r5f"; diff --git a/dts/src/arm64/ti/k3-am62p.dtsi b/dts/src/arm64/ti/k3-am62p.dtsi index 84ffe7b9dc..94babc4125 100644 --- a/dts/src/arm64/ti/k3-am62p.dtsi +++ b/dts/src/arm64/ti/k3-am62p.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM62P SoC Family * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> @@ -71,7 +71,7 @@ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ - <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ diff --git a/dts/src/arm64/ti/k3-am62p5-sk.dts b/dts/src/arm64/ti/k3-am62p5-sk.dts index 1773c05f75..e86f34e835 100644 --- a/dts/src/arm64/ti/k3-am62p5-sk.dts +++ b/dts/src/arm64/ti/k3-am62p5-sk.dts @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P5-SK - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Schematics: https://www.ti.com/lit/zip/sprr487 */ @@ -413,6 +413,7 @@ status = "okay"; ti,driver-strength-ohm = <50>; disable-wp; + bootph-all; }; &sdhci1 { @@ -422,9 +423,7 @@ vqmmc-supply = <&vddshv_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; - no-1-8-v; bootph-all; }; @@ -445,6 +444,10 @@ }; &cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + status = "okay"; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; diff --git a/dts/src/arm64/ti/k3-am62p5.dtsi b/dts/src/arm64/ti/k3-am62p5.dtsi index 50147bb63e..41f479dca4 100644 --- a/dts/src/arm64/ti/k3-am62p5.dtsi +++ b/dts/src/arm64/ti/k3-am62p5.dtsi @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree file for the AM62P5 SoC family (quad core) - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ * * TRM: https://www.ti.com/lit/pdf/spruj83 */ diff --git a/dts/src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso b/dts/src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso new file mode 100644 index 0000000000..f0b2fd4165 --- /dev/null +++ b/dts/src/arm64/ti/k3-am62x-phyboard-lyra-gpio-fan.dtso @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 PHYTEC America LLC + * Author: Garrett Giordano <ggiordano@phytec.com> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> +#include "k3-pinctrl.h" + +&{/} { + fan: gpio-fan { + compatible = "gpio-fan"; + gpio-fan,speed-map = <0 0 8600 1>; + gpios = <&main_gpio0 40 GPIO_ACTIVE_LOW>; + #cooling-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_fan_pins_default>; + }; +}; + +&main_pmx0 { + gpio_fan_pins_default: gpio-fan-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0a4, PIN_OUTPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ + >; + }; +}; + +&thermal_zones { + main0_thermal: main0-thermal { + trips { + main0_thermal_trip0: main0-thermal-trip { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&main0_thermal_trip0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/dts/src/arm64/ti/k3-am62x-sk-common.dtsi b/dts/src/arm64/ti/k3-am62x-sk-common.dtsi index 33768c02d8..3c45782ab2 100644 --- a/dts/src/arm64/ti/k3-am62x-sk-common.dtsi +++ b/dts/src/arm64/ti/k3-am62x-sk-common.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Common dtsi for AM62x SK and derivatives * - * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/leds/common.h> @@ -411,7 +411,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -421,7 +420,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -460,6 +458,7 @@ }; &usbss0 { + bootph-all; status = "okay"; ti,vbus-divider; }; @@ -470,6 +469,7 @@ }; &usb0 { + bootph-all; #address-cells = <1>; #size-cells = <0>; usb-role-switch; diff --git a/dts/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso b/dts/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso index 6f4cd73c2f..76ca02127f 100644 --- a/dts/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso +++ b/dts/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * IMX219 (RPi v2) Camera Module - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso b/dts/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso index 9323a4b383..ccc7f5e431 100644 --- a/dts/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso +++ b/dts/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso b/dts/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso index dcaa33a4c8..4eaf9d757d 100644 --- a/dts/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso +++ b/dts/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso @@ -1,7 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Technexion TEVI-OV5640-*-RPI - OV5640 camera module - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso b/dts/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso index 43a0ddc123..18c3082f68 100644 --- a/dts/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso +++ b/dts/src/arm64/ti/k3-am62x-sk-hdmi-audio.dtso @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * Audio playback via HDMI for AM625-SK and AM62-LP SK. * @@ -6,7 +6,7 @@ * AM625 SK: https://www.ti.com/tool/SK-AM62 * AM62-LP SK: https://www.ti.com/tool/SK-AM62-LP * - * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am64-main.dtsi b/dts/src/arm64/ti/k3-am64-main.dtsi index e348114f42..6f9aa5e021 100644 --- a/dts/src/arm64/ti/k3-am64-main.dtsi +++ b/dts/src/arm64/ti/k3-am64-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM642 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy-cadence.h> @@ -51,10 +51,11 @@ reg = <0x00000014 0x4>; }; - serdes_ln_ctrl: mux-controller { - compatible = "mmio-mux"; + serdes_ln_ctrl: mux-controller@4080 { + compatible = "reg-mux"; + reg = <0x4080 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ + mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ }; phy_gmii_sel: phy@4044 { @@ -626,13 +627,18 @@ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; clock-names = "clk_ahb", "clk_xin"; + bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x2>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x7>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; status = "disabled"; }; @@ -643,15 +649,19 @@ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; clock-names = "clk_ahb", "clk_xin"; - ti,trm-icp = <0x2>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x6>; ti,otap-del-sel-ddr50 = <0x9>; - ti,clkbuf-sel = <0x7>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -1041,25 +1051,6 @@ status = "disabled"; }; - pcie0_ep: pcie-ep@f102000 { - compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x0f102000 0x00 0x1000>, - <0x00 0x0f100000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; - max-link-speed = <2>; - num-lanes = <1>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "fck"; - max-functions = /bits/ 8 <1>; - status = "disabled"; - }; - epwm0: pwm@23000000 { compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; @@ -1244,6 +1235,18 @@ }; }; + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1385,6 +1388,18 @@ }; }; + icssg1_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; diff --git a/dts/src/arm64/ti/k3-am64-mcu.dtsi b/dts/src/arm64/ti/k3-am64-mcu.dtsi index b9508072be..ec17285869 100644 --- a/dts/src/arm64/ti/k3-am64-mcu.dtsi +++ b/dts/src/arm64/ti/k3-am64-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM64 SoC Family MCU Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/dts/src/arm64/ti/k3-am64-phycore-som.dtsi b/dts/src/arm64/ti/k3-am64-phycore-som.dtsi index 1678e74cb7..125e507966 100644 --- a/dts/src/arm64/ti/k3-am64-phycore-som.dtsi +++ b/dts/src/arm64/ti/k3-am64-phycore-som.dtsi @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com * Author: Matt McKee <mmckee@phytec.com> * - * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> * * Product homepage: @@ -318,3 +318,10 @@ disable-wp; keep-power-in-suspend; }; + +&tscadc0 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; diff --git a/dts/src/arm64/ti/k3-am64-thermal.dtsi b/dts/src/arm64/ti/k3-am64-thermal.dtsi index 036db56ba7..b1cd554242 100644 --- a/dts/src/arm64/ti/k3-am64-thermal.dtsi +++ b/dts/src/arm64/ti/k3-am64-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/dts/src/arm64/ti/k3-am64.dtsi b/dts/src/arm64/ti/k3-am64.dtsi index 0187c42aed..74e56cc68d 100644 --- a/dts/src/arm64/ti/k3-am64.dtsi +++ b/dts/src/arm64/ti/k3-am64.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM642 SoC Family * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/dts/src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso b/dts/src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso new file mode 100644 index 0000000000..af2fd3e744 --- /dev/null +++ b/dts/src/arm64/ti/k3-am642-evm-icssg1-dualemac.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling 2nd ICSSG1 port on AM642 EVM + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/icssg1-eth/ethernet-ports/port@1"; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mdio_mux>; + mdio-parent-bus = <&icssg1_mdio>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + icssg1_phy2: ethernet-phy@3 { + reg = <3>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mdio_mux_1 { + status = "disabled"; +}; + +&icssg1_eth { + pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>; +}; + +&icssg1_emac1 { + status = "okay"; + phy-handle = <&icssg1_phy2>; + phy-mode = "rgmii-id"; +}; diff --git a/dts/src/arm64/ti/k3-am642-evm.dts b/dts/src/arm64/ti/k3-am642-evm.dts index 8c5651d2cf..53fe1d065d 100644 --- a/dts/src/arm64/ti/k3-am642-evm.dts +++ b/dts/src/arm64/ti/k3-am642-evm.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -32,6 +32,7 @@ mmc1 = &sdhci1; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; + ethernet2 = &icssg1_emac0; }; memory@80000000 { @@ -198,7 +199,7 @@ mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; }; - mdio-mux-1 { + mdio_mux_1: mdio-mux-1 { compatible = "mdio-mux-multiplexer"; mux-controls = <&mdio_mux>; mdio-parent-bus = <&cpsw3g_mdio>; @@ -229,6 +230,64 @@ max-bitrate = <5000000>; standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; }; + + icssg1_eth: icssg1-eth { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii1_pins_default>; + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg = <1>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + }; + }; }; &main_pmx0 { @@ -383,6 +442,30 @@ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >; }; + + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; }; &main_uart0 { @@ -494,10 +577,10 @@ /* eMMC */ &sdhci0 { status = "okay"; - bus-width = <8>; non-removable; ti,driver-strength-ohm = <50>; disable-wp; + bootph-all; }; /* SD/MMC */ @@ -506,9 +589,7 @@ status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -660,25 +741,25 @@ }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; @@ -705,12 +786,6 @@ num-lanes = <1>; }; -&pcie0_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - &ecap0 { status = "okay"; /* PWM is available on Pin 1 of header J12 */ @@ -731,3 +806,15 @@ pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; }; + +&icssg1_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio1_pins_default>; + + icssg1_phy1: ethernet-phy@f { + reg = <0xf>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; +}; diff --git a/dts/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso b/dts/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso new file mode 100644 index 0000000000..bd9a5caf20 --- /dev/null +++ b/dts/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> + * + * Overlay for SolidRun AM642 HummingBoard-T to enable PCI-E. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +#include "k3-serdes.h" + +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_pins>; + reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "okay"; +}; + +&serdes0 { + #address-cells = <1>; + #size-cells = <0>; + + serdes0_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + cdns,phy-type = <PHY_TYPE_PCIE>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_PCIE0>; +}; + +&serdes_mux { + idle-state = <1>; +}; diff --git a/dts/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso b/dts/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso new file mode 100644 index 0000000000..ffcc3bd3c7 --- /dev/null +++ b/dts/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> + * + * Overlay for SolidRun AM642 HummingBoard-T to enable USB-3.1. + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/phy/phy.h> + +#include "k3-serdes.h" + +&serdes0 { + #address-cells = <1>; + #size-cells = <0>; + + serdes0_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + cdns,phy-type = <PHY_TYPE_USB3>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_USB>; +}; + +&serdes_mux { + idle-state = <0>; +}; + +&usbss0 { + /delete-property/ ti,usb2-only; +}; + +&usb0 { + maximum-speed = "super-speed"; + phys = <&serdes0_link>; + phy-names = "cdns3,usb3-phy"; +}; diff --git a/dts/src/arm64/ti/k3-am642-hummingboard-t.dts b/dts/src/arm64/ti/k3-am642-hummingboard-t.dts new file mode 100644 index 0000000000..234d76e4e9 --- /dev/null +++ b/dts/src/arm64/ti/k3-am642-hummingboard-t.dts @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> + * + * DTS for SolidRun AM642 HummingBoard-T, + * running on Cortex A53. + * + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy.h> + +#include "k3-am642.dtsi" +#include "k3-am642-sr-som.dtsi" + +/ { + model = "SolidRun AM642 HummingBoard-T"; + compatible = "solidrun,am642-hummingboard-t", "solidrun,am642-sr-som", "ti,am642"; + + aliases { + serial5 = &main_uart3; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_default_pins>; + + /* D24 */ + led1: led-1 { + label = "led1"; + gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + }; + + /* D25 */ + led2: led-2 { + label = "led2"; + gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + }; + + /* D26 */ + led3: led-3 { + label = "led3"; + gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + }; + }; + + regulator-m2-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®ulator_pcie_3v3_default_pins>; + regulator-name = "m2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio1 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-vpp-1v8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®ulator_vpp_1v8_default_pins>; + regulator-name = "vpp-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&main_gpio1 78 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + serdes_mux: mux-controller { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&serdes_mux_default_pins>; + #mux-control-cells = <0>; + /* + * Mux has 2 IOs: + * - select: 0 = USB-3 (M2); 1 = PCIE (M1) + * - shutdown: 0 = active; 1 = disabled (high impedance) + */ + mux-gpios = <&main_gpio1 40 GPIO_ACTIVE_HIGH>, <&main_gpio1 41 GPIO_ACTIVE_HIGH>; + /* default disabled */ + idle-state = <2>; + }; +}; + +&main_gpio0 { + m2-reset-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + output-low; /* deasserted */ + line-name = "m2-reset"; + }; + + m1-m2-w-disable1-hog { + gpio-hog; + gpios = <32 GPIO_ACTIVE_LOW>; + output-low; /* deasserted */ + line-name = "m1-m2-pcie-w-disable1"; + }; + + m1-m2-w-disable2-hog { + gpio-hog; + gpios = <34 GPIO_ACTIVE_LOW>; + output-low; /* deasserted */ + line-name = "m1-m2-pcie-w-disable2"; + }; +}; + +&main_gpio1 { + m1-pcie-clkreq0-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_LOW>; + input; + line-name = "m1-pcie-clkreq0"; + }; + + m2-pcie-clkreq-hog { + gpio-hog; + gpios = <35 GPIO_ACTIVE_LOW>; + input; + line-name = "m2-pcie-clkreq"; + }; +}; + +&main_i2c0 { + pinctrl-0 = <&main_i2c0_default_pins>, <&main_i2c0_int_default_pins>; + + humidity-sensor@41 { + compatible = "ti,hdc2010"; + reg = <0x41>; + interrupt-parent = <&main_gpio0>; + interrupts = <37 IRQ_TYPE_EDGE_FALLING>; + }; + + light-sensor@44 { + compatible = "ti,opt3001"; + reg = <0x44>; + interrupt-parent = <&main_gpio0>; + interrupts = <37 IRQ_TYPE_EDGE_FALLING>; + }; + + /* charger@6a */ +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_default_pins>; + status = "okay"; + + rtc@69 { + compatible = "abracon,abx80x"; + reg = <0x69>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_default_pins>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + interrupt-parent = <&main_gpio0>; + interrupts = <44 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_default_pins>; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_default_pins>; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&main_pmx0 { + leds_default_pins: leds-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0074, PIN_OUTPUT, 7) /* GPMC0_AD14.GPIO0_29 */ + AM64X_IOPAD(0x0078, PIN_OUTPUT, 7) /* GPMC0_AD15.GPIO0_30 */ + AM64X_IOPAD(0x0088, PIN_OUTPUT, 7) /* GPMC0_OEn_REn.GPIO0_33 */ + >; + }; + + main_i2c0_int_default_pins: main-i2c0-int-default-pins { + pinctrl-single,pins = < + /* external pull-up on Carrier */ + AM64X_IOPAD(0x0098, PIN_INPUT, 7) /* GPMC0_WAIT0.GPIO0_37 */ + >; + }; + + main_i2c1_default_pins: main-i2c1-default-pins { + pinctrl-single,pins = < + /* external pull-up on SoM */ + AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* I2C1_SCL.I2C1_SCL */ + AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* I2C1_SDA.I2C1_SDA */ + >; + }; + + main_mcan0_default_pins: main-mcan0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* MCAN0_RX.MCAN0_RX */ + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* MCAN0_TX.MCAN0_TX */ + >; + }; + + main_mcan1_default_pins: main-mcan1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* MCAN1_RX.MCAN1_RX */ + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* MCAN1_TX.MCAN1_TX */ + >; + }; + + main_uart3_default_pins: main-uart3-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x016c, PIN_INPUT, 10) /* PRG0_PRU0_GPO3.UART3_CTSn */ + AM64X_IOPAD(0x0170, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO4.UART3_TXD */ + AM64X_IOPAD(0x0174, PIN_OUTPUT, 10) /* PRG0_PRU0_GPO5.UART3_RTSn */ + AM64X_IOPAD(0x01ac, PIN_INPUT, 10) /* PRG0_PRU0_GPO19.UART3_RXD */ + >; + }; + + pcie0_default_pins: pcie0-default-pins { + pinctrl-single,pins = < + /* connector M2 RESET */ + AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* OSPI0_CSn1.GPIO0_12 */ + /* connectors M1 & M2 W_DISABLE1 */ + AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* GPMC0_ADVN_ALE.GPIO0_32 */ + /* connectors M1 & M2 W_DISABLE2 */ + AM64X_IOPAD(0x008c, PIN_OUTPUT, 7) /* GPMC0_WEN.GPIO0_34 */ + /* connectors M1 & M2 PERST0 (PCI Reset) */ + AM64X_IOPAD(0x019c, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO15.GPIO1_15 */ + /* connector M1 CLKREQ0 */ + AM64X_IOPAD(0x018c, PIN_INPUT, 7) /* PRG0_PRU0_GPO11.GPIO1_11 */ + /* connector M2 CLKREQ0 */ + AM64X_IOPAD(0x01ec, PIN_INPUT, 7) /* PRG0_PRU1_GPO15.GPIO1_35 */ + >; + }; + + regulator_pcie_3v3_default_pins: regulator-pcie-3v3-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01a4, PIN_OUTPUT, 7) /* PRG0_PRU0_GPO17.GPIO1_17 */ + >; + }; + + regulator_vpp_1v8_default_pins: regulator-vpp-1v8-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x029c, PIN_OUTPUT, 7) /* MMC1_SDWP.GPIO1_78 */ + >; + }; + + rtc_int_default_pins: rtc-int-default-pins { + pinctrl-single,pins = < + /* external pull-up on Carrier */ + AM64X_IOPAD(0x00b4, PIN_INPUT, 7) /* GPMC0_CSn3.GPIO0_44 */ + >; + }; + + serdes_mux_default_pins: serdes-mux-default-pins { + pinctrl-single,pins = < + /* SEL, 10k pull-down on carrier, 2.2k pullup on SoM */ + AM64X_IOPAD(0x0200, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDIO.GPIO1_40 */ + /* EN */ + AM64X_IOPAD(0x0204, PIN_OUTPUT, 7) /* PRG0_MDIO0_MDC.GPIO1_41 */ + >; + }; +}; + +&main_uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_default_pins>; + uart-has-rtscts; + rs485-rts-active-low; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; +}; diff --git a/dts/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts b/dts/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts index 53b64e5541..8237b8c815 100644 --- a/dts/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts +++ b/dts/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com * Author: Matt McKee <mmckee@phytec.com> * - * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH * Author: Wadim Egorov <w.egorov@phytec.de> * * Product homepage: @@ -159,6 +159,15 @@ >; }; + main_spi0_pins_default: main-spi0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) /* (C13) SPI0_CS1.GPIO1_43 */ + AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ + AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ + AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ @@ -248,6 +257,20 @@ phys = <&can_tc2>; }; +&main_spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins_default>; + cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>; + ti,pindir-d0-out-d1-in; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <10000000>; + }; +}; + &main_uart0 { status = "okay"; pinctrl-names = "default"; @@ -269,7 +292,6 @@ pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; bus-width = <4>; - ti,driver-strength-ohm = <50>; disable-wp; no-1-8-v; }; diff --git a/dts/src/arm64/ti/k3-am642-sk.dts b/dts/src/arm64/ti/k3-am642-sk.dts index 1dddd6fc1a..67cd41bf80 100644 --- a/dts/src/arm64/ti/k3-am642-sk.dts +++ b/dts/src/arm64/ti/k3-am642-sk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -469,9 +469,7 @@ status = "okay"; vmmc-supply = <&vdd_mmc1>; pinctrl-names = "default"; - bus-width = <4>; pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; disable-wp; }; @@ -646,25 +644,25 @@ }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; diff --git a/dts/src/arm64/ti/k3-am642-sr-som.dtsi b/dts/src/arm64/ti/k3-am642-sr-som.dtsi new file mode 100644 index 0000000000..c19d0b8bbf --- /dev/null +++ b/dts/src/arm64/ti/k3-am642-sr-som.dtsi @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Josua Mayer <josua@solid-run.com> + * + */ + +#include <dt-bindings/net/ti-dp83869.h> + +/ { + model = "SolidRun AM642 SoM"; + compatible = "solidrun,am642-sr-som", "ti,am642"; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &icssg1_emac0; + ethernet2 = &icssg1_emac1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + serial2 = &main_uart0; + }; + + chosen { + /* SoC default UART console */ + stdout-path = "serial2:115200n8"; + }; + + /* PRU Ethernet Controller */ + ethernet { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&pru_rgmii1_default_pins>, <&pru_rgmii2_default_pins>; + + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + /* configure internal pinmux for mii mode */ + ti,pruss-gp-mux-sel = <2>, <2>, <2>, <2>, <2>, <2>; + + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + + /* + * Configure icssg interrupt controller to map pru-internal + * interrupts 8/9 via channels 0/1 to host interrupts 0/1. + * + * For details see interrupt controller documentation: + * Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml + */ + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + icssg1_emac0: port@0 { + reg = <0>; + ti,syscon-rgmii-delay = <&main_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðernet_phy2>; + phy-mode = "rgmii-id"; + }; + + icssg1_emac1: port@1 { + reg = <1>; + ti,syscon-rgmii-delay = <&main_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðernet_phy1>; + phy-mode = "rgmii-id"; + }; + }; + }; + + /* DDR16SS0: + * - Bank 1 @ 0x080000000-0x0FFFFFFFF: max. 2GB in 32-bit address space + * - Bank 2 @ 0x880000000-0x9FFFFFFFF: max. 6GB in 64-bit address space + */ + memory@80000000 { + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + }; + + vdd_mmc0: regulator-vdd-mmc0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-mmc0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_default_pins>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_default_pins>; + status = "okay"; + + ethernet_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.a0f1"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy0_default_pins>; + ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; + ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; + /* + * Disable interrupts because ISR never clears 0x0040 + * + * interrupt-parent = <&main_gpio1>; + * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; + */ + /* + * Disable HW Reset because clock signal is daisy-chained + * + * reset-gpios = <&main_gpio0 84 GPIO_ACTIVE_LOW>; + * reset-assert-us = <1>; + * reset-deassert-us = <30>; + */ + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&icssg1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pru1_mdio0_default_pins>; + status = "okay"; + + ethernet_phy1: ethernet-phy@3 { + compatible = "ethernet-phy-id2000.a0f1"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy1_default_pins>; + ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; + ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; + /* + * Disable interrupts because ISR never clears 0x0040 + * + * interrupt-parent = <&main_gpio1>; + * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; + */ + /* + * Disable HW Reset because clock signal is daisy-chained + * + * reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; + * reset-assert-us = <1>; + * reset-deassert-us = <30>; + */ + }; + + ethernet_phy2: ethernet-phy@f { + compatible = "ethernet-phy-id2000.a0f1"; + reg = <0xf>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy2_default_pins>; + ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>; + /* + * Disable interrupts because ISR never clears 0x0040 + * + * interrupt-parent = <&main_gpio1>; + * interrupts = <70 IRQ_TYPE_LEVEL_LOW>; + */ + /* + * Disable HW Reset because clock signal is daisy-chained + * + * reset-gpios = <&main_gpio0 52 GPIO_ACTIVE_LOW>; + * reset-assert-us = <1>; + * reset-deassert-us = <30>; + */ + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_default_pins>; + status = "okay"; + + som_eeprom: eeprom@50 { + compatible = "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&main_pmx0 { + /* hog global functions */ + pinctrl-names = "default"; + pinctrl-0 = <ðernet_phy_default_pins>; + + ethernet_phy_default_pins: ethernet-phy-default-pins { + pinctrl-single,pins = < + /* interrupt / power-down, external pull-up on SoM */ + AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* EXTINTn.GPIO1_70 */ + >; + }; + + ethernet_phy0_default_pins: ethernet-phy0-default-pins { + pinctrl-single,pins = < + /* reset */ + AM64X_IOPAD(0x0154, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO19.GPIO0_84 */ + /* reference clock */ + AM64X_IOPAD(0x0274, PIN_OUTPUT, 5) /* EXT_REFCLK1.CLKOUT0 */ + >; + }; + + ethernet_phy1_default_pins: ethernet-phy1-default-pins { + pinctrl-single,pins = < + /* reset */ + AM64X_IOPAD(0x0150, PIN_OUTPUT, 7) /* PRG1_PRU1_GPO18.GPIO0_20 */ + /* led0, external pull-down on SoM */ + AM64X_IOPAD(0x0128, PIN_INPUT, 7) /* PRG1_PRU1_GPO8.GPIO0_73 */ + /* led1/rxer */ + AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* PRG1_PRU1_GPO5.GPIO0_70 */ + >; + }; + + ethernet_phy2_default_pins: ethernet-phy2-default-pins { + pinctrl-single,pins = < + /* reset */ + AM64X_IOPAD(0x00d4, PIN_OUTPUT, 7) /* PRG1_PRU0_GPO7.GPIO0_52 */ + /* led0, external pull-down on SoM */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* PRG1_PRU0_GPO8.GPIO0_53 */ + /* led1/rxer */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* PRG1_PRU0_GPO5.GPIO0_50 */ + >; + }; + + main_i2c0_default_pins: main-i2c0-default-pins { + pinctrl-single,pins = < + /* external pull-up on SoM */ + AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* I2C0_SCL.I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* I2C0_SDA.I2C0_SDA */ + >; + }; + + /* + * main_mmc0_default_pins: main-mmc0-default-pins + * + * MMC0_CMD: no padconfig + * MMC0_CLK: no padconfig, external pull-up on SoM + * MMC0_DAT0: no padconfig + * MMC0_DAT1: no padconfig + * MMC0_DAT2: no padconfig + * MMC0_DAT3: no padconfig + * MMC0_DAT4: no padconfig + * MMC0_DAT5: no padconfig + * MMC0_DAT6: no padconfig + * MMC0_DAT7: no padconfig + * MMC0_DS: no padconfig, external pull-down on SoM + */ + + main_mmc1_default_pins: main-mmc1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* MMC1_CLK.MMC1_CLK */ + AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* MMC1_DAT0.MMC1_DAT0 */ + AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* MMC1_DAT1.MMC1_DAT1 */ + AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* MMC1_DAT2.MMC1_DAT2 */ + AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* MMC1_DAT3.MMC1_DAT3 */ + /* external pull-down on SoM & Carrier */ + AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* MMC1_SDCD.MMC1_SDCD */ + AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB: clock loopback */ + >; + }; + + main_uart0_default_pins: main-uart0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* UART0_RXD.UART0_RXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* UART0_TXD.UART0_TXD */ + >; + }; + + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* PRG0_PRU1_GPO18.MDIO0_MDIO */ + >; + }; + + ospi0_default_pins: ospi0-default-pins { + pinctrl-single,pins = < + /* external pull-down on SoM */ + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* OSPI0_CLK.OSPI0_CLK */ + AM64X_IOPAD(0x0008, PIN_OUTPUT, 0) /* OSPI0_DQS.OSPI0_DQS */ + /* external pull-up on SoM */ + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* OSPI0_CSn0.OSPI0_CSn0 */ + AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* OSPI0_D0.OSPI0_D0 */ + AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* OSPI0_D1.OSPI0_D1 */ + AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* OSPI0_D2.OSPI0_D2 */ + AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* OSPI0_D3.OSPI0_D3 */ + AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* OSPI0_D4.OSPI0_D4 */ + AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* OSPI0_D5.OSPI0_D5 */ + AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* OSPI0_D6.OSPI0_D6 */ + AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* OSPI0_D7.OSPI0_D7 */ + >; + }; + + ospi0_flash0_default_pins: ospi0-flash0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* OSPI0_CSn2.GPIO0_13 */ + AM64X_IOPAD(0x0038, PIN_INPUT, 7) /* OSPI0_CSn3.GPIO0_14 */ + >; + }; + + pru1_mdio0_default_pins: pru1-mdio0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* PRG1_MDIO0_MDC.PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* PRG1_MDIO0_MDIO.PRG1_MDIO0_MDIO */ + >; + }; + + pru_rgmii1_default_pins: pru-rgmii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; + + pru_rgmii2_default_pins: pru-rgmii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; + + rgmii1_default_pins: rgmii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* PRG0_PRU1_GPO7.RGMII1_RD0 */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* PRG0_PRU1_GPO9.RGMII1_RD1 */ + AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* PRG0_PRU1_GPO10.RGMII1_RD2 */ + AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* PRG0_PRU1_GPO17.RGMII1_RD3 */ + AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* PRG0_PRU0_GPO10.RGMII1_RXC */ + AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* PRG0_PRU0_GPO9.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x00e0, PIN_INPUT, 4) /* PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + >; + }; + + usb0_default_pins: usb0-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */ + >; + }; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +/* SoC default UART console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_default_pins>; + status = "okay"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_default_pins>; + num-cs = <1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_flash0_default_pins>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <200000000>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + cdns,read-delay = <0>; + interrupt-parent = <&main_gpio0>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&main_gpio0 13 GPIO_ACTIVE_LOW>; + }; +}; + +&sdhci0 { + /* mmc0 pins have no padconfig */ + bus-width = <8>; + ti,driver-strength-ohm = <50>; + disable-wp; + non-removable; + cap-mmc-hw-reset; + no-sd; + /* + * MMC controller supports switching between 1.8V and 3.3V signalling. + * However MMC0 (unlike MMC1) does not integrate an LDO. + * Explicitly link a regulator node for indicating to the driver which + * voltages are actually usable. + */ + vqmmc-supply = <&vdd_mmc0>; + status = "okay"; +}; + +/* + * microSD is on carrier - however since SoC can boot from it, + * configure it just in case. + */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_default_pins>; + bus-width = <4>; + ti,driver-strength-ohm = <50>; + disable-wp; + status = "okay"; +}; + +/* + * USB settings are a carrier choice - however since SoC can boot from it, + * configure as USB-2.0 OTG here, keeping USB-3 serdes disabled. + */ +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_default_pins>; + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + +&usbss0 { + ti,vbus-divider; + ti,usb2-only; +}; diff --git a/dts/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/dts/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 55102d35ce..1f4dc5ad16 100644 --- a/dts/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/dts/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -422,7 +422,6 @@ cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>; disable-wp; no-mmc; - ti,driver-strength-ohm = <50>; ti,fails-without-test-cd; /* Enabled by overlay */ }; diff --git a/dts/src/arm64/ti/k3-am642.dtsi b/dts/src/arm64/ti/k3-am642.dtsi index 7a6eedea3a..8589ee55ef 100644 --- a/dts/src/arm64/ti/k3-am642.dtsi +++ b/dts/src/arm64/ti/k3-am642.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM642 SoC family in Dual core configuration * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi b/dts/src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi new file mode 100644 index 0000000000..7ff0abd7c6 --- /dev/null +++ b/dts/src/arm64/ti/k3-am65-iot2050-arduino-connector.dtsi @@ -0,0 +1,768 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2018-2023 + * + * Authors: + * Le Jin <le.jin@siemens.com> + * Jan Kiszka <jan.kiszka@siemens.com> + * + * Common bits for IOT2050 variants with Arduino connector + */ + +&wkup_pmx0 { + pinctrl-names = + "default", + "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown", + "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown", + "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown", + "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown", + "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown", + "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown", + "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown", + "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown", + "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown", + "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown", + "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown", + "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown", + "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown", + "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown"; + + pinctrl-0 = <&d0_uart0_rxd>; + pinctrl-1 = <&d0_uart0_rxd>; + pinctrl-2 = <&d0_gpio>; + pinctrl-3 = <&d0_gpio_pullup>; + pinctrl-4 = <&d0_gpio_pulldown>; + pinctrl-5 = <&d1_uart0_txd>; + pinctrl-6 = <&d1_gpio>; + pinctrl-7 = <&d1_gpio_pullup>; + pinctrl-8 = <&d1_gpio_pulldown>; + pinctrl-9 = <&d2_uart0_ctsn>; + pinctrl-10 = <&d2_gpio>; + pinctrl-11 = <&d2_gpio_pullup>; + pinctrl-12 = <&d2_gpio_pulldown>; + pinctrl-13 = <&d3_uart0_rtsn>; + pinctrl-14 = <&d3_gpio>; + pinctrl-15 = <&d3_gpio_pullup>; + pinctrl-16 = <&d3_gpio_pulldown>; + pinctrl-17 = <&d10_spi0_cs0>; + pinctrl-18 = <&d10_gpio>; + pinctrl-19 = <&d10_gpio_pullup>; + pinctrl-20 = <&d10_gpio_pulldown>; + pinctrl-21 = <&d11_spi0_d0>; + pinctrl-22 = <&d11_gpio>; + pinctrl-23 = <&d11_gpio_pullup>; + pinctrl-24 = <&d11_gpio_pulldown>; + pinctrl-25 = <&d12_spi0_d1>; + pinctrl-26 = <&d12_gpio>; + pinctrl-27 = <&d12_gpio_pullup>; + pinctrl-28 = <&d12_gpio_pulldown>; + pinctrl-29 = <&d13_spi0_clk>; + pinctrl-30 = <&d13_gpio>; + pinctrl-31 = <&d13_gpio_pullup>; + pinctrl-32 = <&d13_gpio_pulldown>; + pinctrl-33 = <&a0_gpio>; + pinctrl-34 = <&a0_gpio_pullup>; + pinctrl-35 = <&a0_gpio_pulldown>; + pinctrl-36 = <&a1_gpio>; + pinctrl-37 = <&a1_gpio_pullup>; + pinctrl-38 = <&a1_gpio_pulldown>; + pinctrl-39 = <&a2_gpio>; + pinctrl-40 = <&a2_gpio_pullup>; + pinctrl-41 = <&a2_gpio_pulldown>; + pinctrl-42 = <&a3_gpio>; + pinctrl-43 = <&a3_gpio_pullup>; + pinctrl-44 = <&a3_gpio_pulldown>; + pinctrl-45 = <&a4_gpio>; + pinctrl-46 = <&a4_gpio_pullup>; + pinctrl-47 = <&a4_gpio_pulldown>; + pinctrl-48 = <&a5_gpio>; + pinctrl-49 = <&a5_gpio_pullup>; + pinctrl-50 = <&a5_gpio_pulldown>; + + d0_uart0_rxd: d0-uart0-rxd-pins { + pinctrl-single,pins = < + /* (P4) MCU_UART0_RXD */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) + >; + }; + + d0_gpio: d0-gpio-pins { + pinctrl-single,pins = < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) + >; + }; + + d0_gpio_pullup: d0-gpio-pullup-pins { + pinctrl-single,pins = < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7) + >; + }; + + d0_gpio_pulldown: d0-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d1_uart0_txd: d1-uart0-txd-pins { + pinctrl-single,pins = < + /* (P5) MCU_UART0_TXD */ + AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) + >; + }; + + d1_gpio: d1-gpio-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) + >; + }; + + d1_gpio_pullup: d1-gpio-pullup-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) + >; + }; + + d1_gpio_pulldown: d1-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d2_uart0_ctsn: d2-uart0-ctsn-pins { + pinctrl-single,pins = < + /* (P1) MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) + >; + }; + + d2_gpio: d2-gpio-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + >; + }; + + d2_gpio_pullup: d2-gpio-pullup-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + >; + }; + + d2_gpio_pulldown: d2-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d3_uart0_rtsn: d3-uart0-rtsn-pins { + pinctrl-single,pins = < + /* (N3) MCU_UART0_RTSn */ + AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) + >; + }; + + d3_gpio: d3-gpio-pins { + pinctrl-single,pins = < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + d3_gpio_pullup: d3-gpio-pullup-pins { + pinctrl-single,pins = < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + d3_gpio_pulldown: d3-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d10_spi0_cs0: d10-spi0-cs0-pins { + pinctrl-single,pins = < + /* (Y4) MCU_SPI0_CS0 */ + AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) + >; + }; + + d10_gpio: d10-gpio-pins { + pinctrl-single,pins = < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) + >; + }; + + d10_gpio_pullup: d10-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) + >; + }; + + d10_gpio_pulldown: d10-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d11_spi0_d0: d11-spi0-d0-pins { + pinctrl-single,pins = < + /* (Y3) MCU_SPI0_D0 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) + >; + }; + + d11_gpio: d11-gpio-pins { + pinctrl-single,pins = < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) + >; + }; + + d11_gpio_pullup: d11-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) + >; + }; + + d11_gpio_pulldown: d11-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d12_spi0_d1: d12-spi0-d1-pins { + pinctrl-single,pins = < + /* (Y2) MCU_SPI0_D1 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) + >; + }; + + d12_gpio: d12-gpio-pins { + pinctrl-single,pins = < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d12_gpio_pullup: d12-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d12_gpio_pulldown: d12-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d13_spi0_clk: d13-spi0-clk-pins { + pinctrl-single,pins = < + /* (Y1) MCU_SPI0_CLK */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) + >; + }; + + d13_gpio: d13-gpio-pins { + pinctrl-single,pins = < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) + >; + }; + + d13_gpio_pullup: d13-gpio-pullup-pins { + pinctrl-single,pins = < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) + >; + }; + + d13_gpio_pulldown: d13-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a0_gpio: a0-gpio-pins { + pinctrl-single,pins = < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + a0_gpio_pullup: a0-gpio-pullup-pins { + pinctrl-single,pins = < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + a0_gpio_pulldown: a0-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a1_gpio: a1-gpio-pins { + pinctrl-single,pins = < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) + >; + }; + + a1_gpio_pullup: a1-gpio-pullup-pins { + pinctrl-single,pins = < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) + >; + }; + + a1_gpio_pulldown: a1-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a2_gpio: a2-gpio-pins { + pinctrl-single,pins = < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + >; + }; + + a2_gpio_pullup: a2-gpio-pullup-pins { + pinctrl-single,pins = < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + >; + }; + + a2_gpio_pulldown: a2-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a3_gpio: a3-gpio-pins { + pinctrl-single,pins = < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + >; + }; + + a3_gpio_pullup: a3-gpio-pullup-pins { + pinctrl-single,pins = < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + >; + }; + + a3_gpio_pulldown: a3-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a4_gpio: a4-gpio-pins { + pinctrl-single,pins = < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) + >; + }; + + a4_gpio_pullup: a4-gpio-pullup-pins { + pinctrl-single,pins = < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) + >; + }; + + a4_gpio_pulldown: a4-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a5_gpio: a5-gpio-pins { + pinctrl-single,pins = < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7) + >; + }; + + a5_gpio_pullup: a5-gpio-pullup-pins { + pinctrl-single,pins = < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7) + >; + }; + + a5_gpio_pulldown: a5-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + /* (AC7) WKUP_I2C0_SCL */ + AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) + /* (AD6) WKUP_I2C0_SDA */ + AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) + >; + }; + + arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { + pinctrl-single,pins = < + /* (R2) WKUP_GPIO0_21 */ + AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) + >; + }; + + arduino_io_oe_pins_default: arduino-io-oe-default-pins { + pinctrl-single,pins = < + /* (N4) WKUP_GPIO0_34 */ + AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) + /* (M2) WKUP_GPIO0_36 */ + AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) + /* (M3) WKUP_GPIO0_37 */ + AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) + /* (M4) WKUP_GPIO0_38 */ + AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) + /* (M1) WKUP_GPIO0_41 */ + AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) + >; + }; +}; + +&main_pmx0 { + pinctrl-names = + "default", + "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown", + "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown", + "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown", + "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown", + "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown", + "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown"; + + pinctrl-0 = <&d4_ehrpwm0_a>; + pinctrl-1 = <&d4_ehrpwm0_a>; + pinctrl-2 = <&d4_gpio>; + pinctrl-3 = <&d4_gpio_pullup>; + pinctrl-4 = <&d4_gpio_pulldown>; + + pinctrl-5 = <&d5_ehrpwm1_a>; + pinctrl-6 = <&d5_gpio>; + pinctrl-7 = <&d5_gpio_pullup>; + pinctrl-8 = <&d5_gpio_pulldown>; + + pinctrl-9 = <&d6_ehrpwm2_a>; + pinctrl-10 = <&d6_gpio>; + pinctrl-11 = <&d6_gpio_pullup>; + pinctrl-12 = <&d6_gpio_pulldown>; + + pinctrl-13 = <&d7_ehrpwm3_a>; + pinctrl-14 = <&d7_gpio>; + pinctrl-15 = <&d7_gpio_pullup>; + pinctrl-16 = <&d7_gpio_pulldown>; + + pinctrl-17 = <&d8_ehrpwm4_a>; + pinctrl-18 = <&d8_gpio>; + pinctrl-19 = <&d8_gpio_pullup>; + pinctrl-20 = <&d8_gpio_pulldown>; + + pinctrl-21 = <&d9_ehrpwm5_a>; + pinctrl-22 = <&d9_gpio>; + pinctrl-23 = <&d9_gpio_pullup>; + pinctrl-24 = <&d9_gpio_pulldown>; + + d4_ehrpwm0_a: d4-ehrpwm0-a-pins { + pinctrl-single,pins = < + /* (AG18) EHRPWM0_A */ + AM65X_IOPAD(0x0084, PIN_OUTPUT, 5) + >; + }; + + d4_gpio: d4-gpio-pins { + pinctrl-single,pins = < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + d4_gpio_pullup: d4-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) + >; + }; + + d4_gpio_pulldown: d4-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d5_ehrpwm1_a: d5-ehrpwm1-a-pins { + pinctrl-single,pins = < + /* (AF17) EHRPWM1_A */ + AM65X_IOPAD(0x008C, PIN_OUTPUT, 5) + >; + }; + + d5_gpio: d5-gpio-pins { + pinctrl-single,pins = < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT, 7) + >; + }; + + d5_gpio_pullup: d5-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7) + >; + }; + + d5_gpio_pulldown: d5-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d6_ehrpwm2_a: d6-ehrpwm2-a-pins { + pinctrl-single,pins = < + /* (AH16) EHRPWM2_A */ + AM65X_IOPAD(0x0098, PIN_OUTPUT, 5) + >; + }; + + d6_gpio: d6-gpio-pins { + pinctrl-single,pins = < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d6_gpio_pullup: d6-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7) + >; + }; + + d6_gpio_pulldown: d6-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d7_ehrpwm3_a: d7-ehrpwm3-a-pins { + pinctrl-single,pins = < + /* (AH15) EHRPWM3_A */ + AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5) + >; + }; + + d7_gpio: d7-gpio-pins { + pinctrl-single,pins = < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT, 7) + >; + }; + + d7_gpio_pullup: d7-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7) + >; + }; + + d7_gpio_pulldown: d7-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d8_ehrpwm4_a: d8-ehrpwm4-a-pins { + pinctrl-single,pins = < + /* (AG15) EHRPWM4_A */ + AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5) + >; + }; + + d8_gpio: d8-gpio-pins { + pinctrl-single,pins = < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT, 7) + >; + }; + + d8_gpio_pullup: d8-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7) + >; + }; + + d8_gpio_pulldown: d8-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d9_ehrpwm5_a: d9-ehrpwm5-a-pins { + pinctrl-single,pins = < + /* (AD15) EHRPWM5_A */ + AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5) + >; + }; + + d9_gpio: d9-gpio-pins { + pinctrl-single,pins = < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT, 7) + >; + }; + + d9_gpio_pullup: d9-gpio-pullup-pins { + pinctrl-single,pins = < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7) + >; + }; + + d9_gpio_pulldown: d9-gpio-pulldown-pins { + pinctrl-single,pins = < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) + >; + }; +}; + +&main_gpio0 { + gpio-line-names = + "main_gpio0-base", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "IO4", "", "IO5", "", "", "IO6", "", + "", "", "", "IO7", "", "", "", "", "IO8", "", + "", "IO9"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = + <&arduino_i2c_aio_switch_pins_default>, + <&arduino_io_oe_pins_default>, + <&push_button_pins_default>, + <&db9_com_mode_pins_default>; + gpio-line-names = + /* 0..9 */ + "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", + "UART0-enable", "UART0-terminate", "", "WIFI-disable", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", + /* 30..39 */ + "IO1", "IO2", "", "IO3", "IO17-direction", "A5", + "IO16-direction", "IO15-direction", "IO14-direction", "A3", + /* 40..49 */ + "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", + "IO11", + /* 50..51 */ + "IO12", "IO10"; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&mcu_i2c0 { + /* D4200 */ + pcal9535_1: gpio@20 { + compatible = "nxp,pcal9535"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", + "A5-pull", "", "", + "IO14-enable", "IO15-enable", "IO16-enable", + "IO17-enable", "IO18-enable", "IO19-enable"; + }; + + /* D4201 */ + pcal9535_2: gpio@21 { + compatible = "nxp,pcal9535"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "IO0-direction", "IO1-direction", "IO2-direction", + "IO3-direction", "IO4-direction", "IO5-direction", + "IO6-direction", "IO7-direction", + "IO8-direction", "IO9-direction", "IO10-direction", + "IO11-direction", "IO12-direction", "IO13-direction", + "IO19-direction"; + }; + + /* D4202 */ + pcal9535_3: gpio@25 { + compatible = "nxp,pcal9535"; + reg = <0x25>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", + "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", + "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", + "IO12-pull", "IO13-pull"; + }; +}; + +&mcu_uart0 { + status = "okay"; +}; + +&tscadc1 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5>; + }; +}; diff --git a/dts/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi b/dts/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi index 1d19798595..c50a585dd6 100644 --- a/dts/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi +++ b/dts/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2021-2023 * @@ -8,10 +8,7 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG1 */ -&dss { - assigned-clocks = <&k3_clks 67 2>; - assigned-clock-parents = <&k3_clks 67 5>; -}; +#include "k3-am65-iot2050-dp.dtsi" &serdes0 { status = "disabled"; diff --git a/dts/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi b/dts/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi index e9b57b87e4..e2584a5efe 100644 --- a/dts/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/dts/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2021 + * Copyright (c) Siemens AG, 2021-2023 * * Authors: * Chao Zeng <chao.zeng@siemens.com> @@ -9,6 +9,11 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG2 */ +&mcu_r5fss0 { + /* lock-step mode not supported on PG2 boards */ + ti,cluster-mode = <0>; +}; + &main_pmx0 { cp2102n_reset_pin_default: cp2102n-reset-default-pins { pinctrl-single,pins = < @@ -33,21 +38,3 @@ /* Workaround needed to get DP clock of 154Mhz */ assigned-clocks = <&k3_clks 67 0>; }; - -&serdes0 { - assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; -}; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ - phys = <&serdes0 PHY_TYPE_USB3 0>; - phy-names = "usb3-phy"; -}; - -&usb0 { - maximum-speed = "super-speed"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; -}; diff --git a/dts/src/arm64/ti/k3-am65-iot2050-common.dtsi b/dts/src/arm64/ti/k3-am65-iot2050-common.dtsi index 61a634afaa..ef34b851e1 100644 --- a/dts/src/arm64/ti/k3-am65-iot2050-common.dtsi +++ b/dts/src/arm64/ti/k3-am65-iot2050-common.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2018-2021 + * Copyright (c) Siemens AG, 2018-2024 * * Authors: * Le Jin <le.jin@siemens.com> @@ -9,6 +9,7 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2 */ +#include <dt-bindings/leds/common.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/net/ti-dp83867.h> @@ -75,6 +76,12 @@ alignment = <0x1000>; no-map; }; + + /* To reserve the power-on(PON) reason for watchdog reset */ + wdt_reset_memory_region: wdt-memory@a2200000 { + reg = <0x00 0xa2200000 0x00 0x1000>; + no-map; + }; }; leds { @@ -82,28 +89,46 @@ pinctrl-names = "default"; pinctrl-0 = <&leds_pins_default>; - status-led-red { + led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_STATUS; + label = "status-led-red"; gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>; panic-indicator; }; - status-led-green { + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + label = "status-led-green"; gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>; }; - user-led1-red { + led-2 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + label = "user-led1-red"; gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>; }; - user-led1-green { + led-3 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + label = "user-led1-green"; gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>; }; - user-led2-red { + led-4 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + label = "user-led2-red"; gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>; }; - user-led2-green { + led-5 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + label = "user-led2-green"; gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>; }; }; @@ -186,434 +211,6 @@ }; &wkup_pmx0 { - pinctrl-names = - "default", - "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown", - "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown", - "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown", - "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown", - "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown", - "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown", - "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown", - "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown", - "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown", - "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown", - "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown", - "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown", - "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown", - "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown"; - - pinctrl-0 = <&d0_uart0_rxd>; - pinctrl-1 = <&d0_uart0_rxd>; - pinctrl-2 = <&d0_gpio>; - pinctrl-3 = <&d0_gpio_pullup>; - pinctrl-4 = <&d0_gpio_pulldown>; - pinctrl-5 = <&d1_uart0_txd>; - pinctrl-6 = <&d1_gpio>; - pinctrl-7 = <&d1_gpio_pullup>; - pinctrl-8 = <&d1_gpio_pulldown>; - pinctrl-9 = <&d2_uart0_ctsn>; - pinctrl-10 = <&d2_gpio>; - pinctrl-11 = <&d2_gpio_pullup>; - pinctrl-12 = <&d2_gpio_pulldown>; - pinctrl-13 = <&d3_uart0_rtsn>; - pinctrl-14 = <&d3_gpio>; - pinctrl-15 = <&d3_gpio_pullup>; - pinctrl-16 = <&d3_gpio_pulldown>; - pinctrl-17 = <&d10_spi0_cs0>; - pinctrl-18 = <&d10_gpio>; - pinctrl-19 = <&d10_gpio_pullup>; - pinctrl-20 = <&d10_gpio_pulldown>; - pinctrl-21 = <&d11_spi0_d0>; - pinctrl-22 = <&d11_gpio>; - pinctrl-23 = <&d11_gpio_pullup>; - pinctrl-24 = <&d11_gpio_pulldown>; - pinctrl-25 = <&d12_spi0_d1>; - pinctrl-26 = <&d12_gpio>; - pinctrl-27 = <&d12_gpio_pullup>; - pinctrl-28 = <&d12_gpio_pulldown>; - pinctrl-29 = <&d13_spi0_clk>; - pinctrl-30 = <&d13_gpio>; - pinctrl-31 = <&d13_gpio_pullup>; - pinctrl-32 = <&d13_gpio_pulldown>; - pinctrl-33 = <&a0_gpio>; - pinctrl-34 = <&a0_gpio_pullup>; - pinctrl-35 = <&a0_gpio_pulldown>; - pinctrl-36 = <&a1_gpio>; - pinctrl-37 = <&a1_gpio_pullup>; - pinctrl-38 = <&a1_gpio_pulldown>; - pinctrl-39 = <&a2_gpio>; - pinctrl-40 = <&a2_gpio_pullup>; - pinctrl-41 = <&a2_gpio_pulldown>; - pinctrl-42 = <&a3_gpio>; - pinctrl-43 = <&a3_gpio_pullup>; - pinctrl-44 = <&a3_gpio_pulldown>; - pinctrl-45 = <&a4_gpio>; - pinctrl-46 = <&a4_gpio_pullup>; - pinctrl-47 = <&a4_gpio_pulldown>; - pinctrl-48 = <&a5_gpio>; - pinctrl-49 = <&a5_gpio_pullup>; - pinctrl-50 = <&a5_gpio_pulldown>; - - d0_uart0_rxd: d0-uart0-rxd-pins { - pinctrl-single,pins = < - /* (P4) MCU_UART0_RXD */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) - >; - }; - - d0_gpio: d0-gpio-pins { - pinctrl-single,pins = < - /* (P4) WKUP_GPIO0_29 */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) - >; - }; - - d0_gpio_pullup: d0-gpio-pullup-pins { - pinctrl-single,pins = < - /* (P4) WKUP_GPIO0_29 */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7) - >; - }; - - d0_gpio_pulldown: d0-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (P4) WKUP_GPIO0_29 */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d1_uart0_txd: d1-uart0-txd-pins { - pinctrl-single,pins = < - /* (P5) MCU_UART0_TXD */ - AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) - >; - }; - - d1_gpio: d1-gpio-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_30 */ - AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) - >; - }; - - d1_gpio_pullup: d1-gpio-pullup-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_30 */ - AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) - >; - }; - - d1_gpio_pulldown: d1-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_30 */ - AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d2_uart0_ctsn: d2-uart0-ctsn-pins { - pinctrl-single,pins = < - /* (P1) MCU_UART0_CTSn */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) - >; - }; - - d2_gpio: d2-gpio-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) - >; - }; - - d2_gpio_pullup: d2-gpio-pullup-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) - >; - }; - - d2_gpio_pulldown: d2-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d3_uart0_rtsn: d3-uart0-rtsn-pins { - pinctrl-single,pins = < - /* (N3) MCU_UART0_RTSn */ - AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) - >; - }; - - d3_gpio: d3-gpio-pins { - pinctrl-single,pins = < - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) - >; - }; - - d3_gpio_pullup: d3-gpio-pullup-pins { - pinctrl-single,pins = < - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) - >; - }; - - d3_gpio_pulldown: d3-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d10_spi0_cs0: d10-spi0-cs0-pins { - pinctrl-single,pins = < - /* (Y4) MCU_SPI0_CS0 */ - AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) - >; - }; - - d10_gpio: d10-gpio-pins { - pinctrl-single,pins = < - /* (Y4) WKUP_GPIO0_51 */ - AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) - >; - }; - - d10_gpio_pullup: d10-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y4) WKUP_GPIO0_51 */ - AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) - >; - }; - - d10_gpio_pulldown: d10-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y4) WKUP_GPIO0_51 */ - AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d11_spi0_d0: d11-spi0-d0-pins { - pinctrl-single,pins = < - /* (Y3) MCU_SPI0_D0 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) - >; - }; - - d11_gpio: d11-gpio-pins { - pinctrl-single,pins = < - /* (Y3) WKUP_GPIO0_49 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) - >; - }; - - d11_gpio_pullup: d11-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y3) WKUP_GPIO0_49 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) - >; - }; - - d11_gpio_pulldown: d11-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y3) WKUP_GPIO0_49 */ - AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d12_spi0_d1: d12-spi0-d1-pins { - pinctrl-single,pins = < - /* (Y2) MCU_SPI0_D1 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) - >; - }; - - d12_gpio: d12-gpio-pins { - pinctrl-single,pins = < - /* (Y2) WKUP_GPIO0_50 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) - >; - }; - - d12_gpio_pullup: d12-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y2) WKUP_GPIO0_50 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) - >; - }; - - d12_gpio_pulldown: d12-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y2) WKUP_GPIO0_50 */ - AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d13_spi0_clk: d13-spi0-clk-pins { - pinctrl-single,pins = < - /* (Y1) MCU_SPI0_CLK */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) - >; - }; - - d13_gpio: d13-gpio-pins { - pinctrl-single,pins = < - /* (Y1) WKUP_GPIO0_48 */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) - >; - }; - - d13_gpio_pullup: d13-gpio-pullup-pins { - pinctrl-single,pins = < - /* (Y1) WKUP_GPIO0_48 */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) - >; - }; - - d13_gpio_pulldown: d13-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (Y1) WKUP_GPIO0_48 */ - AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a0_gpio: a0-gpio-pins { - pinctrl-single,pins = < - /* (L6) WKUP_GPIO0_45 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) - >; - }; - - a0_gpio_pullup: a0-gpio-pullup-pins { - pinctrl-single,pins = < - /* (L6) WKUP_GPIO0_45 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) - >; - }; - - a0_gpio_pulldown: a0-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (L6) WKUP_GPIO0_45 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a1_gpio: a1-gpio-pins { - pinctrl-single,pins = < - /* (M6) WKUP_GPIO0_44 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) - >; - }; - - a1_gpio_pullup: a1-gpio-pullup-pins { - pinctrl-single,pins = < - /* (M6) WKUP_GPIO0_44 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) - >; - }; - - a1_gpio_pulldown: a1-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (M6) WKUP_GPIO0_44 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a2_gpio: a2-gpio-pins { - pinctrl-single,pins = < - /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) - >; - }; - - a2_gpio_pullup: a2-gpio-pullup-pins { - pinctrl-single,pins = < - /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) - >; - }; - - a2_gpio_pulldown: a2-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a3_gpio: a3-gpio-pins { - pinctrl-single,pins = < - /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) - >; - }; - - a3_gpio_pullup: a3-gpio-pullup-pins { - pinctrl-single,pins = < - /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) - >; - }; - - a3_gpio_pulldown: a3-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a4_gpio: a4-gpio-pins { - pinctrl-single,pins = < - /* (L2) WKUP_GPIO0_42 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) - >; - }; - - a4_gpio_pullup: a4-gpio-pullup-pins { - pinctrl-single,pins = < - /* (L2) WKUP_GPIO0_42 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) - >; - }; - - a4_gpio_pulldown: a4-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (L2) WKUP_GPIO0_42 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7) - >; - }; - - a5_gpio: a5-gpio-pins { - pinctrl-single,pins = < - /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7) - >; - }; - - a5_gpio_pullup: a5-gpio-pullup-pins { - pinctrl-single,pins = < - /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7) - >; - }; - - a5_gpio_pulldown: a5-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - /* (AC7) WKUP_I2C0_SCL */ - AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) - /* (AD6) WKUP_I2C0_SDA */ - AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) - >; - }; - mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < /* (AD8) MCU_I2C0_SCL */ @@ -623,13 +220,6 @@ >; }; - arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { - pinctrl-single,pins = < - /* (R2) WKUP_GPIO0_21 */ - AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) - >; - }; - push_button_pins_default: push-button-default-pins { pinctrl-single,pins = < /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ @@ -637,22 +227,6 @@ >; }; - - arduino_io_oe_pins_default: arduino-io-oe-default-pins { - pinctrl-single,pins = < - /* (N4) WKUP_GPIO0_34 */ - AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) - /* (M2) WKUP_GPIO0_36 */ - AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7) - /* (M3) WKUP_GPIO0_37 */ - AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7) - /* (M4) WKUP_GPIO0_38 */ - AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7) - /* (M1) WKUP_GPIO0_41 */ - AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) - >; - }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < /* (V1) MCU_OSPI0_CLK */ @@ -716,214 +290,6 @@ }; &main_pmx0 { - pinctrl-names = - "default", - "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown", - "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown", - "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown", - "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown", - "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown", - "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown"; - - pinctrl-0 = <&d4_ehrpwm0_a>; - pinctrl-1 = <&d4_ehrpwm0_a>; - pinctrl-2 = <&d4_gpio>; - pinctrl-3 = <&d4_gpio_pullup>; - pinctrl-4 = <&d4_gpio_pulldown>; - - pinctrl-5 = <&d5_ehrpwm1_a>; - pinctrl-6 = <&d5_gpio>; - pinctrl-7 = <&d5_gpio_pullup>; - pinctrl-8 = <&d5_gpio_pulldown>; - - pinctrl-9 = <&d6_ehrpwm2_a>; - pinctrl-10 = <&d6_gpio>; - pinctrl-11 = <&d6_gpio_pullup>; - pinctrl-12 = <&d6_gpio_pulldown>; - - pinctrl-13 = <&d7_ehrpwm3_a>; - pinctrl-14 = <&d7_gpio>; - pinctrl-15 = <&d7_gpio_pullup>; - pinctrl-16 = <&d7_gpio_pulldown>; - - pinctrl-17 = <&d8_ehrpwm4_a>; - pinctrl-18 = <&d8_gpio>; - pinctrl-19 = <&d8_gpio_pullup>; - pinctrl-20 = <&d8_gpio_pulldown>; - - pinctrl-21 = <&d9_ehrpwm5_a>; - pinctrl-22 = <&d9_gpio>; - pinctrl-23 = <&d9_gpio_pullup>; - pinctrl-24 = <&d9_gpio_pulldown>; - - d4_ehrpwm0_a: d4-ehrpwm0-a-pins { - pinctrl-single,pins = < - /* (AG18) EHRPWM0_A */ - AM65X_IOPAD(0x0084, PIN_OUTPUT, 5) - >; - }; - - d4_gpio: d4-gpio-pins { - pinctrl-single,pins = < - /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x0084, PIN_INPUT, 7) - >; - }; - - d4_gpio_pullup: d4-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) - >; - }; - - d4_gpio_pulldown: d4-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d5_ehrpwm1_a: d5-ehrpwm1-a-pins { - pinctrl-single,pins = < - /* (AF17) EHRPWM1_A */ - AM65X_IOPAD(0x008C, PIN_OUTPUT, 5) - >; - }; - - d5_gpio: d5-gpio-pins { - pinctrl-single,pins = < - /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT, 7) - >; - }; - - d5_gpio_pullup: d5-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7) - >; - }; - - d5_gpio_pulldown: d5-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d6_ehrpwm2_a: d6-ehrpwm2-a-pins { - pinctrl-single,pins = < - /* (AH16) EHRPWM2_A */ - AM65X_IOPAD(0x0098, PIN_OUTPUT, 5) - >; - }; - - d6_gpio: d6-gpio-pins { - pinctrl-single,pins = < - /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x0098, PIN_INPUT, 7) - >; - }; - - d6_gpio_pullup: d6-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7) - >; - }; - - d6_gpio_pulldown: d6-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d7_ehrpwm3_a: d7-ehrpwm3-a-pins { - pinctrl-single,pins = < - /* (AH15) EHRPWM3_A */ - AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5) - >; - }; - - d7_gpio: d7-gpio-pins { - pinctrl-single,pins = < - /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT, 7) - >; - }; - - d7_gpio_pullup: d7-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7) - >; - }; - - d7_gpio_pulldown: d7-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d8_ehrpwm4_a: d8-ehrpwm4-a-pins { - pinctrl-single,pins = < - /* (AG15) EHRPWM4_A */ - AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5) - >; - }; - - d8_gpio: d8-gpio-pins { - pinctrl-single,pins = < - /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT, 7) - >; - }; - - d8_gpio_pullup: d8-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7) - >; - }; - - d8_gpio_pulldown: d8-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7) - >; - }; - - d9_ehrpwm5_a: d9-ehrpwm5-a-pins { - pinctrl-single,pins = < - /* (AD15) EHRPWM5_A */ - AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5) - >; - }; - - d9_gpio: d9-gpio-pins { - pinctrl-single,pins = < - /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT, 7) - >; - }; - - d9_gpio_pullup: d9-gpio-pullup-pins { - pinctrl-single,pins = < - /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7) - >; - }; - - d9_gpio_pulldown: d9-gpio-pulldown-pins { - pinctrl-single,pins = < - /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) - >; - }; - main_pcie_enable_pins_default: main-pcie-enable-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ @@ -971,45 +337,6 @@ >; }; - dss_vout1_pins_default: dss-vout1-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ - AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ - AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ - AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ - AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ - AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ - AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ - AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ - AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ - AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ - AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ - AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ - AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ - AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ - AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ - AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ - AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ - AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ - AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ - AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ - AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ - AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ - AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ - AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ - AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ - AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ - AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ - AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ - >; - }; - - dp_pins_default: dp-default-pins { - pinctrl-single,pins = < - AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ - >; - }; - main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ @@ -1082,57 +409,11 @@ pinctrl-0 = <&main_uart1_pins_default>; }; -&mcu_uart0 { - status = "okay"; -}; - -&main_gpio0 { - gpio-line-names = - "main_gpio0-base", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "IO4", "", "IO5", "", "", "IO6", "", - "", "", "", "IO7", "", "", "", "", "IO8", "", - "", "IO9"; -}; - &main_gpio1 { pinctrl-names = "default"; pinctrl-0 = <&main_pcie_enable_pins_default>; }; -&wkup_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = - <&arduino_i2c_aio_switch_pins_default>, - <&arduino_io_oe_pins_default>, - <&push_button_pins_default>, - <&db9_com_mode_pins_default>; - gpio-line-names = - /* 0..9 */ - "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", - "UART0-enable", "UART0-terminate", "", "WIFI-disable", - /* 10..19 */ - "", "", "", "", "", "", "", "", "", "", - /* 20..29 */ - "", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0", - /* 30..39 */ - "IO1", "IO2", "", "IO3", "IO17-direction", "A5", - "IO16-direction", "IO15-direction", "IO14-direction", "A3", - /* 40..49 */ - "", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13", - "IO11", - /* 50..51 */ - "IO12", "IO10"; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; -}; - &mcu_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -1150,47 +431,6 @@ ti,vsel1-state-high; ti,enable-vout-discharge; }; - - /* D4200 */ - pcal9535_1: gpio@20 { - compatible = "nxp,pcal9535"; - reg = <0x20>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull", - "A5-pull", "", "", - "IO14-enable", "IO15-enable", "IO16-enable", - "IO17-enable", "IO18-enable", "IO19-enable"; - }; - - /* D4201 */ - pcal9535_2: gpio@21 { - compatible = "nxp,pcal9535"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "IO0-direction", "IO1-direction", "IO2-direction", - "IO3-direction", "IO4-direction", "IO5-direction", - "IO6-direction", "IO7-direction", - "IO8-direction", "IO9-direction", "IO10-direction", - "IO11-direction", "IO12-direction", "IO13-direction", - "IO19-direction"; - }; - - /* D4202 */ - pcal9535_3: gpio@25 { - compatible = "nxp,pcal9535"; - reg = <0x25>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull", - "IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull", - "IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull", - "IO12-pull", "IO13-pull"; - }; }; &main_i2c0 { @@ -1233,32 +473,6 @@ #address-cells = <1>; #size-cells = <0>; - - edp-bridge@f { - compatible = "toshiba,tc358767"; - reg = <0x0f>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_pins_default>; - reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; - - clock-names = "ref"; - clocks = <&dp_refclk>; - - toshiba,hpd-pin = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - bridge_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - }; }; &mcu_cpsw { @@ -1292,13 +506,6 @@ ti,pindir-d0-out-d1-in; }; -&tscadc1 { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5>; - }; -}; - &ospi0 { status = "okay"; pinctrl-names = "default"; @@ -1364,26 +571,6 @@ }; }; -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&dss_vout1_pins_default>; - - assigned-clocks = <&k3_clks 67 2>; - assigned-clock-parents = <&k3_clks 67 5>; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - - dpi_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; -}; - &pcie1_rc { status = "okay"; pinctrl-names = "default"; @@ -1418,13 +605,17 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; +}; + +&mcu_rti1 { + memory-region = <&wdt_reset_memory_region>; }; &icssg0_mdio { diff --git a/dts/src/arm64/ti/k3-am65-iot2050-dp.dtsi b/dts/src/arm64/ti/k3-am65-iot2050-dp.dtsi new file mode 100644 index 0000000000..984cc80913 --- /dev/null +++ b/dts/src/arm64/ti/k3-am65-iot2050-dp.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + * + * Common bits for IOT2050 variants with Display Port + */ + +&main_pmx0 { + dss_vout1_pins_default: dss-vout1-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ + AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ + AM65X_IOPAD(0x0008, PIN_OUTPUT, 1) /* VOUT1_DATA2 */ + AM65X_IOPAD(0x000c, PIN_OUTPUT, 1) /* VOUT1_DATA3 */ + AM65X_IOPAD(0x0010, PIN_OUTPUT, 1) /* VOUT1_DATA4 */ + AM65X_IOPAD(0x0014, PIN_OUTPUT, 1) /* VOUT1_DATA5 */ + AM65X_IOPAD(0x0018, PIN_OUTPUT, 1) /* VOUT1_DATA6 */ + AM65X_IOPAD(0x001c, PIN_OUTPUT, 1) /* VOUT1_DATA7 */ + AM65X_IOPAD(0x0020, PIN_OUTPUT, 1) /* VOUT1_DATA8 */ + AM65X_IOPAD(0x0024, PIN_OUTPUT, 1) /* VOUT1_DATA9 */ + AM65X_IOPAD(0x0028, PIN_OUTPUT, 1) /* VOUT1_DATA10 */ + AM65X_IOPAD(0x002c, PIN_OUTPUT, 1) /* VOUT1_DATA11 */ + AM65X_IOPAD(0x0030, PIN_OUTPUT, 1) /* VOUT1_DATA12 */ + AM65X_IOPAD(0x0034, PIN_OUTPUT, 1) /* VOUT1_DATA13 */ + AM65X_IOPAD(0x0038, PIN_OUTPUT, 1) /* VOUT1_DATA14 */ + AM65X_IOPAD(0x003c, PIN_OUTPUT, 1) /* VOUT1_DATA15 */ + AM65X_IOPAD(0x0040, PIN_OUTPUT, 1) /* VOUT1_DATA16 */ + AM65X_IOPAD(0x0044, PIN_OUTPUT, 1) /* VOUT1_DATA17 */ + AM65X_IOPAD(0x0048, PIN_OUTPUT, 1) /* VOUT1_DATA18 */ + AM65X_IOPAD(0x004c, PIN_OUTPUT, 1) /* VOUT1_DATA19 */ + AM65X_IOPAD(0x0050, PIN_OUTPUT, 1) /* VOUT1_DATA20 */ + AM65X_IOPAD(0x0054, PIN_OUTPUT, 1) /* VOUT1_DATA21 */ + AM65X_IOPAD(0x0058, PIN_OUTPUT, 1) /* VOUT1_DATA22 */ + AM65X_IOPAD(0x005c, PIN_OUTPUT, 1) /* VOUT1_DATA23 */ + AM65X_IOPAD(0x0060, PIN_OUTPUT, 1) /* VOUT1_VSYNC */ + AM65X_IOPAD(0x0064, PIN_OUTPUT, 1) /* VOUT1_HSYNC */ + AM65X_IOPAD(0x0068, PIN_OUTPUT, 1) /* VOUT1_PCLK */ + AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ + >; + }; + + dp_pins_default: dp-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ + >; + }; +}; + +&main_i2c3 { + edp-bridge@f { + compatible = "toshiba,tc358767"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&dp_pins_default>; + reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + + clock-names = "ref"; + clocks = <&dp_refclk>; + + toshiba,hpd-pin = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + bridge_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout1_pins_default>; + + assigned-clocks = <&k3_clks 67 2>; + assigned-clock-parents = <&k3_clks 67 5>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + + dpi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; +}; diff --git a/dts/src/arm64/ti/k3-am65-iot2050-usb3.dtsi b/dts/src/arm64/ti/k3-am65-iot2050-usb3.dtsi new file mode 100644 index 0000000000..e5bd7c301b --- /dev/null +++ b/dts/src/arm64/ti/k3-am65-iot2050-usb3.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + * + * Common bits for IOT2050 variants with USB3 support + */ + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; diff --git a/dts/src/arm64/ti/k3-am65-main.dtsi b/dts/src/arm64/ti/k3-am65-main.dtsi index fcea544656..ff857117d7 100644 --- a/dts/src/arm64/ti/k3-am65-main.dtsi +++ b/dts/src/arm64/ti/k3-am65-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family Main Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy-am654-serdes.h> @@ -886,20 +886,6 @@ status = "disabled"; }; - pcie0_ep: pcie-ep@5500000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&scm_conf 0x4060>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - pcie1_rc: pcie@5600000 { compatible = "ti,am654-pcie-rc"; reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; @@ -921,20 +907,6 @@ status = "disabled"; }; - pcie1_ep: pcie-ep@5600000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&scm_conf 0x4070>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - mcasp0: mcasp@2b00000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b00000 0x0 0x2000>, @@ -1019,9 +991,10 @@ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; @@ -1050,6 +1023,13 @@ }; }; + gpu: gpu@7000000 { + compatible = "ti,am6548-gpu", "img,powervr-sgx544"; + reg = <0x0 0x7000000 0x0 0x10000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + }; + ehrpwm0: pwm@3000000 { compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; diff --git a/dts/src/arm64/ti/k3-am65-mcu.dtsi b/dts/src/arm64/ti/k3-am65-mcu.dtsi index ecd7356f33..6ff3ccc39f 100644 --- a/dts/src/arm64/ti/k3-am65-mcu.dtsi +++ b/dts/src/arm64/ti/k3-am65-mcu.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family MCU Domain peripherals * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { diff --git a/dts/src/arm64/ti/k3-am65-wakeup.dtsi b/dts/src/arm64/ti/k3-am65-wakeup.dtsi index f037b36243..37527890dd 100644 --- a/dts/src/arm64/ti/k3-am65-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-am65-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_wakeup { diff --git a/dts/src/arm64/ti/k3-am65.dtsi b/dts/src/arm64/ti/k3-am65.dtsi index 4d7b6155a7..c59baebc5a 100644 --- a/dts/src/arm64/ti/k3-am65.dtsi +++ b/dts/src/arm64/ti/k3-am65.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC Family * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/dts/src/arm64/ti/k3-am652.dtsi b/dts/src/arm64/ti/k3-am652.dtsi index 0f22e00faa..cbb3caaf82 100644 --- a/dts/src/arm64/ti/k3-am652.dtsi +++ b/dts/src/arm64/ti/k3-am652.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM65 SoC family in Dual core configuration * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am65.dtsi" diff --git a/dts/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi b/dts/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi index 1d6cddb119..eed6fe70d2 100644 --- a/dts/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/dts/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -11,6 +11,7 @@ #include "k3-am652.dtsi" #include "k3-am65-iot2050-common.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" / { memory@80000000 { @@ -40,8 +41,3 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; - -&mcu_r5fss0 { - /* lock-step mode not supported on Basic boards */ - ti,cluster-mode = <0>; -}; diff --git a/dts/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts b/dts/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts index c62549a4b4..c1faf9497b 100644 --- a/dts/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts +++ b/dts/src/arm64/ti/k3-am6528-iot2050-basic-pg2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -17,6 +17,8 @@ #include "k3-am6528-iot2050-basic-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-dp.dtsi" +#include "k3-am65-iot2050-usb3.dtsi" / { compatible = "siemens,iot2050-basic-pg2", "ti,am654"; diff --git a/dts/src/arm64/ti/k3-am6528-iot2050-basic.dts b/dts/src/arm64/ti/k3-am6528-iot2050-basic.dts index 87928ff282..29a31891b3 100644 --- a/dts/src/arm64/ti/k3-am6528-iot2050-basic.dts +++ b/dts/src/arm64/ti/k3-am6528-iot2050-basic.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -22,3 +22,8 @@ compatible = "siemens,iot2050-basic", "ti,am654"; model = "SIMATIC IOT2050 Basic"; }; + +&mcu_r5fss0 { + /* lock-step mode not supported on this board */ + ti,cluster-mode = <0>; +}; diff --git a/dts/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso b/dts/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso index 3be92c39ec..364c57b3b3 100644 --- a/dts/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso +++ b/dts/src/arm64/ti/k3-am654-base-board-rocktech-rk101-panel.dtso @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM. * Panel Link: https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT * AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM * - * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am654-base-board.dts b/dts/src/arm64/ti/k3-am654-base-board.dts index 822c288d27..aba0c52b12 100644 --- a/dts/src/arm64/ti/k3-am654-base-board.dts +++ b/dts/src/arm64/ti/k3-am654-base-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -531,13 +531,13 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; &ospi0 { diff --git a/dts/src/arm64/ti/k3-am654-icssg2.dtso b/dts/src/arm64/ti/k3-am654-icssg2.dtso index ec8cf20ca3..0a6e75265b 100644 --- a/dts/src/arm64/ti/k3-am654-icssg2.dtso +++ b/dts/src/arm64/ti/k3-am654-icssg2.dtso @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT overlay for IDK application board on AM654 EVM * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am654-idk.dtso b/dts/src/arm64/ti/k3-am654-idk.dtso index 150428dfce..8bdb87fcbd 100644 --- a/dts/src/arm64/ti/k3-am654-idk.dtso +++ b/dts/src/arm64/ti/k3-am654-idk.dtso @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT overlay for IDK application board on AM654 EVM * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-am654-industrial-thermal.dtsi b/dts/src/arm64/ti/k3-am654-industrial-thermal.dtsi index 9021c73805..de5a2ed907 100644 --- a/dts/src/arm64/ti/k3-am654-industrial-thermal.dtsi +++ b/dts/src/arm64/ti/k3-am654-industrial-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/dts/src/arm64/ti/k3-am654-pcie-usb2.dtso b/dts/src/arm64/ti/k3-am654-pcie-usb2.dtso new file mode 100644 index 0000000000..c3cb752f8c --- /dev/null +++ b/dts/src/arm64/ti/k3-am654-pcie-usb2.dtso @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-am654-serdes.h> +#include "k3-pinctrl.h" + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, + <&serdes0 AM654_SERDES_CMU_REFCLK>, + <&serdes0 AM654_SERDES_RO_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, + <&k3_clks 153 4>, + <&k3_clks 153 4>; + status = "okay"; +}; + +&serdes1 { + assigned-clocks = <&serdes1 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&serdes0 AM654_SERDES_RO_REFCLK>; + status = "okay"; +}; + +&pcie0_rc { + num-lanes = <2>; + phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0", "pcie-phy1"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_pmx0 { + usb0_pins_default: usb0-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&dwc3_0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; +}; diff --git a/dts/src/arm64/ti/k3-am654-pcie-usb3.dtso b/dts/src/arm64/ti/k3-am654-pcie-usb3.dtso new file mode 100644 index 0000000000..333e423e8b --- /dev/null +++ b/dts/src/arm64/ti/k3-am654-pcie-usb3.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-am654-serdes.h> + +#include "k3-pinctrl.h" + +&serdes1 { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_pmx0 { + usb0_pins_default: usb0-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&serdes0 { + status = "okay"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + status = "okay"; + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; + +&usb0_phy { + status = "okay"; +}; diff --git a/dts/src/arm64/ti/k3-am654.dtsi b/dts/src/arm64/ti/k3-am654.dtsi index 888567b921..bb77c84547 100644 --- a/dts/src/arm64/ti/k3-am654.dtsi +++ b/dts/src/arm64/ti/k3-am654.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for AM6 SoC family in Quad core configuration * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am65.dtsi" diff --git a/dts/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi b/dts/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi index 3864ec54e3..ae842b85b7 100644 --- a/dts/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/dts/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * diff --git a/dts/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts b/dts/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts index bd6f2e696e..cc619bbec1 100644 --- a/dts/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/dts/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2023 * @@ -15,17 +15,14 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" +#include "k3-am65-iot2050-dp.dtsi" / { compatible = "siemens,iot2050-advanced-m2", "ti,am654"; model = "SIMATIC IOT2050 Advanced M2"; }; -&mcu_r5fss0 { - /* lock-step mode not supported on this board */ - ti,cluster-mode = <0>; -}; - &main_pmx0 { main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { pinctrl-single,pins = < @@ -96,16 +93,3 @@ &pcie1_rc { status = "disabled"; }; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ - /delete-property/ phys; - /delete-property/ phy-names; -}; - -&usb0 { - maximum-speed = "high-speed"; - /delete-property/ snps,dis-u1-entry-quirk; - /delete-property/ snps,dis-u2-entry-quirk; -}; diff --git a/dts/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts b/dts/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts index f00dc86d01..ec721275e8 100644 --- a/dts/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts +++ b/dts/src/arm64/ti/k3-am6548-iot2050-advanced-pg2.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2018-2021 + * Copyright (c) Siemens AG, 2018-2023 * * Authors: * Le Jin <le.jin@siemens.com> @@ -17,13 +17,11 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" +#include "k3-am65-iot2050-dp.dtsi" +#include "k3-am65-iot2050-usb3.dtsi" / { compatible = "siemens,iot2050-advanced-pg2", "ti,am654"; model = "SIMATIC IOT2050 Advanced PG2"; }; - -&mcu_r5fss0 { - /* lock-step mode not supported on this board */ - ti,cluster-mode = <0>; -}; diff --git a/dts/src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts b/dts/src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts new file mode 100644 index 0000000000..b829f4bcab --- /dev/null +++ b/dts/src/arm64/ti/k3-am6548-iot2050-advanced-sm.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Siemens AG, 2023 + * + * Authors: + * Baocheng Su <baocheng.su@siemens.com> + * Chao Zeng <chao.zeng@siemens.com> + * Huaqian Li <huaqian.li@siemens.com> + * + * AM6548-based (quad-core) IOT2050 SM variant, Product Generation 2 + * 4 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 + * + * Product homepage: + * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html + */ + +/dts-v1/; + +#include "k3-am6548-iot2050-advanced-common.dtsi" +#include "k3-am65-iot2050-common-pg2.dtsi" + +/ { + compatible = "siemens,iot2050-advanced-sm", "ti,am654"; + model = "SIMATIC IOT2050 Advanced SM"; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + aliases { + spi1 = &main_spi0; + }; + + leds { + pinctrl-0 = <&leds_pins_default>, <&user1_led_pins>; + + led-2 { + gpios = <&wkup_gpio0 52 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + gpios = <&wkup_gpio0 53 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&main_pmx0 { + main_pcie_enable_pins_default: main-pcie-enable-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x01d8, PIN_OUTPUT, 7) /* (AH12) GPIO1_22 */ + >; + }; + + main_spi0_pins: main-spi0-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ + AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ + AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ + AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ + >; + }; +}; + +&main_pmx1 { + asic_spi_mux_ctrl_pin: asic-spi-mux-ctrl-default-pins { + pinctrl-single,pins = < + AM65X_IOPAD(0x0010, PIN_OUTPUT, 7) /* (D21) GPIO1_86 */ + >; + }; +}; + +&wkup_pmx0 { + user1_led_pins: user1-led-default-pins { + pinctrl-single,pins = < + /* (AB1) WKUP_UART0_RXD:WKUP_GPIO0_52, as USER 1 led red */ + AM65X_WKUP_IOPAD(0x00a0, PIN_OUTPUT, 7) + /* (AB5) WKUP_UART0_TXD:WKUP_GPIO0_53, as USER 1 led green */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 7) + >; + }; + + soc_asic_pins: soc-asic-default-pins { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7) /* (P1) WKUP_GPIO0_31 */ + >; + }; +}; + +&main_gpio0 { + gpio-line-names = "main_gpio0-base"; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = + <&cp2102n_reset_pin_default>, + <&main_pcie_enable_pins_default>, + <&asic_spi_mux_ctrl_pin>; + gpio-line-names = + /* 0..9 */ + "", "", "", "", "", "", "", "", "", "", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "", "", "", "CP2102N-RESET", "", "", "", "", "", + /* 30..39 */ + "", "", "", "", "", "", "", "", "", "", + /* 40..49 */ + "", "", "", "", "", "", "", "", "", "", + /* 50..59 */ + "", "", "", "", "", "", "", "", "", "", + /* 60..69 */ + "", "", "", "", "", "", "", "", "", "", + /* 70..79 */ + "", "", "", "", "", "", "", "", "", "", + /* 80..86 */ + "", "", "", "", "", "", "ASIC-spi-mux-ctrl"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = + <&push_button_pins_default>, + <&db9_com_mode_pins_default>, + <&soc_asic_pins>; + gpio-line-names = + /* 0..9 */ + "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", + "UART0-enable", "UART0-terminate", "", "WIFI-disable", + /* 10..19 */ + "", "", "", "", "", "", "", "", "", "", + /* 20..29 */ + "", "", "", "", "", "USER-button", "", "", "","ASIC-gpio-0", + /* 30..31 */ + "ASIC-gpio-1", "ASIC-gpio-2"; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins>; + + #address-cells = <1>; + #size-cells= <0>; +}; + +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins_default>; +}; + +&main_i2c3 { + accelerometer: lsm6dso@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&dss { + status = "disabled"; +}; + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; +}; + +&serdes1 { + status = "disabled"; +}; + +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pins_default>; + + num-lanes = <1>; + phys = <&serdes0 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0"; + reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie1_rc { + status = "disabled"; +}; diff --git a/dts/src/arm64/ti/k3-am6548-iot2050-advanced.dts b/dts/src/arm64/ti/k3-am6548-iot2050-advanced.dts index 077f165bdc..649652a540 100644 --- a/dts/src/arm64/ti/k3-am6548-iot2050-advanced.dts +++ b/dts/src/arm64/ti/k3-am6548-iot2050-advanced.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) Siemens AG, 2018-2021 * @@ -17,6 +17,7 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg1.dtsi" +#include "k3-am65-iot2050-arduino-connector.dtsi" / { compatible = "siemens,iot2050-advanced", "ti,am654"; diff --git a/dts/src/arm64/ti/k3-am68-sk-base-board.dts b/dts/src/arm64/ti/k3-am68-sk-base-board.dts index d0cfdeac21..d743f023cd 100644 --- a/dts/src/arm64/ti/k3-am68-sk-base-board.dts +++ b/dts/src/arm64/ti/k3-am68-sk-base-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Base Board: https://www.ti.com/lit/zip/SPRR463 */ @@ -169,6 +169,13 @@ }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; }; &main_pmx0 { @@ -186,6 +193,13 @@ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -431,6 +445,42 @@ }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + status = "okay"; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_i2c4 { status = "okay"; pinctrl-names = "default"; diff --git a/dts/src/arm64/ti/k3-am68-sk-som.dtsi b/dts/src/arm64/ti/k3-am68-sk-som.dtsi index 20861a0a46..0f4a5da0eb 100644 --- a/dts/src/arm64/ti/k3-am68-sk-som.dtsi +++ b/dts/src/arm64/ti/k3-am68-sk-som.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -209,51 +209,51 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; &c71_1 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; diff --git a/dts/src/arm64/ti/k3-am69-sk.dts b/dts/src/arm64/ti/k3-am69-sk.dts index 8da5915798..50de2a448a 100644 --- a/dts/src/arm64/ti/k3-am69-sk.dts +++ b/dts/src/arm64/ti/k3-am69-sk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Design Files: https://www.ti.com/lit/zip/SPRR466 * TRM: https://www.ti.com/lit/zip/spruj52 @@ -33,6 +33,7 @@ memory@80000000 { device_type = "memory"; + bootph-all; /* 32G RAM */ reg = <0x00 0x80000000 0x00 0x80000000>, <0x08 0x80000000 0x07 0x80000000>; @@ -321,6 +322,38 @@ }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + }; &main_pmx0 { @@ -340,6 +373,13 @@ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -429,6 +469,40 @@ J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ >; }; + + main_mcan6_pins_default: main-mcan6-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */ + J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */ + >; + }; + + main_mcan7_pins_default: main-mcan7-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ + J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ + >; + }; + +}; + +&wkup_pmx0 { + bootph-all; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; }; &wkup_pmx2 { @@ -525,6 +599,21 @@ J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + }; &wkup_pmx3 { @@ -646,7 +735,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pmic_irq_pins_default>; interrupt-parent = <&wkup_gpio0>; - interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + interrupts = <83 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; ti,primary-pmic; @@ -774,6 +863,42 @@ }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ @@ -822,77 +947,77 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &main_r5fss2_core0 { - mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core0>; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; memory-region = <&main_r5fss2_core0_dma_memory_region>, <&main_r5fss2_core0_memory_region>; }; &main_r5fss2_core1 { - mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core1>; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; memory-region = <&main_r5fss2_core1_dma_memory_region>, <&main_r5fss2_core1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; &c71_1 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; &c71_2 { status = "okay"; - mboxes = <&mailbox0_cluster5>, <&mbox_c71_2>; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; memory-region = <&c71_2_dma_memory_region>, <&c71_2_memory_region>; }; &c71_3 { status = "okay"; - mboxes = <&mailbox0_cluster5>, <&mbox_c71_3>; + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; memory-region = <&c71_3_dma_memory_region>, <&c71_3_memory_region>; }; @@ -918,13 +1043,9 @@ pinctrl-names = "default"; pinctrl-0 = <&dss_vout0_pins_default>; assigned-clocks = <&k3_clks 218 2>, - <&k3_clks 218 5>, - <&k3_clks 218 14>, - <&k3_clks 218 18>; + <&k3_clks 218 5>; assigned-clock-parents = <&k3_clks 218 3>, - <&k3_clks 218 7>, - <&k3_clks 218 16>, - <&k3_clks 218 22>; + <&k3_clks 218 7>; }; &serdes_wiz4 { @@ -992,3 +1113,93 @@ }; }; }; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan6_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan7_pins_default>; + phys = <&transceiver4>; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + bootph-all; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-pre-ram; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; diff --git a/dts/src/arm64/ti/k3-j7200-common-proc-board.dts b/dts/src/arm64/ti/k3-j7200-common-proc-board.dts index cee2b4b0eb..6593c5da82 100644 --- a/dts/src/arm64/ti/k3-j7200-common-proc-board.dts +++ b/dts/src/arm64/ti/k3-j7200-common-proc-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -88,27 +88,56 @@ states = <1800000 0x0>, <3300000 0x1>; }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_LOW>; + enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; + standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + mux-states = <&mux0 1>; + }; }; &wkup_pmx0 { +}; + +&wkup_pmx2 { mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ - J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ - J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ - J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0x90, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ >; }; wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ >; }; -}; -&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ @@ -138,6 +167,33 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x54, PIN_INPUT, 0) /* (A17) MCU_MCAN0_RX */ + J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (A16) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 0) /* (B16) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (D13) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; + + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x58, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */ + J721E_WKUP_IOPAD(0x40, PIN_INPUT, 7) /* (B17) MCU_SPI0_D1 */ + >; + }; + + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x60, PIN_INPUT, 7) /* (D14) WKUP_GPIO0_2 */ + >; + }; }; &main_pmx0 { @@ -189,6 +245,13 @@ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ >; }; + + main_mcan3_pins_default: main-mcan3-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x3c, PIN_INPUT, 0) /* (W16) MCAN3_RX */ + J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */ + >; + }; }; &main_pmx1 { @@ -210,7 +273,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; - clock-frequency = <96000000>; }; &main_uart0 { @@ -382,15 +444,30 @@ }; &pcie1_rc { + status = "okay"; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; -&pcie1_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan3_pins_default>; + phys = <&transceiver3>; }; diff --git a/dts/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/dts/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso index 32d905235e..6432ca08ee 100644 --- a/dts/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso +++ b/dts/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with * J7200 board. * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-j7200-main.dtsi b/dts/src/arm64/ti/k3-j7200-main.dtsi index da67bf8fe7..657f9cc9f4 100644 --- a/dts/src/arm64/ti/k3-j7200-main.dtsi +++ b/dts/src/arm64/ti/k3-j7200-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J7200 SoC Family Main Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ / { @@ -33,10 +33,11 @@ ranges = <0x00 0x00 0x00100000 0x1c000>; serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; + compatible = "reg-mux"; + reg = <0x4080 0x20>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */ }; cpsw0_phy_gmii_sel: phy@4044 { @@ -47,9 +48,10 @@ }; usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; + compatible = "reg-mux"; + reg = <0x4000 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; }; @@ -399,7 +401,7 @@ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x104200 0x0 0x50>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -408,7 +410,7 @@ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x104280 0x0 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -416,7 +418,7 @@ }; main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c000 0x00 0x10c>; #pinctrl-cells = <1>; @@ -425,7 +427,7 @@ }; main_pmx1: pinctrl@11c11c { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x11c11c 0x00 0xc>; #pinctrl-cells = <1>; @@ -770,26 +772,7 @@ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <4>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 6>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; + status = "disabled"; }; usbss0: cdns-usb@4104000 { @@ -895,6 +878,276 @@ status = "disabled"; }; + main_mcan0: can@2701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02701000 0x00 0x200>, + <0x00 0x02708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>, <&k3_clks 156 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan1: can@2711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02711000 0x00 0x200>, + <0x00 0x02718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>, <&k3_clks 158 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan2: can@2721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02721000 0x00 0x200>, + <0x00 0x02728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 160 0>, <&k3_clks 160 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan3: can@2731000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02731000 0x00 0x200>, + <0x00 0x02738000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 161 0>, <&k3_clks 161 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan4: can@2741000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02741000 0x00 0x200>, + <0x00 0x02748000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan5: can@2751000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02751000 0x00 0x200>, + <0x00 0x02758000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 163 0>, <&k3_clks 163 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan6: can@2761000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02761000 0x00 0x200>, + <0x00 0x02768000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 164 0>, <&k3_clks 164 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan7: can@2771000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02771000 0x00 0x200>, + <0x00 0x02778000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 165 0>, <&k3_clks 165 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan8: can@2781000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02781000 0x00 0x200>, + <0x00 0x02788000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 166 0>, <&k3_clks 166 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan9: can@2791000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02791000 0x00 0x200>, + <0x00 0x02798000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 167 0>, <&k3_clks 167 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan10: can@27a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027a1000 0x00 0x200>, + <0x00 0x027a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 168 0>, <&k3_clks 168 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan11: can@27b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027b1000 0x00 0x200>, + <0x00 0x027b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 169 0>, <&k3_clks 169 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan12: can@27c1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027c1000 0x00 0x200>, + <0x00 0x027c8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 170 0>, <&k3_clks 170 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan13: can@27d1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x027d1000 0x00 0x200>, + <0x00 0x027d8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 171 0>, <&k3_clks 171 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan14: can@2681000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02681000 0x00 0x200>, + <0x00 0x02688000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 150 0>, <&k3_clks 150 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan15: can@2691000 { + compatible = "bosch,m_can"; + reg = <0x00 0x02691000 0x00 0x200>, + <0x00 0x02698000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 151 0>, <&k3_clks 151 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan16: can@26a1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026a1000 0x00 0x200>, + <0x00 0x026a8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>, <&k3_clks 152 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_mcan17: can@26b1000 { + compatible = "bosch,m_can"; + reg = <0x00 0x026b1000 0x00 0x200>, + <0x00 0x026b8000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>, <&k3_clks 153 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + main_spi0: spi@2100000 { compatible = "ti,am654-mcspi","ti,omap4-mcspi"; reg = <0x00 0x02100000 0x00 0x400>; diff --git a/dts/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/dts/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi index 60b26374ae..7cf21c9995 100644 --- a/dts/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -192,7 +192,7 @@ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x40f04200 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -202,7 +202,7 @@ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x0 0x40f04280 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -211,7 +211,7 @@ }; wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x34>; #pinctrl-cells = <1>; @@ -220,7 +220,7 @@ }; wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x8>; #pinctrl-cells = <1>; @@ -229,7 +229,7 @@ }; wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0xec>; #pinctrl-cells = <1>; @@ -238,7 +238,7 @@ }; wkup_pmx3: pinctrl@4301c174 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c174 0x00 0x20>; #pinctrl-cells = <1>; @@ -518,17 +518,18 @@ status = "disabled"; }; - fss: syscon@47000000 { - compatible = "syscon", "simple-mfd"; + fss: bus@47000000 { + compatible = "simple-bus"; reg = <0x00 0x47000000 0x00 0x100>; #address-cells = <2>; #size-cells = <2>; ranges; - hbmc_mux: hbmc-mux { - compatible = "mmio-mux"; + hbmc_mux: mux-controller@47000004 { + compatible = "reg-mux"; + reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ + mux-reg-masks = <0x0 0x2>; /* HBMC select */ }; hbmc: hyperbus@47034000 { @@ -655,4 +656,34 @@ ti,esm-pins = <95>; bootph-pre-ram; }; + + mcu_mcan0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40528000 0x00 0x200>, + <0x00 0x40500000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>, <&k3_clks 172 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x00 0x40568000 0x00 0x200>, + <0x00 0x40540000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>, <&k3_clks 173 2>; + clock-names = "hclk", "cclk"; + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; diff --git a/dts/src/arm64/ti/k3-j7200-som-p0.dtsi b/dts/src/arm64/ti/k3-j7200-som-p0.dtsi index ea47f10d39..7e6a584ac6 100644 --- a/dts/src/arm64/ti/k3-j7200-som-p0.dtsi +++ b/dts/src/arm64/ti/k3-j7200-som-p0.dtsi @@ -1,10 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> + #include "k3-j7200.dtsi" / { @@ -80,6 +82,25 @@ no-map; }; }; + + mux0: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; + }; + + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver0: can-phy0 { + /* standby pin has been grounded by default */ + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; }; &wkup_pmx0 { @@ -142,6 +163,13 @@ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ >; }; + + main_mcan0_pins_default: main-mcan0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */ + J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */ + >; + }; }; &hbmc { @@ -222,25 +250,25 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; @@ -478,3 +506,10 @@ }; }; }; + +&main_mcan0 { + status = "okay"; + pinctrl-0 = <&main_mcan0_pins_default>; + pinctrl-names = "default"; + phys = <&transceiver0>; +}; diff --git a/dts/src/arm64/ti/k3-j7200-thermal.dtsi b/dts/src/arm64/ti/k3-j7200-thermal.dtsi index e7e3a643a6..2d22a95a6f 100644 --- a/dts/src/arm64/ti/k3-j7200-thermal.dtsi +++ b/dts/src/arm64/ti/k3-j7200-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/dts/src/arm64/ti/k3-j7200.dtsi b/dts/src/arm64/ti/k3-j7200.dtsi index ef73e6d7e8..d411911fdf 100644 --- a/dts/src/arm64/ti/k3-j7200.dtsi +++ b/dts/src/arm64/ti/k3-j7200.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J7200 SoC Family * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/irq.h> diff --git a/dts/src/arm64/ti/k3-j721e-beagleboneai64.dts b/dts/src/arm64/ti/k3-j721e-beagleboneai64.dts index 2f954729f3..a2925555fe 100644 --- a/dts/src/arm64/ti/k3-j721e-beagleboneai64.dts +++ b/dts/src/arm64/ti/k3-j721e-beagleboneai64.dts @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * https://beagleboard.org/ai-64 - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation - * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Jason Kridner, BeagleBoard.org Foundation + * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation */ /dts-v1/; @@ -936,58 +936,58 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/dts/src/arm64/ti/k3-j721e-common-proc-board.dts b/dts/src/arm64/ti/k3-j721e-common-proc-board.dts index fe5207ac7d..8230d53cd6 100644 --- a/dts/src/arm64/ti/k3-j721e-common-proc-board.dts +++ b/dts/src/arm64/ti/k3-j721e-common-proc-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Product Link: https://www.ti.com/tool/J721EXCPXEVM */ diff --git a/dts/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso b/dts/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso index 6a7d37575d..f84aa9f945 100644 --- a/dts/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso +++ b/dts/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso @@ -1,11 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with * J721E board. * * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso b/dts/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso index 0c82a13b65..4062709d65 100644 --- a/dts/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso +++ b/dts/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso @@ -1,11 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the * J7 common processor board. * * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/dts/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso index d4c51ffc3d..8376fa4b6e 100644 --- a/dts/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso +++ b/dts/src/arm64/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -1,9 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with * J721E board. * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-j721e-main.dtsi b/dts/src/arm64/ti/k3-j721e-main.dtsi index 2569b4c08f..c7eafbc862 100644 --- a/dts/src/arm64/ti/k3-j721e-main.dtsi +++ b/dts/src/arm64/ti/k3-j721e-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family Main Domain peripherals * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy-ti.h> @@ -45,15 +45,15 @@ ranges = <0x0 0x0 0x00100000 0x1c000>; serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - reg = <0x00004080 0x50>; + compatible = "reg-mux"; + reg = <0x4080 0x50>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ - <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; - /* SERDES4 lane0/1/2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ + <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ + <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */ + <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ + <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, @@ -70,10 +70,11 @@ }; usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; + compatible = "reg-mux"; + reg = <0x4000 0x20>; #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ - <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ + mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */ + <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */ }; ehrpwm_tbclk: clock-controller@4140 { @@ -572,6 +573,128 @@ pinctrl-single,function-mask = <0x0000001f>; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4500000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4504000 0x0 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4510000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4960>; + dma-names = "rx0"; + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4514000 0x0 0x1000>; + clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4580000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4590000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; diff --git a/dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi index a74912d9e4..4618b697fb 100644 --- a/dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -353,9 +353,9 @@ hbmc_mux: mux-controller@47000004 { compatible = "reg-mux"; - reg = <0x00 0x47000004 0x00 0x2>; + reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ + mux-reg-masks = <0x0 0x2>; /* HBMC select */ }; hbmc: hyperbus@47034000 { diff --git a/dts/src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/dts/src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso new file mode 100644 index 0000000000..47bb5480b5 --- /dev/null +++ b/dts/src/arm64/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 + * on J721E SK, AM68 SK or AM69-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&csi_mux { + idle-state = <1>; +}; + +/* CAM0 I2C */ +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_0: imx219-0@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +/* CAM1 I2C */ +&cam1_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_1: imx219-1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; diff --git a/dts/src/arm64/ti/k3-j721e-sk.dts b/dts/src/arm64/ti/k3-j721e-sk.dts index 188dfe291a..0c4575ad8d 100644 --- a/dts/src/arm64/ti/k3-j721e-sk.dts +++ b/dts/src/arm64/ti/k3-j721e-sk.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ * * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM */ @@ -286,6 +286,15 @@ }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_csi_mux_sel_pins_default>; + }; }; &main_pmx0 { @@ -352,6 +361,12 @@ >; }; + main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -574,7 +589,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pmic_irq_pins_default>; interrupt-parent = <&wkup_gpio0>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; ti,primary-pmic; @@ -651,7 +666,7 @@ reg = <0x4c>; system-power-controller; interrupt-parent = <&wkup_gpio0>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; gpio-controller; #gpio-cells = <2>; buck1234-supply = <&vsys_3v3>; @@ -858,14 +873,14 @@ reg = <0x70>; /* CSI0 I2C */ - i2c@0 { + cam0_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; /* CSI1 I2C */ - i2c@1 { + cam1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -1168,58 +1183,58 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/dts/src/arm64/ti/k3-j721e-som-p0.dtsi b/dts/src/arm64/ti/k3-j721e-som-p0.dtsi index a75611eec7..1fae6495db 100644 --- a/dts/src/arm64/ti/k3-j721e-som-p0.dtsi +++ b/dts/src/arm64/ti/k3-j721e-som-p0.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Product Link: https://www.ti.com/tool/J721EXSOMXEVM */ @@ -549,58 +549,58 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; diff --git a/dts/src/arm64/ti/k3-j721e-thermal.dtsi b/dts/src/arm64/ti/k3-j721e-thermal.dtsi index c252327900..927f7614ae 100644 --- a/dts/src/arm64/ti/k3-j721e-thermal.dtsi +++ b/dts/src/arm64/ti/k3-j721e-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/dts/src/arm64/ti/k3-j721e.dtsi b/dts/src/arm64/ti/k3-j721e.dtsi index a200810df5..5a72c518ce 100644 --- a/dts/src/arm64/ti/k3-j721e.dtsi +++ b/dts/src/arm64/ti/k3-j721e.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721E SoC Family * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/irq.h> diff --git a/dts/src/arm64/ti/k3-j721s2-common-proc-board.dts b/dts/src/arm64/ti/k3-j721s2-common-proc-board.dts index c6b85bbf9a..c5a0b7cbb1 100644 --- a/dts/src/arm64/ti/k3-j721s2-common-proc-board.dts +++ b/dts/src/arm64/ti/k3-j721s2-common-proc-board.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ * * Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM */ @@ -147,6 +147,13 @@ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -190,8 +197,6 @@ &wkup_pmx2 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; @@ -356,6 +361,24 @@ }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status = "okay"; diff --git a/dts/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso b/dts/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso index b78feea31b..1be28283c7 100644 --- a/dts/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso +++ b/dts/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board. * * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso b/dts/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso index 43568eb67d..5ff390915b 100644 --- a/dts/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso +++ b/dts/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso @@ -1,11 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /** * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the * J7 common processor board. * * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/dts/src/arm64/ti/k3-j721s2-main.dtsi b/dts/src/arm64/ti/k3-j721s2-main.dtsi index ea7f2b2ab1..b70c8615e3 100644 --- a/dts/src/arm64/ti/k3-j721s2-main.dtsi +++ b/dts/src/arm64/ti/k3-j721s2-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family Main Domain peripherals * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/phy/phy-cadence.h> @@ -45,7 +45,7 @@ ranges = <0x00 0x00 0x00104000 0x18000>; usb_serdes_mux: mux-controller@0 { - compatible = "mmio-mux"; + compatible = "reg-mux"; reg = <0x0 0x4>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ @@ -58,11 +58,11 @@ }; serdes_ln_ctrl: mux-controller@80 { - compatible = "mmio-mux"; + compatible = "reg-mux"; reg = <0x80 0x10>; #mux-control-cells = <1>; - mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ - <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */ }; ehrpwm_tbclk: clock-controller@140 { @@ -716,6 +716,14 @@ status = "disabled"; }; + vpu: video-codec@4210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4210000 0x00 0x10000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 179 2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, @@ -1122,7 +1130,6 @@ ti,sci-dev-id = <225>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { @@ -1233,6 +1240,128 @@ }; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x1000>; + clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x1000>; + clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5060000 { compatible = "ti,j721s2-wiz-10g"; #address-cells = <1>; diff --git a/dts/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi b/dts/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi index 80aa33c58a..eaf7f70944 100644 --- a/dts/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -663,7 +663,7 @@ compatible = "ti,j7200-vtm"; reg = <0x00 0x42040000 0x0 0x350>, <0x00 0x42050000 0x0 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; diff --git a/dts/src/arm64/ti/k3-j721s2-som-p0.dtsi b/dts/src/arm64/ti/k3-j721s2-som-p0.dtsi index da3237b23b..623c842152 100644 --- a/dts/src/arm64/ti/k3-j721s2-som-p0.dtsi +++ b/dts/src/arm64/ti/k3-j721s2-som-p0.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * SoM: https://www.ti.com/lit/zip/sprr439 * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -504,51 +504,51 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c71_0 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; &c71_1 { status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; diff --git a/dts/src/arm64/ti/k3-j721s2-thermal.dtsi b/dts/src/arm64/ti/k3-j721s2-thermal.dtsi index f7b1a15b8f..e3ef61c165 100644 --- a/dts/src/arm64/ti/k3-j721s2-thermal.dtsi +++ b/dts/src/arm64/ti/k3-j721s2-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/dts/src/arm64/ti/k3-j721s2.dtsi b/dts/src/arm64/ti/k3-j721s2.dtsi index 1f636acd4e..be4502fe1c 100644 --- a/dts/src/arm64/ti/k3-j721s2.dtsi +++ b/dts/src/arm64/ti/k3-j721s2.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J721S2 SoC Family * * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 * - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ * */ diff --git a/dts/src/arm64/ti/k3-j722s-evm.dts b/dts/src/arm64/ti/k3-j722s-evm.dts new file mode 100644 index 0000000000..cee3a8661d --- /dev/null +++ b/dts/src/arm64/ti/k3-j722s-evm.dts @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the J722S EVM + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr495 + */ + +/dts-v1/; + +#include <dt-bindings/net/ti-dp83867.h> +#include "k3-j722s.dtsi" + +/ { + compatible = "ti,j722s-evm", "ti,j722s"; + model = "Texas Instruments J722S EVM"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vsys_5v0: regulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-mmc1 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_sd_dv: regulator-TLV71033 { + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ + J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ + >; + bootph-all; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ + >; + bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ + J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ + J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ + J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ + J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ + J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ + >; + bootph-all; + }; + + mdio_pins_default: mdio-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ + J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ + J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ + J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ + J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ + J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ + J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */ + J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */ + J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */ + J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */ + J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */ + >; + bootph-all; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; +}; + +&cpsw3g { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&main_gpio1 { + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; + bootph-all; +}; + +&mcu_pmx0 { + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ + J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ + >; + bootph-all; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by Device Manager firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; + bootph-all; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + bootph-all; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + bootph-all; + + exp1: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL", + "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#", + "CSI_VIO_SEL", "USB2.0_MUX_SEL", + "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2", + "LMK1_OE1", "LMK1_OE0", + "LMK2_OE0", "LMK2_OE1", + "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN", + "USER_LED2", "MCAN0_STB", + "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", + "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", + "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x00 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; + +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; + status = "okay"; + bootph-all; +}; diff --git a/dts/src/arm64/ti/k3-j722s.dtsi b/dts/src/arm64/ti/k3-j722s.dtsi new file mode 100644 index 0000000000..c75744edb1 --- /dev/null +++ b/dts/src/arm64/ti/k3-j722s.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J722S SoC Family + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/ti,sci_pm_domain.h> + +#include "k3-am62p5.dtsi" + +/ { + model = "Texas Instruments K3 J722S SoC"; + compatible = "ti,j722s"; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ + <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ + <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */ + <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */ + <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */ + <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */ + <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + }; +}; + +/* Main domain overrides */ + +&inta_main_dmss { + ti,interrupt-ranges = <7 71 21>; +}; + +&oc_sram { + reg = <0x00 0x70000000 0x00 0x40000>; + ranges = <0x00 0x00 0x70000000 0x40000>; +}; diff --git a/dts/src/arm64/ti/k3-j784s4-evm.dts b/dts/src/arm64/ti/k3-j784s4-evm.dts index f34b92acc5..81fd7afac8 100644 --- a/dts/src/arm64/ti/k3-j784s4-evm.dts +++ b/dts/src/arm64/ti/k3-j784s4-evm.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ * * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 */ @@ -31,6 +31,7 @@ memory@80000000 { device_type = "memory"; + bootph-all; /* 32G RAM */ reg = <0x00 0x80000000 0x00 0x80000000>, <0x08 0x80000000 0x07 0x80000000>; @@ -296,6 +297,13 @@ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -335,8 +343,6 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; @@ -760,6 +766,24 @@ }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ diff --git a/dts/src/arm64/ti/k3-j784s4-main.dtsi b/dts/src/arm64/ti/k3-j784s4-main.dtsi index f2b720ed1e..b67c37460a 100644 --- a/dts/src/arm64/ti/k3-j784s4-main.dtsi +++ b/dts/src/arm64/ti/k3-j784s4-main.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J784S4 SoC Family Main Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/mux/mux.h> @@ -52,12 +52,12 @@ compatible = "reg-mux"; reg = <0x00004080 0x30>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ + <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ + <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ + <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ + <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>, <J784S4_SERDES0_LANE2_IP3_UNUSED>, @@ -662,6 +662,204 @@ status = "disabled"; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x00001000>; + clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x00001000>; + clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04520000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4980 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04524000 0x00 0x00001000>; + clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@45a0000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + vpu0: video-codec@4210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4210000 0x00 0x10000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 241 2>; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + }; + + vpu1: video-codec@4220000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4220000 0x00 0x10000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 242 2>; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, @@ -1224,7 +1422,6 @@ ti,sci-dev-id = <281>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { diff --git a/dts/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi b/dts/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi index 3902a921d7..77a8d99139 100644 --- a/dts/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/dts/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi @@ -1,8 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -628,7 +628,7 @@ compatible = "ti,j7200-vtm"; reg = <0x00 0x42040000 0x00 0x350>, <0x00 0x42050000 0x00 0x350>; - power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; diff --git a/dts/src/arm64/ti/k3-j784s4-thermal.dtsi b/dts/src/arm64/ti/k3-j784s4-thermal.dtsi index f7b1a15b8f..e3ef61c165 100644 --- a/dts/src/arm64/ti/k3-j784s4-thermal.dtsi +++ b/dts/src/arm64/ti/k3-j784s4-thermal.dtsi @@ -1,4 +1,7 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ #include <dt-bindings/thermal/thermal.h> diff --git a/dts/src/arm64/ti/k3-j784s4.dtsi b/dts/src/arm64/ti/k3-j784s4.dtsi index 4398c3a463..6e2e92ffe7 100644 --- a/dts/src/arm64/ti/k3-j784s4.dtsi +++ b/dts/src/arm64/ti/k3-j784s4.dtsi @@ -1,10 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only OR MIT /* * Device Tree Source for J784S4 SoC Family * * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ * */ @@ -235,6 +235,8 @@ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ + <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ + <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ diff --git a/dts/src/arm64/ti/k3-pinctrl.h b/dts/src/arm64/ti/k3-pinctrl.h index 2a4e0e084d..4cd2df467d 100644 --- a/dts/src/arm64/ti/k3-pinctrl.h +++ b/dts/src/arm64/ti/k3-pinctrl.h @@ -1,9 +1,9 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /* * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H @@ -59,6 +59,9 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J722S_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J722S_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) diff --git a/dts/src/arm64/ti/k3-serdes.h b/dts/src/arm64/ti/k3-serdes.h index 21b4886c47..a011ad893b 100644 --- a/dts/src/arm64/ti/k3-serdes.h +++ b/dts/src/arm64/ti/k3-serdes.h @@ -1,8 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /* * This header provides constants for SERDES MUX for TI SoCs * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef DTS_ARM64_TI_K3_SERDES_H diff --git a/dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi b/dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi index ccaca29200..dd4569e7bd 100644 --- a/dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi +++ b/dts/src/arm64/xilinx/zynqmp-clk-ccf.dtsi @@ -230,18 +230,30 @@ &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART0_REF>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART1_REF>; }; -&dwc3_0 { +&usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; -&dwc3_1 { +&dwc3_0 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; +}; + +&usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +}; + +&dwc3_1 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { diff --git a/dts/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso b/dts/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso index 92f4190d56..d7535a77b4 100644 --- a/dts/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/dts/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -139,7 +139,7 @@ bus-width = <4>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; @@ -166,9 +166,28 @@ }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -185,6 +204,7 @@ conf-tx { pins = "MIO36"; bias-disable; + output-enable; }; mux { @@ -207,7 +227,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = <SLEW_RATE_SLOW>; @@ -236,6 +256,7 @@ conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; + output-enable; low-power-disable; }; @@ -243,6 +264,7 @@ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; + output-enable; low-power-enable; }; @@ -251,6 +273,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; mux-mdio { @@ -281,6 +304,7 @@ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = <SLEW_RATE_SLOW>; }; @@ -319,6 +343,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/dts/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso b/dts/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso index f88b71f5b0..a7b8fffad4 100644 --- a/dts/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/dts/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -94,6 +94,7 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + assigned-clock-rates = <250000000>, <20000000>; }; &dwc3_0 { @@ -122,7 +123,7 @@ bus-width = <4>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; @@ -149,9 +150,28 @@ }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -168,6 +188,7 @@ conf-tx { pins = "MIO36"; bias-disable; + output-enable; }; mux { @@ -190,7 +211,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = <SLEW_RATE_SLOW>; @@ -219,6 +240,7 @@ conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; + output-enable; low-power-disable; }; @@ -226,6 +248,7 @@ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; + output-enable; low-power-enable; }; @@ -234,6 +257,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; mux-mdio { @@ -264,6 +288,7 @@ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = <SLEW_RATE_SLOW>; }; @@ -302,6 +327,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/dts/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts b/dts/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts index 73491626e0..6aff22d433 100644 --- a/dts/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/dts/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -148,7 +148,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; diff --git a/dts/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts b/dts/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts index f767708fb5..1850325e1d 100644 --- a/dts/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/dts/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -219,7 +219,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; diff --git a/dts/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts b/dts/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts index b1857e17ab..53aa3dca1d 100644 --- a/dts/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/dts/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -125,7 +125,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_74_grp", "gpio0_75_grp"; function = "gpio0"; @@ -152,7 +152,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_76_grp", "gpio0_77_grp"; function = "gpio0"; diff --git a/dts/src/arm64/xilinx/zynqmp-zcu100-revC.dts b/dts/src/arm64/xilinx/zynqmp-zcu100-revC.dts index 52f998c225..c5945067cd 100644 --- a/dts/src/arm64/xilinx/zynqmp-zcu100-revC.dts +++ b/dts/src/arm64/xilinx/zynqmp-zcu100-revC.dts @@ -275,7 +275,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; diff --git a/dts/src/arm64/xilinx/zynqmp-zcu102-revA.dts b/dts/src/arm64/xilinx/zynqmp-zcu102-revA.dts index 84952c14f0..ad8f23a0ec 100644 --- a/dts/src/arm64/xilinx/zynqmp-zcu102-revA.dts +++ b/dts/src/arm64/xilinx/zynqmp-zcu102-revA.dts @@ -603,7 +603,7 @@ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; @@ -689,7 +689,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -716,7 +716,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/dts/src/arm64/xilinx/zynqmp-zcu104-revA.dts b/dts/src/arm64/xilinx/zynqmp-zcu104-revA.dts index 5084ddcee0..b1eca1bb6a 100644 --- a/dts/src/arm64/xilinx/zynqmp-zcu104-revA.dts +++ b/dts/src/arm64/xilinx/zynqmp-zcu104-revA.dts @@ -272,7 +272,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/dts/src/arm64/xilinx/zynqmp-zcu104-revC.dts b/dts/src/arm64/xilinx/zynqmp-zcu104-revC.dts index b273bd1d92..ddc74d963a 100644 --- a/dts/src/arm64/xilinx/zynqmp-zcu104-revC.dts +++ b/dts/src/arm64/xilinx/zynqmp-zcu104-revC.dts @@ -284,7 +284,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/dts/src/arm64/xilinx/zynqmp-zcu106-revA.dts b/dts/src/arm64/xilinx/zynqmp-zcu106-revA.dts index 50c384aa25..7beedd730f 100644 --- a/dts/src/arm64/xilinx/zynqmp-zcu106-revA.dts +++ b/dts/src/arm64/xilinx/zynqmp-zcu106-revA.dts @@ -605,7 +605,7 @@ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; @@ -700,7 +700,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -727,7 +727,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/dts/src/arm64/xilinx/zynqmp-zcu111-revA.dts b/dts/src/arm64/xilinx/zynqmp-zcu111-revA.dts index 617cb0405a..b67ff7ecf3 100644 --- a/dts/src/arm64/xilinx/zynqmp-zcu111-revA.dts +++ b/dts/src/arm64/xilinx/zynqmp-zcu111-revA.dts @@ -589,7 +589,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -616,7 +616,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/dts/src/arm64/xilinx/zynqmp-zcu1275-revA.dts b/dts/src/arm64/xilinx/zynqmp-zcu1275-revA.dts index c406017b03..a38c2baeba 100644 --- a/dts/src/arm64/xilinx/zynqmp-zcu1275-revA.dts +++ b/dts/src/arm64/xilinx/zynqmp-zcu1275-revA.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * dts file for Xilinx ZynqMP ZC1275 + * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017 - 2021, Xilinx, Inc. * diff --git a/dts/src/arm64/xilinx/zynqmp.dtsi b/dts/src/arm64/xilinx/zynqmp.dtsi index eaba466804..25d20d8032 100644 --- a/dts/src/arm64/xilinx/zynqmp.dtsi +++ b/dts/src/arm64/xilinx/zynqmp.dtsi @@ -24,6 +24,13 @@ #address-cells = <2>; #size-cells = <2>; + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x20000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -180,13 +187,18 @@ }; firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; method = "smc"; bootph-all; - zynqmp_power: zynqmp-power { + zynqmp_power: power-management { bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; @@ -281,6 +293,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; @@ -293,6 +306,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; @@ -326,7 +340,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e8>; + /* iommus = <&smmu 0x14e8>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -339,7 +353,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e9>; + /* iommus = <&smmu 0x14e9>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -352,7 +366,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ea>; + /* iommus = <&smmu 0x14ea>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -365,7 +379,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14eb>; + /* iommus = <&smmu 0x14eb>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -378,7 +392,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ec>; + /* iommus = <&smmu 0x14ec>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -391,7 +405,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ed>; + /* iommus = <&smmu 0x14ed>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -404,7 +418,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ee>; + /* iommus = <&smmu 0x14ee>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -417,7 +431,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ef>; + /* iommus = <&smmu 0x14ef>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -462,7 +476,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x868>; + /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -475,7 +489,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x869>; + /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -488,7 +502,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86a>; + /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -501,7 +515,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86b>; + /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -514,7 +528,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86c>; + /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -527,7 +541,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86d>; + /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -540,7 +554,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86e>; + /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -553,7 +567,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86f>; + /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -573,7 +587,7 @@ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x872>; + /* iommus = <&smmu 0x872>; */ power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -585,7 +599,7 @@ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x874>; + /* iommus = <&smmu 0x874>; */ power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; @@ -599,7 +613,7 @@ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x875>; + /* iommus = <&smmu 0x875>; */ power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; @@ -613,7 +627,7 @@ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x876>; + /* iommus = <&smmu 0x876>; */ power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; @@ -627,7 +641,7 @@ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x877>; + /* iommus = <&smmu 0x877>; */ power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; @@ -689,7 +703,7 @@ msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ @@ -699,7 +713,7 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - iommus = <&smmu 0x4d0>; + /* iommus = <&smmu 0x4d0>; */ power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; @@ -720,7 +734,7 @@ <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x873>; + /* iommus = <&smmu 0x873>; */ power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -752,8 +766,7 @@ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, - <&smmu 0x4c2>, <&smmu 0x4c3>; + /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ }; sdhci0: mmc@ff160000 { @@ -764,7 +777,7 @@ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x870>; + /* iommus = <&smmu 0x870>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; @@ -779,7 +792,7 @@ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x871>; + /* iommus = <&smmu 0x871>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; @@ -912,6 +925,7 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, @@ -922,14 +936,15 @@ dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "bus_early", "ref"; - iommus = <&smmu 0x860>; + clock-names = "ref"; + /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations; /* dma-coherent; */ @@ -942,6 +957,7 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, @@ -951,14 +967,15 @@ dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "bus_early", "ref"; - iommus = <&smmu 0x861>; + clock-names = "ref"; + /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations; /* dma-coherent; */ @@ -1018,6 +1035,7 @@ interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; + /* iommus = <&smmu 0xce4>; */ #dma-cells = <1>; }; @@ -1032,6 +1050,7 @@ reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; + /* iommus = <&smmu 0xce3>; */ clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; diff --git a/dts/src/loongarch/loongson-2k1000.dtsi b/dts/src/loongarch/loongson-2k1000.dtsi index 49a70f8c3c..b6aeb1f70e 100644 --- a/dts/src/loongarch/loongson-2k1000.dtsi +++ b/dts/src/loongarch/loongson-2k1000.dtsi @@ -100,6 +100,13 @@ #size-cells = <2>; dma-coherent; + isa@18000000 { + compatible = "isa"; + #size-cells = <1>; + #address-cells = <2>; + ranges = <1 0x0 0x0 0x18000000 0x4000>; + }; + liointc0: interrupt-controller@1fe01400 { compatible = "loongson,liointc-2.0"; reg = <0x0 0x1fe01400 0x0 0x40>, diff --git a/dts/src/loongarch/loongson-2k2000-ref.dts b/dts/src/loongarch/loongson-2k2000-ref.dts index dca91caf89..74b99bd234 100644 --- a/dts/src/loongarch/loongson-2k2000-ref.dts +++ b/dts/src/loongarch/loongson-2k2000-ref.dts @@ -61,12 +61,45 @@ &gmac0 { status = "okay"; + + phy-mode = "gmii"; + phy-handle = <&phy0>; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <2>; + }; + }; }; &gmac1 { status = "okay"; + + phy-mode = "gmii"; + phy-handle = <&phy1>; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + reg = <2>; + }; + }; }; &gmac2 { status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <&phy2>; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy2: ethernet-phy@2 { + reg = <0>; + }; + }; }; diff --git a/dts/src/loongarch/loongson-2k2000.dtsi b/dts/src/loongarch/loongson-2k2000.dtsi index a231949b5f..9eab2d02cb 100644 --- a/dts/src/loongarch/loongson-2k2000.dtsi +++ b/dts/src/loongarch/loongson-2k2000.dtsi @@ -51,6 +51,13 @@ #address-cells = <2>; #size-cells = <2>; + isa@18400000 { + compatible = "isa"; + #size-cells = <1>; + #address-cells = <2>; + ranges = <1 0x0 0x0 0x18400000 0x4000>; + }; + pmc: power-management@100d0000 { compatible = "loongson,ls2k2000-pmc", "loongson,ls2k0500-pmc", "syscon"; reg = <0x0 0x100d0000 0x0 0x58>; @@ -109,6 +116,8 @@ msi: msi-controller@1fe01140 { compatible = "loongson,pch-msi-1.0"; reg = <0x0 0x1fe01140 0x0 0x8>; + interrupt-controller; + #interrupt-cells = <1>; msi-controller; loongson,msi-base-vec = <64>; loongson,msi-num-vecs = <192>; @@ -140,27 +149,34 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + msi-parent = <&msi>; bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00008000 0x0 0x18400000 0x0 0x00008000>, + ranges = <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>, <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; gmac0: ethernet@3,0 { reg = <0x1800 0x0 0x0 0x0 0x0>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, + <13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&pic>; status = "disabled"; }; gmac1: ethernet@3,1 { reg = <0x1900 0x0 0x0 0x0 0x0>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&pic>; status = "disabled"; }; gmac2: ethernet@3,2 { reg = <0x1a00 0x0 0x0 0x0 0x0>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; interrupt-parent = <&pic>; status = "disabled"; }; diff --git a/dts/src/mips/mobileye/eyeq5-epm5.dts b/dts/src/mips/mobileye/eyeq5-epm5.dts new file mode 100644 index 0000000000..6898b2d826 --- /dev/null +++ b/dts/src/mips/mobileye/eyeq5-epm5.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/dts-v1/; + +#include "eyeq5.dtsi" + +/ { + compatible = "mobileye,eyeq5-epm5", "mobileye,eyeq5"; + model = "Mobile EyeQ5 MP5 Evaluation board"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x02000000>, + <0x8 0x02000000 0x0 0x7E000000>; + }; +}; diff --git a/dts/src/mips/mobileye/eyeq5-fixed-clocks.dtsi b/dts/src/mips/mobileye/eyeq5-fixed-clocks.dtsi new file mode 100644 index 0000000000..78f5533a95 --- /dev/null +++ b/dts/src/mips/mobileye/eyeq5-fixed-clocks.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/ { + /* Fixed clock */ + pll_cpu: pll-cpu { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1500000000>; + }; + + pll_vdi: pll-vdi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1280000000>; + }; + + pll_per: pll-per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + pll_ddr0: pll-ddr0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + + pll_ddr1: pll-ddr1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + +/* PLL_CPU derivatives */ + occ_cpu: occ-cpu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ + compatible = "fixed-factor-clock"; + clocks = <&occ_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cpc_clk: cpc-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core0_clk: core0-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core1_clk: core1-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core2_clk: core2-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core3_clk: core3-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cm_clk: cm-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + mem_clk: mem-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_isram: occ-isram { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + isram_clk: isram-clk { /* gate ClkRstGen_isram */ + compatible = "fixed-factor-clock"; + clocks = <&occ_isram>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_dbu: occ-dbu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + }; + si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ + compatible = "fixed-factor-clock"; + clocks = <&occ_dbu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; +/* PLL_VDI derivatives */ + occ_vdi: occ-vdi { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ + compatible = "fixed-factor-clock"; + clocks = <&occ_vdi>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_can_ser: occ-can-ser { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ + compatible = "fixed-factor-clock"; + clocks = <&occ_can_ser>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_ser_clk: i2c-ser-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + }; +/* PLL_PER derivatives */ + occ_periph: occ-periph { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + periph_clk: periph-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + can_clk: can-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + spi_clk: spi-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_clk: i2c-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "i2c_clk"; + }; + timer_clk: timer-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "timer_clk"; + }; + gpio_clk: gpio-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "gpio_clk"; + }; + emmc_sys_clk: emmc-sys-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + clock-output-names = "emmc_sys_clk"; + }; + ccf_ctrl_clk: ccf-ctrl-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "ccf_ctrl_clk"; + }; + occ_mjpeg_core: occ-mjpeg-core { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "occ_mjpeg_core"; + }; + hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "hsm_clk"; + }; + mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "mjpeg_core_clk"; + }; + fcmu_a_clk: fcmu-a-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + clock-output-names = "fcmu_a_clk"; + }; + occ_pci_sys: occ-pci-sys { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "occ_pci_sys"; + }; + pclk: pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; /* 250MHz */ + }; + tsu_clk: tsu-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125MHz */ + }; +}; diff --git a/dts/src/mips/mobileye/eyeq5.dtsi b/dts/src/mips/mobileye/eyeq5.dtsi new file mode 100644 index 0000000000..6cc5980e2f --- /dev/null +++ b/dts/src/mips/mobileye/eyeq5.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* +* Copyright 2023 Mobileye Vision Technologies Ltd. +*/ + +#include <dt-bindings/interrupt-controller/mips-gic.h> + +#include "eyeq5-fixed-clocks.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "img,i6500"; + reg = <0>; + clocks = <&core0_clk>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* These reserved memory regions are also defined in bootmanager + * for configuring inbound translation for BARS, don't change + * these without syncing with bootmanager + */ + shmem0_reserved: shmem@804000000 { + reg = <0x8 0x04000000 0x0 0x1000000>; + }; + shmem1_reserved: shmem@805000000 { + reg = <0x8 0x05000000 0x0 0x1000000>; + }; + pci0_msi_reserved: pci0-msi@806000000 { + reg = <0x8 0x06000000 0x0 0x100000>; + }; + pci1_msi_reserved: pci1-msi@806100000 { + reg = <0x8 0x06100000 0x0 0x100000>; + }; + + mini_coredump0_reserved: mini-coredump0@806200000 { + reg = <0x8 0x06200000 0x0 0x100000>; + }; + mhm_reserved_0: the-mhm-reserved-0@0 { + reg = <0x8 0x00000000 0x0 0x0000800>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "simple-bus"; + + uart0: serial@800000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x800000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@900000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x900000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart2: serial@a00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xa00000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + gic: interrupt-controller@140000 { + compatible = "mti,gic"; + reg = <0x0 0x140000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; + clocks = <&core0_clk>; + }; + }; + }; +}; diff --git a/dts/src/mips/ralink/mt7621.dtsi b/dts/src/mips/ralink/mt7621.dtsi index 35a10258f2..6e95e6f19a 100644 --- a/dts/src/mips/ralink/mt7621.dtsi +++ b/dts/src/mips/ralink/mt7621.dtsi @@ -115,14 +115,58 @@ compatible = "ns16550a"; reg = <0xc00 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&sysc MT7621_CLK_UART1>; interrupt-parent = <&gic>; interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; + no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + }; + + serial1: serial@d00 { + compatible = "ns16550a"; + reg = <0xd00 0x100>; + + reg-io-width = <4>; reg-shift = <2>; + + clocks = <&sysc MT7621_CLK_UART2>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>; + + no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "disabled"; + }; + + serial2: serial@e00 { + compatible = "ns16550a"; + reg = <0xe00 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + + clocks = <&sysc MT7621_CLK_UART3>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>; + no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + status = "disabled"; }; spi0: spi@b00 { @@ -263,6 +307,9 @@ 0x1e1d0700 0x0100>; reg-names = "mac", "ippc"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysc MT7621_CLK_XTAL>; clock-names = "sys_ck"; diff --git a/dts/src/powerpc/akebono.dts b/dts/src/powerpc/akebono.dts index df18f8dc46..343326c303 100644 --- a/dts/src/powerpc/akebono.dts +++ b/dts/src/powerpc/akebono.dts @@ -126,7 +126,7 @@ interrupts = <93 2>; }; - EHCI0: ehci@30010000000 { + EHCI0: usb@30010000000 { compatible = "ibm,476gtr-ehci", "generic-ehci"; reg = <0x300 0x10000000 0x0 0x10000>; interrupt-parent = <&MPIC>; @@ -140,14 +140,14 @@ interrupt-parent = <&MPIC>; }; - OHCI0: ohci@30010010000 { + OHCI0: usb@30010010000 { compatible = "ibm,476gtr-ohci", "generic-ohci"; reg = <0x300 0x10010000 0x0 0x10000>; interrupt-parent = <&MPIC>; interrupts = <89 1>; }; - OHCI1: ohci@30010020000 { + OHCI1: usb@30010020000 { compatible = "ibm,476gtr-ohci", "generic-ohci"; reg = <0x300 0x10020000 0x0 0x10000>; interrupt-parent = <&MPIC>; diff --git a/dts/src/riscv/microchip/mpfs.dtsi b/dts/src/riscv/microchip/mpfs.dtsi index 59fd2d4ea5..9883ca3554 100644 --- a/dts/src/riscv/microchip/mpfs.dtsi +++ b/dts/src/riscv/microchip/mpfs.dtsi @@ -243,7 +243,7 @@ }; pdma: dma-controller@3000000 { - compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; + compatible = "microchip,mpfs-pdma", "sifive,pdma0"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; interrupts = <5 6>, <7 8>, <9 10>, <11 12>; @@ -422,7 +422,7 @@ can0: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010c000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN0>; + clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <56>; status = "disabled"; @@ -431,7 +431,7 @@ can1: can@2010d000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010d000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN1>; + clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <57>; status = "disabled"; diff --git a/dts/src/riscv/renesas/r9a07g043f.dtsi b/dts/src/riscv/renesas/r9a07g043f.dtsi index a92cfcfc02..f35324b917 100644 --- a/dts/src/riscv/renesas/r9a07g043f.dtsi +++ b/dts/src/riscv/renesas/r9a07g043f.dtsi @@ -27,7 +27,7 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xandespmu"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>; @@ -39,13 +39,17 @@ cpu0_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; }; }; +&pinctrl { + gpio-ranges = <&pinctrl 0 0 232>; +}; + &soc { dma-noncoherent; interrupt-parent = <&plic>; diff --git a/dts/src/riscv/sophgo/sg2042.dtsi b/dts/src/riscv/sophgo/sg2042.dtsi index ead1cc35d8..81fda312f9 100644 --- a/dts/src/riscv/sophgo/sg2042.dtsi +++ b/dts/src/riscv/sophgo/sg2042.dtsi @@ -6,6 +6,8 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/reset/sophgo,sg2042-reset.h> + #include "sg2042-cpus.dtsi" / { @@ -327,6 +329,12 @@ riscv,ndev = <224>; }; + rstgen: reset-controller@7030013000 { + compatible = "sophgo,sg2042-reset"; + reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; + #reset-cells = <1>; + }; + uart0: serial@7040000000 { compatible = "snps,dw-apb-uart"; reg = <0x00000070 0x40000000 0x00000000 0x00001000>; @@ -335,6 +343,7 @@ clock-frequency = <500000000>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rstgen RST_UART0>; status = "disabled"; }; }; diff --git a/dts/src/riscv/starfive/jh7100-beaglev-starlight.dts b/dts/src/riscv/starfive/jh7100-beaglev-starlight.dts index 7cda3a8902..168f5d9895 100644 --- a/dts/src/riscv/starfive/jh7100-beaglev-starlight.dts +++ b/dts/src/riscv/starfive/jh7100-beaglev-starlight.dts @@ -11,3 +11,14 @@ model = "BeagleV Starlight Beta"; compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100"; }; + +&gmac { + phy-handle = <&phy>; +}; + +&mdio { + phy: ethernet-phy@7 { + reg = <7>; + reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/dts/src/riscv/starfive/jh7100-common.dtsi b/dts/src/riscv/starfive/jh7100-common.dtsi index 42fb61c360..ae1a6aeb0a 100644 --- a/dts/src/riscv/starfive/jh7100-common.dtsi +++ b/dts/src/riscv/starfive/jh7100-common.dtsi @@ -72,7 +72,91 @@ }; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + &gpio { + gmac_pins: gmac-0 { + gtxclk-pins { + pins = <PAD_FUNC_SHARE(115)>; + bias-pull-up; + drive-strength = <35>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + miitxclk-pins { + pins = <PAD_FUNC_SHARE(116)>; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + tx-pins { + pins = <PAD_FUNC_SHARE(117)>, + <PAD_FUNC_SHARE(119)>, + <PAD_FUNC_SHARE(120)>, + <PAD_FUNC_SHARE(121)>, + <PAD_FUNC_SHARE(122)>, + <PAD_FUNC_SHARE(123)>, + <PAD_FUNC_SHARE(124)>, + <PAD_FUNC_SHARE(125)>, + <PAD_FUNC_SHARE(126)>; + bias-pull-up; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + rxclk-pins { + pins = <PAD_FUNC_SHARE(127)>; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <6>; + }; + rxer-pins { + pins = <PAD_FUNC_SHARE(129)>; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + rx-pins { + pins = <PAD_FUNC_SHARE(128)>, + <PAD_FUNC_SHARE(130)>, + <PAD_FUNC_SHARE(131)>, + <PAD_FUNC_SHARE(132)>, + <PAD_FUNC_SHARE(133)>, + <PAD_FUNC_SHARE(134)>, + <PAD_FUNC_SHARE(135)>, + <PAD_FUNC_SHARE(136)>, + <PAD_FUNC_SHARE(137)>, + <PAD_FUNC_SHARE(138)>, + <PAD_FUNC_SHARE(139)>, + <PAD_FUNC_SHARE(140)>, + <PAD_FUNC_SHARE(141)>; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + i2c0_pins: i2c0-0 { i2c-pins { pinmux = <GPIOMUX(62, GPO_LOW, @@ -115,6 +199,24 @@ }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = <GPIOMUX(7, + GPO_PWM_PAD_OUT_BIT0, + GPO_PWM_PAD_OE_N_BIT0, + GPI_NONE)>, + <GPIOMUX(5, + GPO_PWM_PAD_OUT_BIT1, + GPO_PWM_PAD_OE_N_BIT1, + GPI_NONE)>; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + sdio0_pins: sdio0-0 { clk-pins { pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT, @@ -257,6 +359,12 @@ clock-frequency = <27000000>; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &sdio0 { broken-cd; bus-width = <4>; diff --git a/dts/src/riscv/starfive/jh7100-starfive-visionfive-v1.dts b/dts/src/riscv/starfive/jh7100-starfive-visionfive-v1.dts index e82af72f1a..692c696e1a 100644 --- a/dts/src/riscv/starfive/jh7100-starfive-visionfive-v1.dts +++ b/dts/src/riscv/starfive/jh7100-starfive-visionfive-v1.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "jh7100-common.dtsi" -#include <dt-bindings/gpio/gpio.h> / { model = "StarFive VisionFive V1"; @@ -18,3 +17,24 @@ priority = <224>; }; }; + +&gmac { + phy-handle = <&phy>; +}; + +/* + * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires + * manual adjustment of the RX internal delay to work properly. The default + * RX delay provided by the driver (1.95ns) is too high, but applying a 50% + * reduction seems to mitigate the issue. + * + * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC, + * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one + * responsible for the misbehaviour, not the GMAC. + */ +&mdio { + phy: ethernet-phy@0 { + reg = <0>; + rx-internal-delay-ps = <900>; + }; +}; diff --git a/dts/src/riscv/starfive/jh7100.dtsi b/dts/src/riscv/starfive/jh7100.dtsi index 8bcf36d07f..9a2e9583af 100644 --- a/dts/src/riscv/starfive/jh7100.dtsi +++ b/dts/src/riscv/starfive/jh7100.dtsi @@ -116,6 +116,7 @@ osc_sys: osc-sys { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "osc_sys"; /* This value must be overridden by the board */ clock-frequency = <0>; }; @@ -123,6 +124,7 @@ osc_aud: osc-aud { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "osc_aud"; /* This value must be overridden by the board */ clock-frequency = <0>; }; @@ -130,6 +132,7 @@ gmac_rmii_ref: gmac-rmii-ref { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "gmac_rmii_ref"; /* Should be overridden by the board when needed */ clock-frequency = <0>; }; @@ -137,6 +140,7 @@ gmac_gr_mii_rxclk: gmac-gr-mii-rxclk { compatible = "fixed-clock"; #clock-cells = <0>; + clock-output-names = "gmac_gr_mii_rxclk"; /* Should be overridden by the board when needed */ clock-frequency = <0>; }; @@ -204,6 +208,37 @@ status = "disabled"; }; + gmac: ethernet@10020000 { + compatible = "starfive,jh7100-dwmac", "snps,dwmac"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, + <&clkgen JH7100_CLK_GMAC_AHB>, + <&clkgen JH7100_CLK_GMAC_PTP_REF>, + <&clkgen JH7100_CLK_GMAC_TX_INV>, + <&clkgen JH7100_CLK_GMAC_GTX>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; + resets = <&rstgen JH7100_RSTN_GMAC_AHB>; + reset-names = "ahb"; + interrupts = <6>, <7>; + interrupt-names = "macirq", "eth_wake_irq"; + max-frame-size = <9000>; + snps,multicast-filter-bins = <32>; + snps,perfect-filter-entries = <128>; + starfive,syscon = <&sysmain 0x70 0>; + rx-fifo-depth = <32768>; + tx-fifo-depth = <16384>; + snps,axi-config = <&stmmac_axi_setup>; + snps,fixed-burst; + snps,force_thresh_dma_mode; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <16>; + snps,rd_osr_lmt = <16>; + snps,blen = <256 128 64 32 0 0 0>; + }; + }; + clkgen: clock-controller@11800000 { compatible = "starfive,jh7100-clkgen"; reg = <0x0 0x11800000 0x0 0x10000>; @@ -218,6 +253,11 @@ #reset-cells = <1>; }; + sysmain: syscon@11850000 { + compatible = "starfive,jh7100-sysmain", "syscon"; + reg = <0x0 0x11850000 0x0 0x10000>; + }; + i2c0: i2c@118b0000 { compatible = "snps,designware-i2c"; reg = <0x0 0x118b0000 0x0 0x10000>; @@ -320,6 +360,15 @@ <&rstgen JH7100_RSTN_WDT>; }; + pwm: pwm@12490000 { + compatible = "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg = <0x0 0x12490000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_PWM_APB>; + resets = <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@124a0000 { compatible = "starfive,jh7100-temp"; reg = <0x0 0x124a0000 0x0 0x10000>; diff --git a/dts/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi b/dts/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi index b89e9791ef..45b58b6f3d 100644 --- a/dts/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/dts/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi @@ -125,6 +125,55 @@ clock-frequency = <49152000>; }; +&camss { + assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, + <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>; + assigned-clock-rates = <49500000>, <198000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + camss_from_csi2rx: endpoint { + remote-endpoint = <&csi2rx_to_camss>; + }; + }; + }; +}; + +&csi2rx { + assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>; + assigned-clock-rates = <297000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + /* remote MIPI sensor endpoint */ + }; + + port@1 { + reg = <1>; + + csi2rx_to_camss: endpoint { + remote-endpoint = <&camss_from_csi2rx>; + }; + }; + }; +}; + &gmac0 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; @@ -323,6 +372,12 @@ }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; @@ -513,6 +568,22 @@ }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0, + GPOEN_SYS_PWM0_CHANNEL0, + GPI_NONE)>, + <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1, + GPOEN_SYS_PWM0_CHANNEL1, + GPI_NONE)>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + spi0_pins: spi0-0 { mosi-pins { pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD, diff --git a/dts/src/riscv/starfive/jh7110.dtsi b/dts/src/riscv/starfive/jh7110.dtsi index 74ed3b9264..4a5708f7fc 100644 --- a/dts/src/riscv/starfive/jh7110.dtsi +++ b/dts/src/riscv/starfive/jh7110.dtsi @@ -829,6 +829,15 @@ status = "disabled"; }; + pwm: pwm@120d0000 { + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg = <0x0 0x120d0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; + resets = <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@120e0000 { compatible = "starfive,jh7110-temp"; reg = <0x0 0x120e0000 0x0 0x10000>; @@ -1104,6 +1113,32 @@ #power-domain-cells = <1>; }; + csi2rx: csi@19800000 { + compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x19800000 0x0 0x10000>; + clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>, + <&ispcrg JH7110_ISPCLK_VIN_APB>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + resets = <&ispcrg JH7110_ISPRST_VIN_SYS>, + <&ispcrg JH7110_ISPRST_VIN_APB>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>; + reset-names = "sys", "reg_bank", + "pixel_if0", "pixel_if1", + "pixel_if2", "pixel_if3"; + phys = <&csi_phy>; + phy-names = "dphy"; + status = "disabled"; + }; + ispcrg: clock-controller@19810000 { compatible = "starfive,jh7110-ispcrg"; reg = <0x0 0x19810000 0x0 0x10000>; @@ -1121,6 +1156,47 @@ power-domains = <&pwrc JH7110_PD_ISP>; }; + csi_phy: phy@19820000 { + compatible = "starfive,jh7110-dphy-rx"; + reg = <0x0 0x19820000 0x0 0x10000>; + clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>; + clock-names = "cfg", "ref", "tx"; + resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>, + <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>; + power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>; + #phy-cells = <0>; + }; + + camss: isp@19840000 { + compatible = "starfive,jh7110-camss"; + reg = <0x0 0x19840000 0x0 0x10000>, + <0x0 0x19870000 0x0 0x30000>; + reg-names = "syscon", "isp"; + clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, + <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>, + <&ispcrg JH7110_ISPCLK_DVP_INV>, + <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>, + <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>, + <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>; + clock-names = "apb_func", "wrapper_clk_c", "dvp_inv", + "axiwr", "mipi_rx0_pxl", "ispcore_2x", + "isp_axi"; + resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>, + <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>, + <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>, + <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>, + <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>; + reset-names = "wrapper_p", "wrapper_c", "axird", + "axiwr", "isp_top_n", "isp_top_axi"; + power-domains = <&pwrc JH7110_PD_ISP>; + interrupts = <92>, <87>, <90>, <88>; + status = "disabled"; + }; + voutcrg: clock-controller@295c0000 { compatible = "starfive,jh7110-voutcrg"; reg = <0x0 0x295c0000 0x0 0x10000>; |