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-rw-r--r--dts/Bindings/arm/amlogic.txt10
-rw-r--r--dts/Bindings/arm/apm/scu.txt17
-rw-r--r--dts/Bindings/arm/arm,scpi.txt188
-rw-r--r--dts/Bindings/arm/bcm/brcm,brcmstb.txt162
-rw-r--r--dts/Bindings/arm/bcm/brcm,nsp.txt34
-rw-r--r--dts/Bindings/arm/coherency-fabric.txt5
-rw-r--r--dts/Bindings/arm/cpus.txt2
-rw-r--r--dts/Bindings/arm/fsl.txt16
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.txt21
-rw-r--r--dts/Bindings/arm/keystone/keystone.txt20
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,imgsys.txt22
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mmsys.txt22
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,vdecsys.txt22
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,vencltsys.txt22
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,vencsys.txt22
-rw-r--r--dts/Bindings/arm/mvebu-cpu-config.txt20
-rw-r--r--dts/Bindings/arm/pmu.txt3
-rw-r--r--dts/Bindings/arm/psci.txt6
-rw-r--r--dts/Bindings/arm/rockchip.txt11
-rw-r--r--dts/Bindings/arm/samsung-boards.txt27
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.txt69
-rw-r--r--dts/Bindings/arm/shmobile.txt10
-rw-r--r--dts/Bindings/arm/sunxi.txt1
-rw-r--r--dts/Bindings/arm/tegra/nvidia,nvec.txt (renamed from dts/Bindings/nvec/nvidia,nvec.txt)0
-rw-r--r--dts/Bindings/arm/twd.txt5
-rw-r--r--dts/Bindings/arm/uniphier/cache-uniphier.txt60
-rw-r--r--dts/Bindings/ata/ahci-fsl-qoriq.txt21
-rw-r--r--dts/Bindings/ata/ahci-platform.txt2
-rw-r--r--dts/Bindings/board/fsl-board.txt (renamed from dts/Bindings/powerpc/fsl/board.txt)14
-rw-r--r--dts/Bindings/bus/sunxi-rsb.txt47
-rw-r--r--dts/Bindings/chosen.txt8
-rw-r--r--dts/Bindings/clock/at91-clock.txt35
-rw-r--r--dts/Bindings/clock/brcm,bcm2835-cprman.txt45
-rw-r--r--dts/Bindings/clock/brcm,iproc-clocks.txt78
-rw-r--r--dts/Bindings/clock/qcom,gcc.txt4
-rw-r--r--dts/Bindings/clock/qcom,mmcc.txt4
-rw-r--r--dts/Bindings/clock/qoriq-clock.txt61
-rw-r--r--dts/Bindings/clock/renesas,cpg-div6-clocks.txt2
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.txt69
-rw-r--r--dts/Bindings/clock/silabs,si514.txt24
-rw-r--r--dts/Bindings/clock/st/st,clkgen-pll.txt1
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt4
-rw-r--r--dts/Bindings/display/arm,pl11x.txt (renamed from dts/Bindings/video/arm,pl11x.txt)0
-rw-r--r--dts/Bindings/display/armada/marvell,dove-lcd.txt (renamed from dts/Bindings/drm/armada/marvell,dove-lcd.txt)0
-rw-r--r--dts/Bindings/display/atmel,lcdc.txt (renamed from dts/Bindings/video/atmel,lcdc.txt)0
-rw-r--r--dts/Bindings/display/atmel/hlcdc-dc.txt (renamed from dts/Bindings/drm/atmel/hlcdc-dc.txt)0
-rw-r--r--dts/Bindings/display/brcm,bcm-vc4.txt65
-rw-r--r--dts/Bindings/display/bridge/adi,adv7123.txt (renamed from dts/Bindings/video/adi,adv7123.txt)0
-rw-r--r--dts/Bindings/display/bridge/adi,adv7511.txt (renamed from dts/Bindings/video/adi,adv7511.txt)0
-rw-r--r--dts/Bindings/display/bridge/dw_hdmi.txt (renamed from dts/Bindings/drm/bridge/dw_hdmi.txt)4
-rw-r--r--dts/Bindings/display/bridge/ps8622.txt (renamed from dts/Bindings/video/bridge/ps8622.txt)0
-rw-r--r--dts/Bindings/display/bridge/ptn3460.txt (renamed from dts/Bindings/video/bridge/ptn3460.txt)0
-rw-r--r--dts/Bindings/display/bridge/tda998x.txt (renamed from dts/Bindings/drm/i2c/tda998x.txt)0
-rw-r--r--dts/Bindings/display/bridge/thine,thc63lvdm83d.txt (renamed from dts/Bindings/video/thine,thc63lvdm83d)0
-rw-r--r--dts/Bindings/display/cirrus,clps711x-fb.txt (renamed from dts/Bindings/video/cirrus,clps711x-fb.txt)2
-rw-r--r--dts/Bindings/display/connector/analog-tv-connector.txt (renamed from dts/Bindings/video/analog-tv-connector.txt)0
-rw-r--r--dts/Bindings/display/connector/dvi-connector.txt (renamed from dts/Bindings/video/dvi-connector.txt)0
-rw-r--r--dts/Bindings/display/connector/hdmi-connector.txt (renamed from dts/Bindings/video/hdmi-connector.txt)0
-rw-r--r--dts/Bindings/display/connector/vga-connector.txt (renamed from dts/Bindings/video/vga-connector.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos-mic.txt (renamed from dts/Bindings/video/exynos-mic.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos5433-decon.txt (renamed from dts/Bindings/video/exynos5433-decon.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos7-decon.txt (renamed from dts/Bindings/video/exynos7-decon.txt)2
-rw-r--r--dts/Bindings/display/exynos/exynos_dp.txt (renamed from dts/Bindings/video/exynos_dp.txt)2
-rw-r--r--dts/Bindings/display/exynos/exynos_dsim.txt (renamed from dts/Bindings/video/exynos_dsim.txt)2
-rw-r--r--dts/Bindings/display/exynos/exynos_hdmi.txt (renamed from dts/Bindings/video/exynos_hdmi.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos_hdmiddc.txt (renamed from dts/Bindings/video/exynos_hdmiddc.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos_hdmiphy.txt (renamed from dts/Bindings/video/exynos_hdmiphy.txt)0
-rw-r--r--dts/Bindings/display/exynos/exynos_mixer.txt (renamed from dts/Bindings/video/exynos_mixer.txt)0
-rw-r--r--dts/Bindings/display/exynos/samsung-fimd.txt (renamed from dts/Bindings/video/samsung-fimd.txt)2
-rw-r--r--dts/Bindings/display/fsl,dcu.txt (renamed from dts/Bindings/video/fsl,dcu.txt)0
-rw-r--r--dts/Bindings/display/imx/fsl,imx-fb.txt (renamed from dts/Bindings/video/fsl,imx-fb.txt)2
-rw-r--r--dts/Bindings/display/imx/fsl-imx-drm.txt (renamed from dts/Bindings/drm/imx/fsl-imx-drm.txt)0
-rw-r--r--dts/Bindings/display/imx/hdmi.txt (renamed from dts/Bindings/drm/imx/hdmi.txt)0
-rw-r--r--dts/Bindings/display/imx/ldb.txt (renamed from dts/Bindings/drm/imx/ldb.txt)2
-rw-r--r--dts/Bindings/display/marvell,pxa2xx-lcdc.txt34
-rw-r--r--dts/Bindings/display/mipi-dsi-bus.txt (renamed from dts/Bindings/mipi/dsi/mipi-dsi-bus.txt)0
-rw-r--r--dts/Bindings/display/msm/dsi.txt (renamed from dts/Bindings/drm/msm/dsi.txt)2
-rw-r--r--dts/Bindings/display/msm/edp.txt (renamed from dts/Bindings/drm/msm/edp.txt)0
-rw-r--r--dts/Bindings/display/msm/gpu.txt (renamed from dts/Bindings/drm/msm/gpu.txt)0
-rw-r--r--dts/Bindings/display/msm/hdmi.txt (renamed from dts/Bindings/drm/msm/hdmi.txt)3
-rw-r--r--dts/Bindings/display/msm/mdp.txt (renamed from dts/Bindings/drm/msm/mdp.txt)3
-rw-r--r--dts/Bindings/display/mxsfb.txt (renamed from dts/Bindings/fb/mxsfb.txt)0
-rw-r--r--dts/Bindings/display/panel/ampire,am800480r3tmqwa1h.txt (renamed from dts/Bindings/panel/ampire,am800480r3tmqwa1h.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b080uan01.txt (renamed from dts/Bindings/panel/auo,b080uan01.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b101aw03.txt (renamed from dts/Bindings/panel/auo,b101aw03.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b101ean01.txt (renamed from dts/Bindings/panel/auo,b101ean01.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b101xtn01.txt (renamed from dts/Bindings/panel/auo,b101xtn01.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b116xw03.txt (renamed from dts/Bindings/panel/auo,b116xw03.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b133htn01.txt (renamed from dts/Bindings/panel/auo,b133htn01.txt)0
-rw-r--r--dts/Bindings/display/panel/auo,b133xtn01.txt (renamed from dts/Bindings/panel/auo,b133xtn01.txt)0
-rw-r--r--dts/Bindings/display/panel/avic,tm070ddh03.txt (renamed from dts/Bindings/panel/avic,tm070ddh03.txt)0
-rw-r--r--dts/Bindings/display/panel/chunghwa,claa101wa01a.txt (renamed from dts/Bindings/panel/chunghwa,claa101wa01a.txt)0
-rw-r--r--dts/Bindings/display/panel/chunghwa,claa101wb03.txt (renamed from dts/Bindings/panel/chunghwa,claa101wb03.txt)0
-rw-r--r--dts/Bindings/display/panel/display-timing.txt (renamed from dts/Bindings/video/display-timing.txt)0
-rw-r--r--dts/Bindings/display/panel/edt,et057090dhu.txt (renamed from dts/Bindings/panel/edt,et057090dhu.txt)0
-rw-r--r--dts/Bindings/display/panel/edt,et070080dh6.txt (renamed from dts/Bindings/panel/edt,et070080dh6.txt)0
-rw-r--r--dts/Bindings/display/panel/edt,etm0700g0dh6.txt (renamed from dts/Bindings/panel/edt,etm0700g0dh6.txt)0
-rw-r--r--dts/Bindings/display/panel/foxlink,fl500wvr00-a0t.txt (renamed from dts/Bindings/panel/foxlink,fl500wvr00-a0t.txt)0
-rw-r--r--dts/Bindings/display/panel/giantplus,gpg482739qs5.txt (renamed from dts/Bindings/panel/giantplus,gpg482739qs5.txt)0
-rw-r--r--dts/Bindings/display/panel/hannstar,hsd070pww1.txt (renamed from dts/Bindings/panel/hannstar,hsd070pww1.txt)0
-rw-r--r--dts/Bindings/display/panel/hannstar,hsd100pxn1.txt (renamed from dts/Bindings/panel/hannstar,hsd100pxn1.txt)0
-rw-r--r--dts/Bindings/display/panel/hit,tx23d38vm0caa.txt (renamed from dts/Bindings/panel/hit,tx23d38vm0caa.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,at043tn24.txt (renamed from dts/Bindings/panel/innolux,at043tn24.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,g121i1-l01.txt (renamed from dts/Bindings/panel/innolux,g121i1-l01.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,n116bge.txt (renamed from dts/Bindings/panel/innolux,n116bge.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,n156bge-l21.txt (renamed from dts/Bindings/panel/innolux,n156bge-l21.txt)0
-rw-r--r--dts/Bindings/display/panel/innolux,zj070na-01p.txt (renamed from dts/Bindings/panel/innolux,zj070na-01p.txt)0
-rw-r--r--dts/Bindings/display/panel/lg,lb070wv8.txt (renamed from dts/Bindings/panel/lg,lb070wv8.txt)0
-rw-r--r--dts/Bindings/display/panel/lg,ld070wx3-sl01.txt (renamed from dts/Bindings/panel/lg,ld070wx3-sl01.txt)0
-rw-r--r--dts/Bindings/display/panel/lg,lg4573.txt (renamed from dts/Bindings/panel/lg,lg4573.txt)0
-rw-r--r--dts/Bindings/display/panel/lg,lh500wx1-sd03.txt (renamed from dts/Bindings/panel/lg,lh500wx1-sd03.txt)0
-rw-r--r--dts/Bindings/display/panel/lg,lp129qe.txt (renamed from dts/Bindings/panel/lg,lp129qe.txt)0
-rw-r--r--dts/Bindings/display/panel/lgphilips,lb035q02.txt (renamed from dts/Bindings/video/lgphilips,lb035q02.txt)0
-rw-r--r--dts/Bindings/display/panel/nec,nl4827hc19-05b.txt (renamed from dts/Bindings/panel/nec,nl4827hc19-05b.txt)0
-rw-r--r--dts/Bindings/display/panel/okaya,rs800480t-7x0gp.txt (renamed from dts/Bindings/panel/okaya,rs800480t-7x0gp.txt)0
-rw-r--r--dts/Bindings/display/panel/ortustech,com43h4m85ulc.txt (renamed from dts/Bindings/panel/ortustech,com43h4m85ulc.txt)0
-rw-r--r--dts/Bindings/display/panel/panasonic,vvx10f004b00.txt (renamed from dts/Bindings/panel/panasonic,vvx10f004b00.txt)0
-rw-r--r--dts/Bindings/display/panel/panel-dpi.txt (renamed from dts/Bindings/video/panel-dpi.txt)2
-rw-r--r--dts/Bindings/display/panel/panel-dsi-cm.txt (renamed from dts/Bindings/video/panel-dsi-cm.txt)0
-rw-r--r--dts/Bindings/display/panel/samsung,ld9040.txt (renamed from dts/Bindings/panel/samsung,ld9040.txt)2
-rw-r--r--dts/Bindings/display/panel/samsung,ltn101nt05.txt (renamed from dts/Bindings/panel/samsung,ltn101nt05.txt)0
-rw-r--r--dts/Bindings/display/panel/samsung,ltn140at29-301.txt (renamed from dts/Bindings/panel/samsung,ltn140at29-301.txt)0
-rw-r--r--dts/Bindings/display/panel/samsung,s6e8aa0.txt (renamed from dts/Bindings/panel/samsung,s6e8aa0.txt)2
-rw-r--r--dts/Bindings/display/panel/sharp,lq101r1sx01.txt (renamed from dts/Bindings/panel/sharp,lq101r1sx01.txt)0
-rw-r--r--dts/Bindings/display/panel/sharp,ls037v7dw01.txt (renamed from dts/Bindings/video/sharp,ls037v7dw01.txt)0
-rw-r--r--dts/Bindings/display/panel/shelly,sca07010-bfn-lnn.txt (renamed from dts/Bindings/panel/shelly,sca07010-bfn-lnn.txt)0
-rw-r--r--dts/Bindings/display/panel/simple-panel.txt (renamed from dts/Bindings/panel/simple-panel.txt)0
-rw-r--r--dts/Bindings/display/panel/sony,acx565akm.txt (renamed from dts/Bindings/video/sony,acx565akm.txt)0
-rw-r--r--dts/Bindings/display/panel/toppoly,td028ttec1.txt (renamed from dts/Bindings/video/toppoly,td028ttec1.txt)0
-rw-r--r--dts/Bindings/display/panel/tpo,td043mtea1.txt (renamed from dts/Bindings/video/tpo,td043mtea1.txt)0
-rw-r--r--dts/Bindings/display/renesas,du.txt (renamed from dts/Bindings/video/renesas,du.txt)14
-rw-r--r--dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt (renamed from dts/Bindings/video/dw_hdmi-rockchip.txt)0
-rw-r--r--dts/Bindings/display/rockchip/rockchip-drm.txt (renamed from dts/Bindings/video/rockchip-drm.txt)2
-rw-r--r--dts/Bindings/display/rockchip/rockchip-vop.txt (renamed from dts/Bindings/video/rockchip-vop.txt)0
-rw-r--r--dts/Bindings/display/simple-framebuffer-sunxi.txt (renamed from dts/Bindings/video/simple-framebuffer-sunxi.txt)0
-rw-r--r--dts/Bindings/display/simple-framebuffer.txt (renamed from dts/Bindings/video/simple-framebuffer.txt)0
-rw-r--r--dts/Bindings/display/sm501fb.txt (renamed from dts/Bindings/fb/sm501fb.txt)0
-rw-r--r--dts/Bindings/display/ssd1289fb.txt (renamed from dts/Bindings/video/ssd1289fb.txt)0
-rw-r--r--dts/Bindings/display/ssd1307fb.txt (renamed from dts/Bindings/video/ssd1307fb.txt)3
-rw-r--r--dts/Bindings/display/st,stih4xx.txt (renamed from dts/Bindings/gpu/st,stih4xx.txt)4
-rw-r--r--dts/Bindings/display/tegra/nvidia,tegra114-mipi.txt (renamed from dts/Bindings/mipi/nvidia,tegra114-mipi.txt)0
-rw-r--r--dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt (renamed from dts/Bindings/gpu/nvidia,tegra20-host1x.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,dra7-dss.txt (renamed from dts/Bindings/video/ti,dra7-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,omap-dss.txt (renamed from dts/Bindings/video/ti,omap-dss.txt)0
-rw-r--r--dts/Bindings/display/ti/ti,omap2-dss.txt (renamed from dts/Bindings/video/ti,omap2-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,omap3-dss.txt (renamed from dts/Bindings/video/ti,omap3-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,omap4-dss.txt (renamed from dts/Bindings/video/ti,omap4-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,omap5-dss.txt (renamed from dts/Bindings/video/ti,omap5-dss.txt)2
-rw-r--r--dts/Bindings/display/ti/ti,opa362.txt (renamed from dts/Bindings/video/ti,opa362.txt)0
-rw-r--r--dts/Bindings/display/ti/ti,tfp410.txt (renamed from dts/Bindings/video/ti,tfp410.txt)0
-rw-r--r--dts/Bindings/display/ti/ti,tpd12s015.txt (renamed from dts/Bindings/video/ti,tpd12s015.txt)0
-rw-r--r--dts/Bindings/display/tilcdc/panel.txt (renamed from dts/Bindings/drm/tilcdc/panel.txt)2
-rw-r--r--dts/Bindings/display/tilcdc/tfp410.txt (renamed from dts/Bindings/drm/tilcdc/tfp410.txt)0
-rw-r--r--dts/Bindings/display/tilcdc/tilcdc.txt (renamed from dts/Bindings/drm/tilcdc/tilcdc.txt)0
-rw-r--r--dts/Bindings/display/via,vt8500-fb.txt (renamed from dts/Bindings/video/via,vt8500-fb.txt)0
-rw-r--r--dts/Bindings/display/wm,prizm-ge-rops.txt (renamed from dts/Bindings/video/wm,prizm-ge-rops.txt)0
-rw-r--r--dts/Bindings/display/wm,wm8505-fb.txt (renamed from dts/Bindings/video/wm,wm8505-fb.txt)0
-rw-r--r--dts/Bindings/dma/ti-dma-crossbar.txt15
-rw-r--r--dts/Bindings/dma/ti-edma.txt117
-rw-r--r--dts/Bindings/edac/apm-xgene-edac.txt23
-rw-r--r--dts/Bindings/eeprom/at25.txt (renamed from dts/Bindings/misc/at25.txt)0
-rw-r--r--dts/Bindings/eeprom/eeprom.txt (renamed from dts/Bindings/eeprom.txt)0
-rw-r--r--dts/Bindings/extcon/extcon-arizona.txt15
-rw-r--r--dts/Bindings/fpga/altera-socfpga-fpga-mgr.txt2
-rw-r--r--dts/Bindings/fpga/xilinx-zynq-fpga-mgr.txt19
-rw-r--r--dts/Bindings/gpio/gpio-mpc8xxx.txt4
-rw-r--r--dts/Bindings/gpio/gpio-msm.txt26
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt1
-rw-r--r--dts/Bindings/gpio/gpio-zynq.txt9
-rw-r--r--dts/Bindings/gpio/gpio.txt41
-rw-r--r--dts/Bindings/gpio/netxbig-gpio-ext.txt22
-rw-r--r--dts/Bindings/hwmon/ina209.txt18
-rw-r--r--dts/Bindings/hwmon/ina2xx.txt1
-rw-r--r--dts/Bindings/hwmon/pwm-fan.txt29
-rw-r--r--dts/Bindings/i2c/i2c-davinci.txt6
-rw-r--r--dts/Bindings/i2c/i2c-imx.txt9
-rw-r--r--dts/Bindings/i2c/i2c-rcar.txt1
-rw-r--r--dts/Bindings/i2c/i2c-sh_mobile.txt1
-rw-r--r--dts/Bindings/i2c/i2c-uniphier-f.txt25
-rw-r--r--dts/Bindings/i2c/i2c-uniphier.txt25
-rw-r--r--dts/Bindings/i2c/trivial-devices.txt3
-rw-r--r--dts/Bindings/iio/accel/lis302.txt (renamed from dts/Bindings/misc/lis302.txt)0
-rw-r--r--dts/Bindings/iio/accel/mma8452.txt24
-rw-r--r--dts/Bindings/iio/adc/hi8435.txt21
-rw-r--r--dts/Bindings/iio/dac/ti,dac7512.txt (renamed from dts/Bindings/misc/ti,dac7512.txt)0
-rw-r--r--dts/Bindings/iio/light/apds9960.txt22
-rw-r--r--dts/Bindings/iio/light/us5182d.txt34
-rw-r--r--dts/Bindings/iio/pressure/bmp085.txt (renamed from dts/Bindings/misc/bmp085.txt)0
-rw-r--r--dts/Bindings/input/ads7846.txt3
-rw-r--r--dts/Bindings/input/da9062-onkey.txt32
-rw-r--r--dts/Bindings/input/gpio-keys-polled.txt10
-rw-r--r--dts/Bindings/input/gpio-keys.txt1
-rw-r--r--dts/Bindings/input/gpio-matrix-keypad.txt1
-rw-r--r--dts/Bindings/input/hid-over-i2c.txt (renamed from dts/Bindings/hid/hid-over-i2c.txt)0
-rw-r--r--dts/Bindings/input/nvidia,tegra20-kbc.txt3
-rw-r--r--dts/Bindings/input/qcom,pm8xxx-keypad.txt1
-rw-r--r--dts/Bindings/input/rotary-encoder.txt10
-rw-r--r--dts/Bindings/input/samsung-keypad.txt3
-rw-r--r--dts/Bindings/input/touchscreen/edt-ft5x06.txt8
-rw-r--r--dts/Bindings/input/touchscreen/focaltech-ft6236.txt35
-rw-r--r--dts/Bindings/input/touchscreen/tsc2005.txt34
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic-v3.txt (renamed from dts/Bindings/arm/gic-v3.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.txt (renamed from dts/Bindings/arm/gic.txt)24
-rw-r--r--dts/Bindings/interrupt-controller/arm,versatile-fpga-irq.txt (renamed from dts/Bindings/arm/versatile-fpga-irq.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/arm,vic.txt (renamed from dts/Bindings/arm/vic.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/axis,crisv32-intc.txt (renamed from dts/Bindings/cris/interrupts.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/img,meta-intc.txt (renamed from dts/Bindings/metag/meta-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/img,pdc-intc.txt (renamed from dts/Bindings/metag/pdc-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/intel,ce4100-ioapic.txt (renamed from dts/Bindings/x86/interrupt.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,sysirq.txt (renamed from dts/Bindings/arm/mediatek/mediatek,sysirq.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/mrvl,intc.txt (renamed from dts/Bindings/arm/mrvl/intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt (renamed from dts/Bindings/arm/lpc32xx-mic.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/open-pic.txt (renamed from dts/Bindings/open-pic.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/renesas,irqc.txt1
-rw-r--r--dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt (renamed from dts/Bindings/arm/samsung/interrupt-combiner.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/snps,arc700-intc.txt (renamed from dts/Bindings/arc/interrupts.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt (renamed from dts/Bindings/arc/archs-idu-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/snps,archs-intc.txt (renamed from dts/Bindings/arc/archs-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt (renamed from dts/Bindings/arm/spear/shirq.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt (renamed from dts/Bindings/c6x/interrupt.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/ti,cp-intc.txt (renamed from dts/Bindings/arm/davinci/cp-intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/ti,omap2-intc.txt (renamed from dts/Bindings/arm/omap/intc.txt)0
-rw-r--r--dts/Bindings/interrupt-controller/via,vt8500-intc.txt (renamed from dts/Bindings/arm/vt8500/via,vt8500-intc.txt)0
-rw-r--r--dts/Bindings/iommu/arm,smmu-v3.txt19
-rw-r--r--dts/Bindings/iommu/samsung,sysmmu.txt2
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-rw-r--r--dts/Bindings/leds/backlight/88pm860x.txt (renamed from dts/Bindings/video/backlight/88pm860x.txt)0
-rw-r--r--dts/Bindings/leds/backlight/gpio-backlight.txt (renamed from dts/Bindings/video/backlight/gpio-backlight.txt)0
-rw-r--r--dts/Bindings/leds/backlight/lp855x.txt (renamed from dts/Bindings/video/backlight/lp855x.txt)0
-rw-r--r--dts/Bindings/leds/backlight/max8925-backlight.txt (renamed from dts/Bindings/video/backlight/max8925-backlight.txt)0
-rw-r--r--dts/Bindings/leds/backlight/pm8941-wled.txt (renamed from dts/Bindings/video/backlight/pm8941-wled.txt)2
-rw-r--r--dts/Bindings/leds/backlight/pwm-backlight.txt (renamed from dts/Bindings/video/backlight/pwm-backlight.txt)0
-rw-r--r--dts/Bindings/leds/backlight/sky81452-backlight.txt (renamed from dts/Bindings/video/backlight/sky81452-backlight.txt)0
-rw-r--r--dts/Bindings/leds/backlight/tps65217-backlight.txt (renamed from dts/Bindings/video/backlight/tps65217-backlight.txt)0
-rw-r--r--dts/Bindings/leds/leds-aat1290.txt8
-rw-r--r--dts/Bindings/leds/leds-bcm6328.txt10
-rw-r--r--dts/Bindings/leds/leds-netxbig.txt92
-rw-r--r--dts/Bindings/mailbox/omap-mailbox.txt8
-rw-r--r--dts/Bindings/mailbox/sti-mailbox.txt51
-rw-r--r--dts/Bindings/media/exynos-jpeg-codec.txt3
-rw-r--r--dts/Bindings/memory-controllers/arm,pl172.txt8
-rw-r--r--dts/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt (renamed from dts/Bindings/arm/calxeda/mem-ctrlr.txt)0
-rw-r--r--dts/Bindings/memory-controllers/renesas-memory-controllers.txt6
-rw-r--r--dts/Bindings/mfd/arizona.txt15
-rw-r--r--dts/Bindings/mfd/atmel-flexcom.txt63
-rw-r--r--dts/Bindings/mfd/atmel-hlcdc.txt2
-rw-r--r--dts/Bindings/mfd/axp20x.txt4
-rw-r--r--dts/Bindings/mfd/cros-ec.txt4
-rw-r--r--dts/Bindings/mfd/da9150.txt33
-rw-r--r--dts/Bindings/mfd/s2mps11.txt28
-rw-r--r--dts/Bindings/mfd/sky81452.txt2
-rw-r--r--dts/Bindings/mfd/tc3589x.txt1
-rw-r--r--dts/Bindings/mips/img/xilfpga.txt83
-rw-r--r--dts/Bindings/misc/sram.txt16
-rw-r--r--dts/Bindings/mmc/fsl-esdhc.txt2
-rw-r--r--dts/Bindings/mmc/mmc.txt6
-rw-r--r--dts/Bindings/mmc/mtk-sd.txt11
-rw-r--r--dts/Bindings/mmc/renesas,mmcif.txt5
-rw-r--r--dts/Bindings/mmc/rockchip-dw-mshc.txt13
-rw-r--r--dts/Bindings/mmc/synopsys-dw-mshc.txt25
-rw-r--r--dts/Bindings/mtd/fsmc-nand.txt6
-rw-r--r--dts/Bindings/mtd/partition.txt71
-rw-r--r--dts/Bindings/mtd/vf610-nfc.txt59
-rw-r--r--dts/Bindings/net/apm-xgene-enet.txt10
-rw-r--r--dts/Bindings/net/brcm,iproc-mdio.txt23
-rw-r--r--dts/Bindings/net/can/sun4i_can.txt36
-rw-r--r--dts/Bindings/net/cpsw.txt12
-rw-r--r--dts/Bindings/net/fsl-tsec-phy.txt4
-rw-r--r--dts/Bindings/net/hisilicon-hip04-net.txt4
-rw-r--r--dts/Bindings/net/hisilicon-hns-dsaf.txt49
-rw-r--r--dts/Bindings/net/hisilicon-hns-mdio.txt22
-rw-r--r--dts/Bindings/net/hisilicon-hns-nic.txt47
-rw-r--r--dts/Bindings/net/ieee802154/mrf24j40.txt20
-rw-r--r--dts/Bindings/net/maxim,ds26522.txt13
-rw-r--r--dts/Bindings/net/nfc/nfcmrvl.txt61
-rw-r--r--dts/Bindings/net/nfc/st-nci-i2c.txt7
-rw-r--r--dts/Bindings/net/nfc/st-nci-spi.txt9
-rw-r--r--dts/Bindings/net/renesas,ravb.txt69
-rw-r--r--dts/Bindings/nvmem/imx-ocotp.txt20
-rw-r--r--dts/Bindings/nvmem/mxs-ocotp.txt25
-rw-r--r--dts/Bindings/nvmem/rockchip-efuse.txt38
-rw-r--r--dts/Bindings/nvmem/vf610-ocotp.txt19
-rw-r--r--dts/Bindings/pci/altera-pcie-msi.txt28
-rw-r--r--dts/Bindings/pci/altera-pcie.txt49
-rw-r--r--dts/Bindings/pci/arm,juno-r1-pcie.txt10
-rw-r--r--dts/Bindings/pci/brcm,iproc-pcie.txt20
-rw-r--r--dts/Bindings/pci/designware-pcie.txt12
-rw-r--r--dts/Bindings/pci/hisilicon-pcie.txt44
-rw-r--r--dts/Bindings/pci/host-generic-pci.txt5
-rw-r--r--dts/Bindings/pci/layerscape-pci.txt14
-rw-r--r--dts/Bindings/pci/pci-msi.txt220
-rw-r--r--dts/Bindings/pci/pci.txt4
-rw-r--r--dts/Bindings/pci/plda,xpressrich3-axi.txt12
-rw-r--r--dts/Bindings/phy/brcm,cygnus-pcie-phy.txt47
-rw-r--r--dts/Bindings/phy/calxeda-combophy.txt (renamed from dts/Bindings/arm/calxeda/combophy.txt)0
-rw-r--r--dts/Bindings/phy/keystone-usb-phy.txt (renamed from dts/Bindings/usb/keystone-phy.txt)0
-rw-r--r--dts/Bindings/phy/mxs-usb-phy.txt (renamed from dts/Bindings/usb/mxs-phy.txt)0
-rw-r--r--dts/Bindings/phy/nvidia,tegra20-usb-phy.txt (renamed from dts/Bindings/usb/nvidia,tegra20-usb-phy.txt)0
-rw-r--r--dts/Bindings/phy/phy-mt65xx-usb.txt68
-rw-r--r--dts/Bindings/phy/qcom,usb-8x16-phy.txt (renamed from dts/Bindings/usb/qcom,usb-8x16-phy.txt)0
-rw-r--r--dts/Bindings/phy/samsung-phy.txt3
-rw-r--r--dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt1
-rw-r--r--dts/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt90
-rw-r--r--dts/Bindings/pinctrl/berlin,pinctrl.txt5
-rw-r--r--dts/Bindings/pinctrl/brcm,cygnus-gpio.txt16
-rw-r--r--dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt63
-rw-r--r--dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt1
-rw-r--r--dts/Bindings/power/bq24257.txt53
-rw-r--r--dts/Bindings/power/da9150-fg.txt23
-rw-r--r--dts/Bindings/power/pd-samsung.txt (renamed from dts/Bindings/arm/exynos/power_domain.txt)5
-rw-r--r--dts/Bindings/power/wakeup-source.txt71
-rw-r--r--dts/Bindings/power_supply/axp20x_usb_power.txt34
-rw-r--r--dts/Bindings/power_supply/qcom_smbb.txt131
-rw-r--r--dts/Bindings/power_supply/tps65217_charger.txt12
-rw-r--r--dts/Bindings/powerpc/fsl/mpc512x_lpbfifo.txt21
-rw-r--r--dts/Bindings/pwm/brcm,bcm7038-pwm.txt20
-rw-r--r--dts/Bindings/pwm/pwm-berlin.txt17
-rw-r--r--dts/Bindings/pwm/pwm-mtk-disp.txt42
-rw-r--r--dts/Bindings/pwm/pwm-sun4i.txt2
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.txt26
-rw-r--r--dts/Bindings/regulator/act8865-regulator.txt3
-rw-r--r--dts/Bindings/regulator/anatop-regulator.txt1
-rw-r--r--dts/Bindings/regulator/arizona-regulator.txt17
-rw-r--r--dts/Bindings/regulator/max77802.txt25
-rw-r--r--dts/Bindings/regulator/regulator.txt1
-rw-r--r--dts/Bindings/regulator/tps65023.txt60
-rw-r--r--dts/Bindings/rng/atmel-trng.txt (renamed from dts/Bindings/hwrng/atmel-trng.txt)0
-rw-r--r--dts/Bindings/rng/brcm,iproc-rng200.txt (renamed from dts/Bindings/hwrng/brcm,iproc-rng200.txt)0
-rw-r--r--dts/Bindings/rng/omap_rng.txt (renamed from dts/Bindings/hwrng/omap_rng.txt)0
-rw-r--r--dts/Bindings/rng/samsung,exynos-rng4.txt17
-rw-r--r--dts/Bindings/rng/st,rng.txt15
-rw-r--r--dts/Bindings/rng/st,stm32-rng.txt21
-rw-r--r--dts/Bindings/rng/timeriomem_rng.txt (renamed from dts/Bindings/hwrng/timeriomem_rng.txt)0
-rw-r--r--dts/Bindings/rtc/dallas,ds1390.txt18
-rw-r--r--dts/Bindings/rtc/isil,isl12057.txt10
-rw-r--r--dts/Bindings/rtc/pcf8563.txt25
-rw-r--r--dts/Bindings/rtc/rtc-opal.txt5
-rw-r--r--dts/Bindings/serial/ingenic,uart.txt3
-rw-r--r--dts/Bindings/serial/mrvl,pxa-ssp.txt1
-rw-r--r--dts/Bindings/serial/pl011.txt2
-rw-r--r--dts/Bindings/serial/qcom,msm-uartdm.txt6
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt2
-rw-r--r--dts/Bindings/serial/snps-dw-apb-uart.txt3
-rw-r--r--dts/Bindings/soc/mediatek/scpsys.txt10
-rw-r--r--dts/Bindings/soc/qcom/qcom,smem.txt57
-rw-r--r--dts/Bindings/soc/rockchip/power_domain.txt46
-rw-r--r--dts/Bindings/soc/ti/keystone-navigator-qmss.txt1
-rw-r--r--dts/Bindings/sound/ak4554.txt (renamed from dts/Bindings/sound/ak4554.c)0
-rw-r--r--dts/Bindings/sound/ak4613.txt17
-rw-r--r--dts/Bindings/sound/ak4642.txt22
-rw-r--r--dts/Bindings/sound/atmel-classd.txt52
-rw-r--r--dts/Bindings/sound/da7213.txt41
-rw-r--r--dts/Bindings/sound/da7219.txt106
-rw-r--r--dts/Bindings/sound/fsl-asoc-card.txt10
-rw-r--r--dts/Bindings/sound/nau8825.txt102
-rw-r--r--dts/Bindings/sound/renesas,rsnd.txt7
-rw-r--r--dts/Bindings/sound/rockchip-i2s.txt6
-rw-r--r--dts/Bindings/sound/rockchip-spdif.txt40
-rw-r--r--dts/Bindings/sound/rt5640.txt9
-rw-r--r--dts/Bindings/sound/sun4i-codec.txt27
-rw-r--r--dts/Bindings/sound/tdm-slot.txt11
-rw-r--r--dts/Bindings/spi/brcm,bcm2835-aux-spi.txt38
-rw-r--r--dts/Bindings/spi/spi-mt65xx.txt9
-rw-r--r--dts/Bindings/thermal/rockchip-thermal.txt11
-rw-r--r--dts/Bindings/thermal/ti_soc_thermal.txt14
-rw-r--r--dts/Bindings/timer/mediatek,mtk-timer.txt8
-rw-r--r--dts/Bindings/ufs/ufs-qcom.txt58
-rw-r--r--dts/Bindings/ufs/ufshcd-pltfrm.txt11
-rw-r--r--dts/Bindings/usb/ci-hdrc-usb2.txt27
-rw-r--r--dts/Bindings/usb/dwc3.txt8
-rw-r--r--dts/Bindings/usb/samsung-usbphy.txt117
-rw-r--r--dts/Bindings/vendor-prefixes.txt10
-rw-r--r--dts/Bindings/w1/omap-hdq.txt7
-rw-r--r--dts/Bindings/watchdog/brcm,bcm7038-wdt.txt19
-rw-r--r--dts/include/dt-bindings/clock/at91.h1
-rw-r--r--dts/include/dt-bindings/clock/bcm-ns2.h72
-rw-r--r--dts/include/dt-bindings/clock/bcm-nsp.h51
-rw-r--r--dts/include/dt-bindings/clock/bcm2835.h47
-rw-r--r--dts/include/dt-bindings/clock/berlin2q.h1
-rw-r--r--dts/include/dt-bindings/clock/exynos5250.h4
-rw-r--r--dts/include/dt-bindings/clock/exynos7-clk.h43
-rw-r--r--dts/include/dt-bindings/clock/imx6qdl-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/imx6sl-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/imx6sx-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/imx7d-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/mt8173-clk.h104
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-apq8084.h6
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-msm8916.h30
-rw-r--r--dts/include/dt-bindings/clock/qcom,gcc-msm8974.h3
-rw-r--r--dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h10
-rw-r--r--dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h8
-rw-r--r--dts/include/dt-bindings/clock/r8a7795-cpg-mssr.h63
-rw-r--r--dts/include/dt-bindings/clock/renesas-cpg-mssr.h15
-rw-r--r--dts/include/dt-bindings/clock/sun4i-a10-pll2.h53
-rw-r--r--dts/include/dt-bindings/clock/vf610-clock.h3
-rw-r--r--dts/include/dt-bindings/gpio/gpio.h12
-rw-r--r--dts/include/dt-bindings/input/input.h510
-rw-r--r--dts/include/dt-bindings/input/linux-event-codes.h805
-rw-r--r--dts/include/dt-bindings/leds/leds-netxbig.h18
-rw-r--r--dts/include/dt-bindings/mfd/arizona.h2
-rw-r--r--dts/include/dt-bindings/mfd/atmel-flexcom.h26
-rw-r--r--dts/include/dt-bindings/power/rk3288-power.h31
-rw-r--r--dts/src/arc/axc001.dtsi2
-rw-r--r--dts/src/arc/axc003.dtsi2
-rw-r--r--dts/src/arc/axc003_idu.dtsi2
-rw-r--r--dts/src/arc/nsim_hs.dts12
-rw-r--r--dts/src/arc/skeleton.dtsi2
-rw-r--r--dts/src/arc/vdk_axc003.dtsi2
-rw-r--r--dts/src/arc/vdk_axc003_idu.dtsi2
-rw-r--r--dts/src/arm/am335x-base0033.dts48
-rw-r--r--dts/src/arm/am335x-bone-common.dtsi3
-rw-r--r--dts/src/arm/am335x-bonegreen.dts53
-rw-r--r--dts/src/arm/am335x-evm.dts2
-rw-r--r--dts/src/arm/am335x-evmsk.dts2
-rw-r--r--dts/src/arm/am335x-igep0033.dtsi40
-rw-r--r--dts/src/arm/am335x-phycore-som.dtsi36
-rw-r--r--dts/src/arm/am335x-wega.dtsi13
-rw-r--r--dts/src/arm/am4372.dtsi1
-rw-r--r--dts/src/arm/am437x-gp-evm.dts31
-rw-r--r--dts/src/arm/am437x-idk-evm.dts2
-rw-r--r--dts/src/arm/am437x-sk-evm.dts4
-rw-r--r--dts/src/arm/am43x-epos-evm.dts2
-rw-r--r--dts/src/arm/am57xx-beagle-x15.dts117
-rw-r--r--dts/src/arm/armada-370-db.dts3
-rw-r--r--dts/src/arm/armada-370-dlink-dns327l.dts3
-rw-r--r--dts/src/arm/armada-370-mirabox.dts7
-rw-r--r--dts/src/arm/armada-370-netgear-rn102.dts9
-rw-r--r--dts/src/arm/armada-370-netgear-rn104.dts9
-rw-r--r--dts/src/arm/armada-370-rd.dts3
-rw-r--r--dts/src/arm/armada-370-seagate-nas-2bay.dts36
-rw-r--r--dts/src/arm/armada-370-seagate-nas-4bay.dts133
-rw-r--r--dts/src/arm/armada-370-seagate-nas-xbay.dtsi231
-rw-r--r--dts/src/arm/armada-370-seagate-personal-cloud-2bay.dts51
-rw-r--r--dts/src/arm/armada-370-seagate-personal-cloud.dts37
-rw-r--r--dts/src/arm/armada-370-seagate-personal-cloud.dtsi178
-rw-r--r--dts/src/arm/armada-370-synology-ds213j.dts3
-rw-r--r--dts/src/arm/armada-370.dtsi37
-rw-r--r--dts/src/arm/armada-375-db.dts4
-rw-r--r--dts/src/arm/armada-375.dtsi33
-rw-r--r--dts/src/arm/armada-385-db-ap.dts4
-rw-r--r--dts/src/arm/armada-385-linksys.dtsi4
-rw-r--r--dts/src/arm/armada-388-db.dts4
-rw-r--r--dts/src/arm/armada-388-gp.dts19
-rw-r--r--dts/src/arm/armada-388-rd.dts4
-rw-r--r--dts/src/arm/armada-38x.dtsi33
-rw-r--r--dts/src/arm/armada-xp-axpwifiap.dts4
-rw-r--r--dts/src/arm/armada-xp-db.dts4
-rw-r--r--dts/src/arm/armada-xp-gp.dts4
-rw-r--r--dts/src/arm/armada-xp-lenovo-ix4-300d.dts4
-rw-r--r--dts/src/arm/armada-xp-linksys-mamba.dts4
-rw-r--r--dts/src/arm/armada-xp-matrix.dts4
-rw-r--r--dts/src/arm/armada-xp-netgear-rn2120.dts90
-rw-r--r--dts/src/arm/armada-xp-openblocks-ax3-4.dts4
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-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-1-10g-0.dtsi61
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-1-1g-0.dtsi68
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-1-1g-1.dtsi68
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-1-1g-2.dtsi68
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-1-1g-3.dtsi68
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-1-1g-4.dtsi68
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman-1.dtsi101
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi66
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-10g-0.dtsi63
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi66
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-10g-1.dtsi63
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-1g-0.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-1g-1.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-1g-2.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-1g-3.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-1g-4.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0-1g-5.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-0.dtsi106
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1-10g-0.dtsi63
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1-10g-1.dtsi63
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1-1g-0.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1-1g-1.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1-1g-2.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1-1g-3.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1-1g-4.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1-1g-5.dtsi62
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3-1.dtsi106
-rw-r--r--dts/src/powerpc/fsl/qoriq-fman3l-0.dtsi94
-rw-r--r--dts/src/powerpc/fsl/t1023rdb.dts (renamed from dts/src/powerpc/t1023rdb.dts)4
-rw-r--r--dts/src/powerpc/fsl/t1023si-post.dtsi19
-rw-r--r--dts/src/powerpc/fsl/t1024qds.dts (renamed from dts/src/powerpc/t1024qds.dts)4
-rw-r--r--dts/src/powerpc/fsl/t1024rdb.dts (renamed from dts/src/powerpc/t1024rdb.dts)4
-rw-r--r--dts/src/powerpc/fsl/t102xsi-pre.dtsi6
-rw-r--r--dts/src/powerpc/fsl/t1040d4rdb.dts (renamed from dts/src/powerpc/t1040d4rdb.dts)4
-rw-r--r--dts/src/powerpc/fsl/t1040qds.dts (renamed from dts/src/powerpc/t1040qds.dts)4
-rw-r--r--dts/src/powerpc/fsl/t1040rdb.dts (renamed from dts/src/powerpc/t1040rdb.dts)4
-rw-r--r--dts/src/powerpc/fsl/t1040si-post.dtsi31
-rw-r--r--dts/src/powerpc/fsl/t1042d4rdb.dts (renamed from dts/src/powerpc/t1042d4rdb.dts)4
-rw-r--r--dts/src/powerpc/fsl/t1042qds.dts (renamed from dts/src/powerpc/t1042qds.dts)4
-rw-r--r--dts/src/powerpc/fsl/t1042rdb.dts (renamed from dts/src/powerpc/t1042rdb.dts)4
-rw-r--r--dts/src/powerpc/fsl/t1042rdb_pi.dts (renamed from dts/src/powerpc/t1042rdb_pi.dts)4
-rw-r--r--dts/src/powerpc/fsl/t104xd4rdb.dtsi (renamed from dts/src/powerpc/t104xd4rdb.dtsi)10
-rw-r--r--dts/src/powerpc/fsl/t104xqds.dtsi (renamed from dts/src/powerpc/t104xqds.dtsi)0
-rw-r--r--dts/src/powerpc/fsl/t104xrdb.dtsi (renamed from dts/src/powerpc/t104xrdb.dtsi)0
-rw-r--r--dts/src/powerpc/fsl/t104xsi-pre.dtsi9
-rw-r--r--dts/src/powerpc/fsl/t2080qds.dts (renamed from dts/src/powerpc/t2080qds.dts)4
-rw-r--r--dts/src/powerpc/fsl/t2080rdb.dts (renamed from dts/src/powerpc/t2080rdb.dts)4
-rw-r--r--dts/src/powerpc/fsl/t2081qds.dts (renamed from dts/src/powerpc/t2081qds.dts)4
-rw-r--r--dts/src/powerpc/fsl/t2081si-post.dtsi43
-rw-r--r--dts/src/powerpc/fsl/t208xqds.dtsi (renamed from dts/src/powerpc/t208xqds.dtsi)0
-rw-r--r--dts/src/powerpc/fsl/t208xrdb.dtsi (renamed from dts/src/powerpc/t208xrdb.dtsi)0
-rw-r--r--dts/src/powerpc/fsl/t208xsi-pre.dtsi11
-rw-r--r--dts/src/powerpc/fsl/t4240qds.dts (renamed from dts/src/powerpc/t4240qds.dts)4
-rw-r--r--dts/src/powerpc/fsl/t4240rdb.dts (renamed from dts/src/powerpc/t4240rdb.dts)4
-rw-r--r--dts/src/powerpc/fsl/t4240si-post.dtsi88
-rw-r--r--dts/src/powerpc/fsl/t4240si-pre.dtsi22
-rw-r--r--dts/src/powerpc/mpc5121.dtsi11
-rw-r--r--dts/src/powerpc/mpc5125twr.dts11
-rw-r--r--dts/src/powerpc/prpmc2800.dts297
-rw-r--r--dts/src/xtensa/kc705_nommu.dts17
1003 files changed, 31786 insertions, 4807 deletions
diff --git a/dts/Bindings/arm/amlogic.txt b/dts/Bindings/arm/amlogic.txt
index 973884a..1dfee20 100644
--- a/dts/Bindings/arm/amlogic.txt
+++ b/dts/Bindings/arm/amlogic.txt
@@ -9,6 +9,12 @@ Boards with the Amlogic Meson8 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson8";
+Boards with the Amlogic Meson8b SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,meson8b";
+
Board compatible values:
- - "geniatech,atv1200"
- - "minix,neo-x8"
+ - "geniatech,atv1200" (Meson6)
+ - "minix,neo-x8" (Meson8)
+ - "tronfy,mxq" (Meson8b)
+ - "hardkernel,odroid-c1" (Meson8b)
diff --git a/dts/Bindings/arm/apm/scu.txt b/dts/Bindings/arm/apm/scu.txt
new file mode 100644
index 0000000..b45be06
--- /dev/null
+++ b/dts/Bindings/arm/apm/scu.txt
@@ -0,0 +1,17 @@
+APM X-GENE SoC series SCU Registers
+
+This system clock unit contain various register that control block resets,
+clock enable/disables, clock divisors and other deepsleep registers.
+
+Properties:
+ - compatible : should contain two values. First value must be:
+ - "apm,xgene-scu"
+ second value must be always "syscon".
+
+ - reg : offset and length of the register set.
+
+Example :
+ scu: system-clk-controller@17000000 {
+ compatible = "apm,xgene-scu","syscon";
+ reg = <0x0 0x17000000 0x0 0x400>;
+ };
diff --git a/dts/Bindings/arm/arm,scpi.txt b/dts/Bindings/arm/arm,scpi.txt
new file mode 100644
index 0000000..86302de
--- /dev/null
+++ b/dts/Bindings/arm/arm,scpi.txt
@@ -0,0 +1,188 @@
+System Control and Power Interface (SCPI) Message Protocol
+----------------------------------------------------------
+
+Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
+("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
+by Linux to initiate various system control and power operations.
+
+Required properties:
+
+- compatible : should be "arm,scpi"
+- mboxes: List of phandle and mailbox channel specifiers
+ All the channels reserved by remote SCP firmware for use by
+ SCPI message protocol should be specified in any order
+- shmem : List of phandle pointing to the shared memory(SHM) area between the
+ processors using these mailboxes for IPC, one for each mailbox
+ SHM can be any memory reserved for the purpose of this communication
+ between the processors.
+
+See Documentation/devicetree/bindings/mailbox/mailbox.txt
+for more details about the generic mailbox controller and
+client driver bindings.
+
+Clock bindings for the clocks based on SCPI Message Protocol
+------------------------------------------------------------
+
+This binding uses the common clock binding[1].
+
+Container Node
+==============
+Required properties:
+- compatible : should be "arm,scpi-clocks"
+ All the clocks provided by SCP firmware via SCPI message
+ protocol much be listed as sub-nodes under this node.
+
+Sub-nodes
+=========
+Required properties:
+- compatible : shall include one of the following
+ "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
+ These clocks don't provide an entire range of values between the
+ limits but only discrete points within the range. The firmware
+ provides the mapping for each such operating frequency and the
+ index associated with it. The firmware also manages the
+ voltage scaling appropriately with the clock scaling.
+ "arm,scpi-variable-clocks" - all the clocks that are variable and provide full
+ range within the specified range. The firmware provides the
+ range of values within a specified range.
+
+Other required properties for all clocks(all from common clock binding):
+- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands.
+- clock-output-names : shall be the corresponding names of the outputs.
+- clock-indices: The identifying number for the clocks(i.e.clock_id) in the
+ node. It can be non linear and hence provide the mapping of identifiers
+ into the clock-output-names array.
+
+SRAM and Shared Memory for SCPI
+-------------------------------
+
+A small area of SRAM is reserved for SCPI communication between application
+processors and SCP.
+
+Required properties:
+- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno
+
+The rest of the properties should follow the generic mmio-sram description
+found in ../../misc/sysram.txt
+
+Each sub-node represents the reserved area for SCPI.
+
+Required sub-node properties:
+- reg : The base offset and size of the reserved area with the SRAM
+- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
+ shared memory on Juno platforms
+
+Sensor bindings for the sensors based on SCPI Message Protocol
+--------------------------------------------------------------
+SCPI provides an API to access the various sensors on the SoC.
+
+Required properties:
+- compatible : should be "arm,scpi-sensors".
+- #thermal-sensor-cells: should be set to 1. This property follows the
+ thermal device tree bindings[2].
+
+ Valid cell values are raw identifiers (Sensor
+ ID) as used by the firmware. Refer to
+ platform documentation for your
+ implementation for the IDs to use. For Juno
+ R0 and Juno R1 refer to [3].
+
+[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/thermal/thermal.txt
+[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
+
+Example:
+
+sram: sram@50000000 {
+ compatible = "arm,juno-sram-ns", "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "arm,juno-scp-shmem";
+ reg = <0x200 0x200>;
+ };
+};
+
+mailbox: mailbox0@40000000 {
+ ....
+ #mbox-cells = <1>;
+};
+
+scpi_protocol: scpi@2e000000 {
+ compatible = "arm,scpi";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>, <1>, <2>;
+ clock-output-names = "atlclk", "aplclk","gpuclk";
+ };
+ scpi_clk: scpi_clocks@3 {
+ compatible = "arm,scpi-variable-clocks";
+ #clock-cells = <1>;
+ clock-indices = <3>, <4>;
+ clock-output-names = "pxlclk0", "pxlclk1";
+ };
+ };
+
+ scpi_sensors0: sensors {
+ compatible = "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+};
+
+cpu@0 {
+ ...
+ reg = <0 0>;
+ clocks = <&scpi_dvfs 0>;
+};
+
+hdlcd@7ff60000 {
+ ...
+ reg = <0 0x7ff60000 0 0x1000>;
+ clocks = <&scpi_clk 4>;
+};
+
+thermal-zones {
+ soc_thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+
+ /* sensor ID */
+ thermal-sensors = <&scpi_sensors0 3>;
+ ...
+ };
+};
+
+In the above example, the #clock-cells is set to 1 as required.
+scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0,
+1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0
+and pxlclk1 with 3 and 4 as clock-indices.
+
+The first consumer in the example is cpu@0 and it has '0' as the clock
+specifier which points to the first entry in the output clocks of
+scpi_dvfs i.e. "atlclk".
+
+Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input
+clock. '4' in the clock specifier here points to the second entry
+in the output clocks of scpi_clocks i.e. "pxlclk1"
+
+The thermal-sensors property in the soc_thermal node uses the
+temperature sensor provided by SCP firmware to setup a thermal
+zone. The ID "3" is the sensor identifier for the temperature sensor
+as used by the firmware.
diff --git a/dts/Bindings/arm/bcm/brcm,brcmstb.txt b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
index 430608e..0d0c1ae 100644
--- a/dts/Bindings/arm/bcm/brcm,brcmstb.txt
+++ b/dts/Bindings/arm/bcm/brcm,brcmstb.txt
@@ -20,6 +20,25 @@ system control is required:
- compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
+hif-cpubiuctrl node
+-------------------
+SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
+(BIU) block which controls and interfaces the CPU complex to the different
+Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
+offers a feature called Write Pairing which consists in collapsing two adjacent
+cache lines into a single (bursted) write transaction towards the memory
+controller (MEMC) to maximize write bandwidth.
+
+Required properties:
+
+ - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
+
+Optional properties:
+
+ - brcm,write-pairing:
+ Boolean property, which when present indicates that the chip
+ supports write-pairing.
+
example:
rdb {
#address-cells = <1>;
@@ -35,6 +54,7 @@ example:
hif_cpubiuctrl: syscon@3e2400 {
compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
reg = <0x3e2400 0x5b4>;
+ brcm,write-pairing;
};
hif_continuation: syscon@452000 {
@@ -43,8 +63,7 @@ example:
};
};
-Lastly, nodes that allow for support of SMP initialization and reboot are
-required:
+Nodes that allow for support of SMP initialization and reboot are required:
smpboot
-------
@@ -95,3 +114,142 @@ example:
compatible = "brcm,brcmstb-reboot";
syscon = <&sun_top_ctrl 0x304 0x308>;
};
+
+
+
+Power management
+----------------
+
+For power management (particularly, S2/S3/S5 system suspend), the following SoC
+components are needed:
+
+= Always-On control block (AON CTRL)
+
+This hardware provides control registers for the "always-on" (even in low-power
+modes) hardware, such as the Power Management State Machine (PMSM).
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-aon-ctrl"
+- reg : the register start and length for the AON CTRL block
+
+Example:
+
+aon-ctrl@410000 {
+ compatible = "brcm,brcmstb-aon-ctrl";
+ reg = <0x410000 0x400>;
+};
+
+= Memory controllers
+
+A Broadcom STB SoC typically has a number of independent memory controllers,
+each of which may have several associated hardware blocks, which are versioned
+independently (control registers, DDR PHYs, etc.). One might consider
+describing these controllers as a parent "memory controllers" block, which
+contains N sub-nodes (one for each controller in the system), each of which is
+associated with a number of hardware register resources (e.g., its PHY). See
+the example device tree snippet below.
+
+== MEMC (MEMory Controller)
+
+Represents a single memory controller instance.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
+
+Should contain subnodes for any of the following relevant hardware resources:
+
+== DDR PHY control
+
+Control registers for this memory controller's DDR PHY.
+
+Required properties:
+- compatible : should contain one of these
+ "brcm,brcmstb-ddr-phy-v225.1"
+ "brcm,brcmstb-ddr-phy-v240.1"
+ "brcm,brcmstb-ddr-phy-v240.2"
+
+- reg : the DDR PHY register range
+
+== DDR SHIMPHY
+
+Control registers for this memory controller's DDR SHIMPHY.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
+- reg : the DDR SHIMPHY register range
+
+== MEMC DDR control
+
+Sequencer DRAM parameters and control registers. Used for Self-Refresh
+Power-Down (SRPD), among other things.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-memc-ddr"
+- reg : the MEMC DDR register range
+
+Example:
+
+memory_controllers {
+ ranges;
+ compatible = "simple-bus";
+
+ memc@0 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges;
+
+ ddr-phy@f1106000 {
+ compatible = "brcm,brcmstb-ddr-phy-v240.1";
+ reg = <0xf1106000 0x21c>;
+ };
+
+ shimphy@f1108000 {
+ compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+ reg = <0xf1108000 0xe4>;
+ };
+
+ memc-ddr@f1102000 {
+ reg = <0xf1102000 0x800>;
+ compatible = "brcm,brcmstb-memc-ddr";
+ };
+ };
+
+ memc@1 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges;
+
+ ddr-phy@f1186000 {
+ compatible = "brcm,brcmstb-ddr-phy-v240.1";
+ reg = <0xf1186000 0x21c>;
+ };
+
+ shimphy@f1188000 {
+ compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+ reg = <0xf1188000 0xe4>;
+ };
+
+ memc-ddr@f1182000 {
+ reg = <0xf1182000 0x800>;
+ compatible = "brcm,brcmstb-memc-ddr";
+ };
+ };
+
+ memc@2 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges;
+
+ ddr-phy@f1206000 {
+ compatible = "brcm,brcmstb-ddr-phy-v240.1";
+ reg = <0xf1206000 0x21c>;
+ };
+
+ shimphy@f1208000 {
+ compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
+ reg = <0xf1208000 0xe4>;
+ };
+
+ memc-ddr@f1202000 {
+ reg = <0xf1202000 0x800>;
+ compatible = "brcm,brcmstb-memc-ddr";
+ };
+ };
+};
diff --git a/dts/Bindings/arm/bcm/brcm,nsp.txt b/dts/Bindings/arm/bcm/brcm,nsp.txt
new file mode 100644
index 0000000..eae53e4
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,nsp.txt
@@ -0,0 +1,34 @@
+Broadcom Northstar Plus device tree bindings
+--------------------------------------------
+
+Broadcom Northstar Plus family of SoCs are used for switching control
+and management applications as well as residential router/gateway
+applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
+several peripheral interfaces including multiple Gigabit Ethernet PHYs,
+DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
+SATA and several other IO controllers.
+
+Boards with Northstar Plus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM58522
+compatible = "brcm,bcm58522", "brcm,nsp";
+
+BCM58525
+compatible = "brcm,bcm58525", "brcm,nsp";
+
+BCM58535
+compatible = "brcm,bcm58535", "brcm,nsp";
+
+BCM58622
+compatible = "brcm,bcm58622", "brcm,nsp";
+
+BCM58623
+compatible = "brcm,bcm58623", "brcm,nsp";
+
+BCM58625
+compatible = "brcm,bcm58625", "brcm,nsp";
+
+BCM88312
+compatible = "brcm,bcm88312", "brcm,nsp";
diff --git a/dts/Bindings/arm/coherency-fabric.txt b/dts/Bindings/arm/coherency-fabric.txt
index 8dd4661..9b5c3f6 100644
--- a/dts/Bindings/arm/coherency-fabric.txt
+++ b/dts/Bindings/arm/coherency-fabric.txt
@@ -27,6 +27,11 @@ Required properties:
* For "marvell,armada-380-coherency-fabric", only one pair is needed
for the per-CPU fabric registers.
+Optional properties:
+
+- broken-idle: boolean to set when the Idle mode is not supported by the
+ hardware.
+
Examples:
coherency-fabric@d0020200 {
diff --git a/dts/Bindings/arm/cpus.txt b/dts/Bindings/arm/cpus.txt
index 91e6e5c..3a07a87 100644
--- a/dts/Bindings/arm/cpus.txt
+++ b/dts/Bindings/arm/cpus.txt
@@ -195,6 +195,8 @@ nodes to be present and contain the properties described below.
"marvell,armada-380-smp"
"marvell,armada-390-smp"
"marvell,armada-xp-smp"
+ "mediatek,mt6589-smp"
+ "mediatek,mt81xx-tz-smp"
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
diff --git a/dts/Bindings/arm/fsl.txt b/dts/Bindings/arm/fsl.txt
index 2a3ba73..34c88b0 100644
--- a/dts/Bindings/arm/fsl.txt
+++ b/dts/Bindings/arm/fsl.txt
@@ -128,10 +128,18 @@ Example:
reg = <0x0 0x1ee0000 0x0 0x10000>;
};
-Freescale LS2085A SoC Device Tree Bindings
-------------------------------------------
+Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
+----------------------------------------------------------------
-LS2085A ARMv8 based Simulator model
+LS2080A ARMv8 based Simulator model
Required root node properties:
- - compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
+ - compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
+
+LS2080A ARMv8 based QDS Board
+Required root node properties:
+ - compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
+
+LS2080A ARMv8 based RDB Board
+Required root node properties:
+ - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt
index c733e28..6ac7c00 100644
--- a/dts/Bindings/arm/hisilicon/hisilicon.txt
+++ b/dts/Bindings/arm/hisilicon/hisilicon.txt
@@ -20,6 +20,10 @@ HiKey Board
Required root node properties:
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+HiP05 D02 Board
+Required root node properties:
+ - compatible = "hisilicon,hip05-d02";
+
Hisilicon system controller
Required properties:
@@ -167,6 +171,23 @@ Example:
};
-----------------------------------------------------------------------
+Hisilicon HiP05 PCIe-SAS system controller
+
+Required properties:
+- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
+HiP05 Soc to implement some basic configurations.
+
+Example:
+ /* for HiP05 PCIe-SAS system */
+ pcie_sas: system_controller@0xb0000000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+ reg = <0xb0000000 0x10000>;
+ };
+
+-----------------------------------------------------------------------
Hisilicon CPU controller
Required properties:
diff --git a/dts/Bindings/arm/keystone/keystone.txt b/dts/Bindings/arm/keystone/keystone.txt
index 59d7a46..3090a8a 100644
--- a/dts/Bindings/arm/keystone/keystone.txt
+++ b/dts/Bindings/arm/keystone/keystone.txt
@@ -9,12 +9,26 @@ Required properties:
the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
type UART should use the specified compatible for those devices.
+SoC families:
+
+- Keystone 2 generic SoC:
+ compatible = "ti,keystone"
+
+SoCs:
+
+- Keystone 2 Hawking/Kepler
+ compatible = "ti,k2hk", "ti,keystone"
+- Keystone 2 Lamarr
+ compatible = "ti,k2l", "ti,keystone"
+- Keystone 2 Edison
+ compatible = "ti,k2e", "ti,keystone"
+
Boards:
- Keystone 2 Hawking/Kepler EVM
- compatible = "ti,k2hk-evm","ti,keystone"
+ compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"
- Keystone 2 Lamarr EVM
- compatible = "ti,k2l-evm","ti,keystone"
+ compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone"
- Keystone 2 Edison EVM
- compatible = "ti,k2e-evm","ti,keystone"
+ compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"
diff --git a/dts/Bindings/arm/mediatek/mediatek,imgsys.txt b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
new file mode 100644
index 0000000..b1f2ce1
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
@@ -0,0 +1,22 @@
+Mediatek imgsys controller
+============================
+
+The Mediatek imgsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-imgsys", "syscon"
+- #clock-cells: Must be 1
+
+The imgsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+imgsys: clock-controller@15000000 {
+ compatible = "mediatek,mt8173-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.txt b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
new file mode 100644
index 0000000..4385946
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.txt
@@ -0,0 +1,22 @@
+Mediatek mmsys controller
+============================
+
+The Mediatek mmsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-mmsys", "syscon"
+- #clock-cells: Must be 1
+
+The mmsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+mmsys: clock-controller@14000000 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
new file mode 100644
index 0000000..1faacf1
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -0,0 +1,22 @@
+Mediatek vdecsys controller
+============================
+
+The Mediatek vdecsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-vdecsys", "syscon"
+- #clock-cells: Must be 1
+
+The vdecsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+vdecsys: clock-controller@16000000 {
+ compatible = "mediatek,mt8173-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mediatek/mediatek,vencltsys.txt b/dts/Bindings/arm/mediatek/mediatek,vencltsys.txt
new file mode 100644
index 0000000..3cc299f
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,vencltsys.txt
@@ -0,0 +1,22 @@
+Mediatek vencltsys controller
+============================
+
+The Mediatek vencltsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-vencltsys", "syscon"
+- #clock-cells: Must be 1
+
+The vencltsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+vencltsys: clock-controller@19000000 {
+ compatible = "mediatek,mt8173-vencltsys", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mediatek/mediatek,vencsys.txt b/dts/Bindings/arm/mediatek/mediatek,vencsys.txt
new file mode 100644
index 0000000..5bb2866a
--- /dev/null
+++ b/dts/Bindings/arm/mediatek/mediatek,vencsys.txt
@@ -0,0 +1,22 @@
+Mediatek vencsys controller
+============================
+
+The Mediatek vencsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt8173-vencsys", "syscon"
+- #clock-cells: Must be 1
+
+The vencsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+vencsys: clock-controller@18000000 {
+ compatible = "mediatek,mt8173-vencsys", "syscon";
+ reg = <0 0x18000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/dts/Bindings/arm/mvebu-cpu-config.txt b/dts/Bindings/arm/mvebu-cpu-config.txt
new file mode 100644
index 0000000..2cdcd71
--- /dev/null
+++ b/dts/Bindings/arm/mvebu-cpu-config.txt
@@ -0,0 +1,20 @@
+MVEBU CPU Config registers
+--------------------------
+
+MVEBU (Marvell SOCs: Armada 370/XP)
+
+Required properties:
+
+- compatible: one of:
+ - "marvell,armada-370-cpu-config"
+ - "marvell,armada-xp-cpu-config"
+
+- reg: Should contain CPU config registers location and length, in
+ their per-CPU variant
+
+Example:
+
+ cpu-config@21000 {
+ compatible = "marvell,armada-xp-cpu-config";
+ reg = <0x21000 0x8>;
+ };
diff --git a/dts/Bindings/arm/pmu.txt b/dts/Bindings/arm/pmu.txt
index 435251f..97ba45a 100644
--- a/dts/Bindings/arm/pmu.txt
+++ b/dts/Bindings/arm/pmu.txt
@@ -7,7 +7,10 @@ representation in the device tree should be done as under:-
Required properties:
- compatible : should be one of
+ "apm,potenza-pmu"
"arm,armv8-pmuv3"
+ "arm.cortex-a57-pmu"
+ "arm.cortex-a53-pmu"
"arm,cortex-a17-pmu"
"arm,cortex-a15-pmu"
"arm,cortex-a12-pmu"
diff --git a/dts/Bindings/arm/psci.txt b/dts/Bindings/arm/psci.txt
index 5aa40ed..a9adab8 100644
--- a/dts/Bindings/arm/psci.txt
+++ b/dts/Bindings/arm/psci.txt
@@ -31,6 +31,10 @@ Main node required properties:
support, but are permitted to be present for compatibility with
existing software when "arm,psci" is later in the compatible list.
+ * "arm,psci-1.0" : for implementations complying to PSCI 1.0. PSCI 1.0 is
+ backward compatible with PSCI 0.2 with minor specification updates,
+ as defined in the PSCI specification[2].
+
- method : The method of calling the PSCI firmware. Permitted
values are:
@@ -100,3 +104,5 @@ Case 3: PSCI v0.2 and PSCI v0.1.
[1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.txt
+[2] Power State Coordination Interface (PSCI) specification
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index af58cd7..8e985dd 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -17,6 +17,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "radxa,rock", "rockchip,rk3188";
+- Radxa Rock2 Square board:
+ Required root node properties:
+ - compatible = "radxa,rock2-square", "rockchip,rk3288";
+
- Firefly Firefly-RK3288 board:
Required root node properties:
- compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
@@ -31,6 +35,13 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "netxeon,r89", "rockchip,rk3288";
+- Google Jaq (Haier Chromebook 11 and more):
+ Required root node properties:
+ - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
+ "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
+ "google,veyron-jaq-rev1", "google,veyron-jaq",
+ "google,veyron", "rockchip,rk3288";
+
- Google Jerry (Hisense Chromebook C11 and more):
Required root node properties:
- compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
diff --git a/dts/Bindings/arm/samsung-boards.txt b/dts/Bindings/arm/samsung-boards.txt
deleted file mode 100644
index 43589d2..0000000
--- a/dts/Bindings/arm/samsung-boards.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Samsung's Exynos SoC based boards
-
-Required root node properties:
- - compatible = should be one or more of the following.
- - "samsung,monk" - for Exynos3250-based Samsung Simband board.
- - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
- - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
- - "samsung,trats" - for Exynos4210-based Tizen Reference board.
- - "samsung,universal_c210" - for Exynos4210-based Samsung board.
- - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
- - "samsung,trats2" - for Exynos4412-based Tizen Reference board.
- - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
- - "samsung,xyref5260" - for Exynos5260-based Samsung board.
- - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
- - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
- - "samsung,sd5v1" - for Exynos5440-based Samsung board.
- - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
-
-Optional:
- - firmware node, specifying presence and type of secure firmware:
- - compatible: only "samsung,secure-firmware" is currently supported
- - reg: address of non-secure SYSRAM used for communication with firmware
-
- firmware@0203F000 {
- compatible = "samsung,secure-firmware";
- reg = <0x0203F000 0x1000>;
- };
diff --git a/dts/Bindings/arm/samsung/samsung-boards.txt b/dts/Bindings/arm/samsung/samsung-boards.txt
new file mode 100644
index 0000000..12129c0
--- /dev/null
+++ b/dts/Bindings/arm/samsung/samsung-boards.txt
@@ -0,0 +1,69 @@
+* Samsung's Exynos SoC based boards
+
+Required root node properties:
+ - compatible = should be one or more of the following.
+ - "samsung,monk" - for Exynos3250-based Samsung Simband board.
+ - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
+ - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
+ - "samsung,trats" - for Exynos4210-based Tizen Reference board.
+ - "samsung,universal_c210" - for Exynos4210-based Samsung board.
+ - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
+ - "samsung,trats2" - for Exynos4412-based Tizen Reference board.
+ - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
+ - "samsung,xyref5260" - for Exynos5260-based Samsung board.
+ - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
+ - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
+ - "samsung,sd5v1" - for Exynos5440-based Samsung board.
+ - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
+
+* Other companies Exynos SoC based
+ * FriendlyARM
+ - "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
+ TINY4412 board.
+
+ * Google
+ - "google,pi" - for Exynos5800-based Google Peach Pi
+ Rev 10+ board,
+ also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14",
+ "google,pi-rev13", "google,pi-rev12", "google,pi-rev11",
+ "google,pi-rev10", "google,peach".
+
+ - "google,pit" - for Exynos5420-based Google Peach Pit
+ Rev 6+ (Exynos5420),
+ also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14",
+ "google,pit-rev13", "google,pit-rev12", "google,pit-rev11",
+ "google,pit-rev10", "google,pit-rev9", "google,pit-rev8",
+ "google,pit-rev7", "google,pit-rev6", "google,peach".
+
+ - "google,snow-rev4" - for Exynos5250-based Google Snow board,
+ also: "google,snow"
+ - "google,snow-rev5" - for Exynos5250-based Google Snow
+ Rev 5+ board.
+ - "google,spring" - for Exynos5250-based Google Spring board.
+
+ * Hardkernel
+ - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
+ - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
+ - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
+ - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
+ - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
+ Odroid XU3 Lite board.
+ - "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4.
+
+ * Insignal
+ - "insignal,arndale" - for Exynos5250-based Insignal Arndale board.
+ - "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale
+ Octa board.
+ - "insignal,origen" - for Exynos4210-based Insignal Origen board.
+ - "insignal,origen4412 - for Exynos4412-based Insignal Origen board.
+
+
+Optional nodes:
+ - firmware node, specifying presence and type of secure firmware:
+ - compatible: only "samsung,secure-firmware" is currently supported
+ - reg: address of non-secure SYSRAM used for communication with firmware
+
+ firmware@0203F000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0203F000 0x1000>;
+ };
diff --git a/dts/Bindings/arm/shmobile.txt b/dts/Bindings/arm/shmobile.txt
index c4f19b2..40bb900 100644
--- a/dts/Bindings/arm/shmobile.txt
+++ b/dts/Bindings/arm/shmobile.txt
@@ -39,8 +39,6 @@ Boards:
compatible = "renesas,armadillo800eva"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- - BOCK-W - Reference Device Tree Implementation
- compatible = "renesas,bockw-reference", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- Gose
@@ -57,7 +55,7 @@ Boards:
compatible = "renesas,lager", "renesas,r8a7790"
- Marzen
compatible = "renesas,marzen", "renesas,r8a7779"
-
-Note: Reference Device Tree Implementations are temporary implementations
- to ease the migration from platform devices to Device Tree, and are
- intended to be removed in the future.
+ - Porter (M2-LCDP)
+ compatible = "renesas,porter", "renesas,r8a7791"
+ - SILK (RTP0RC7794LCB00011S)
+ compatible = "renesas,silk", "renesas,r8a7794"
diff --git a/dts/Bindings/arm/sunxi.txt b/dts/Bindings/arm/sunxi.txt
index 67da205..bb9b0fa 100644
--- a/dts/Bindings/arm/sunxi.txt
+++ b/dts/Bindings/arm/sunxi.txt
@@ -6,6 +6,7 @@ using one of the following compatible strings:
allwinner,sun4i-a10
allwinner,sun5i-a10s
allwinner,sun5i-a13
+ allwinner,sun5i-r8
allwinner,sun6i-a31
allwinner,sun7i-a20
allwinner,sun8i-a23
diff --git a/dts/Bindings/nvec/nvidia,nvec.txt b/dts/Bindings/arm/tegra/nvidia,nvec.txt
index 5ae601e..5ae601e 100644
--- a/dts/Bindings/nvec/nvidia,nvec.txt
+++ b/dts/Bindings/arm/tegra/nvidia,nvec.txt
diff --git a/dts/Bindings/arm/twd.txt b/dts/Bindings/arm/twd.txt
index 75b8610..383ea19 100644
--- a/dts/Bindings/arm/twd.txt
+++ b/dts/Bindings/arm/twd.txt
@@ -19,6 +19,11 @@ interrupts.
- reg : Specify the base address and the size of the TWD timer
register window.
+Optional
+
+- always-on : a boolean property. If present, the timer is powered through
+ an always-on power domain, therefore it never loses context.
+
Example:
twd-timer@2c000600 {
diff --git a/dts/Bindings/arm/uniphier/cache-uniphier.txt b/dts/Bindings/arm/uniphier/cache-uniphier.txt
new file mode 100644
index 0000000..d27a646
--- /dev/null
+++ b/dts/Bindings/arm/uniphier/cache-uniphier.txt
@@ -0,0 +1,60 @@
+UniPhier outer cache controller
+
+UniPhier SoCs are integrated with a full-custom outer cache controller system.
+All of them have a level 2 cache controller, and some have a level 3 cache
+controller as well.
+
+Required properties:
+- compatible: should be "socionext,uniphier-system-cache"
+- reg: offsets and lengths of the register sets for the device. It should
+ contain 3 regions: control register, revision register, operation register,
+ in this order.
+- cache-unified: specifies the cache is a unified cache.
+- cache-size: specifies the size in bytes of the cache
+- cache-sets: specifies the number of associativity sets of the cache
+- cache-line-size: specifies the line size in bytes
+- cache-level: specifies the level in the cache hierarchy. The value should
+ be 2 for L2 cache, 3 for L3 cache, etc.
+
+Optional properties:
+- next-level-cache: phandle to the next level cache if present. The next level
+ cache should be also compatible with "socionext,uniphier-system-cache".
+
+The L2 cache must exist to use the L3 cache; the cache hierarchy must be
+indicated correctly with "next-level-cache" properties.
+
+Example 1 (system with L2):
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+ <0x506c0000 0x400>;
+ cache-unified;
+ cache-size = <0x80000>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
+Example 2 (system with L2 and L3):
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+ <0x506c0000 0x400>;
+ cache-unified;
+ cache-size = <0x200000>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ next-level-cache = <&l3>;
+ };
+
+ l3: l3-cache@500c8000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
+ <0x506c8000 0x400>;
+ cache-unified;
+ cache-size = <0x400000>;
+ cache-sets = <512>;
+ cache-line-size = <256>;
+ cache-level = <3>;
+ };
diff --git a/dts/Bindings/ata/ahci-fsl-qoriq.txt b/dts/Bindings/ata/ahci-fsl-qoriq.txt
new file mode 100644
index 0000000..032a760
--- /dev/null
+++ b/dts/Bindings/ata/ahci-fsl-qoriq.txt
@@ -0,0 +1,21 @@
+Binding for Freescale QorIQ AHCI SATA Controller
+
+Required properties:
+ - reg: Physical base address and size of the controller's register area.
+ - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
+ chip could be ls1021a, ls2080a, ls1043a etc.
+ - clocks: Input clock specifier. Refer to common clock bindings.
+ - interrupts: Interrupt specifier. Refer to interrupt binding.
+
+Optional properties:
+ - dma-coherent: Enable AHCI coherent DMA operation.
+ - reg-names: register area names when there are more than 1 register area.
+
+Examples:
+ sata@3200000 {
+ compatible = "fsl,ls1021a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ dma-coherent;
+ };
diff --git a/dts/Bindings/ata/ahci-platform.txt b/dts/Bindings/ata/ahci-platform.txt
index a232181..c2340ee 100644
--- a/dts/Bindings/ata/ahci-platform.txt
+++ b/dts/Bindings/ata/ahci-platform.txt
@@ -16,8 +16,6 @@ Required properties:
- "snps,dwc-ahci"
- "snps,exynos5440-ahci"
- "snps,spear-ahci"
- - "fsl,qoriq-ahci" : for qoriq series socs which include ls1021, ls2085, etc.
- - "fsl,<chip>-ahci" : chip could be ls1021, ls2085 etc.
- "generic-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
diff --git a/dts/Bindings/powerpc/fsl/board.txt b/dts/Bindings/board/fsl-board.txt
index cff38bd..fb7b03e 100644
--- a/dts/Bindings/powerpc/fsl/board.txt
+++ b/dts/Bindings/board/fsl-board.txt
@@ -21,11 +21,14 @@ Example:
This is the memory-mapped registers for on board FPGA.
-Required properities:
+Required properties:
- compatible: should be a board-specific string followed by a string
indicating the type of FPGA. Example:
- "fsl,<board>-fpga", "fsl,fpga-pixis"
+ "fsl,<board>-fpga", "fsl,fpga-pixis", or
+ "fsl,<board>-fpga", "fsl,fpga-qixis"
- reg: should contain the address and the length of the FPGA register set.
+
+Optional properties:
- interrupt-parent: should specify phandle for the interrupt controller.
- interrupts: should specify event (wakeup) IRQ.
@@ -38,6 +41,13 @@ Example (P1022DS):
interrupts = <8 8 0 0>;
};
+Example (LS2080A-RDB):
+
+ cpld@3,0 {
+ compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
+ reg = <0x3 0 0x10000>;
+ };
+
* Freescale BCSR GPIO banks
Some BCSR registers act as simple GPIO controllers, each such
diff --git a/dts/Bindings/bus/sunxi-rsb.txt b/dts/Bindings/bus/sunxi-rsb.txt
new file mode 100644
index 0000000..3dd2834
--- /dev/null
+++ b/dts/Bindings/bus/sunxi-rsb.txt
@@ -0,0 +1,47 @@
+Allwinner Reduced Serial Bus (RSB) controller
+
+The RSB controller found on later Allwinner SoCs is an SMBus like 2 wire
+serial bus with 1 master and up to 15 slaves. It is represented by a node
+for the controller itself, and child nodes representing the slave devices.
+
+Required properties :
+
+ - reg : Offset and length of the register set for the controller.
+ - compatible : Shall be "allwinner,sun8i-a23-rsb".
+ - interrupts : The interrupt line associated to the RSB controller.
+ - clocks : The gate clk associated to the RSB controller.
+ - resets : The reset line associated to the RSB controller.
+ - #address-cells : shall be 1
+ - #size-cells : shall be 0
+
+Optional properties :
+
+ - clock-frequency : Desired RSB bus clock frequency in Hz. Maximum is 20MHz.
+ If not set this defaults to 3MHz.
+
+Child nodes:
+
+An RSB controller node can contain zero or more child nodes representing
+slave devices on the bus. Child 'reg' properties should contain the slave
+device's hardware address. The hardware address is hardwired in the device,
+which can normally be found in the datasheet.
+
+Example:
+
+ rsb@01f03400 {
+ compatible = "allwinner,sun8i-a23-rsb";
+ reg = <0x01f03400 0x400>;
+ interrupts = <0 39 4>;
+ clocks = <&apb0_gates 3>;
+ clock-frequency = <3000000>;
+ resets = <&apb0_rst 3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@3e3 {
+ compatible = "...";
+ reg = <0x3e3>;
+
+ /* ... */
+ };
+ };
diff --git a/dts/Bindings/chosen.txt b/dts/Bindings/chosen.txt
index ed838f4..6ae9d82 100644
--- a/dts/Bindings/chosen.txt
+++ b/dts/Bindings/chosen.txt
@@ -44,3 +44,11 @@ Implementation note: Linux will look for the property "linux,stdout-path" or
on PowerPC "stdout" if "stdout-path" is not found. However, the
"linux,stdout-path" and "stdout" properties are deprecated. New platforms
should only use the "stdout-path" property.
+
+linux,booted-from-kexec
+-----------------------
+
+This property is set (currently only on PowerPC, and only needed on
+book3e) by some versions of kexec-tools to tell the new kernel that it
+is being booted by kexec, as the booting environment may differ (e.g.
+a different secondary CPU release mechanism)
diff --git a/dts/Bindings/clock/at91-clock.txt b/dts/Bindings/clock/at91-clock.txt
index 5ba6450..181bc8a 100644
--- a/dts/Bindings/clock/at91-clock.txt
+++ b/dts/Bindings/clock/at91-clock.txt
@@ -77,6 +77,9 @@ Required properties:
"atmel,sama5d4-clk-h32mx":
at91 h32mx clock
+ "atmel,sama5d2-clk-generated":
+ at91 generated clock
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
@@ -461,3 +464,35 @@ For example:
compatible = "atmel,sama5d4-clk-h32mx";
clocks = <&mck>;
};
+
+Required properties for generated clocks:
+- #size-cells : shall be 0 (reg is used to encode clk id).
+- #address-cells : shall be 1 (reg is used to encode clk id).
+- clocks : shall be the generated clock source phandles.
+ e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
+- name: device tree node describing a specific generated clock.
+ * #clock-cells : from common clock binding; shall be set to 0.
+ * reg: peripheral id. See Atmel's datasheets to get a full
+ list of peripheral ids.
+ * atmel,clk-output-range : minimum and maximum clock frequency
+ (two u32 fields).
+
+For example:
+ gck {
+ compatible = "atmel,sama5d2-clk-generated";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
+
+ tcb0_gclk: tcb0_gclk {
+ #clock-cells = <0>;
+ reg = <35>;
+ atmel,clk-output-range = <0 83000000>;
+ };
+
+ pwm_gclk: pwm_gclk {
+ #clock-cells = <0>;
+ reg = <38>;
+ atmel,clk-output-range = <0 83000000>;
+ };
+ };
diff --git a/dts/Bindings/clock/brcm,bcm2835-cprman.txt b/dts/Bindings/clock/brcm,bcm2835-cprman.txt
new file mode 100644
index 0000000..e56a1df
--- /dev/null
+++ b/dts/Bindings/clock/brcm,bcm2835-cprman.txt
@@ -0,0 +1,45 @@
+Broadcom BCM2835 CPRMAN clocks
+
+This binding uses the common clock binding:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CPRMAN clock controller generates clocks in the audio power domain
+of the BCM2835. There is a level of PLLs deriving from an external
+oscillator, a level of PLL dividers that produce channels off of the
+few PLLs, and a level of mostly-generic clock generators sourcing from
+the PLL channels. Most other hardware components source from the
+clock generators, but a few (like the ARM or HDMI) will source from
+the PLL dividers directly.
+
+Required properties:
+- compatible: Should be "brcm,bcm2835-cprman"
+- #clock-cells: Should be <1>. The permitted clock-specifier values can be
+ found in include/dt-bindings/clock/bcm2835.h
+- reg: Specifies base physical address and size of the registers
+- clocks: The external oscillator clock phandle
+
+Example:
+
+ clk_osc: clock@3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ #clock-cells = <0>;
+ clock-output-names = "osc";
+ clock-frequency = <19200000>;
+ };
+
+ clocks: cprman@7e101000 {
+ compatible = "brcm,bcm2835-cprman";
+ #clock-cells = <1>;
+ reg = <0x7e101000 0x2000>;
+ clocks = <&clk_osc>;
+ };
+
+ i2c0: i2c@7e205000 {
+ compatible = "brcm,bcm2835-i2c";
+ reg = <0x7e205000 0x1000>;
+ interrupts = <2 21>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/Bindings/clock/brcm,iproc-clocks.txt b/dts/Bindings/clock/brcm,iproc-clocks.txt
index da8d9bb..ede65a5 100644
--- a/dts/Bindings/clock/brcm,iproc-clocks.txt
+++ b/dts/Bindings/clock/brcm,iproc-clocks.txt
@@ -130,3 +130,81 @@ These clock IDs are defined in:
ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
+
+Northstar and Northstar Plus
+------
+PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
+ "brcm,nsp-armpll"
+ "brcm,nsp-genpll"
+ "brcm,nsp-lcpll0"
+
+The following table defines the set of PLL/clock index and ID for Northstar and
+Northstar Plus. These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-nsp.h"
+
+ Clock Source Index ID
+ --- ----- ----- ---------
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+
+ genpll crystal 0 BCM_NSP_GENPLL
+ phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
+ ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
+ usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
+ iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
+ sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
+ sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
+
+ lcpll0 crystal 0 BCM_NSP_LCPLL0
+ pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
+ sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
+ ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
+
+Northstar 2
+-----------
+PLL and leaf clock compatible strings for Northstar 2 are:
+ "brcm,ns2-genpll-scr"
+ "brcm,ns2-genpll-sw"
+ "brcm,ns2-lcpll-ddr"
+ "brcm,ns2-lcpll-ports"
+
+The following table defines the set of PLL/clock index and ID for Northstar 2.
+These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-ns2.h"
+
+ Clock Source Index ID
+ --- ----- ----- ---------
+ crystal N/A N/A N/A
+
+ genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
+ scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
+ fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
+ audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
+ ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
+ ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
+ ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
+
+ genpll_sw crystal 0 BCM_NS2_GENPLL_SW
+ rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
+ 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
+ nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
+ chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
+ port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
+ sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
+
+ lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
+ pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
+ ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
+ ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
+ ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
+ ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
+ ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
+
+ lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
+ wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
+ rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
+ ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
+ ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
+ ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
+ ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
diff --git a/dts/Bindings/clock/qcom,gcc.txt b/dts/Bindings/clock/qcom,gcc.txt
index 54c23f3..152dfaa 100644
--- a/dts/Bindings/clock/qcom,gcc.txt
+++ b/dts/Bindings/clock/qcom,gcc.txt
@@ -18,10 +18,14 @@ Required properties :
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
+Optional properties :
+- #power-domain-cells : shall contain 1
+
Example:
clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
};
diff --git a/dts/Bindings/clock/qcom,mmcc.txt b/dts/Bindings/clock/qcom,mmcc.txt
index 29ebf84..34e7614 100644
--- a/dts/Bindings/clock/qcom,mmcc.txt
+++ b/dts/Bindings/clock/qcom,mmcc.txt
@@ -14,10 +14,14 @@ Required properties :
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
+Optional properties :
+- #power-domain-cells : shall contain 1
+
Example:
clock-controller@4000000 {
compatible = "qcom,mmcc-msm8960";
reg = <0x4000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
};
diff --git a/dts/Bindings/clock/qoriq-clock.txt b/dts/Bindings/clock/qoriq-clock.txt
index df4a259..16a3ec4 100644
--- a/dts/Bindings/clock/qoriq-clock.txt
+++ b/dts/Bindings/clock/qoriq-clock.txt
@@ -1,6 +1,6 @@
* Clock Block on Freescale QorIQ Platforms
-Freescale qoriq chips take primary clocking input from the external
+Freescale QorIQ chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
@@ -13,14 +13,16 @@ which the chip complies.
Chassis Version Example Chips
--------------- -------------
1.0 p4080, p5020, p5040
-2.0 t4240, b4860, t1040
+2.0 t4240, b4860
1. Clock Block Binding
Required properties:
-- compatible: Should contain a specific clock block compatible string
- and a single chassis clock compatible string.
- Clock block strings include, but not limited to, one of the:
+- compatible: Should contain a chip-specific clock block compatible
+ string and (if applicable) may contain a chassis-version clock
+ compatible string.
+
+ Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
* "fsl,p2041-clockgen"
* "fsl,p3041-clockgen"
* "fsl,p4080-clockgen"
@@ -30,15 +32,14 @@ Required properties:
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
* "fsl,ls1021a-clockgen"
- Chassis clock strings include:
+ Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
- reg: Describes the address of the device's resources within the
address space defined by its parent bus, and resource zero
represents the clock register set
-- clock-frequency: Input system clock frequency
-Recommended properties:
+Optional properties:
- ranges: Allows valid translation between child's address space and
parent's. Must be present if the device has sub-nodes.
- #address-cells: Specifies the number of cells used to represent
@@ -47,8 +48,46 @@ Recommended properties:
- #size-cells: Specifies the number of cells used to represent
the size of an address. Must be present if the device has
sub-nodes and set to 1 if present
+- clock-frequency: Input system clock frequency (SYSCLK)
+- clocks: If clock-frequency is not specified, sysclk may be provided
+ as an input clock. Either clock-frequency or clocks must be
+ provided.
+
+2. Clock Provider
+
+The clockgen node should act as a clock provider, though in older device
+trees the children of the clockgen node are the clock providers.
+
+When the clockgen node is a clock provider, #clock-cells = <2>.
+The first cell of the clock specifier is the clock type, and the
+second cell is the clock index for the specified type.
+
+ Type# Name Index Cell
+ 0 sysclk must be 0
+ 1 cmux index (n in CLKCnCSR)
+ 2 hwaccel index (n in CLKCGnHWACSR)
+ 3 fman 0 for fm1, 1 for fm2
+ 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+
+3. Example
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+ clock-frequency = <133333333>;
+ reg = <0xe1000 0x1000>;
+ #clock-cells = <2>;
+ };
+
+ fman@400000 {
+ ...
+ clocks = <&clockgen 3 0>;
+ ...
+ };
+}
+4. Legacy Child Nodes
-2. Clock Provider/Consumer Binding
+NOTE: These nodes are deprecated. Kernels should continue to support
+device trees with these nodes, but new device trees should not use them.
Most of the bindings are from the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -82,7 +121,7 @@ Recommended properties:
- reg: Should be the offset and length of clock block base address.
The length should be 4.
-Example for clock block and clock provider:
+Legacy Example:
/ {
clockgen: global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
@@ -142,7 +181,7 @@ Example for clock block and clock provider:
};
};
-Example for clock consumer:
+Example for legacy clock consumer:
/ {
cpu0: PowerPC,e5500@0 {
diff --git a/dts/Bindings/clock/renesas,cpg-div6-clocks.txt b/dts/Bindings/clock/renesas,cpg-div6-clocks.txt
index 5ddb684..38dcf03 100644
--- a/dts/Bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/dts/Bindings/clock/renesas,cpg-div6-clocks.txt
@@ -1,7 +1,7 @@
* Renesas CPG DIV6 Clock
The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
-Generator (CPG). They clock input is divided by a configurable factor from 1
+Generator (CPG). Their clock input is divided by a configurable factor from 1
to 64.
Required Properties:
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.txt b/dts/Bindings/clock/renesas,cpg-mssr.txt
new file mode 100644
index 0000000..59297d3
--- /dev/null
+++ b/dts/Bindings/clock/renesas,cpg-mssr.txt
@@ -0,0 +1,69 @@
+* Renesas Clock Pulse Generator / Module Standby and Software Reset
+
+On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
+and MSSR (Module Standby and Software Reset) blocks are intimately connected,
+and share the same register block.
+
+They provide the following functionalities:
+ - The CPG block generates various core clocks,
+ - The MSSR block provides two functions:
+ 1. Module Standby, providing a Clock Domain to control the clock supply
+ to individual SoC devices,
+ 2. Reset Control, to perform a software reset of individual SoC devices.
+
+Required Properties:
+ - compatible: Must be one of:
+ - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC
+
+ - reg: Base address and length of the memory resource used by the CPG/MSSR
+ block
+
+ - clocks: References to external parent clocks, one entry for each entry in
+ clock-names
+ - clock-names: List of external parent clock names. Valid names are:
+ - "extal" (r8a7795)
+ - "extalr" (r8a7795)
+
+ - #clock-cells: Must be 2
+ - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+ and a core clock reference, as defined in
+ <dt-bindings/clock/*-cpg-mssr.h>.
+ - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+ a module number, as defined in the datasheet.
+
+ - #power-domain-cells: Must be 0
+ - SoC devices that are part of the CPG/MSSR Clock Domain and can be
+ power-managed through Module Standby should refer to the CPG device
+ node in their "power-domains" property, as documented by the generic PM
+ Domain bindings in
+ Documentation/devicetree/bindings/power/power_domain.txt.
+
+
+Examples
+--------
+
+ - CPG device node:
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7795-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSSR Clock Domain member device node:
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a7795", "renesas,scif";
+ reg = <0 0xe6e88000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>;
+ clock-names = "sci_ick";
+ dmas = <&dmac1 0x13>, <&dmac1 0x12>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/clock/silabs,si514.txt b/dts/Bindings/clock/silabs,si514.txt
new file mode 100644
index 0000000..ea1a9db
--- /dev/null
+++ b/dts/Bindings/clock/silabs,si514.txt
@@ -0,0 +1,24 @@
+Binding for Silicon Labs 514 programmable I2C clock generator.
+
+Reference
+This binding uses the common clock binding[1]. Details about the device can be
+found in the datasheet[2].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Si514 datasheet
+ http://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
+
+Required properties:
+ - compatible: Shall be "silabs,si514"
+ - reg: I2C device address.
+ - #clock-cells: From common clock bindings: Shall be 0.
+
+Optional properties:
+ - clock-output-names: From common clock bindings. Recommended to be "si514".
+
+Example:
+ si514: clock-generator@55 {
+ reg = <0x55>;
+ #clock-cells = <0>;
+ compatible = "silabs,si514";
+ };
diff --git a/dts/Bindings/clock/st/st,clkgen-pll.txt b/dts/Bindings/clock/st/st,clkgen-pll.txt
index d8b168e..844b3a0 100644
--- a/dts/Bindings/clock/st/st,clkgen-pll.txt
+++ b/dts/Bindings/clock/st/st,clkgen-pll.txt
@@ -23,6 +23,7 @@ Required properties:
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"sst,plls-c32-cx_0", "st,clkgen-plls-c32"
"sst,plls-c32-cx_1", "st,clkgen-plls-c32"
+ "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt
index 6831d02..adeca34 100644
--- a/dts/Bindings/crypto/fsl-sec4.txt
+++ b/dts/Bindings/crypto/fsl-sec4.txt
@@ -441,7 +441,7 @@ EXAMPLE:
regmap = <&snvs>;
interrupts = <0 4 0x4>
linux,keycode = <116>; /* KEY_POWER */
- wakeup;
+ wakeup-source;
};
=====================================================================
@@ -530,7 +530,7 @@ FULL EXAMPLE
regmap = <&sec_mon>;
interrupts = <0 4 0x4>;
linux,keycode = <116>; /* KEY_POWER */
- wakeup;
+ wakeup-source;
};
};
diff --git a/dts/Bindings/video/arm,pl11x.txt b/dts/Bindings/display/arm,pl11x.txt
index 3e3039a..3e3039a 100644
--- a/dts/Bindings/video/arm,pl11x.txt
+++ b/dts/Bindings/display/arm,pl11x.txt
diff --git a/dts/Bindings/drm/armada/marvell,dove-lcd.txt b/dts/Bindings/display/armada/marvell,dove-lcd.txt
index 46525ea..46525ea 100644
--- a/dts/Bindings/drm/armada/marvell,dove-lcd.txt
+++ b/dts/Bindings/display/armada/marvell,dove-lcd.txt
diff --git a/dts/Bindings/video/atmel,lcdc.txt b/dts/Bindings/display/atmel,lcdc.txt
index ecb8da0..ecb8da0 100644
--- a/dts/Bindings/video/atmel,lcdc.txt
+++ b/dts/Bindings/display/atmel,lcdc.txt
diff --git a/dts/Bindings/drm/atmel/hlcdc-dc.txt b/dts/Bindings/display/atmel/hlcdc-dc.txt
index ebc1a91..ebc1a91 100644
--- a/dts/Bindings/drm/atmel/hlcdc-dc.txt
+++ b/dts/Bindings/display/atmel/hlcdc-dc.txt
diff --git a/dts/Bindings/display/brcm,bcm-vc4.txt b/dts/Bindings/display/brcm,bcm-vc4.txt
new file mode 100644
index 0000000..56a961a
--- /dev/null
+++ b/dts/Bindings/display/brcm,bcm-vc4.txt
@@ -0,0 +1,65 @@
+Broadcom VC4 (VideoCore4) GPU
+
+The VC4 device present on the Raspberry Pi includes a display system
+with HDMI output and the HVS (Hardware Video Scaler) for compositing
+display planes.
+
+Required properties for VC4:
+- compatible: Should be "brcm,bcm2835-vc4"
+
+Required properties for Pixel Valve:
+- compatible: Should be one of "brcm,bcm2835-pixelvalve0",
+ "brcm,bcm2835-pixelvalve1", or "brcm,bcm2835-pixelvalve2"
+- reg: Physical base address and length of the PV's registers
+- interrupts: The interrupt number
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+
+Required properties for HVS:
+- compatible: Should be "brcm,bcm2835-hvs"
+- reg: Physical base address and length of the HVS's registers
+- interrupts: The interrupt number
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+
+Required properties for HDMI
+- compatible: Should be "brcm,bcm2835-hdmi"
+- reg: Physical base address and length of the two register ranges
+ ("HDMI" and "HD", in that order)
+- interrupts: The interrupt numbers
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+- ddc: phandle of the I2C controller used for DDC EDID probing
+- clocks: a) hdmi: The HDMI state machine clock
+ b) pixel: The pixel clock.
+
+Optional properties for HDMI:
+- hpd-gpios: The GPIO pin for HDMI hotplug detect (if it doesn't appear
+ as an interrupt/status bit in the HDMI controller
+ itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt
+
+Example:
+pixelvalve@7e807000 {
+ compatible = "brcm,bcm2835-pixelvalve2";
+ reg = <0x7e807000 0x100>;
+ interrupts = <2 10>; /* pixelvalve */
+};
+
+hvs@7e400000 {
+ compatible = "brcm,bcm2835-hvs";
+ reg = <0x7e400000 0x6000>;
+ interrupts = <2 1>;
+};
+
+hdmi: hdmi@7e902000 {
+ compatible = "brcm,bcm2835-hdmi";
+ reg = <0x7e902000 0x600>,
+ <0x7e808000 0x100>;
+ interrupts = <2 8>, <2 9>;
+ ddc = <&i2c2>;
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+ clocks = <&clocks BCM2835_PLLH_PIX>,
+ <&clocks BCM2835_CLOCK_HSM>;
+ clock-names = "pixel", "hdmi";
+};
+
+vc4: gpu {
+ compatible = "brcm,bcm2835-vc4";
+};
diff --git a/dts/Bindings/video/adi,adv7123.txt b/dts/Bindings/display/bridge/adi,adv7123.txt
index a6b2b2b..a6b2b2b 100644
--- a/dts/Bindings/video/adi,adv7123.txt
+++ b/dts/Bindings/display/bridge/adi,adv7123.txt
diff --git a/dts/Bindings/video/adi,adv7511.txt b/dts/Bindings/display/bridge/adi,adv7511.txt
index 96c25ee..96c25ee 100644
--- a/dts/Bindings/video/adi,adv7511.txt
+++ b/dts/Bindings/display/bridge/adi,adv7511.txt
diff --git a/dts/Bindings/drm/bridge/dw_hdmi.txt b/dts/Bindings/display/bridge/dw_hdmi.txt
index a905c14..dc1452f 100644
--- a/dts/Bindings/drm/bridge/dw_hdmi.txt
+++ b/dts/Bindings/display/bridge/dw_hdmi.txt
@@ -14,8 +14,8 @@ Required properties:
-port@[X]: SoC specific port nodes with endpoint definitions as defined
in Documentation/devicetree/bindings/media/video-interfaces.txt,
please refer to the SoC specific binding document:
- * Documentation/devicetree/bindings/drm/imx/hdmi.txt
- * Documentation/devicetree/bindings/video/dw_hdmi-rockchip.txt
+ * Documentation/devicetree/bindings/display/imx/hdmi.txt
+ * Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
Optional properties
- reg-io-width: the width of the reg:1,4, default set to 1 if not present
diff --git a/dts/Bindings/video/bridge/ps8622.txt b/dts/Bindings/display/bridge/ps8622.txt
index c989c38..c989c38 100644
--- a/dts/Bindings/video/bridge/ps8622.txt
+++ b/dts/Bindings/display/bridge/ps8622.txt
diff --git a/dts/Bindings/video/bridge/ptn3460.txt b/dts/Bindings/display/bridge/ptn3460.txt
index 361971b..361971b 100644
--- a/dts/Bindings/video/bridge/ptn3460.txt
+++ b/dts/Bindings/display/bridge/ptn3460.txt
diff --git a/dts/Bindings/drm/i2c/tda998x.txt b/dts/Bindings/display/bridge/tda998x.txt
index e9e4bce..e9e4bce 100644
--- a/dts/Bindings/drm/i2c/tda998x.txt
+++ b/dts/Bindings/display/bridge/tda998x.txt
diff --git a/dts/Bindings/video/thine,thc63lvdm83d b/dts/Bindings/display/bridge/thine,thc63lvdm83d.txt
index 527e236..527e236 100644
--- a/dts/Bindings/video/thine,thc63lvdm83d
+++ b/dts/Bindings/display/bridge/thine,thc63lvdm83d.txt
diff --git a/dts/Bindings/video/cirrus,clps711x-fb.txt b/dts/Bindings/display/cirrus,clps711x-fb.txt
index 6fc3c6a..d685be8 100644
--- a/dts/Bindings/video/cirrus,clps711x-fb.txt
+++ b/dts/Bindings/display/cirrus,clps711x-fb.txt
@@ -6,7 +6,7 @@ Required properties:
location and size of the framebuffer memory.
- clocks : phandle + clock specifier pair of the FB reference clock.
- display : phandle to a display node as described in
- Documentation/devicetree/bindings/video/display-timing.txt.
+ Documentation/devicetree/bindings/display/display-timing.txt.
Additionally, the display node has to define properties:
- bits-per-pixel: Bits per pixel.
- ac-prescale : LCD AC bias frequency. This frequency is the required
diff --git a/dts/Bindings/video/analog-tv-connector.txt b/dts/Bindings/display/connector/analog-tv-connector.txt
index 0c0970c..0c0970c 100644
--- a/dts/Bindings/video/analog-tv-connector.txt
+++ b/dts/Bindings/display/connector/analog-tv-connector.txt
diff --git a/dts/Bindings/video/dvi-connector.txt b/dts/Bindings/display/connector/dvi-connector.txt
index fc53f7c..fc53f7c 100644
--- a/dts/Bindings/video/dvi-connector.txt
+++ b/dts/Bindings/display/connector/dvi-connector.txt
diff --git a/dts/Bindings/video/hdmi-connector.txt b/dts/Bindings/display/connector/hdmi-connector.txt
index acd5668..acd5668 100644
--- a/dts/Bindings/video/hdmi-connector.txt
+++ b/dts/Bindings/display/connector/hdmi-connector.txt
diff --git a/dts/Bindings/video/vga-connector.txt b/dts/Bindings/display/connector/vga-connector.txt
index c727f29..c727f29 100644
--- a/dts/Bindings/video/vga-connector.txt
+++ b/dts/Bindings/display/connector/vga-connector.txt
diff --git a/dts/Bindings/video/exynos-mic.txt b/dts/Bindings/display/exynos/exynos-mic.txt
index 0fba2ee..0fba2ee 100644
--- a/dts/Bindings/video/exynos-mic.txt
+++ b/dts/Bindings/display/exynos/exynos-mic.txt
diff --git a/dts/Bindings/video/exynos5433-decon.txt b/dts/Bindings/display/exynos/exynos5433-decon.txt
index 377afbf..377afbf 100644
--- a/dts/Bindings/video/exynos5433-decon.txt
+++ b/dts/Bindings/display/exynos/exynos5433-decon.txt
diff --git a/dts/Bindings/video/exynos7-decon.txt b/dts/Bindings/display/exynos/exynos7-decon.txt
index f5f9c8d..3938caa 100644
--- a/dts/Bindings/video/exynos7-decon.txt
+++ b/dts/Bindings/display/exynos/exynos7-decon.txt
@@ -38,7 +38,7 @@ Optional Properties:
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
-[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/display-timing.txt
Example:
diff --git a/dts/Bindings/video/exynos_dp.txt b/dts/Bindings/display/exynos/exynos_dp.txt
index 7a3a9cd..64693f2 100644
--- a/dts/Bindings/video/exynos_dp.txt
+++ b/dts/Bindings/display/exynos/exynos_dp.txt
@@ -50,7 +50,7 @@ Required properties for dp-controller:
number of lanes supported by the panel.
LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
- display-timings: timings for the connected panel as described by
- Documentation/devicetree/bindings/video/display-timing.txt
+ Documentation/devicetree/bindings/display/display-timing.txt
Optional properties for dp-controller:
-interlaced:
diff --git a/dts/Bindings/video/exynos_dsim.txt b/dts/Bindings/display/exynos/exynos_dsim.txt
index 0be0362..0e6f0c0 100644
--- a/dts/Bindings/video/exynos_dsim.txt
+++ b/dts/Bindings/display/exynos/exynos_dsim.txt
@@ -49,7 +49,7 @@ Video interfaces:
mode
- samsung,esc-clock-frequency: specifies DSI frequency in escape mode
-[1]: Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
diff --git a/dts/Bindings/video/exynos_hdmi.txt b/dts/Bindings/display/exynos/exynos_hdmi.txt
index 1fd8cf9..1fd8cf9 100644
--- a/dts/Bindings/video/exynos_hdmi.txt
+++ b/dts/Bindings/display/exynos/exynos_hdmi.txt
diff --git a/dts/Bindings/video/exynos_hdmiddc.txt b/dts/Bindings/display/exynos/exynos_hdmiddc.txt
index 41eee97..41eee97 100644
--- a/dts/Bindings/video/exynos_hdmiddc.txt
+++ b/dts/Bindings/display/exynos/exynos_hdmiddc.txt
diff --git a/dts/Bindings/video/exynos_hdmiphy.txt b/dts/Bindings/display/exynos/exynos_hdmiphy.txt
index 162f641..162f641 100644
--- a/dts/Bindings/video/exynos_hdmiphy.txt
+++ b/dts/Bindings/display/exynos/exynos_hdmiphy.txt
diff --git a/dts/Bindings/video/exynos_mixer.txt b/dts/Bindings/display/exynos/exynos_mixer.txt
index 3e38128..3e38128 100644
--- a/dts/Bindings/video/exynos_mixer.txt
+++ b/dts/Bindings/display/exynos/exynos_mixer.txt
diff --git a/dts/Bindings/video/samsung-fimd.txt b/dts/Bindings/display/exynos/samsung-fimd.txt
index a8bbbde..27c3ce0 100644
--- a/dts/Bindings/video/samsung-fimd.txt
+++ b/dts/Bindings/display/exynos/samsung-fimd.txt
@@ -82,7 +82,7 @@ in [2]. The following are properties specific to those nodes:
3 - for parallel output,
4 - for write-back interface
-[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/display-timing.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
diff --git a/dts/Bindings/video/fsl,dcu.txt b/dts/Bindings/display/fsl,dcu.txt
index ebf1be9..ebf1be9 100644
--- a/dts/Bindings/video/fsl,dcu.txt
+++ b/dts/Bindings/display/fsl,dcu.txt
diff --git a/dts/Bindings/video/fsl,imx-fb.txt b/dts/Bindings/display/imx/fsl,imx-fb.txt
index 8c8c2f4..00d5f8e 100644
--- a/dts/Bindings/video/fsl,imx-fb.txt
+++ b/dts/Bindings/display/imx/fsl,imx-fb.txt
@@ -9,7 +9,7 @@ Required properties:
Required nodes:
- display: Phandle to a display node as described in
- Documentation/devicetree/bindings/video/display-timing.txt
+ Documentation/devicetree/bindings/display/display-timing.txt
Additional, the display node has to define properties:
- bits-per-pixel: Bits per pixel
- fsl,pcr: LCDC PCR value
diff --git a/dts/Bindings/drm/imx/fsl-imx-drm.txt b/dts/Bindings/display/imx/fsl-imx-drm.txt
index 971c3ee..971c3ee 100644
--- a/dts/Bindings/drm/imx/fsl-imx-drm.txt
+++ b/dts/Bindings/display/imx/fsl-imx-drm.txt
diff --git a/dts/Bindings/drm/imx/hdmi.txt b/dts/Bindings/display/imx/hdmi.txt
index 1b756cf..1b756cf 100644
--- a/dts/Bindings/drm/imx/hdmi.txt
+++ b/dts/Bindings/display/imx/hdmi.txt
diff --git a/dts/Bindings/drm/imx/ldb.txt b/dts/Bindings/display/imx/ldb.txt
index 9a21366..0a175d9 100644
--- a/dts/Bindings/drm/imx/ldb.txt
+++ b/dts/Bindings/display/imx/ldb.txt
@@ -63,7 +63,7 @@ Required properties:
Optional properties (required if display-timings are used):
- display-timings : A node that describes the display timings as defined in
- Documentation/devicetree/bindings/video/display-timing.txt.
+ Documentation/devicetree/bindings/display/display-timing.txt.
- fsl,data-mapping : should be "spwg" or "jeida"
This describes how the color bits are laid out in the
serialized LVDS signal.
diff --git a/dts/Bindings/display/marvell,pxa2xx-lcdc.txt b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
new file mode 100644
index 0000000..309c47f
--- /dev/null
+++ b/dts/Bindings/display/marvell,pxa2xx-lcdc.txt
@@ -0,0 +1,34 @@
+PXA LCD Controller
+------------------
+
+Required properties:
+ - compatible : one of these
+ "marvell,pxa2xx-lcdc",
+ "marvell,pxa270-lcdc",
+ "marvell,pxa300-lcdc"
+ - reg : should contain 1 register range (address and length).
+ - interrupts : framebuffer controller interrupt.
+ - clocks: phandle to input clocks
+
+Required nodes:
+ - port: connection to the LCD panel (see video-interfaces.txt)
+ This node must have its properties bus-width and remote-endpoint set.
+ If the panel is not a TFT color panel, then a "lcd-type" property in
+ the panel should specify the panel type.
+ This panel node should be in the board dts.
+
+Example:
+ lcd-controller@40500000 {
+ compatible = "marvell,pxa2xx-lcdc";
+ reg = <0x44000000 0x10000>;
+ interrupts = <17>;
+ clocks = <&clks CLK_LCD>;
+ status = "okay";
+
+ port {
+ lcdc_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ bus-width = <16>;
+ };
+ };
+ };
diff --git a/dts/Bindings/mipi/dsi/mipi-dsi-bus.txt b/dts/Bindings/display/mipi-dsi-bus.txt
index 973c272..973c272 100644
--- a/dts/Bindings/mipi/dsi/mipi-dsi-bus.txt
+++ b/dts/Bindings/display/mipi-dsi-bus.txt
diff --git a/dts/Bindings/drm/msm/dsi.txt b/dts/Bindings/display/msm/dsi.txt
index d56923c..f344b9e 100644
--- a/dts/Bindings/drm/msm/dsi.txt
+++ b/dts/Bindings/display/msm/dsi.txt
@@ -28,7 +28,7 @@ Required properties:
Optional properties:
- panel@0: Node of panel connected to this DSI controller.
- See files in Documentation/devicetree/bindings/panel/ for each supported
+ See files in Documentation/devicetree/bindings/display/panel/ for each supported
panel.
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
driving a panel which needs 2 DSI links.
diff --git a/dts/Bindings/drm/msm/edp.txt b/dts/Bindings/display/msm/edp.txt
index 3a20f6e..3a20f6e 100644
--- a/dts/Bindings/drm/msm/edp.txt
+++ b/dts/Bindings/display/msm/edp.txt
diff --git a/dts/Bindings/drm/msm/gpu.txt b/dts/Bindings/display/msm/gpu.txt
index 67d0a58..67d0a58 100644
--- a/dts/Bindings/drm/msm/gpu.txt
+++ b/dts/Bindings/display/msm/gpu.txt
diff --git a/dts/Bindings/drm/msm/hdmi.txt b/dts/Bindings/display/msm/hdmi.txt
index e926239..379ee2e 100644
--- a/dts/Bindings/drm/msm/hdmi.txt
+++ b/dts/Bindings/display/msm/hdmi.txt
@@ -2,6 +2,7 @@ Qualcomm adreno/snapdragon hdmi output
Required properties:
- compatible: one of the following
+ * "qcom,hdmi-tx-8996"
* "qcom,hdmi-tx-8994"
* "qcom,hdmi-tx-8084"
* "qcom,hdmi-tx-8974"
@@ -21,6 +22,7 @@ Required properties:
Optional properties:
- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
+- power-domains: reference to the power domain(s), if available.
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-1: the "sleep" pinctrl state
@@ -35,6 +37,7 @@ Example:
reg-names = "core_physical";
reg = <0x04a00000 0x1000>;
interrupts = <GIC_SPI 79 0>;
+ power-domains = <&mmcc MDSS_GDSC>;
clock-names =
"core_clk",
"master_iface_clk",
diff --git a/dts/Bindings/drm/msm/mdp.txt b/dts/Bindings/display/msm/mdp.txt
index 1a0598e..0833eda 100644
--- a/dts/Bindings/drm/msm/mdp.txt
+++ b/dts/Bindings/display/msm/mdp.txt
@@ -11,13 +11,14 @@ Required properties:
- clock-names: the following clocks are required:
* "core_clk"
* "iface_clk"
- * "lut_clk"
* "src_clk"
* "hdmi_clk"
* "mpd_clk"
Optional properties:
- gpus: phandle for gpu device
+- clock-names: the following clocks are optional:
+ * "lut_clk"
Example:
diff --git a/dts/Bindings/fb/mxsfb.txt b/dts/Bindings/display/mxsfb.txt
index 96ec517..96ec517 100644
--- a/dts/Bindings/fb/mxsfb.txt
+++ b/dts/Bindings/display/mxsfb.txt
diff --git a/dts/Bindings/panel/ampire,am800480r3tmqwa1h.txt b/dts/Bindings/display/panel/ampire,am800480r3tmqwa1h.txt
index 83e2cae..83e2cae 100644
--- a/dts/Bindings/panel/ampire,am800480r3tmqwa1h.txt
+++ b/dts/Bindings/display/panel/ampire,am800480r3tmqwa1h.txt
diff --git a/dts/Bindings/panel/auo,b080uan01.txt b/dts/Bindings/display/panel/auo,b080uan01.txt
index bae0e2b..bae0e2b 100644
--- a/dts/Bindings/panel/auo,b080uan01.txt
+++ b/dts/Bindings/display/panel/auo,b080uan01.txt
diff --git a/dts/Bindings/panel/auo,b101aw03.txt b/dts/Bindings/display/panel/auo,b101aw03.txt
index 72e088a..72e088a 100644
--- a/dts/Bindings/panel/auo,b101aw03.txt
+++ b/dts/Bindings/display/panel/auo,b101aw03.txt
diff --git a/dts/Bindings/panel/auo,b101ean01.txt b/dts/Bindings/display/panel/auo,b101ean01.txt
index 3590b07..3590b07 100644
--- a/dts/Bindings/panel/auo,b101ean01.txt
+++ b/dts/Bindings/display/panel/auo,b101ean01.txt
diff --git a/dts/Bindings/panel/auo,b101xtn01.txt b/dts/Bindings/display/panel/auo,b101xtn01.txt
index 889d511..889d511 100644
--- a/dts/Bindings/panel/auo,b101xtn01.txt
+++ b/dts/Bindings/display/panel/auo,b101xtn01.txt
diff --git a/dts/Bindings/panel/auo,b116xw03.txt b/dts/Bindings/display/panel/auo,b116xw03.txt
index 690d0a5..690d0a5 100644
--- a/dts/Bindings/panel/auo,b116xw03.txt
+++ b/dts/Bindings/display/panel/auo,b116xw03.txt
diff --git a/dts/Bindings/panel/auo,b133htn01.txt b/dts/Bindings/display/panel/auo,b133htn01.txt
index 302226b..302226b 100644
--- a/dts/Bindings/panel/auo,b133htn01.txt
+++ b/dts/Bindings/display/panel/auo,b133htn01.txt
diff --git a/dts/Bindings/panel/auo,b133xtn01.txt b/dts/Bindings/display/panel/auo,b133xtn01.txt
index 7443b7c..7443b7c 100644
--- a/dts/Bindings/panel/auo,b133xtn01.txt
+++ b/dts/Bindings/display/panel/auo,b133xtn01.txt
diff --git a/dts/Bindings/panel/avic,tm070ddh03.txt b/dts/Bindings/display/panel/avic,tm070ddh03.txt
index b6f2f3e..b6f2f3e 100644
--- a/dts/Bindings/panel/avic,tm070ddh03.txt
+++ b/dts/Bindings/display/panel/avic,tm070ddh03.txt
diff --git a/dts/Bindings/panel/chunghwa,claa101wa01a.txt b/dts/Bindings/display/panel/chunghwa,claa101wa01a.txt
index f24614e..f24614e 100644
--- a/dts/Bindings/panel/chunghwa,claa101wa01a.txt
+++ b/dts/Bindings/display/panel/chunghwa,claa101wa01a.txt
diff --git a/dts/Bindings/panel/chunghwa,claa101wb03.txt b/dts/Bindings/display/panel/chunghwa,claa101wb03.txt
index 0ab2c05..0ab2c05 100644
--- a/dts/Bindings/panel/chunghwa,claa101wb03.txt
+++ b/dts/Bindings/display/panel/chunghwa,claa101wb03.txt
diff --git a/dts/Bindings/video/display-timing.txt b/dts/Bindings/display/panel/display-timing.txt
index e1d4a0b..e1d4a0b 100644
--- a/dts/Bindings/video/display-timing.txt
+++ b/dts/Bindings/display/panel/display-timing.txt
diff --git a/dts/Bindings/panel/edt,et057090dhu.txt b/dts/Bindings/display/panel/edt,et057090dhu.txt
index 4903d7b..4903d7b 100644
--- a/dts/Bindings/panel/edt,et057090dhu.txt
+++ b/dts/Bindings/display/panel/edt,et057090dhu.txt
diff --git a/dts/Bindings/panel/edt,et070080dh6.txt b/dts/Bindings/display/panel/edt,et070080dh6.txt
index 20cb38e..20cb38e 100644
--- a/dts/Bindings/panel/edt,et070080dh6.txt
+++ b/dts/Bindings/display/panel/edt,et070080dh6.txt
diff --git a/dts/Bindings/panel/edt,etm0700g0dh6.txt b/dts/Bindings/display/panel/edt,etm0700g0dh6.txt
index ee4b180..ee4b180 100644
--- a/dts/Bindings/panel/edt,etm0700g0dh6.txt
+++ b/dts/Bindings/display/panel/edt,etm0700g0dh6.txt
diff --git a/dts/Bindings/panel/foxlink,fl500wvr00-a0t.txt b/dts/Bindings/display/panel/foxlink,fl500wvr00-a0t.txt
index b47f9d8..b47f9d8 100644
--- a/dts/Bindings/panel/foxlink,fl500wvr00-a0t.txt
+++ b/dts/Bindings/display/panel/foxlink,fl500wvr00-a0t.txt
diff --git a/dts/Bindings/panel/giantplus,gpg482739qs5.txt b/dts/Bindings/display/panel/giantplus,gpg482739qs5.txt
index 24b0b62..24b0b62 100644
--- a/dts/Bindings/panel/giantplus,gpg482739qs5.txt
+++ b/dts/Bindings/display/panel/giantplus,gpg482739qs5.txt
diff --git a/dts/Bindings/panel/hannstar,hsd070pww1.txt b/dts/Bindings/display/panel/hannstar,hsd070pww1.txt
index 7da1d5c..7da1d5c 100644
--- a/dts/Bindings/panel/hannstar,hsd070pww1.txt
+++ b/dts/Bindings/display/panel/hannstar,hsd070pww1.txt
diff --git a/dts/Bindings/panel/hannstar,hsd100pxn1.txt b/dts/Bindings/display/panel/hannstar,hsd100pxn1.txt
index 8270319..8270319 100644
--- a/dts/Bindings/panel/hannstar,hsd100pxn1.txt
+++ b/dts/Bindings/display/panel/hannstar,hsd100pxn1.txt
diff --git a/dts/Bindings/panel/hit,tx23d38vm0caa.txt b/dts/Bindings/display/panel/hit,tx23d38vm0caa.txt
index 04caaae..04caaae 100644
--- a/dts/Bindings/panel/hit,tx23d38vm0caa.txt
+++ b/dts/Bindings/display/panel/hit,tx23d38vm0caa.txt
diff --git a/dts/Bindings/panel/innolux,at043tn24.txt b/dts/Bindings/display/panel/innolux,at043tn24.txt
index 4104226..4104226 100644
--- a/dts/Bindings/panel/innolux,at043tn24.txt
+++ b/dts/Bindings/display/panel/innolux,at043tn24.txt
diff --git a/dts/Bindings/panel/innolux,g121i1-l01.txt b/dts/Bindings/display/panel/innolux,g121i1-l01.txt
index 2743b07..2743b07 100644
--- a/dts/Bindings/panel/innolux,g121i1-l01.txt
+++ b/dts/Bindings/display/panel/innolux,g121i1-l01.txt
diff --git a/dts/Bindings/panel/innolux,n116bge.txt b/dts/Bindings/display/panel/innolux,n116bge.txt
index 081bb93..081bb93 100644
--- a/dts/Bindings/panel/innolux,n116bge.txt
+++ b/dts/Bindings/display/panel/innolux,n116bge.txt
diff --git a/dts/Bindings/panel/innolux,n156bge-l21.txt b/dts/Bindings/display/panel/innolux,n156bge-l21.txt
index 7825844..7825844 100644
--- a/dts/Bindings/panel/innolux,n156bge-l21.txt
+++ b/dts/Bindings/display/panel/innolux,n156bge-l21.txt
diff --git a/dts/Bindings/panel/innolux,zj070na-01p.txt b/dts/Bindings/display/panel/innolux,zj070na-01p.txt
index 824f87f..824f87f 100644
--- a/dts/Bindings/panel/innolux,zj070na-01p.txt
+++ b/dts/Bindings/display/panel/innolux,zj070na-01p.txt
diff --git a/dts/Bindings/panel/lg,lb070wv8.txt b/dts/Bindings/display/panel/lg,lb070wv8.txt
index a7588e5..a7588e5 100644
--- a/dts/Bindings/panel/lg,lb070wv8.txt
+++ b/dts/Bindings/display/panel/lg,lb070wv8.txt
diff --git a/dts/Bindings/panel/lg,ld070wx3-sl01.txt b/dts/Bindings/display/panel/lg,ld070wx3-sl01.txt
index 5e649cb..5e649cb 100644
--- a/dts/Bindings/panel/lg,ld070wx3-sl01.txt
+++ b/dts/Bindings/display/panel/lg,ld070wx3-sl01.txt
diff --git a/dts/Bindings/panel/lg,lg4573.txt b/dts/Bindings/display/panel/lg,lg4573.txt
index 824441f..824441f 100644
--- a/dts/Bindings/panel/lg,lg4573.txt
+++ b/dts/Bindings/display/panel/lg,lg4573.txt
diff --git a/dts/Bindings/panel/lg,lh500wx1-sd03.txt b/dts/Bindings/display/panel/lg,lh500wx1-sd03.txt
index a04fd2b..a04fd2b 100644
--- a/dts/Bindings/panel/lg,lh500wx1-sd03.txt
+++ b/dts/Bindings/display/panel/lg,lh500wx1-sd03.txt
diff --git a/dts/Bindings/panel/lg,lp129qe.txt b/dts/Bindings/display/panel/lg,lp129qe.txt
index 9f262e0..9f262e0 100644
--- a/dts/Bindings/panel/lg,lp129qe.txt
+++ b/dts/Bindings/display/panel/lg,lp129qe.txt
diff --git a/dts/Bindings/video/lgphilips,lb035q02.txt b/dts/Bindings/display/panel/lgphilips,lb035q02.txt
index 1a1e653..1a1e653 100644
--- a/dts/Bindings/video/lgphilips,lb035q02.txt
+++ b/dts/Bindings/display/panel/lgphilips,lb035q02.txt
diff --git a/dts/Bindings/panel/nec,nl4827hc19-05b.txt b/dts/Bindings/display/panel/nec,nl4827hc19-05b.txt
index 8e1914d..8e1914d 100644
--- a/dts/Bindings/panel/nec,nl4827hc19-05b.txt
+++ b/dts/Bindings/display/panel/nec,nl4827hc19-05b.txt
diff --git a/dts/Bindings/panel/okaya,rs800480t-7x0gp.txt b/dts/Bindings/display/panel/okaya,rs800480t-7x0gp.txt
index ddf8e21..ddf8e21 100644
--- a/dts/Bindings/panel/okaya,rs800480t-7x0gp.txt
+++ b/dts/Bindings/display/panel/okaya,rs800480t-7x0gp.txt
diff --git a/dts/Bindings/panel/ortustech,com43h4m85ulc.txt b/dts/Bindings/display/panel/ortustech,com43h4m85ulc.txt
index de19e93..de19e93 100644
--- a/dts/Bindings/panel/ortustech,com43h4m85ulc.txt
+++ b/dts/Bindings/display/panel/ortustech,com43h4m85ulc.txt
diff --git a/dts/Bindings/panel/panasonic,vvx10f004b00.txt b/dts/Bindings/display/panel/panasonic,vvx10f004b00.txt
index d328b03..d328b03 100644
--- a/dts/Bindings/panel/panasonic,vvx10f004b00.txt
+++ b/dts/Bindings/display/panel/panasonic,vvx10f004b00.txt
diff --git a/dts/Bindings/video/panel-dpi.txt b/dts/Bindings/display/panel/panel-dpi.txt
index a40180b..216c894 100644
--- a/dts/Bindings/video/panel-dpi.txt
+++ b/dts/Bindings/display/panel/panel-dpi.txt
@@ -10,7 +10,7 @@ Optional properties:
Required nodes:
- "panel-timing" containing video timings
- (Documentation/devicetree/bindings/video/display-timing.txt)
+ (Documentation/devicetree/bindings/display/display-timing.txt)
- Video port for DPI input
Example
diff --git a/dts/Bindings/video/panel-dsi-cm.txt b/dts/Bindings/display/panel/panel-dsi-cm.txt
index dce48eb..dce48eb 100644
--- a/dts/Bindings/video/panel-dsi-cm.txt
+++ b/dts/Bindings/display/panel/panel-dsi-cm.txt
diff --git a/dts/Bindings/panel/samsung,ld9040.txt b/dts/Bindings/display/panel/samsung,ld9040.txt
index 07c36c3..fc595d9 100644
--- a/dts/Bindings/panel/samsung,ld9040.txt
+++ b/dts/Bindings/display/panel/samsung,ld9040.txt
@@ -20,7 +20,7 @@ The device node can contain one 'port' child node with one child
'endpoint' node, according to the bindings defined in [3]. This
node should describe panel's video bus.
-[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/display-timing.txt
[2]: Documentation/devicetree/bindings/spi/spi-bus.txt
[3]: Documentation/devicetree/bindings/media/video-interfaces.txt
diff --git a/dts/Bindings/panel/samsung,ltn101nt05.txt b/dts/Bindings/display/panel/samsung,ltn101nt05.txt
index ef522c6..ef522c6 100644
--- a/dts/Bindings/panel/samsung,ltn101nt05.txt
+++ b/dts/Bindings/display/panel/samsung,ltn101nt05.txt
diff --git a/dts/Bindings/panel/samsung,ltn140at29-301.txt b/dts/Bindings/display/panel/samsung,ltn140at29-301.txt
index e7f969d..e7f969d 100644
--- a/dts/Bindings/panel/samsung,ltn140at29-301.txt
+++ b/dts/Bindings/display/panel/samsung,ltn140at29-301.txt
diff --git a/dts/Bindings/panel/samsung,s6e8aa0.txt b/dts/Bindings/display/panel/samsung,s6e8aa0.txt
index e7ee988..25701c8 100644
--- a/dts/Bindings/panel/samsung,s6e8aa0.txt
+++ b/dts/Bindings/display/panel/samsung,s6e8aa0.txt
@@ -21,7 +21,7 @@ The device node can contain one 'port' child node with one child
'endpoint' node, according to the bindings defined in [2]. This
node should describe panel's video bus.
-[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/display-timing.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
diff --git a/dts/Bindings/panel/sharp,lq101r1sx01.txt b/dts/Bindings/display/panel/sharp,lq101r1sx01.txt
index f522bb8..f522bb8 100644
--- a/dts/Bindings/panel/sharp,lq101r1sx01.txt
+++ b/dts/Bindings/display/panel/sharp,lq101r1sx01.txt
diff --git a/dts/Bindings/video/sharp,ls037v7dw01.txt b/dts/Bindings/display/panel/sharp,ls037v7dw01.txt
index 0cc8981..0cc8981 100644
--- a/dts/Bindings/video/sharp,ls037v7dw01.txt
+++ b/dts/Bindings/display/panel/sharp,ls037v7dw01.txt
diff --git a/dts/Bindings/panel/shelly,sca07010-bfn-lnn.txt b/dts/Bindings/display/panel/shelly,sca07010-bfn-lnn.txt
index fc1ea9e..fc1ea9e 100644
--- a/dts/Bindings/panel/shelly,sca07010-bfn-lnn.txt
+++ b/dts/Bindings/display/panel/shelly,sca07010-bfn-lnn.txt
diff --git a/dts/Bindings/panel/simple-panel.txt b/dts/Bindings/display/panel/simple-panel.txt
index 1341bbf..1341bbf 100644
--- a/dts/Bindings/panel/simple-panel.txt
+++ b/dts/Bindings/display/panel/simple-panel.txt
diff --git a/dts/Bindings/video/sony,acx565akm.txt b/dts/Bindings/display/panel/sony,acx565akm.txt
index e123332..e123332 100644
--- a/dts/Bindings/video/sony,acx565akm.txt
+++ b/dts/Bindings/display/panel/sony,acx565akm.txt
diff --git a/dts/Bindings/video/toppoly,td028ttec1.txt b/dts/Bindings/display/panel/toppoly,td028ttec1.txt
index 7175dc3..7175dc3 100644
--- a/dts/Bindings/video/toppoly,td028ttec1.txt
+++ b/dts/Bindings/display/panel/toppoly,td028ttec1.txt
diff --git a/dts/Bindings/video/tpo,td043mtea1.txt b/dts/Bindings/display/panel/tpo,td043mtea1.txt
index ec6d629..ec6d629 100644
--- a/dts/Bindings/video/tpo,td043mtea1.txt
+++ b/dts/Bindings/display/panel/tpo,td043mtea1.txt
diff --git a/dts/Bindings/video/renesas,du.txt b/dts/Bindings/display/renesas,du.txt
index c902323..eccd4f4 100644
--- a/dts/Bindings/video/renesas,du.txt
+++ b/dts/Bindings/display/renesas,du.txt
@@ -5,7 +5,9 @@ Required Properties:
- compatible: must be one of the following.
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
- - "renesas,du-r8a7791" for R8A7791 (R-Car M2) compatible DU
+ - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
+ - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
+ - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
- reg: A list of base address and length of each memory resource, one for
each entry in the reg-names property.
@@ -22,9 +24,9 @@ Required Properties:
- clock-names: Name of the clocks. This property is model-dependent.
- R8A7779 uses a single functional clock. The clock doesn't need to be
named.
- - R8A7790 and R8A7791 use one functional clock per channel and one clock
- per LVDS encoder. The functional clocks must be named "du.x" with "x"
- being the channel numerical index. The LVDS clocks must be named
+ - R8A779[0134] use one functional clock per channel and one clock per LVDS
+ encoder (if available). The functional clocks must be named "du.x" with
+ "x" being the channel numerical index. The LVDS clocks must be named
"lvds.x" with "x" being the LVDS encoder numerical index.
- In addition to the functional and encoder clocks, all DU versions also
support externally supplied pixel clocks. Those clocks are optional.
@@ -43,7 +45,9 @@ corresponding to each DU output.
-----------------------------------------------------------------------------
R8A7779 (H1) DPAD 0 DPAD 1 -
R8A7790 (H2) DPAD LVDS 0 LVDS 1
- R8A7791 (M2) DPAD LVDS 0 -
+ R8A7791 (M2-W) DPAD LVDS 0 -
+ R8A7793 (M2-N) DPAD LVDS 0 -
+ R8A7794 (E2) DPAD 0 DPAD 1 -
Example: R8A7790 (R-Car H2) DU
diff --git a/dts/Bindings/video/dw_hdmi-rockchip.txt b/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
index 668091f..668091f 100644
--- a/dts/Bindings/video/dw_hdmi-rockchip.txt
+++ b/dts/Bindings/display/rockchip/dw_hdmi-rockchip.txt
diff --git a/dts/Bindings/video/rockchip-drm.txt b/dts/Bindings/display/rockchip/rockchip-drm.txt
index 7fff582..5707af8 100644
--- a/dts/Bindings/video/rockchip-drm.txt
+++ b/dts/Bindings/display/rockchip/rockchip-drm.txt
@@ -9,7 +9,7 @@ Required properties:
- compatible: Should be "rockchip,display-subsystem"
- ports: Should contain a list of phandles pointing to display interface port
of vop devices. vop definitions as defined in
- Documentation/devicetree/bindings/video/rockchip-vop.txt
+ Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
example:
diff --git a/dts/Bindings/video/rockchip-vop.txt b/dts/Bindings/display/rockchip/rockchip-vop.txt
index d15351f..d15351f 100644
--- a/dts/Bindings/video/rockchip-vop.txt
+++ b/dts/Bindings/display/rockchip/rockchip-vop.txt
diff --git a/dts/Bindings/video/simple-framebuffer-sunxi.txt b/dts/Bindings/display/simple-framebuffer-sunxi.txt
index c46ba64..c46ba64 100644
--- a/dts/Bindings/video/simple-framebuffer-sunxi.txt
+++ b/dts/Bindings/display/simple-framebuffer-sunxi.txt
diff --git a/dts/Bindings/video/simple-framebuffer.txt b/dts/Bindings/display/simple-framebuffer.txt
index 4474ef6..4474ef6 100644
--- a/dts/Bindings/video/simple-framebuffer.txt
+++ b/dts/Bindings/display/simple-framebuffer.txt
diff --git a/dts/Bindings/fb/sm501fb.txt b/dts/Bindings/display/sm501fb.txt
index 9d9f009..9d9f009 100644
--- a/dts/Bindings/fb/sm501fb.txt
+++ b/dts/Bindings/display/sm501fb.txt
diff --git a/dts/Bindings/video/ssd1289fb.txt b/dts/Bindings/display/ssd1289fb.txt
index 4fcd5e6..4fcd5e6 100644
--- a/dts/Bindings/video/ssd1289fb.txt
+++ b/dts/Bindings/display/ssd1289fb.txt
diff --git a/dts/Bindings/video/ssd1307fb.txt b/dts/Bindings/display/ssd1307fb.txt
index d1be78d..eb31ed4 100644
--- a/dts/Bindings/video/ssd1307fb.txt
+++ b/dts/Bindings/display/ssd1307fb.txt
@@ -2,7 +2,8 @@
Required properties:
- compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
- now is i2c, and the supported chips are ssd1305, ssd1306 and ssd1307.
+ now is i2c, and the supported chips are ssd1305, ssd1306, ssd1307 and
+ ssd1309.
- reg: Should contain address of the controller on the I2C bus. Most likely
0x3c or 0x3d
- pwm: Should contain the pwm to use according to the OF device tree PWM
diff --git a/dts/Bindings/gpu/st,stih4xx.txt b/dts/Bindings/display/st,stih4xx.txt
index a36dfce..a352ed3 100644
--- a/dts/Bindings/gpu/st,stih4xx.txt
+++ b/dts/Bindings/display/st,stih4xx.txt
@@ -61,7 +61,7 @@ STMicroelectronics stih4xx platforms
- reg-names: names of the mapped memory regions listed in regs property in
the same order.
- interrupts : HDMI interrupt number to the CPU.
- - interrupt-names: name of the interrupts listed in interrupts property in
+ - interrupt-names: names of the interrupts listed in interrupts property in
the same order
- clocks: from common clock binding: handle hardware IP needed clocks, the
number of clocks may depend of the SoC type.
@@ -95,7 +95,7 @@ sti-dvo:
- clock-names: names of the clocks listed in clocks property in the same
order.
- pinctrl-0: pin control handle
- - pinctrl-name: names of the pin control to use
+ - pinctrl-names: names of the pin control states to use
- sti,panel: phandle of the panel connected to the DVO output
sti-hqvdp:
diff --git a/dts/Bindings/mipi/nvidia,tegra114-mipi.txt b/dts/Bindings/display/tegra/nvidia,tegra114-mipi.txt
index e4a25ce..e4a25ce 100644
--- a/dts/Bindings/mipi/nvidia,tegra114-mipi.txt
+++ b/dts/Bindings/display/tegra/nvidia,tegra114-mipi.txt
diff --git a/dts/Bindings/gpu/nvidia,tegra20-host1x.txt b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
index e685610..a3bd8c0 100644
--- a/dts/Bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -184,7 +184,7 @@ of the following host1x client modules:
- avdd-dsi-supply: phandle of a supply that powers the DSI controller
- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
which pads are used by this DSI output and need to be calibrated. See also
- ../mipi/nvidia,tegra114-mipi.txt.
+ ../display/tegra/nvidia,tegra114-mipi.txt.
Optional properties:
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
diff --git a/dts/Bindings/video/ti,dra7-dss.txt b/dts/Bindings/display/ti/ti,dra7-dss.txt
index f33a051..c30f9ec 100644
--- a/dts/Bindings/video/ti,dra7-dss.txt
+++ b/dts/Bindings/display/ti/ti,dra7-dss.txt
@@ -1,7 +1,7 @@
Texas Instruments DRA7x Display Subsystem
=========================================
-See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic
+See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.
DSS Core
diff --git a/dts/Bindings/video/ti,omap-dss.txt b/dts/Bindings/display/ti/ti,omap-dss.txt
index e1ef295..e1ef295 100644
--- a/dts/Bindings/video/ti,omap-dss.txt
+++ b/dts/Bindings/display/ti/ti,omap-dss.txt
diff --git a/dts/Bindings/video/ti,omap2-dss.txt b/dts/Bindings/display/ti/ti,omap2-dss.txt
index fa8bb2e..afcd5a8 100644
--- a/dts/Bindings/video/ti,omap2-dss.txt
+++ b/dts/Bindings/display/ti/ti,omap2-dss.txt
@@ -1,7 +1,7 @@
Texas Instruments OMAP2 Display Subsystem
=========================================
-See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic
+See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.
DSS Core
diff --git a/dts/Bindings/video/ti,omap3-dss.txt b/dts/Bindings/display/ti/ti,omap3-dss.txt
index 0023fa4..dc66e14 100644
--- a/dts/Bindings/video/ti,omap3-dss.txt
+++ b/dts/Bindings/display/ti/ti,omap3-dss.txt
@@ -1,7 +1,7 @@
Texas Instruments OMAP3 Display Subsystem
=========================================
-See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic
+See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.
DSS Core
diff --git a/dts/Bindings/video/ti,omap4-dss.txt b/dts/Bindings/display/ti/ti,omap4-dss.txt
index b8c29fb..bc624db 100644
--- a/dts/Bindings/video/ti,omap4-dss.txt
+++ b/dts/Bindings/display/ti/ti,omap4-dss.txt
@@ -1,7 +1,7 @@
Texas Instruments OMAP4 Display Subsystem
=========================================
-See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic
+See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.
DSS Core
diff --git a/dts/Bindings/video/ti,omap5-dss.txt b/dts/Bindings/display/ti/ti,omap5-dss.txt
index 38ffc8f..118a486 100644
--- a/dts/Bindings/video/ti,omap5-dss.txt
+++ b/dts/Bindings/display/ti/ti,omap5-dss.txt
@@ -1,7 +1,7 @@
Texas Instruments OMAP5 Display Subsystem
=========================================
-See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic
+See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.
DSS Core
diff --git a/dts/Bindings/video/ti,opa362.txt b/dts/Bindings/display/ti/ti,opa362.txt
index f96083c..f96083c 100644
--- a/dts/Bindings/video/ti,opa362.txt
+++ b/dts/Bindings/display/ti/ti,opa362.txt
diff --git a/dts/Bindings/video/ti,tfp410.txt b/dts/Bindings/display/ti/ti,tfp410.txt
index 2cbe32a..2cbe32a 100644
--- a/dts/Bindings/video/ti,tfp410.txt
+++ b/dts/Bindings/display/ti/ti,tfp410.txt
diff --git a/dts/Bindings/video/ti,tpd12s015.txt b/dts/Bindings/display/ti/ti,tpd12s015.txt
index 26e6d32..26e6d32 100644
--- a/dts/Bindings/video/ti,tpd12s015.txt
+++ b/dts/Bindings/display/ti/ti,tpd12s015.txt
diff --git a/dts/Bindings/drm/tilcdc/panel.txt b/dts/Bindings/display/tilcdc/panel.txt
index 4ab9e23..f20b31c 100644
--- a/dts/Bindings/drm/tilcdc/panel.txt
+++ b/dts/Bindings/display/tilcdc/panel.txt
@@ -15,7 +15,7 @@ Required properties:
- display-timings: typical videomode of lcd panel. Multiple video modes
can be listed if the panel supports multiple timings, but the 'native-mode'
should be the preferred/default resolution. Refer to
- Documentation/devicetree/bindings/video/display-timing.txt for display
+ Documentation/devicetree/bindings/display/display-timing.txt for display
timing binding details.
Optional properties:
diff --git a/dts/Bindings/drm/tilcdc/tfp410.txt b/dts/Bindings/display/tilcdc/tfp410.txt
index a58ae77..a58ae77 100644
--- a/dts/Bindings/drm/tilcdc/tfp410.txt
+++ b/dts/Bindings/display/tilcdc/tfp410.txt
diff --git a/dts/Bindings/drm/tilcdc/tilcdc.txt b/dts/Bindings/display/tilcdc/tilcdc.txt
index 2136ee8..2136ee8 100644
--- a/dts/Bindings/drm/tilcdc/tilcdc.txt
+++ b/dts/Bindings/display/tilcdc/tilcdc.txt
diff --git a/dts/Bindings/video/via,vt8500-fb.txt b/dts/Bindings/display/via,vt8500-fb.txt
index 2871e21..2871e21 100644
--- a/dts/Bindings/video/via,vt8500-fb.txt
+++ b/dts/Bindings/display/via,vt8500-fb.txt
diff --git a/dts/Bindings/video/wm,prizm-ge-rops.txt b/dts/Bindings/display/wm,prizm-ge-rops.txt
index a850fa0..a850fa0 100644
--- a/dts/Bindings/video/wm,prizm-ge-rops.txt
+++ b/dts/Bindings/display/wm,prizm-ge-rops.txt
diff --git a/dts/Bindings/video/wm,wm8505-fb.txt b/dts/Bindings/display/wm,wm8505-fb.txt
index 0bcadb2..0bcadb2 100644
--- a/dts/Bindings/video/wm,wm8505-fb.txt
+++ b/dts/Bindings/display/wm,wm8505-fb.txt
diff --git a/dts/Bindings/dma/ti-dma-crossbar.txt b/dts/Bindings/dma/ti-dma-crossbar.txt
index 63a4892..b152a75 100644
--- a/dts/Bindings/dma/ti-dma-crossbar.txt
+++ b/dts/Bindings/dma/ti-dma-crossbar.txt
@@ -2,9 +2,10 @@ Texas Instruments DMA Crossbar (DMA request router)
Required properties:
- compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
+ "ti,am335x-edma-crossbar" for AM335x and AM437x
- reg: Memory map for accessing module
-- #dma-cells: Should be set to <1>.
- Clients should use the crossbar request number (input)
+- #dma-cells: Should be set to to match with the DMA controller's dma-cells
+ for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
- dma-requests: Number of DMA requests the crossbar can receive
- dma-masters: phandle pointing to the DMA controller
@@ -14,6 +15,15 @@ The DMA controller node need to have the following poroperties:
Optional properties:
- ti,dma-safe-map: Safe routing value for unused request lines
+Notes:
+When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request
+the DMA event number as crossbar ID (input to the DMA crossbar).
+
+For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:
+dmas = <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC
+the event should be assigned and <1> is the mux selection for in the crossbar.
+When mux 0 is used the DMA channel can be requested directly from edma node.
+
Example:
/* DMA controller */
@@ -47,6 +57,7 @@ uart1: serial@4806a000 {
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
+ /* Requesting crossbar input 49 and 50 */
dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
dma-names = "tx", "rx";
};
diff --git a/dts/Bindings/dma/ti-edma.txt b/dts/Bindings/dma/ti-edma.txt
index 5ba525a..d3d0a4f 100644
--- a/dts/Bindings/dma/ti-edma.txt
+++ b/dts/Bindings/dma/ti-edma.txt
@@ -1,4 +1,119 @@
-TI EDMA
+Texas Instruments eDMA
+
+The eDMA3 consists of two components: Channel controller (CC) and Transfer
+Controller(s) (TC). The CC is the main entry for DMA users since it is
+responsible for the DMA channel handling, while the TCs are responsible to
+execute the actual DMA tansfer.
+
+------------------------------------------------------------------------------
+eDMA3 Channel Controller
+
+Required properties:
+- compatible: "ti,edma3-tpcc" for the channel controller(s)
+- #dma-cells: Should be set to <2>. The first number is the DMA request
+ number and the second is the TC the channel is serviced on.
+- reg: Memory map of eDMA CC
+- reg-names: "edma3_cc"
+- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
+- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint"
+- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
+ <&tptc_phandle TC_priority_number>. The highest priority is 0.
+
+Optional properties:
+- ti,hwmods: Name of the hwmods associated to the eDMA CC
+- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
+ these channels will be SW triggered channels. The list must
+ contain 16 bits numbers, see example.
+- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
+ the driver, they are allocated to be used by for example the
+ DSP. See example.
+
+------------------------------------------------------------------------------
+eDMA3 Transfer Controller
+
+Required properties:
+- compatible: "ti,edma3-tptc" for the transfer controller(s)
+- reg: Memory map of eDMA TC
+- interrupts: Interrupt number for TCerrint.
+
+Optional properties:
+- ti,hwmods: Name of the hwmods associated to the given eDMA TC
+- interrupt-names: "edma3_tcerrint"
+
+------------------------------------------------------------------------------
+Example:
+
+edma: edma@49000000 {
+ compatible = "ti,edma3-tpcc";
+ ti,hwmods = "tpcc";
+ reg = <0x49000000 0x10000>;
+ reg-names = "edma3_cc";
+ interrupts = <12 13 14>;
+ interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
+
+ /* Channel 20 and 21 is allocated for memcpy */
+ ti,edma-memcpy-channels = /bits/ 16 <20 21>;
+ /* The following PaRAM slots are reserved: 35-45 and 100-110 */
+ ti,edma-reserved-slot-ranges = /bits/ 16 <35 10>,
+ /bits/ 16 <100 10>;
+};
+
+edma_tptc0: tptc@49800000 {
+ compatible = "ti,edma3-tptc";
+ ti,hwmods = "tptc0";
+ reg = <0x49800000 0x100000>;
+ interrupts = <112>;
+ interrupt-names = "edm3_tcerrint";
+};
+
+edma_tptc1: tptc@49900000 {
+ compatible = "ti,edma3-tptc";
+ ti,hwmods = "tptc1";
+ reg = <0x49900000 0x100000>;
+ interrupts = <113>;
+ interrupt-names = "edm3_tcerrint";
+};
+
+edma_tptc2: tptc@49a00000 {
+ compatible = "ti,edma3-tptc";
+ ti,hwmods = "tptc2";
+ reg = <0x49a00000 0x100000>;
+ interrupts = <114>;
+ interrupt-names = "edm3_tcerrint";
+};
+
+sham: sham@53100000 {
+ compatible = "ti,omap4-sham";
+ ti,hwmods = "sham";
+ reg = <0x53100000 0x200>;
+ interrupts = <109>;
+ /* DMA channel 36 executed on eDMA TC0 - low priority queue */
+ dmas = <&edma 36 0>;
+ dma-names = "rx";
+};
+
+mcasp0: mcasp@48038000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ ti,hwmods = "mcasp0";
+ reg = <0x48038000 0x2000>,
+ <0x46000000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <80>, <81>;
+ interrupt-names = "tx", "rx";
+ status = "disabled";
+ /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
+ dmas = <&edma 8 2>,
+ <&edma 9 2>;
+ dma-names = "tx", "rx";
+};
+
+------------------------------------------------------------------------------
+DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
+binding.
Required properties:
- compatible : "ti,edma3"
diff --git a/dts/Bindings/edac/apm-xgene-edac.txt b/dts/Bindings/edac/apm-xgene-edac.txt
index 78edb80..78e2a31 100644
--- a/dts/Bindings/edac/apm-xgene-edac.txt
+++ b/dts/Bindings/edac/apm-xgene-edac.txt
@@ -5,6 +5,8 @@ The follow error types are supported:
memory controller - Memory controller
PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
+ L3 - L3 cache controller
+ SoC - SoC IP's such as Ethernet, SATA, and etc
The following section describes the EDAC DT node binding.
@@ -30,6 +32,17 @@ Required properties for PMD subnode:
- reg : First resource shall be the PMD resource.
- pmd-controller : Instance number of the PMD controller.
+Required properties for L3 subnode:
+- compatible : Shall be "apm,xgene-edac-l3" or
+ "apm,xgene-edac-l3-v2".
+- reg : First resource shall be the L3 EDAC resource.
+
+Required properties for SoC subnode:
+- compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or
+ "apm,xgene-edac-l3-soc" for general value reporting
+ only.
+- reg : First resource shall be the SoC EDAC resource.
+
Example:
csw: csw@7e200000 {
compatible = "apm,xgene-csw", "syscon";
@@ -76,4 +89,14 @@ Example:
reg = <0x0 0x7c000000 0x0 0x200000>;
pmd-controller = <0>;
};
+
+ edacl3@7e600000 {
+ compatible = "apm,xgene-edac-l3";
+ reg = <0x0 0x7e600000 0x0 0x1000>;
+ };
+
+ edacsoc@7e930000 {
+ compatible = "apm,xgene-edac-soc-v1";
+ reg = <0x0 0x7e930000 0x0 0x1000>;
+ };
};
diff --git a/dts/Bindings/misc/at25.txt b/dts/Bindings/eeprom/at25.txt
index 1d34471..1d34471 100644
--- a/dts/Bindings/misc/at25.txt
+++ b/dts/Bindings/eeprom/at25.txt
diff --git a/dts/Bindings/eeprom.txt b/dts/Bindings/eeprom/eeprom.txt
index 4342c10..4342c10 100644
--- a/dts/Bindings/eeprom.txt
+++ b/dts/Bindings/eeprom/eeprom.txt
diff --git a/dts/Bindings/extcon/extcon-arizona.txt b/dts/Bindings/extcon/extcon-arizona.txt
new file mode 100644
index 0000000..e1705fa
--- /dev/null
+++ b/dts/Bindings/extcon/extcon-arizona.txt
@@ -0,0 +1,15 @@
+Cirrus Logic Arizona class audio SoCs
+
+These devices are audio SoCs with extensive digital capabilities and a range
+of analogue I/O.
+
+This document lists Extcon specific bindings, see the primary binding document:
+ ../mfd/arizona.txt
+
+Optional properties:
+
+ - wlf,hpdet-channel : Headphone detection channel.
+ ARIZONA_ACCDET_MODE_HPL or 1 - Headphone detect mode is set to HPDETL
+ ARIZONA_ACCDET_MODE_HPR or 2 - Headphone detect mode is set to HPDETR
+ If this node is not mentioned or if the value is unknown, then
+ headphone detection mode is set to HPDETL.
diff --git a/dts/Bindings/fpga/altera-socfpga-fpga-mgr.txt b/dts/Bindings/fpga/altera-socfpga-fpga-mgr.txt
index 9b027a6..d52f334 100644
--- a/dts/Bindings/fpga/altera-socfpga-fpga-mgr.txt
+++ b/dts/Bindings/fpga/altera-socfpga-fpga-mgr.txt
@@ -9,7 +9,7 @@ Required properties:
Example:
- hps_0_fpgamgr: fpgamgr@0xff706000 {
+ hps_0_fpgamgr: fpgamgr@ff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xFF706000 0x1000
0xFFB90000 0x1000>;
diff --git a/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.txt b/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.txt
new file mode 100644
index 0000000..7018aa8
--- /dev/null
+++ b/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.txt
@@ -0,0 +1,19 @@
+Xilinx Zynq FPGA Manager
+
+Required properties:
+- compatible: should contain "xlnx,zynq-devcfg-1.0"
+- reg: base address and size for memory mapped io
+- interrupts: interrupt for the FPGA manager device
+- clocks: phandle for clocks required operation
+- clock-names: name for the clock, should be "ref_clk"
+- syscon: phandle for access to SLCR registers
+
+Example:
+ devcfg: devcfg@f8007000 {
+ compatible = "xlnx,zynq-devcfg-1.0";
+ reg = <0xf8007000 0x100>;
+ interrupts = <0 8 4>;
+ clocks = <&clkc 12>;
+ clock-names = "ref_clk";
+ syscon = <&slcr>;
+ };
diff --git a/dts/Bindings/gpio/gpio-mpc8xxx.txt b/dts/Bindings/gpio/gpio-mpc8xxx.txt
index 805ddcd..f2455c5 100644
--- a/dts/Bindings/gpio/gpio-mpc8xxx.txt
+++ b/dts/Bindings/gpio/gpio-mpc8xxx.txt
@@ -1,9 +1,9 @@
-* Freescale MPC512x/MPC8xxx GPIO controller
+* Freescale MPC512x/MPC8xxx/Layerscape GPIO controller
Required properties:
- compatible : Should be "fsl,<soc>-gpio"
The following <soc>s are known to be supported:
- mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq
+ mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq.
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all 32 pins.
- #gpio-cells : Should be two. The first cell is the pin number and
diff --git a/dts/Bindings/gpio/gpio-msm.txt b/dts/Bindings/gpio/gpio-msm.txt
deleted file mode 100644
index ac20e68..0000000
--- a/dts/Bindings/gpio/gpio-msm.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-MSM GPIO controller bindings
-
-Required properties:
-- compatible:
- - "qcom,msm-gpio" for MSM controllers
-- #gpio-cells : Should be two.
- - first cell is the pin number
- - second cell is used to specify optional parameters (unused)
-- gpio-controller : Marks the device node as a GPIO controller.
-- #interrupt-cells : Should be 2.
-- interrupt-controller: Mark the device node as an interrupt controller
-- interrupts : Specify the TLMM summary interrupt number
-- ngpio : Specify the number of MSM GPIOs
-
-Example:
-
- msmgpio: gpio@fd510000 {
- compatible = "qcom,msm-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xfd510000 0x4000>;
- interrupts = <0 208 0>;
- ngpio = <150>;
- };
diff --git a/dts/Bindings/gpio/gpio-pca953x.txt b/dts/Bindings/gpio/gpio-pca953x.txt
index b9a42f2..13df993 100644
--- a/dts/Bindings/gpio/gpio-pca953x.txt
+++ b/dts/Bindings/gpio/gpio-pca953x.txt
@@ -24,6 +24,7 @@ Required properties:
ti,tca6408
ti,tca6416
ti,tca6424
+ ti,tca9539
exar,xra1202
Example:
diff --git a/dts/Bindings/gpio/gpio-zynq.txt b/dts/Bindings/gpio/gpio-zynq.txt
index db4c6a6..7b54265 100644
--- a/dts/Bindings/gpio/gpio-zynq.txt
+++ b/dts/Bindings/gpio/gpio-zynq.txt
@@ -12,6 +12,13 @@ Required properties:
- interrupts : Interrupt specifier (see interrupt bindings for
details)
- interrupt-parent : Must be core interrupt controller
+- interrupt-controller : Marks the device node as an interrupt controller.
+- #interrupt-cells : Should be 2. The first cell is the GPIO number.
+ The second cell bits[3:0] is used to specify trigger type and level flags:
+ 1 = low-to-high edge triggered.
+ 2 = high-to-low edge triggered.
+ 4 = active high level-sensitive.
+ 8 = active low level-sensitive.
- reg : Address and length of the register set for the device
Example:
@@ -22,5 +29,7 @@ Example:
gpio-controller;
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0xe000a000 0x1000>;
};
diff --git a/dts/Bindings/gpio/gpio.txt b/dts/Bindings/gpio/gpio.txt
index 82d40e2..069cdf6 100644
--- a/dts/Bindings/gpio/gpio.txt
+++ b/dts/Bindings/gpio/gpio.txt
@@ -54,9 +54,13 @@ only uses one.
gpio-specifier may encode: bank, pin position inside the bank,
whether pin is open-drain and whether pin is logically inverted.
+
Exact meaning of each specifier cell is controller specific, and must
-be documented in the device tree binding for the device. Use the macros
-defined in include/dt-bindings/gpio/gpio.h whenever possible:
+be documented in the device tree binding for the device.
+
+Most controllers are however specifying a generic flag bitfield
+in the last cell, so for these, use the macros defined in
+include/dt-bindings/gpio/gpio.h whenever possible:
Example of a node using GPIOs:
@@ -67,6 +71,15 @@ Example of a node using GPIOs:
GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
+Optional standard bitfield specifiers for the last cell:
+
+- Bit 0: 0 means active high, 1 means active low
+- Bit 1: 1 means single-ended wiring, see:
+ https://en.wikipedia.org/wiki/Single-ended_triode
+ When used with active-low, this means open drain/collector, see:
+ https://en.wikipedia.org/wiki/Open_collector
+ When used with active-high, this means open source/emitter
+
1.1) GPIO specifier best practices
----------------------------------
@@ -118,6 +131,30 @@ Every GPIO controller node must contain both an empty "gpio-controller"
property, and a #gpio-cells integer property, which indicates the number of
cells in a gpio-specifier.
+Optionally, a GPIO controller may have a "ngpios" property. This property
+indicates the number of in-use slots of available slots for GPIOs. The
+typical example is something like this: the hardware register is 32 bits
+wide, but only 18 of the bits have a physical counterpart. The driver is
+generally written so that all 32 bits can be used, but the IP block is reused
+in a lot of designs, some using all 32 bits, some using 18 and some using
+12. In this case, setting "ngpios = <18>;" informs the driver that only the
+first 18 GPIOs, at local offset 0 .. 17, are in use.
+
+If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
+additional bitmask is needed to specify which GPIOs are actually in use,
+and which are dummies. The bindings for this case has not yet been
+specified, but should be specified if/when such hardware appears.
+
+Example:
+
+gpio-controller@00000000 {
+ compatible = "foo";
+ reg = <0x00000000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <18>;
+}
+
The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
providing automatic GPIO request and configuration as part of the
gpio-controller's driver probe function.
diff --git a/dts/Bindings/gpio/netxbig-gpio-ext.txt b/dts/Bindings/gpio/netxbig-gpio-ext.txt
new file mode 100644
index 0000000..50ec2e6
--- /dev/null
+++ b/dts/Bindings/gpio/netxbig-gpio-ext.txt
@@ -0,0 +1,22 @@
+Binding for the GPIO extension bus found on some LaCie/Seagate boards
+(Example: 2Big/5Big Network v2, 2Big NAS).
+
+Required properties:
+- compatible: "lacie,netxbig-gpio-ext".
+- addr-gpios: GPIOs representing the address register (LSB -> MSB).
+- data-gpios: GPIOs representing the data register (LSB -> MSB).
+- enable-gpio: latches the new configuration (address, data) on raising edge.
+
+Example:
+
+netxbig_gpio_ext: netxbig-gpio-ext {
+ compatible = "lacie,netxbig-gpio-ext";
+
+ addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH
+ &gpio1 16 GPIO_ACTIVE_HIGH
+ &gpio1 17 GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH
+ &gpio1 13 GPIO_ACTIVE_HIGH
+ &gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+};
diff --git a/dts/Bindings/hwmon/ina209.txt b/dts/Bindings/hwmon/ina209.txt
deleted file mode 100644
index 9dd2bee..0000000
--- a/dts/Bindings/hwmon/ina209.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-ina209 properties
-
-Required properties:
-- compatible: Must be "ti,ina209"
-- reg: I2C address
-
-Optional properties:
-
-- shunt-resistor
- Shunt resistor value in micro-Ohm
-
-Example:
-
-temp-sensor@4c {
- compatible = "ti,ina209";
- reg = <0x4c>;
- shunt-resistor = <5000>;
-};
diff --git a/dts/Bindings/hwmon/ina2xx.txt b/dts/Bindings/hwmon/ina2xx.txt
index a2ad85d..9bcd5e8 100644
--- a/dts/Bindings/hwmon/ina2xx.txt
+++ b/dts/Bindings/hwmon/ina2xx.txt
@@ -2,6 +2,7 @@ ina2xx properties
Required properties:
- compatible: Must be one of the following:
+ - "ti,ina209" for ina209
- "ti,ina219" for ina219
- "ti,ina220" for ina220
- "ti,ina226" for ina226
diff --git a/dts/Bindings/hwmon/pwm-fan.txt b/dts/Bindings/hwmon/pwm-fan.txt
index 610757c..c6d5332 100644
--- a/dts/Bindings/hwmon/pwm-fan.txt
+++ b/dts/Bindings/hwmon/pwm-fan.txt
@@ -3,10 +3,35 @@ Bindings for a fan connected to the PWM lines
Required properties:
- compatible : "pwm-fan"
- pwms : the PWM that is used to control the PWM fan
+- cooling-levels : PWM duty cycle values in a range from 0 to 255
+ which correspond to thermal cooling states
Example:
- pwm-fan {
+ fan0: pwm-fan {
compatible = "pwm-fan";
- status = "okay";
+ cooling-min-state = <0>;
+ cooling-max-state = <3>;
+ #cooling-cells = <2>;
pwms = <&pwm 0 10000 0>;
+ cooling-levels = <0 102 170 230>;
};
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ thermal-sensors = <&tmu 0>;
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ trips {
+ cpu_alert1: cpu-alert1 {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&fan0 0 1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/i2c/i2c-davinci.txt b/dts/Bindings/i2c/i2c-davinci.txt
index a4e1cbc..5b123e0 100644
--- a/dts/Bindings/i2c/i2c-davinci.txt
+++ b/dts/Bindings/i2c/i2c-davinci.txt
@@ -1,10 +1,10 @@
-* Texas Instruments Davinci I2C
+* Texas Instruments Davinci/Keystone I2C
This file provides information, what the device node for the
-davinci i2c interface contain.
+davinci/keystone i2c interface contains.
Required properties:
-- compatible: "ti,davinci-i2c";
+- compatible: "ti,davinci-i2c" or "ti,keystone-i2c";
- reg : Offset and length of the register set for the device
Recommended properties :
diff --git a/dts/Bindings/i2c/i2c-imx.txt b/dts/Bindings/i2c/i2c-imx.txt
index ce4311d..eab5836 100644
--- a/dts/Bindings/i2c/i2c-imx.txt
+++ b/dts/Bindings/i2c/i2c-imx.txt
@@ -14,6 +14,10 @@ Optional properties:
The absence of the propoerty indicates the default frequency 100 kHz.
- dmas: A list of two dma specifiers, one for each entry in dma-names.
- dma-names: should contain "tx" and "rx".
+- scl-gpios: specify the gpio related to SCL pin
+- sda-gpios: specify the gpio related to SDA pin
+- pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c
+ bus recovery, call it "gpio" state
Examples:
@@ -37,4 +41,9 @@ i2c0: i2c@40066000 { /* i2c0 on vf610 */
dmas = <&edma0 0 50>,
<&edma0 0 51>;
dma-names = "rx","tx";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/Bindings/i2c/i2c-rcar.txt b/dts/Bindings/i2c/i2c-rcar.txt
index 16b3e07..ea406eb 100644
--- a/dts/Bindings/i2c/i2c-rcar.txt
+++ b/dts/Bindings/i2c/i2c-rcar.txt
@@ -10,6 +10,7 @@ Required properties:
"renesas,i2c-r8a7792"
"renesas,i2c-r8a7793"
"renesas,i2c-r8a7794"
+ "renesas,i2c-r8a7795"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt specifier.
diff --git a/dts/Bindings/i2c/i2c-sh_mobile.txt b/dts/Bindings/i2c/i2c-sh_mobile.txt
index 2bfc6e7..214f94c 100644
--- a/dts/Bindings/i2c/i2c-sh_mobile.txt
+++ b/dts/Bindings/i2c/i2c-sh_mobile.txt
@@ -10,6 +10,7 @@ Required properties:
- "renesas,iic-r8a7792" (R-Car V2H)
- "renesas,iic-r8a7793" (R-Car M2-N)
- "renesas,iic-r8a7794" (R-Car E2)
+ - "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- reg : address start and address range size of device
- interrupts : interrupt of device
diff --git a/dts/Bindings/i2c/i2c-uniphier-f.txt b/dts/Bindings/i2c/i2c-uniphier-f.txt
new file mode 100644
index 0000000..27fc6f8
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-uniphier-f.txt
@@ -0,0 +1,25 @@
+UniPhier I2C controller (FIFO-builtin)
+
+Required properties:
+- compatible: should be "socionext,uniphier-fi2c".
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- reg: offset and length of the register set for the device.
+- interrupts: a single interrupt specifier.
+- clocks: phandle to the input clock.
+
+Optional properties:
+- clock-frequency: desired I2C bus frequency in Hz. The maximum supported
+ value is 400000. Defaults to 100000 if not specified.
+
+Examples:
+
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
diff --git a/dts/Bindings/i2c/i2c-uniphier.txt b/dts/Bindings/i2c/i2c-uniphier.txt
new file mode 100644
index 0000000..26f9d95
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-uniphier.txt
@@ -0,0 +1,25 @@
+UniPhier I2C controller (FIFO-less)
+
+Required properties:
+- compatible: should be "socionext,uniphier-i2c".
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- reg: offset and length of the register set for the device.
+- interrupts: a single interrupt specifier.
+- clocks: phandle to the input clock.
+
+Optional properties:
+- clock-frequency: desired I2C bus frequency in Hz. The maximum supported
+ value is 400000. Defaults to 100000 if not specified.
+
+Examples:
+
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
diff --git a/dts/Bindings/i2c/trivial-devices.txt b/dts/Bindings/i2c/trivial-devices.txt
index d77d412..c50cf13 100644
--- a/dts/Bindings/i2c/trivial-devices.txt
+++ b/dts/Bindings/i2c/trivial-devices.txt
@@ -54,7 +54,6 @@ epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51
fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
-fsl,mma8452 MMA8452Q: 3-axis 12-bit / 8-bit Digital Accelerometer
fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller
fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
@@ -80,6 +79,7 @@ oki,ml86v7667 OKI ML86V7667 video decoder
ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
pericom,pt7c4338 Real-time Clock Module
plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
+pulsedlight,lidar-lite-v2 Pulsedlight LIDAR range-finding sensor
ramtron,24c64 i2c serial eeprom (24cxx)
ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
@@ -88,6 +88,7 @@ ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
+sgx,vz89x SGX Sensortech VZ89X Sensors
sii,s35390a 2-wire CMOS real-time clock
skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
st-micro,24c256 i2c serial eeprom (24cxx)
diff --git a/dts/Bindings/misc/lis302.txt b/dts/Bindings/iio/accel/lis302.txt
index 2a19bff..2a19bff 100644
--- a/dts/Bindings/misc/lis302.txt
+++ b/dts/Bindings/iio/accel/lis302.txt
diff --git a/dts/Bindings/iio/accel/mma8452.txt b/dts/Bindings/iio/accel/mma8452.txt
new file mode 100644
index 0000000..e3c3746
--- /dev/null
+++ b/dts/Bindings/iio/accel/mma8452.txt
@@ -0,0 +1,24 @@
+Freescale MMA8452Q, MMA8453Q, MMA8652FC or MMA8653FC triaxial accelerometer
+
+Required properties:
+
+ - compatible: should contain one of
+ * "fsl,mma8452"
+ * "fsl,mma8453"
+ * "fsl,mma8652"
+ * "fsl,mma8653"
+ - reg: the I2C address of the chip
+
+Optional properties:
+
+ - interrupt-parent: should be the phandle for the interrupt controller
+ - interrupts: interrupt mapping for GPIO IRQ
+
+Example:
+
+ mma8453fc@1d {
+ compatible = "fsl,mma8453";
+ reg = <0x1d>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <5 0>;
+ };
diff --git a/dts/Bindings/iio/adc/hi8435.txt b/dts/Bindings/iio/adc/hi8435.txt
new file mode 100644
index 0000000..3b0348c
--- /dev/null
+++ b/dts/Bindings/iio/adc/hi8435.txt
@@ -0,0 +1,21 @@
+Holt Integrated Circuits HI-8435 threshold detector bindings
+
+Required properties:
+ - compatible: should be "holt,hi8435"
+ - reg: spi chip select number for the device
+
+Recommended properties:
+ - spi-max-frequency: definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+ - gpios: GPIO used for controlling the reset pin
+
+Example:
+sensor@0 {
+ compatible = "holt,hi8435";
+ reg = <0>;
+ gpios = <&gpio6 1 0>;
+
+ spi-max-frequency = <1000000>;
+};
diff --git a/dts/Bindings/misc/ti,dac7512.txt b/dts/Bindings/iio/dac/ti,dac7512.txt
index 1db4593..1db4593 100644
--- a/dts/Bindings/misc/ti,dac7512.txt
+++ b/dts/Bindings/iio/dac/ti,dac7512.txt
diff --git a/dts/Bindings/iio/light/apds9960.txt b/dts/Bindings/iio/light/apds9960.txt
new file mode 100644
index 0000000..174b709
--- /dev/null
+++ b/dts/Bindings/iio/light/apds9960.txt
@@ -0,0 +1,22 @@
+* Avago APDS9960 gesture/RGB/ALS/proximity sensor
+
+http://www.avagotech.com/docs/AV02-4191EN
+
+Required properties:
+
+ - compatible: must be "avago,apds9960"
+ - reg: the I2c address of the sensor
+ - interrupt-parent: should be the phandle for the interrupt controller
+ - interrupts : the sole interrupt generated by the device
+
+ Refer to interrupt-controller/interrupts.txt for generic interrupt client
+ node bindings.
+
+Example:
+
+apds9960@39 {
+ compatible = "avago,apds9960";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 1>;
+};
diff --git a/dts/Bindings/iio/light/us5182d.txt b/dts/Bindings/iio/light/us5182d.txt
new file mode 100644
index 0000000..6f0a530
--- /dev/null
+++ b/dts/Bindings/iio/light/us5182d.txt
@@ -0,0 +1,34 @@
+* UPISEMI us5182d I2C ALS and Proximity sensor
+
+Required properties:
+- compatible: must be "upisemi,usd5182"
+- reg: the I2C address of the device
+
+Optional properties:
+- upisemi,glass-coef: glass attenuation factor - compensation factor of
+ resolution 1000 for material transmittance.
+- upisemi,dark-ths: array of 8 elements containing 16-bit thresholds (adc
+ counts) corresponding to every scale.
+- upisemi,upper-dark-gain: 8-bit dark gain compensation factor(4 int and 4
+ fractional bits - Q4.4) applied when light > threshold
+- upisemi,lower-dark-gain: 8-bit dark gain compensation factor(4 int and 4
+ fractional bits - Q4.4) applied when light < threshold
+
+If the optional properties are not specified these factors will default to the
+values in the below example.
+The glass-coef defaults to no compensation for the covering material.
+The threshold array defaults to experimental values that work with US5182D
+sensor on evaluation board - roughly between 12-32 lux.
+There will be no dark-gain compensation by default when ALS > thresh
+(0 * dark-gain), and a 1.35 compensation factor when ALS < thresh.
+
+Example:
+
+ usd5182@39 {
+ compatible = "upisemi,usd5182";
+ reg = <0x39>;
+ upisemi,glass-coef = < 1000 >;
+ upisemi,dark-ths = /bits/ 16 <170 200 512 512 800 2000 4000 8000>;
+ upisemi,upper-dark-gain = /bits/ 8 <0x00>;
+ upisemi,lower-dark-gain = /bits/ 8 <0x16>;
+ };
diff --git a/dts/Bindings/misc/bmp085.txt b/dts/Bindings/iio/pressure/bmp085.txt
index d7a6deb..d7a6deb 100644
--- a/dts/Bindings/misc/bmp085.txt
+++ b/dts/Bindings/iio/pressure/bmp085.txt
diff --git a/dts/Bindings/input/ads7846.txt b/dts/Bindings/input/ads7846.txt
index df8b127..33a1638 100644
--- a/dts/Bindings/input/ads7846.txt
+++ b/dts/Bindings/input/ads7846.txt
@@ -65,6 +65,7 @@ Optional properties:
pendown-gpio GPIO handle describing the pin the !PENIRQ
line is connected to.
wakeup-source use any event on touchscreen as wakeup event.
+ (Legacy property support: "linux,wakeup")
Example for a TSC2046 chip connected to an McSPI controller of an OMAP SoC::
@@ -86,6 +87,6 @@ Example for a TSC2046 chip connected to an McSPI controller of an OMAP SoC::
ti,x-plate-ohms = /bits/ 16 <40>;
ti,pressure-max = /bits/ 16 <255>;
- linux,wakeup;
+ wakeup-source;
};
};
diff --git a/dts/Bindings/input/da9062-onkey.txt b/dts/Bindings/input/da9062-onkey.txt
new file mode 100644
index 0000000..ab0e048
--- /dev/null
+++ b/dts/Bindings/input/da9062-onkey.txt
@@ -0,0 +1,32 @@
+* Dialog DA9062/63 OnKey Module
+
+This module is part of the DA9062/DA9063. For more details about entire
+chips see Documentation/devicetree/bindings/mfd/da9062.txt and
+Documentation/devicetree/bindings/mfd/da9063.txt
+
+This module provides KEY_POWER, KEY_SLEEP and events.
+
+Required properties:
+
+- compatible: should be one of:
+ dlg,da9062-onkey
+ dlg,da9063-onkey
+
+Optional properties:
+
+ - dlg,disable-key-power : Disable power-down using a long key-press. If this
+ entry exists the OnKey driver will remove support for the KEY_POWER key
+ press. If this entry does not exist then by default the key-press
+ triggered power down is enabled and the OnKey will support both KEY_POWER
+ and KEY_SLEEP.
+
+Example:
+
+ pmic0: da9062@58 {
+
+ onkey {
+ compatible = "dlg,da9063-onkey";
+ dlg,disable-key-power;
+ };
+
+ };
diff --git a/dts/Bindings/input/gpio-keys-polled.txt b/dts/Bindings/input/gpio-keys-polled.txt
index 5b91f5a..95d0fb1 100644
--- a/dts/Bindings/input/gpio-keys-polled.txt
+++ b/dts/Bindings/input/gpio-keys-polled.txt
@@ -13,14 +13,22 @@ Subnode properties:
- gpios: OF device-tree gpio specification.
- label: Descriptive name of the key.
- - linux,code: Keycode to emit.
+ - linux,code: Key / Axis code to emit.
Optional subnode-properties:
- linux,input-type: Specify event type this button/key generates.
If not specified defaults to <1> == EV_KEY.
+ - linux,input-value: If linux,input-type is EV_ABS or EV_REL then this
+ value is sent for events this button generates when pressed.
+ EV_ABS/EV_REL axis will generate an event with a value of 0 when
+ all buttons with linux,input-type == type and linux,code == axis
+ are released. This value is interpreted as a signed 32 bit value,
+ e.g. to make a button generate a value of -1 use:
+ linux,input-value = <0xffffffff>; /* -1 */
- debounce-interval: Debouncing interval time in milliseconds.
If not specified defaults to 5.
- wakeup-source: Boolean, button can wake-up the system.
+ (Legacy property supported: "gpio-key,wakeup")
Example nodes:
diff --git a/dts/Bindings/input/gpio-keys.txt b/dts/Bindings/input/gpio-keys.txt
index 072bf75..cf1333d 100644
--- a/dts/Bindings/input/gpio-keys.txt
+++ b/dts/Bindings/input/gpio-keys.txt
@@ -24,6 +24,7 @@ Optional subnode-properties:
- debounce-interval: Debouncing interval time in milliseconds.
If not specified defaults to 5.
- wakeup-source: Boolean, button can wake-up the system.
+ (Legacy property supported: "gpio-key,wakeup")
- linux,can-disable: Boolean, indicates that button is connected
to dedicated (not shared) interrupt which can be disabled to
suppress events from the button.
diff --git a/dts/Bindings/input/gpio-matrix-keypad.txt b/dts/Bindings/input/gpio-matrix-keypad.txt
index 4d86059..d0ea09b 100644
--- a/dts/Bindings/input/gpio-matrix-keypad.txt
+++ b/dts/Bindings/input/gpio-matrix-keypad.txt
@@ -20,6 +20,7 @@ Required Properties:
Optional Properties:
- linux,no-autorepeat: do no enable autorepeat feature.
- wakeup-source: use any event on keypad as wakeup event.
+ (Legacy property supported: "linux,wakeup")
- debounce-delay-ms: debounce interval in milliseconds
- col-scan-delay-us: delay, measured in microseconds, that is needed
before we can scan keypad after activating column gpio
diff --git a/dts/Bindings/hid/hid-over-i2c.txt b/dts/Bindings/input/hid-over-i2c.txt
index 488edcb..488edcb 100644
--- a/dts/Bindings/hid/hid-over-i2c.txt
+++ b/dts/Bindings/input/hid-over-i2c.txt
diff --git a/dts/Bindings/input/nvidia,tegra20-kbc.txt b/dts/Bindings/input/nvidia,tegra20-kbc.txt
index 0382b8b..1faa729 100644
--- a/dts/Bindings/input/nvidia,tegra20-kbc.txt
+++ b/dts/Bindings/input/nvidia,tegra20-kbc.txt
@@ -29,7 +29,8 @@ matrix-keyboard bindings:
- nvidia,debounce-delay-ms: delay in milliseconds per row scan for debouncing
- nvidia,repeat-delay-ms: delay in milliseconds before repeat starts
- nvidia,ghost-filter: enable ghost filtering for this device
-- nvidia,wakeup-source: configure keyboard as a wakeup source for suspend/resume
+- wakeup-source: configure keyboard as a wakeup source for suspend/resume
+ (Legacy property supported: "nvidia,wakeup-source")
Example:
diff --git a/dts/Bindings/input/qcom,pm8xxx-keypad.txt b/dts/Bindings/input/qcom,pm8xxx-keypad.txt
index ee62156..4a9dc6b 100644
--- a/dts/Bindings/input/qcom,pm8xxx-keypad.txt
+++ b/dts/Bindings/input/qcom,pm8xxx-keypad.txt
@@ -37,6 +37,7 @@ PROPERTIES
Usage: optional
Value type: <bool>
Definition: use any event on keypad as wakeup event.
+ (Legacy property supported: "linux,keypad-wakeup")
- keypad,num-rows:
Usage: required
diff --git a/dts/Bindings/input/rotary-encoder.txt b/dts/Bindings/input/rotary-encoder.txt
index 3315495..de99cbb 100644
--- a/dts/Bindings/input/rotary-encoder.txt
+++ b/dts/Bindings/input/rotary-encoder.txt
@@ -14,7 +14,17 @@ Optional properties:
device, hence no steps need to be passed.
- rotary-encoder,rollover: Automatic rollove when the rotary value becomes
greater than the specified steps or smaller than 0. For absolute axis only.
+- rotary-encoder,steps-per-period: Number of steps (stable states) per period.
+ The values have the following meaning:
+ 1: Full-period mode (default)
+ 2: Half-period mode
+ 4: Quarter-period mode
+- wakeup-source: Boolean, rotary encoder can wake up the system.
+
+Deprecated properties:
- rotary-encoder,half-period: Makes the driver work on half-period mode.
+ This property is deprecated. Instead, a 'steps-per-period ' value should
+ be used, such as "rotary-encoder,steps-per-period = <2>".
See Documentation/input/rotary-encoder.txt for more information.
diff --git a/dts/Bindings/input/samsung-keypad.txt b/dts/Bindings/input/samsung-keypad.txt
index 863e77f..5305e74 100644
--- a/dts/Bindings/input/samsung-keypad.txt
+++ b/dts/Bindings/input/samsung-keypad.txt
@@ -38,6 +38,7 @@ Required Board Specific Properties:
Optional Properties:
- wakeup-source: use any event on keypad as wakeup event.
+ (Legacy property supported: "linux,input-wakeup")
Optional Properties specific to linux:
- linux,keypad-no-autorepeat: do no enable autorepeat feature.
@@ -51,7 +52,7 @@ Example:
samsung,keypad-num-rows = <2>;
samsung,keypad-num-columns = <8>;
linux,input-no-autorepeat;
- linux,input-wakeup;
+ wakeup-source;
pinctrl-names = "default";
pinctrl-0 = <&keypad_rows &keypad_columns>;
diff --git a/dts/Bindings/input/touchscreen/edt-ft5x06.txt b/dts/Bindings/input/touchscreen/edt-ft5x06.txt
index 76db967..f99528d 100644
--- a/dts/Bindings/input/touchscreen/edt-ft5x06.txt
+++ b/dts/Bindings/input/touchscreen/edt-ft5x06.txt
@@ -5,6 +5,7 @@ There are 3 variants of the chip for various touch panel sizes
FT5206GE1 2.8" .. 3.8"
FT5306DE4 4.3" .. 7"
FT5406EE8 7" .. 8.9"
+FT5506EEG 7" .. 8.9"
The software interface is identical for all those chips, so that
currently there is no need for the driver to distinguish between the
@@ -17,6 +18,7 @@ Required properties:
- compatible: "edt,edt-ft5206"
or: "edt,edt-ft5306"
or: "edt,edt-ft5406"
+ or: "edt,edt-ft5506"
- reg: I2C slave address of the chip (0x38)
- interrupt-parent: a phandle pointing to the interrupt controller
@@ -49,7 +51,7 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&edt_ft5x06_pins>;
interrupt-parent = <&gpio2>;
- interrupts = <5 0>;
- reset-gpios = <&gpio2 6 1>;
- wake-gpios = <&gpio4 9 0>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/Bindings/input/touchscreen/focaltech-ft6236.txt b/dts/Bindings/input/touchscreen/focaltech-ft6236.txt
new file mode 100644
index 0000000..777521d
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/focaltech-ft6236.txt
@@ -0,0 +1,35 @@
+* FocalTech FT6236 I2C touchscreen controller
+
+Required properties:
+ - compatible : "focaltech,ft6236"
+ - reg : I2C slave address of the chip (0x38)
+ - interrupt-parent : a phandle pointing to the interrupt controller
+ serving the interrupt for this chip
+ - interrupts : interrupt specification for the touch controller
+ interrupt
+ - reset-gpios : GPIO specification for the RSTN input
+ - touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
+ - touchscreen-size-y : vertical resolution of touchscreen (in pixels)
+
+Optional properties:
+ - touchscreen-fuzz-x : horizontal noise value of the absolute input
+ device (in pixels)
+ - touchscreen-fuzz-y : vertical noise value of the absolute input
+ device (in pixels)
+ - touchscreen-inverted-x : X axis is inverted (boolean)
+ - touchscreen-inverted-y : Y axis is inverted (boolean)
+ - touchscreen-swapped-x-y: X and Y axis are swapped (boolean)
+ Swapping is done after inverting the axis
+
+Example:
+
+ ft6x06@38 {
+ compatible = "focaltech,ft6236";
+ reg = <0x38>;
+ interrupt-parent = <&gpio>;
+ interrupts = <23 2>;
+ touchscreen-size-x = <320>;
+ touchscreen-size-y = <480>;
+ touchscreen-inverted-x;
+ touchscreen-swapped-x-y;
+ };
diff --git a/dts/Bindings/input/touchscreen/tsc2005.txt b/dts/Bindings/input/touchscreen/tsc2005.txt
index 09089a6..b80c04b 100644
--- a/dts/Bindings/input/touchscreen/tsc2005.txt
+++ b/dts/Bindings/input/touchscreen/tsc2005.txt
@@ -1,14 +1,15 @@
-* Texas Instruments tsc2005 touchscreen controller
+* Texas Instruments tsc2004 and tsc2005 touchscreen controllers
Required properties:
- - compatible : "ti,tsc2005"
- - reg : SPI device address
- - spi-max-frequency : Maximal SPI speed
+ - compatible : "ti,tsc2004" or "ti,tsc2005"
+ - reg : Device address
- interrupts : IRQ specifier
- - reset-gpios : GPIO specifier
- - vio-supply : Regulator specifier
+ - spi-max-frequency : Maximum SPI clocking speed of the device
+ (for tsc2005)
Optional properties:
+ - vio-supply : Regulator specifier
+ - reset-gpios : GPIO specifier for the controller reset line
- ti,x-plate-ohms : integer, resistance of the touchscreen's X plates
in ohm (defaults to 280)
- ti,esd-recovery-timeout-ms : integer, if the touchscreen does not respond after
@@ -18,6 +19,27 @@ Optional properties:
Example:
+&i2c3 {
+ tsc2004@48 {
+ compatible = "ti,tsc2004";
+ reg = <0x48>;
+ vio-supply = <&vio>;
+
+ reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+ interrupts-extended = <&gpio1 27 IRQ_TYPE_EDGE_RISING>;
+
+ touchscreen-fuzz-x = <4>;
+ touchscreen-fuzz-y = <7>;
+ touchscreen-fuzz-pressure = <2>;
+ touchscreen-size-x = <4096>;
+ touchscreen-size-y = <4096>;
+ touchscreen-max-pressure = <2048>;
+
+ ti,x-plate-ohms = <280>;
+ ti,esd-recovery-timeout-ms = <8000>;
+ };
+}
+
&mcspi1 {
tsc2005@0 {
compatible = "ti,tsc2005";
diff --git a/dts/Bindings/arm/gic-v3.txt b/dts/Bindings/interrupt-controller/arm,gic-v3.txt
index 7803e77..7803e77 100644
--- a/dts/Bindings/arm/gic-v3.txt
+++ b/dts/Bindings/interrupt-controller/arm,gic-v3.txt
diff --git a/dts/Bindings/arm/gic.txt b/dts/Bindings/interrupt-controller/arm,gic.txt
index 2da059a..cc56021 100644
--- a/dts/Bindings/arm/gic.txt
+++ b/dts/Bindings/interrupt-controller/arm,gic.txt
@@ -11,13 +11,14 @@ have PPIs or SGIs.
Main node required properties:
- compatible : should be one of:
- "arm,gic-400"
+ "arm,arm1176jzf-devchip-gic"
+ "arm,arm11mp-gic"
"arm,cortex-a15-gic"
- "arm,cortex-a9-gic"
"arm,cortex-a7-gic"
- "arm,arm11mp-gic"
+ "arm,cortex-a9-gic"
+ "arm,gic-400"
+ "arm,pl390"
"brcm,brahma-b15-gic"
- "arm,arm1176jzf-devchip-gic"
"qcom,msm-8660-qgic"
"qcom,msm-qgic2"
- interrupt-controller : Identifies the node as an interrupt controller
@@ -58,6 +59,21 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
+- clocks : List of phandle and clock-specific pairs, one for each entry
+ in clock-names.
+- clock-names : List of names for the GIC clock input(s). Valid clock names
+ depend on the GIC variant:
+ "ic_clk" (for "arm,arm11mp-gic")
+ "PERIPHCLKEN" (for "arm,cortex-a15-gic")
+ "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
+ "clk" (for "arm,gic-400")
+ "gclk" (for "arm,pl390")
+
+- power-domains : A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle, used when the GIC
+ is part of a Power or Clock Domain.
+
+
Example:
intc: interrupt-controller@fff11000 {
diff --git a/dts/Bindings/arm/versatile-fpga-irq.txt b/dts/Bindings/interrupt-controller/arm,versatile-fpga-irq.txt
index c9cf605..c9cf605 100644
--- a/dts/Bindings/arm/versatile-fpga-irq.txt
+++ b/dts/Bindings/interrupt-controller/arm,versatile-fpga-irq.txt
diff --git a/dts/Bindings/arm/vic.txt b/dts/Bindings/interrupt-controller/arm,vic.txt
index dd52721..dd52721 100644
--- a/dts/Bindings/arm/vic.txt
+++ b/dts/Bindings/interrupt-controller/arm,vic.txt
diff --git a/dts/Bindings/cris/interrupts.txt b/dts/Bindings/interrupt-controller/axis,crisv32-intc.txt
index e8b123b..e8b123b 100644
--- a/dts/Bindings/cris/interrupts.txt
+++ b/dts/Bindings/interrupt-controller/axis,crisv32-intc.txt
diff --git a/dts/Bindings/metag/meta-intc.txt b/dts/Bindings/interrupt-controller/img,meta-intc.txt
index 80994ad..80994ad 100644
--- a/dts/Bindings/metag/meta-intc.txt
+++ b/dts/Bindings/interrupt-controller/img,meta-intc.txt
diff --git a/dts/Bindings/metag/pdc-intc.txt b/dts/Bindings/interrupt-controller/img,pdc-intc.txt
index a691185..a691185 100644
--- a/dts/Bindings/metag/pdc-intc.txt
+++ b/dts/Bindings/interrupt-controller/img,pdc-intc.txt
diff --git a/dts/Bindings/x86/interrupt.txt b/dts/Bindings/interrupt-controller/intel,ce4100-ioapic.txt
index 7d19f49..7d19f49 100644
--- a/dts/Bindings/x86/interrupt.txt
+++ b/dts/Bindings/interrupt-controller/intel,ce4100-ioapic.txt
diff --git a/dts/Bindings/arm/mediatek/mediatek,sysirq.txt b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
index afef6a8..afef6a8 100644
--- a/dts/Bindings/arm/mediatek/mediatek,sysirq.txt
+++ b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
diff --git a/dts/Bindings/arm/mrvl/intc.txt b/dts/Bindings/interrupt-controller/mrvl,intc.txt
index 8b53273..8b53273 100644
--- a/dts/Bindings/arm/mrvl/intc.txt
+++ b/dts/Bindings/interrupt-controller/mrvl,intc.txt
diff --git a/dts/Bindings/arm/lpc32xx-mic.txt b/dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt
index 539adca..539adca 100644
--- a/dts/Bindings/arm/lpc32xx-mic.txt
+++ b/dts/Bindings/interrupt-controller/nxp,lpc3220-mic.txt
diff --git a/dts/Bindings/open-pic.txt b/dts/Bindings/interrupt-controller/open-pic.txt
index 909a902..909a902 100644
--- a/dts/Bindings/open-pic.txt
+++ b/dts/Bindings/interrupt-controller/open-pic.txt
diff --git a/dts/Bindings/interrupt-controller/renesas,irqc.txt b/dts/Bindings/interrupt-controller/renesas,irqc.txt
index 63633bd..ae5054c 100644
--- a/dts/Bindings/interrupt-controller/renesas,irqc.txt
+++ b/dts/Bindings/interrupt-controller/renesas,irqc.txt
@@ -10,6 +10,7 @@ Required properties:
- "renesas,irqc-r8a7792" (R-Car V2H)
- "renesas,irqc-r8a7793" (R-Car M2-N)
- "renesas,irqc-r8a7794" (R-Car E2)
+ - "renesas,intc-ex-r8a7795" (R-Car H3)
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
interrupts.txt in this directory
- clocks: Must contain a reference to the functional clock.
diff --git a/dts/Bindings/arm/samsung/interrupt-combiner.txt b/dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt
index 9e5f734..9e5f734 100644
--- a/dts/Bindings/arm/samsung/interrupt-combiner.txt
+++ b/dts/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt
diff --git a/dts/Bindings/arc/interrupts.txt b/dts/Bindings/interrupt-controller/snps,arc700-intc.txt
index 9a5d562..9a5d562 100644
--- a/dts/Bindings/arc/interrupts.txt
+++ b/dts/Bindings/interrupt-controller/snps,arc700-intc.txt
diff --git a/dts/Bindings/arc/archs-idu-intc.txt b/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt
index 0dcb7c7..0dcb7c7 100644
--- a/dts/Bindings/arc/archs-idu-intc.txt
+++ b/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt
diff --git a/dts/Bindings/arc/archs-intc.txt b/dts/Bindings/interrupt-controller/snps,archs-intc.txt
index 69f326d..69f326d 100644
--- a/dts/Bindings/arc/archs-intc.txt
+++ b/dts/Bindings/interrupt-controller/snps,archs-intc.txt
diff --git a/dts/Bindings/arm/spear/shirq.txt b/dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt
index 715a013..715a013 100644
--- a/dts/Bindings/arm/spear/shirq.txt
+++ b/dts/Bindings/interrupt-controller/st,spear3xx-shirq.txt
diff --git a/dts/Bindings/c6x/interrupt.txt b/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt
index 42bb796..42bb796 100644
--- a/dts/Bindings/c6x/interrupt.txt
+++ b/dts/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt
diff --git a/dts/Bindings/arm/davinci/cp-intc.txt b/dts/Bindings/interrupt-controller/ti,cp-intc.txt
index 597e8a0..597e8a0 100644
--- a/dts/Bindings/arm/davinci/cp-intc.txt
+++ b/dts/Bindings/interrupt-controller/ti,cp-intc.txt
diff --git a/dts/Bindings/arm/omap/intc.txt b/dts/Bindings/interrupt-controller/ti,omap2-intc.txt
index f2583e6..f2583e6 100644
--- a/dts/Bindings/arm/omap/intc.txt
+++ b/dts/Bindings/interrupt-controller/ti,omap2-intc.txt
diff --git a/dts/Bindings/arm/vt8500/via,vt8500-intc.txt b/dts/Bindings/interrupt-controller/via,vt8500-intc.txt
index 0a4ce10..0a4ce10 100644
--- a/dts/Bindings/arm/vt8500/via,vt8500-intc.txt
+++ b/dts/Bindings/interrupt-controller/via,vt8500-intc.txt
diff --git a/dts/Bindings/iommu/arm,smmu-v3.txt b/dts/Bindings/iommu/arm,smmu-v3.txt
index 3443e0f..947863a 100644
--- a/dts/Bindings/iommu/arm,smmu-v3.txt
+++ b/dts/Bindings/iommu/arm,smmu-v3.txt
@@ -36,5 +36,24 @@ the PCIe specification.
NOTE: this only applies to the SMMU itself, not
masters connected upstream of the SMMU.
+- msi-parent : See the generic MSI binding described in
+ devicetree/bindings/interrupt-controller/msi.txt
+ for a description of the msi-parent property.
+
- hisilicon,broken-prefetch-cmd
: Avoid sending CMD_PREFETCH_* commands to the SMMU.
+
+** Example
+
+ smmu@2b400000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x2b400000 0x0 0x20000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+ dma-coherent;
+ #iommu-cells = <0>;
+ msi-parent = <&its 0xff0000>;
+ };
diff --git a/dts/Bindings/iommu/samsung,sysmmu.txt b/dts/Bindings/iommu/samsung,sysmmu.txt
index 729543c..bc620fe 100644
--- a/dts/Bindings/iommu/samsung,sysmmu.txt
+++ b/dts/Bindings/iommu/samsung,sysmmu.txt
@@ -47,7 +47,7 @@ Required properties:
- clocks: Required if the System MMU is needed to gate its clock.
- power-domains: Required if the System MMU is needed to gate its power.
Please refer to the following document:
- Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+ Documentation/devicetree/bindings/power/pd-samsung.txt
Examples:
gsc_0: gsc@13e00000 {
diff --git a/dts/Bindings/iommu/ti,omap-iommu.txt b/dts/Bindings/iommu/ti,omap-iommu.txt
index 8696999..4bd10dd 100644
--- a/dts/Bindings/iommu/ti,omap-iommu.txt
+++ b/dts/Bindings/iommu/ti,omap-iommu.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible : Should be one of,
"ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
"ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
+ "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
"ti,dra7-iommu" for DRA7xx IOMMU instances
- ti,hwmods : Name of the hwmod associated with the IOMMU instance
- reg : Address space for the configuration registers
@@ -19,6 +20,13 @@ Optional properties:
Should be either 8 or 32 (default: 32)
- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
back a bus error response on MMU faults.
+- ti,syscon-mmuconfig : Should be a pair of the phandle to the DSP_SYSTEM
+ syscon node that contains the additional control
+ register for enabling the MMU, and the MMU instance
+ number (0-indexed) within the sub-system. This property
+ is required for DSP IOMMU instances on DRA7xx SoCs. The
+ instance number should be 0 for DSP MDMA MMUs and 1 for
+ DSP EDMA MMUs.
Example:
/* OMAP3 ISP MMU */
@@ -30,3 +38,22 @@ Example:
ti,hwmods = "mmu_isp";
ti,#tlb-entries = <8>;
};
+
+ /* DRA74x DSP2 MMUs */
+ mmu0_dsp2: mmu@41501000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x41501000 0x100>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu0_dsp2";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x0>;
+ };
+
+ mmu1_dsp2: mmu@41502000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x41502000 0x100>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu1_dsp2";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x1>;
+ };
diff --git a/dts/Bindings/video/backlight/88pm860x.txt b/dts/Bindings/leds/backlight/88pm860x.txt
index 261df27..261df27 100644
--- a/dts/Bindings/video/backlight/88pm860x.txt
+++ b/dts/Bindings/leds/backlight/88pm860x.txt
diff --git a/dts/Bindings/video/backlight/gpio-backlight.txt b/dts/Bindings/leds/backlight/gpio-backlight.txt
index 321be66..321be66 100644
--- a/dts/Bindings/video/backlight/gpio-backlight.txt
+++ b/dts/Bindings/leds/backlight/gpio-backlight.txt
diff --git a/dts/Bindings/video/backlight/lp855x.txt b/dts/Bindings/leds/backlight/lp855x.txt
index 0a3ecbc..0a3ecbc 100644
--- a/dts/Bindings/video/backlight/lp855x.txt
+++ b/dts/Bindings/leds/backlight/lp855x.txt
diff --git a/dts/Bindings/video/backlight/max8925-backlight.txt b/dts/Bindings/leds/backlight/max8925-backlight.txt
index b4cffda..b4cffda 100644
--- a/dts/Bindings/video/backlight/max8925-backlight.txt
+++ b/dts/Bindings/leds/backlight/max8925-backlight.txt
diff --git a/dts/Bindings/video/backlight/pm8941-wled.txt b/dts/Bindings/leds/backlight/pm8941-wled.txt
index 424f844..e5b294d 100644
--- a/dts/Bindings/video/backlight/pm8941-wled.txt
+++ b/dts/Bindings/leds/backlight/pm8941-wled.txt
@@ -5,6 +5,8 @@ Required properties:
- reg: slave address
Optional properties:
+- default-brightness: brightness value on boot, value from: 0-4095
+ default: 2048
- label: The name of the backlight device
- qcom,cs-out: bool; enable current sink output
- qcom,cabc: bool; enable content adaptive backlight control
diff --git a/dts/Bindings/video/backlight/pwm-backlight.txt b/dts/Bindings/leds/backlight/pwm-backlight.txt
index 764db86..764db86 100644
--- a/dts/Bindings/video/backlight/pwm-backlight.txt
+++ b/dts/Bindings/leds/backlight/pwm-backlight.txt
diff --git a/dts/Bindings/video/backlight/sky81452-backlight.txt b/dts/Bindings/leds/backlight/sky81452-backlight.txt
index 8bf2940..8bf2940 100644
--- a/dts/Bindings/video/backlight/sky81452-backlight.txt
+++ b/dts/Bindings/leds/backlight/sky81452-backlight.txt
diff --git a/dts/Bindings/video/backlight/tps65217-backlight.txt b/dts/Bindings/leds/backlight/tps65217-backlight.txt
index 5fb9279..5fb9279 100644
--- a/dts/Bindings/video/backlight/tps65217-backlight.txt
+++ b/dts/Bindings/leds/backlight/tps65217-backlight.txt
diff --git a/dts/Bindings/leds/leds-aat1290.txt b/dts/Bindings/leds/leds-aat1290.txt
index c05ed91..85c0c58 100644
--- a/dts/Bindings/leds/leds-aat1290.txt
+++ b/dts/Bindings/leds/leds-aat1290.txt
@@ -27,9 +27,9 @@ Required properties of the LED child node:
- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt
Maximum flash LED supply current can be calculated using
following formula: I = 1A * 162kohm / Rset.
-- flash-timeout-us : see Documentation/devicetree/bindings/leds/common.txt
- Maximum flash timeout can be calculated using following
- formula: T = 8.82 * 10^9 * Ct.
+- flash-max-timeout-us : see Documentation/devicetree/bindings/leds/common.txt
+ Maximum flash timeout can be calculated using following
+ formula: T = 8.82 * 10^9 * Ct.
Optional properties of the LED child node:
- label : see Documentation/devicetree/bindings/leds/common.txt
@@ -54,7 +54,7 @@ aat1290 {
label = "aat1290-flash";
led-max-microamp = <520833>;
flash-max-microamp = <1012500>;
- flash-timeout-us = <1940000>;
+ flash-max-timeout-us = <1940000>;
};
};
diff --git a/dts/Bindings/leds/leds-bcm6328.txt b/dts/Bindings/leds/leds-bcm6328.txt
index f9e36ad..3f48c1e 100644
--- a/dts/Bindings/leds/leds-bcm6328.txt
+++ b/dts/Bindings/leds/leds-bcm6328.txt
@@ -29,6 +29,14 @@ Required properties:
Optional properties:
- brcm,serial-leds : Boolean, enables Serial LEDs.
Default : false
+ - brcm,serial-mux : Boolean, enables Serial LEDs multiplexing.
+ Default : false
+ - brcm,serial-clk-low : Boolean, makes clock signal active low.
+ Default : false
+ - brcm,serial-dat-low : Boolean, makes data signal active low.
+ Default : false
+ - brcm,serial-shift-inv : Boolean, inverts Serial LEDs shift direction.
+ Default : false
Each LED is represented as a sub-node of the brcm,bcm6328-leds device.
@@ -110,6 +118,8 @@ Scenario 2 : BCM63268 with Serial/GPHY0 LEDs
#size-cells = <0>;
reg = <0x10001900 0x24>;
brcm,serial-leds;
+ brcm,serial-dat-low;
+ brcm,serial-shift-inv;
gphy0_spd0@0 {
reg = <0>;
diff --git a/dts/Bindings/leds/leds-netxbig.txt b/dts/Bindings/leds/leds-netxbig.txt
new file mode 100644
index 0000000..5ef92a2
--- /dev/null
+++ b/dts/Bindings/leds/leds-netxbig.txt
@@ -0,0 +1,92 @@
+Binding for the CPLD LEDs (GPIO extension bus) found on some LaCie/Seagate
+boards (Example: 2Big/5Big Network v2, 2Big NAS).
+
+Required properties:
+- compatible: "lacie,netxbig-leds".
+- gpio-ext: Phandle for the gpio-ext bus.
+
+Optional properties:
+- timers: Timer array. Each timer entry is represented by three integers:
+ Mode (gpio-ext bus), delay_on and delay_off.
+
+Each LED is represented as a sub-node of the netxbig-leds device.
+
+Required sub-node properties:
+- mode-addr: Mode register address on gpio-ext bus.
+- mode-val: Mode to value mapping. Each entry is represented by two integers:
+ A mode and the corresponding value on the gpio-ext bus.
+- bright-addr: Brightness register address on gpio-ext bus.
+- max-brightness: Maximum brightness value.
+
+Optional sub-node properties:
+- label: Name for this LED. If omitted, the label is taken from the node name.
+- linux,default-trigger: Trigger assigned to the LED.
+
+Example:
+
+netxbig-leds {
+ compatible = "lacie,netxbig-leds";
+
+ gpio-ext = &gpio_ext;
+
+ timers = <NETXBIG_LED_TIMER1 500 500
+ NETXBIG_LED_TIMER2 500 1000>;
+
+ blue-power {
+ label = "netxbig:blue:power";
+ mode-addr = <0>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 1
+ NETXBIG_LED_TIMER1 3
+ NETXBIG_LED_TIMER2 7>;
+ bright-addr = <1>;
+ max-brightness = <7>;
+ };
+ red-power {
+ label = "netxbig:red:power";
+ mode-addr = <0>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 2
+ NETXBIG_LED_TIMER1 4>;
+ bright-addr = <1>;
+ max-brightness = <7>;
+ };
+ blue-sata0 {
+ label = "netxbig:blue:sata0";
+ mode-addr = <3>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 7
+ NETXBIG_LED_SATA 1
+ NETXBIG_LED_TIMER1 3>;
+ bright-addr = <2>;
+ max-brightness = <7>;
+ };
+ red-sata0 {
+ label = "netxbig:red:sata0";
+ mode-addr = <3>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 2
+ NETXBIG_LED_TIMER1 4>;
+ bright-addr = <2>;
+ max-brightness = <7>;
+ };
+ blue-sata1 {
+ label = "netxbig:blue:sata1";
+ mode-addr = <4>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 7
+ NETXBIG_LED_SATA 1
+ NETXBIG_LED_TIMER1 3>;
+ bright-addr = <2>;
+ max-brightness = <7>;
+ };
+ red-sata1 {
+ label = "netxbig:red:sata1";
+ mode-addr = <4>;
+ mode-val = <NETXBIG_LED_OFF 0
+ NETXBIG_LED_ON 2
+ NETXBIG_LED_TIMER1 4>;
+ bright-addr = <2>;
+ max-brightness = <7>;
+ };
+};
diff --git a/dts/Bindings/mailbox/omap-mailbox.txt b/dts/Bindings/mailbox/omap-mailbox.txt
index d1a0433..9b40c49 100644
--- a/dts/Bindings/mailbox/omap-mailbox.txt
+++ b/dts/Bindings/mailbox/omap-mailbox.txt
@@ -75,6 +75,14 @@ data that represent the following:
Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
associated with generating a tx/rx fifo interrupt.
+Optional Properties:
+--------------------
+- ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox
+ to send messages without triggering a Tx ready interrupt,
+ and to control the Tx ticker. Should be used only on
+ sub-mailboxes used to communicate with WkupM3 remote
+ processor on AM33xx/AM43xx SoCs.
+
Mailbox Users:
==============
A device needing to communicate with a target processor device should specify
diff --git a/dts/Bindings/mailbox/sti-mailbox.txt b/dts/Bindings/mailbox/sti-mailbox.txt
new file mode 100644
index 0000000..b61eec9
--- /dev/null
+++ b/dts/Bindings/mailbox/sti-mailbox.txt
@@ -0,0 +1,51 @@
+ST Microelectronics Mailbox Driver
+
+Each ST Mailbox IP currently consists of 4 instances of 32 channels. Messages
+are passed between Application and Remote processors using shared memory.
+
+Controller
+----------
+
+Required properties:
+- compatible : Should be "st,stih407-mailbox"
+- reg : Offset and length of the device's register set
+- mbox-name : Name of the mailbox
+- #mbox-cells: : Must be 2
+ <&phandle instance channel direction>
+ phandle : Label name of controller
+ instance : Instance number
+ channel : Channel number
+
+Optional properties
+- interrupts : Contains the IRQ line for a Rx mailbox
+
+Example:
+
+mailbox0: mailbox@0 {
+ compatible = "st,stih407-mailbox";
+ reg = <0x08f00000 0x1000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
+ #mbox-cells = <2>;
+ mbox-name = "a9";
+};
+
+Client
+------
+
+Required properties:
+- compatible : Many (See the client docs)
+- reg : Shared (between Application and Remote) memory address
+- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
+ Cells must match 'mbox-cells' (See Controller docs above)
+
+Optional properties
+- mbox-names : Name given to channels seen in the 'mboxes' property.
+
+Example:
+
+mailbox_test {
+ compatible = "mailbox_test";
+ reg = <0x[shared_memory_address], [shared_memory_size]>;
+ mboxes = <&mailbox2 0 1>, <&mailbox0 2 1>;
+ mbox-names = "tx", "rx";
+};
diff --git a/dts/Bindings/media/exynos-jpeg-codec.txt b/dts/Bindings/media/exynos-jpeg-codec.txt
index 4ef4563..38941db 100644
--- a/dts/Bindings/media/exynos-jpeg-codec.txt
+++ b/dts/Bindings/media/exynos-jpeg-codec.txt
@@ -4,7 +4,8 @@ Required properties:
- compatible : should be one of:
"samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg",
- "samsung,exynos3250-jpeg", "samsung,exynos5420-jpeg";
+ "samsung,exynos3250-jpeg", "samsung,exynos5420-jpeg",
+ "samsung,exynos5433-jpeg";
- reg : address and length of the JPEG codec IP register set;
- interrupts : specifies the JPEG codec IP interrupt;
- clock-names : should contain:
diff --git a/dts/Bindings/memory-controllers/arm,pl172.txt b/dts/Bindings/memory-controllers/arm,pl172.txt
index e6df32f..22b77ee 100644
--- a/dts/Bindings/memory-controllers/arm,pl172.txt
+++ b/dts/Bindings/memory-controllers/arm,pl172.txt
@@ -1,8 +1,9 @@
-* Device tree bindings for ARM PL172 MultiPort Memory Controller
+* Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller
Required properties:
-- compatible: "arm,pl172", "arm,primecell"
+- compatible: Must be "arm,primecell" and exactly one from
+ "arm,pl172", "arm,pl175" or "arm,pl176".
- reg: Must contains offset/length value for controller.
@@ -56,7 +57,8 @@ Optional child cs node config properties:
- mpmc,extended-wait: Enable extended wait.
-- mpmc,buffer-enable: Enable write buffer.
+- mpmc,buffer-enable: Enable write buffer, option is not supported by
+ PL175 and PL176 controllers.
- mpmc,write-protect: Enable write protect.
diff --git a/dts/Bindings/arm/calxeda/mem-ctrlr.txt b/dts/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt
index 0496759..0496759 100644
--- a/dts/Bindings/arm/calxeda/mem-ctrlr.txt
+++ b/dts/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt
diff --git a/dts/Bindings/memory-controllers/renesas-memory-controllers.txt b/dts/Bindings/memory-controllers/renesas-memory-controllers.txt
index c64b792..9f78e6c 100644
--- a/dts/Bindings/memory-controllers/renesas-memory-controllers.txt
+++ b/dts/Bindings/memory-controllers/renesas-memory-controllers.txt
@@ -24,9 +24,9 @@ Required properties:
Optional properties:
- interrupts: Must contain a list of interrupt specifiers for memory
controller interrupts, if available.
- - interrupts-names: Must contain a list of interrupt names corresponding to
- the interrupts in the interrupts property, if available.
- Valid interrupt names are:
+ - interrupt-names: Must contain a list of interrupt names corresponding to
+ the interrupts in the interrupts property, if available.
+ Valid interrupt names are:
- "sec" (secure interrupt)
- "temp" (normal (temperature) interrupt)
- power-domains: Must contain a reference to the PM domain that the memory
diff --git a/dts/Bindings/mfd/arizona.txt b/dts/Bindings/mfd/arizona.txt
index a8fee60..18be0cb 100644
--- a/dts/Bindings/mfd/arizona.txt
+++ b/dts/Bindings/mfd/arizona.txt
@@ -44,7 +44,6 @@ Required properties:
Optional properties:
- wlf,reset : GPIO specifier for the GPIO controlling /RESET
- - wlf,ldoena : GPIO specifier for the GPIO controlling LDOENA
- wlf,gpio-defaults : A list of GPIO configuration register values. Defines
for the appropriate values can found in <dt-bindings/mfd/arizona.txt>. If
@@ -67,21 +66,13 @@ Optional properties:
present, the number of values should be less than or equal to the
number of inputs, unspecified inputs will use the chip default.
- - wlf,hpdet-channel : Headphone detection channel.
- ARIZONA_ACCDET_MODE_HPL or 1 - Headphone detect mode is set to HPDETL
- ARIZONA_ACCDET_MODE_HPR or 2 - Headphone detect mode is set to HPDETR
- If this node is not mentioned or if the value is unknown, then
- headphone detection mode is set to HPDETL.
-
- DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if
they are being externally supplied. As covered in
Documentation/devicetree/bindings/regulator/regulator.txt
-Optional subnodes:
- - ldo1 : Initial data for the LDO1 regulator, as covered in
- Documentation/devicetree/bindings/regulator/regulator.txt
- - micvdd : Initial data for the MICVDD regulator, as covered in
- Documentation/devicetree/bindings/regulator/regulator.txt
+Also see child specific device properties:
+ Regulator - ../regulator/arizona-regulator.txt
+ Extcon - ../extcon/extcon-arizona.txt
Example:
diff --git a/dts/Bindings/mfd/atmel-flexcom.txt b/dts/Bindings/mfd/atmel-flexcom.txt
new file mode 100644
index 0000000..6923001
--- /dev/null
+++ b/dts/Bindings/mfd/atmel-flexcom.txt
@@ -0,0 +1,63 @@
+* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit)
+
+The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C
+controller and an USART. Only one function can be used at a time and is chosen
+at boot time according to the device tree.
+
+Required properties:
+- compatible: Should be "atmel,sama5d2-flexcom"
+- reg: Should be the offset/length value for Flexcom dedicated
+ I/O registers (without USART, TWI or SPI registers).
+- clocks: Should be the Flexcom peripheral clock from PMC.
+- #address-cells: Should be <1>
+- #size-cells: Should be <1>
+- ranges: Should be one range for the full I/O register region
+ (including USART, TWI and SPI registers).
+- atmel,flexcom-mode: Should be one of the following values:
+ - <1> for USART
+ - <2> for SPI
+ - <3> for I2C
+
+Required child:
+A single available child device of type matching the "atmel,flexcom-mode"
+property.
+
+The phandle provided by the clocks property of the child is the same as one for
+the Flexcom parent.
+
+For other properties, please refer to the documentations of the respective
+device:
+- ../serial/atmel-usart.txt
+- ../spi/spi_atmel.txt
+- ../i2c/i2c-at91.txt
+
+Example:
+
+flexcom@f8034000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8034000 0x200>;
+ clocks = <&flx0_clk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8034000 0x800>;
+ atmel,flexcom-mode = <2>;
+
+ spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&flx0_clk>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <32>;
+
+ mtd_dataflash@0 {
+ compatible = "atmel,at25f512b";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+};
diff --git a/dts/Bindings/mfd/atmel-hlcdc.txt b/dts/Bindings/mfd/atmel-hlcdc.txt
index ad5d904..670831b 100644
--- a/dts/Bindings/mfd/atmel-hlcdc.txt
+++ b/dts/Bindings/mfd/atmel-hlcdc.txt
@@ -15,7 +15,7 @@ Required properties:
The HLCDC IP exposes two subdevices:
- a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt
- - a Display Controller: see ../drm/atmel-hlcdc-dc.txt
+ - a Display Controller: see ../display/atmel-hlcdc-dc.txt
Example:
diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt
index 4181122..a474359 100644
--- a/dts/Bindings/mfd/axp20x.txt
+++ b/dts/Bindings/mfd/axp20x.txt
@@ -60,8 +60,8 @@ DCDC2 : DC-DC buck : vin2-supply
DCDC3 : DC-DC buck : vin3-supply
DCDC4 : DC-DC buck : vin4-supply
DCDC5 : DC-DC buck : vin5-supply
-DC1SW : On/Off Switch : dcdc1-supply : DCDC1 secondary output
-DC5LDO : LDO : dcdc5-supply : input from DCDC5
+DC1SW : On/Off Switch : : DCDC1 secondary output
+DC5LDO : LDO : : input from DCDC5
ALDO1 : LDO : aldoin-supply : shared supply
ALDO2 : LDO : aldoin-supply : shared supply
ALDO3 : LDO : aldoin-supply : shared supply
diff --git a/dts/Bindings/mfd/cros-ec.txt b/dts/Bindings/mfd/cros-ec.txt
index 1777916..136e0c2 100644
--- a/dts/Bindings/mfd/cros-ec.txt
+++ b/dts/Bindings/mfd/cros-ec.txt
@@ -34,6 +34,10 @@ Required properties (LPC):
- compatible: "google,cros-ec-lpc"
- reg: List of (IO address, size) pairs defining the interface uses
+Optional properties (all):
+- google,has-vbc-nvram: Some implementations of the EC include a small
+ nvram space used to store verified boot context data. This boolean flag
+ is used to specify whether this nvram is present or not.
Example for I2C:
diff --git a/dts/Bindings/mfd/da9150.txt b/dts/Bindings/mfd/da9150.txt
index d0588ea..fd4dca7 100644
--- a/dts/Bindings/mfd/da9150.txt
+++ b/dts/Bindings/mfd/da9150.txt
@@ -6,6 +6,7 @@ Device Description
------ -----------
da9150-gpadc : General Purpose ADC
da9150-charger : Battery Charger
+da9150-fg : Battery Fuel-Gauge
======
@@ -16,13 +17,13 @@ Required properties:
the IRQs from da9150 are delivered to.
- interrupts: IRQ line info for da9150 chip.
- interrupt-controller: da9150 has internal IRQs (own IRQ domain).
- (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+ (See ../interrupt-controller/interrupts.txt for
further information relating to interrupt properties)
Sub-devices:
-- da9150-gpadc: See Documentation/devicetree/bindings/iio/adc/da9150-gpadc.txt
-- da9150-charger: See Documentation/devicetree/bindings/power/da9150-charger.txt
-
+- da9150-gpadc: See ../iio/adc/da9150-gpadc.txt
+- da9150-charger: See ../power/da9150-charger.txt
+- da9150-fg: See ../power/da9150-fg.txt
Example:
@@ -34,10 +35,28 @@ Example:
interrupt-controller;
gpadc: da9150-gpadc {
- ...
+ compatible = "dlg,da9150-gpadc";
+ #io-channel-cells = <1>;
+ };
+
+ charger {
+ compatible = "dlg,da9150-charger";
+
+ io-channels = <&gpadc 0>,
+ <&gpadc 2>,
+ <&gpadc 8>,
+ <&gpadc 5>;
+ io-channel-names = "CHAN_IBUS",
+ "CHAN_VBUS",
+ "CHAN_TJUNC",
+ "CHAN_VBAT";
};
- da9150-charger {
- ...
+ fuel-gauge {
+ compatible = "dlg,da9150-fuel-gauge";
+
+ dlg,update-interval = <10000>;
+ dlg,warn-soc-level = /bits/ 8 <15>;
+ dlg,crit-soc-level = /bits/ 8 <5>
};
};
diff --git a/dts/Bindings/mfd/s2mps11.txt b/dts/Bindings/mfd/s2mps11.txt
index 57a0450..09b94c9 100644
--- a/dts/Bindings/mfd/s2mps11.txt
+++ b/dts/Bindings/mfd/s2mps11.txt
@@ -1,5 +1,5 @@
-* Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator
+* Samsung S2MPS11/13/14/15 and S2MPU02 Voltage and Current Regulator
The Samsung S2MPS11 is a multi-function device which includes voltage and
current regulators, RTC, charger controller and other sub-blocks. It is
@@ -7,17 +7,28 @@ interfaced to the host controller using an I2C interface. Each sub-block is
addressed by the host system using different I2C slave addresses.
Required properties:
-- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic"
- or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic".
+- compatible: Should be one of the following
+ - "samsung,s2mps11-pmic"
+ - "samsung,s2mps13-pmic"
+ - "samsung,s2mps14-pmic"
+ - "samsung,s2mps15-pmic"
+ - "samsung,s2mpu02-pmic".
- reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
Optional properties:
- interrupt-parent: Specifies the phandle of the interrupt controller to which
the interrupts from s2mps11 are delivered to.
- interrupts: Interrupt specifiers for interrupt sources.
+- samsung,s2mps11-wrstbi-ground: Indicates that WRSTBI pin of PMIC is pulled
+ down. When the system is suspended it will always go down thus triggerring
+ unwanted buck warm reset (setting buck voltages to default values).
+- samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is
+ connected to the ground so the PMIC must manually set PWRHOLD bit in CTRL1
+ register to turn off the power. Usually the ACOKB is pulled up to VBATT so
+ when PWRHOLD pin goes low, the rising ACOKB will trigger power off.
Optional nodes:
-- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768
+- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768
KHz outputs, so to register these as clocks with common clock framework
instantiate a sub-node named "clocks". It uses the common clock binding
documented in :
@@ -30,12 +41,13 @@ Optional nodes:
the clock which they consume.
Clock ID Devices
----------------------------------------------------------
- 32KhzAP 0 S2MPS11, S2MPS13, S2MPS14, S5M8767
- 32KhzCP 1 S2MPS11, S2MPS13, S5M8767
- 32KhzBT 2 S2MPS11, S2MPS13, S2MPS14, S5M8767
+ 32KhzAP 0 S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767
+ 32KhzCP 1 S2MPS11, S2MPS13, S2MPS15, S5M8767
+ 32KhzBT 2 S2MPS11, S2MPS13, S2MPS14, S2MPS15, S5M8767
- compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk",
"samsung,s2mps14-clk", "samsung,s5m8767-clk"
+ The s2msp15 uses the same compatible as s2mps13, as both provides similar clocks.
- regulators: The regulators of s2mps11 that have to be instantiated should be
included in a sub-node named 'regulators'. Regulator nodes included in this
@@ -83,6 +95,7 @@ as per the datasheet of s2mps11.
- S2MPS11: 1 to 38
- S2MPS13: 1 to 40
- S2MPS14: 1 to 25
+ - S2MPS15: 1 to 27
- S2MPU02: 1 to 28
- Example: LDO1, LDO2, LDO28
- BUCKn
@@ -90,6 +103,7 @@ as per the datasheet of s2mps11.
- S2MPS11: 1 to 10
- S2MPS13: 1 to 10
- S2MPS14: 1 to 5
+ - S2MPS15: 1 to 10
- S2MPU02: 1 to 7
- Example: BUCK1, BUCK2, BUCK9
diff --git a/dts/Bindings/mfd/sky81452.txt b/dts/Bindings/mfd/sky81452.txt
index 3518179..511764a 100644
--- a/dts/Bindings/mfd/sky81452.txt
+++ b/dts/Bindings/mfd/sky81452.txt
@@ -6,7 +6,7 @@ Required properties:
Required child nodes:
- backlight : container node for backlight following the binding
- in video/backlight/sky81452-backlight.txt
+ in leds/backlight/sky81452-backlight.txt
- regulator : container node for regulators following the binding
in regulator/sky81452-regulator.txt
diff --git a/dts/Bindings/mfd/tc3589x.txt b/dts/Bindings/mfd/tc3589x.txt
index 37bf7f1..23fc2f2 100644
--- a/dts/Bindings/mfd/tc3589x.txt
+++ b/dts/Bindings/mfd/tc3589x.txt
@@ -56,6 +56,7 @@ Optional nodes:
bindings/input/matrix-keymap.txt
- linux,no-autorepeat: do no enable autorepeat feature.
- wakeup-source: use any event on keypad as wakeup event.
+ (Legacy property supported: "linux,wakeup")
Example:
diff --git a/dts/Bindings/mips/img/xilfpga.txt b/dts/Bindings/mips/img/xilfpga.txt
new file mode 100644
index 0000000..57e7ee9
--- /dev/null
+++ b/dts/Bindings/mips/img/xilfpga.txt
@@ -0,0 +1,83 @@
+Imagination University Program MIPSfpga
+=======================================
+
+Under the Imagination University Program, a microAptiv UP core has been
+released for academic usage.
+
+As we are dealing with a MIPS core instantiated on an FPGA, specifications
+are fluid and can be varied in RTL.
+
+This binding document is provided as baseline guidance for the example
+project provided by IMG.
+
+The example project runs on the Nexys4DDR board by Digilent powered by
+the ARTIX-7 FPGA by Xilinx.
+
+Relevant details about the example project and the Nexys4DDR board:
+
+- microAptiv UP core m14Kc
+- 50MHz clock speed
+- 128Mbyte DDR RAM at 0x0000_0000
+- 8Kbyte RAM at 0x1000_0000
+- axi_intc at 0x1020_0000
+- axi_uart16550 at 0x1040_0000
+- axi_gpio at 0x1060_0000
+- axi_i2c at 0x10A0_0000
+- custom_gpio at 0x10C0_0000
+- axi_ethernetlite at 0x10E0_0000
+- 8Kbyte BootRAM at 0x1FC0_0000
+
+Required properties:
+--------------------
+ - compatible: Must include "digilent,nexys4ddr","img,xilfpga".
+
+CPU nodes:
+----------
+A "cpus" node is required. Required properties:
+ - #address-cells: Must be 1.
+ - #size-cells: Must be 0.
+A CPU sub-node is also required for at least CPU 0. Required properties:
+ - device_type: Must be "cpu".
+ - compatible: Must be "mips,m14Kc".
+ - reg: Must be <0>.
+ - clocks: phandle to ext clock for fixed-clock received by MIPS core.
+
+Example:
+
+ compatible = "img,xilfpga","digilent,nexys4ddr";
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,m14Kc";
+ reg = <0>;
+ clocks = <&ext>;
+ };
+ };
+
+ ext: ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+Boot protocol:
+--------------
+
+The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
+This is for easy reprogrammibility via JTAG.
+
+The BootRAM initializes the cache and the axi_uart peripheral.
+
+DDR initialization is already handled by a HW IP block.
+
+When the example project bitstream is loaded, the cpu_reset button
+needs to be pressed.
+
+The bootram initializes the cache and axi_uart.
+Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board.
+
+At this point, the board is ready to load the Linux kernel
+vmlinux file via JTAG.
diff --git a/dts/Bindings/misc/sram.txt b/dts/Bindings/misc/sram.txt
index 36cbe5a..42ee943 100644
--- a/dts/Bindings/misc/sram.txt
+++ b/dts/Bindings/misc/sram.txt
@@ -33,6 +33,12 @@ Optional properties in the area nodes:
- compatible : standard definition, should contain a vendor specific string
in the form <vendor>,[<device>-]<usage>
+- pool : indicates that the particular reserved SRAM area is addressable
+ and in use by another device or devices
+- export : indicates that the reserved SRAM area may be accessed outside
+ of the kernel, e.g. by bootloader or userspace
+- label : the name for the reserved partition, if omitted, the label
+ is taken from the node name excluding the unit address.
Example:
@@ -48,4 +54,14 @@ sram: sram@5c000000 {
compatible = "socvendor,smp-sram";
reg = <0x100 0x50>;
};
+
+ device-sram@1000 {
+ reg = <0x1000 0x1000>;
+ pool;
+ };
+
+ exported@20000 {
+ reg = <0x20000 0x20000>;
+ export;
+ };
};
diff --git a/dts/Bindings/mmc/fsl-esdhc.txt b/dts/Bindings/mmc/fsl-esdhc.txt
index b7943f3..dedfb02 100644
--- a/dts/Bindings/mmc/fsl-esdhc.txt
+++ b/dts/Bindings/mmc/fsl-esdhc.txt
@@ -22,6 +22,8 @@ Optional properties:
- voltage-ranges : two cells are required, first cell specifies minimum
slot voltage (mV), second cell specifies maximum slot voltage (mV).
Several ranges could be specified.
+ - little-endian : If the host controller is little-endian mode, specify
+ this property. The default endian mode is big-endian.
Example:
diff --git a/dts/Bindings/mmc/mmc.txt b/dts/Bindings/mmc/mmc.txt
index 0384fc3..ed23b9b 100644
--- a/dts/Bindings/mmc/mmc.txt
+++ b/dts/Bindings/mmc/mmc.txt
@@ -37,6 +37,7 @@ Optional properties:
- sd-uhs-sdr104: SD UHS SDR104 speed is supported
- sd-uhs-ddr50: SD UHS DDR50 speed is supported
- cap-power-off-card: powering off the card is safe
+- cap-mmc-hw-reset: eMMC hardware reset is supported
- cap-sdio-irq: enable SDIO IRQ signalling on this interface
- full-pwr-cycle: full power cycle of the card is supported
- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
@@ -67,7 +68,8 @@ polarity is in effect.
Optional SDIO properties:
- keep-power-in-suspend: Preserves card power during a suspend/resume cycle
-- enable-sdio-wakeup: Enables wake up of host system on SDIO IRQ assertion
+- wakeup-source: Enables wake up of host system on SDIO IRQ assertion
+ (Legacy property supported: "enable-sdio-wakeup")
MMC power sequences:
@@ -117,7 +119,7 @@ sdhci@ab000000 {
wp-gpios = <&gpio 70 0>;
max-frequency = <50000000>;
keep-power-in-suspend;
- enable-sdio-wakeup;
+ wakeup-source;
mmc-pwrseq = <&sdhci0_pwrseq>
}
diff --git a/dts/Bindings/mmc/mtk-sd.txt b/dts/Bindings/mmc/mtk-sd.txt
index a1adfa4..0120c7f 100644
--- a/dts/Bindings/mmc/mtk-sd.txt
+++ b/dts/Bindings/mmc/mtk-sd.txt
@@ -17,6 +17,11 @@ Required properties:
- vmmc-supply: power to the Core
- vqmmc-supply: power to the IO
+Optional properties:
+- assigned-clocks: PLL of the source clock
+- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
+- hs400-ds-delay: HS400 DS delay setting
+
Examples:
mmc0: mmc@11230000 {
compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
@@ -24,9 +29,13 @@ mmc0: mmc@11230000 {
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
vmmc-supply = <&mt6397_vemc_3v3_reg>;
vqmmc-supply = <&mt6397_vio18_reg>;
- clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
clock-names = "source", "hclk";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ hs400-ds-delay = <0x14015>;
};
diff --git a/dts/Bindings/mmc/renesas,mmcif.txt b/dts/Bindings/mmc/renesas,mmcif.txt
index d38942f..cae29eb 100644
--- a/dts/Bindings/mmc/renesas,mmcif.txt
+++ b/dts/Bindings/mmc/renesas,mmcif.txt
@@ -6,11 +6,12 @@ and the properties used by the MMCIF device.
Required properties:
-- compatible: must contain one of the following
+- compatible: should be "renesas,mmcif-<soctype>", "renesas,sh-mmcif" as a
+ fallback. Examples with <soctype> are:
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
- - "renesas,sh-mmcif" for the generic MMCIF
+ - "renesas,mmcif-r8a7794" for the MMCIF found in r8a7794 SoCs
- clocks: reference to the functional clock
diff --git a/dts/Bindings/mmc/rockchip-dw-mshc.txt b/dts/Bindings/mmc/rockchip-dw-mshc.txt
index c327c2d..3dc13b6 100644
--- a/dts/Bindings/mmc/rockchip-dw-mshc.txt
+++ b/dts/Bindings/mmc/rockchip-dw-mshc.txt
@@ -14,6 +14,19 @@ Required Properties:
before RK3288
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
+Optional Properties:
+* clocks: from common clock binding: if ciu_drive and ciu_sample are
+ specified in clock-names, should contain handles to these clocks.
+
+* clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt
+ two more clocks "ciu-drive" and "ciu-sample" are supported. They are used
+ to control the clock phases, "ciu-sample" is required for tuning high-
+ speed modes.
+
+* rockchip,default-sample-phase: The default phase to set ciu_sample at
+ probing, low speeds or in case where all phases work at tuning time.
+ If not specified 0 deg will be used.
+
Example:
rkdwmmc0@12200000 {
diff --git a/dts/Bindings/mmc/synopsys-dw-mshc.txt b/dts/Bindings/mmc/synopsys-dw-mshc.txt
index 346c609..8636f5a 100644
--- a/dts/Bindings/mmc/synopsys-dw-mshc.txt
+++ b/dts/Bindings/mmc/synopsys-dw-mshc.txt
@@ -75,6 +75,12 @@ Optional properties:
* vmmc-supply: The phandle to the regulator to use for vmmc. If this is
specified we'll defer probe until we can find this regulator.
+* dmas: List of DMA specifiers with the controller specific format as described
+ in the generic DMA client binding. Refer to dma.txt for details.
+
+* dma-names: request names for generic DMA client binding. Must be "rx-tx".
+ Refer to dma.txt for details.
+
Aliases:
- All the MSHC controller nodes should be represented in the aliases node using
@@ -95,6 +101,23 @@ board specific portions as listed below.
#size-cells = <0>;
};
+[board specific internal DMA resources]
+
+ dwmmc0@12200000 {
+ clock-frequency = <400000000>;
+ clock-freq-min-max = <400000 200000000>;
+ num-slots = <1>;
+ broken-cd;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ vmmc-supply = <&buck8>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ };
+
+[board specific generic DMA request binding]
+
dwmmc0@12200000 {
clock-frequency = <400000000>;
clock-freq-min-max = <400000 200000000>;
@@ -106,4 +129,6 @@ board specific portions as listed below.
bus-width = <8>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ dmas = <&pdma 12>;
+ dma-names = "rx-tx";
};
diff --git a/dts/Bindings/mtd/fsmc-nand.txt b/dts/Bindings/mtd/fsmc-nand.txt
index 5235cbc..32636eb 100644
--- a/dts/Bindings/mtd/fsmc-nand.txt
+++ b/dts/Bindings/mtd/fsmc-nand.txt
@@ -30,6 +30,12 @@ Optional properties:
command is asserted. Zero means one cycle, 255 means 256
cycles.
- bank: default NAND bank to use (0-3 are valid, 0 is the default).
+- nand-ecc-mode : see nand.txt
+- nand-ecc-strength : see nand.txt
+- nand-ecc-step-size : see nand.txt
+
+Can support 1-bit HW ECC (default) or if stronger correction is required,
+software-based BCH.
Example:
diff --git a/dts/Bindings/mtd/partition.txt b/dts/Bindings/mtd/partition.txt
index 8e5557d..f1e2a02 100644
--- a/dts/Bindings/mtd/partition.txt
+++ b/dts/Bindings/mtd/partition.txt
@@ -4,10 +4,17 @@ Partitions can be represented by sub-nodes of an mtd device. This can be used
on platforms which have strong conventions about which portions of a flash are
used for what purposes, but which don't use an on-flash partition table such
as RedBoot.
-NOTE: if the sub-node has a compatible string, then it is not a partition.
-#address-cells & #size-cells must both be present in the mtd device. There are
-two valid values for both:
+The partition table should be a subnode of the mtd node and should be named
+'partitions'. Partitions are defined in subnodes of the partitions node.
+
+For backwards compatibility partitions as direct subnodes of the mtd device are
+supported. This use is discouraged.
+NOTE: also for backwards compatibility, direct subnodes that have a compatible
+string are not considered partitions, as they may be used for other bindings.
+
+#address-cells & #size-cells must both be present in the partitions subnode of the
+mtd device. There are two valid values for both:
<1>: for partitions that require a single 32-bit cell to represent their
size/address (aka the value is below 4 GiB)
<2>: for partitions that require two 32-bit cells to represent their
@@ -28,44 +35,50 @@ Examples:
flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x100000>;
- read-only;
- };
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
- uimage@100000 {
- reg = <0x0100000 0x200000>;
+ uimage@100000 {
+ reg = <0x0100000 0x200000>;
+ };
};
};
flash@1 {
- #address-cells = <1>;
- #size-cells = <2>;
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <2>;
- /* a 4 GiB partition */
- partition@0 {
- label = "filesystem";
- reg = <0x00000000 0x1 0x00000000>;
+ /* a 4 GiB partition */
+ partition@0 {
+ label = "filesystem";
+ reg = <0x00000000 0x1 0x00000000>;
+ };
};
};
flash@2 {
- #address-cells = <2>;
- #size-cells = <2>;
+ partitions {
+ #address-cells = <2>;
+ #size-cells = <2>;
- /* an 8 GiB partition */
- partition@0 {
- label = "filesystem #1";
- reg = <0x0 0x00000000 0x2 0x00000000>;
- };
+ /* an 8 GiB partition */
+ partition@0 {
+ label = "filesystem #1";
+ reg = <0x0 0x00000000 0x2 0x00000000>;
+ };
- /* a 4 GiB partition */
- partition@200000000 {
- label = "filesystem #2";
- reg = <0x2 0x00000000 0x1 0x00000000>;
+ /* a 4 GiB partition */
+ partition@200000000 {
+ label = "filesystem #2";
+ reg = <0x2 0x00000000 0x1 0x00000000>;
+ };
};
};
diff --git a/dts/Bindings/mtd/vf610-nfc.txt b/dts/Bindings/mtd/vf610-nfc.txt
new file mode 100644
index 0000000..c96eeb6
--- /dev/null
+++ b/dts/Bindings/mtd/vf610-nfc.txt
@@ -0,0 +1,59 @@
+Freescale's NAND flash controller (NFC)
+
+This variant of the Freescale NAND flash controller (NFC) can be found on
+Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70.
+
+Required properties:
+- compatible: Should be set to "fsl,vf610-nfc".
+- reg: address range of the NFC.
+- interrupts: interrupt of the NFC.
+- #address-cells: shall be set to 1. Encode the nand CS.
+- #size-cells : shall be set to 0.
+- assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
+- assigned-clock-rates: The NAND bus timing is derived from this clock
+ rate and should not exceed maximum timing for any NAND memory chip
+ in a board stuffing. Typical NAND memory timings derived from this
+ clock are found in the SoC hardware reference manual. Furthermore,
+ there might be restrictions on maximum rates when using hardware ECC.
+
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+ representing partitions.
+
+Required children nodes:
+Children nodes represent the available nand chips. Currently the driver can
+only handle one NAND chip.
+
+Required properties:
+- compatible: Should be set to "fsl,vf610-nfc-cs".
+- nand-bus-width: see nand.txt
+- nand-ecc-mode: see nand.txt
+
+Required properties for hardware ECC:
+- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt)
+- nand-ecc-step-size: step size equals page size, currently only 2k pages are
+ supported
+- nand-on-flash-bbt: see nand.txt
+
+Example:
+
+ nfc: nand@400e0000 {
+ compatible = "fsl,vf610-nfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x400e0000 0x4000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks VF610_CLK_NFC>;
+ clock-names = "nfc";
+ assigned-clocks = <&clks VF610_CLK_NFC>;
+ assigned-clock-rates = <33000000>;
+
+ nand@0 {
+ compatible = "fsl,vf610-nfc-nandcs";
+ reg = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <32>;
+ nand-ecc-step-size = <2048>;
+ nand-on-flash-bbt;
+ };
+ };
diff --git a/dts/Bindings/net/apm-xgene-enet.txt b/dts/Bindings/net/apm-xgene-enet.txt
index f55aa28..078060a 100644
--- a/dts/Bindings/net/apm-xgene-enet.txt
+++ b/dts/Bindings/net/apm-xgene-enet.txt
@@ -37,6 +37,14 @@ Required properties for ethernet interfaces that have external PHY:
Optional properties:
- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok".
+- tx-delay: Delay value for RGMII bridge TX clock.
+ Valid values are between 0 to 7, that maps to
+ 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps
+ Default value is 4, which corresponds to 1611 ps
+- rx-delay: Delay value for RGMII bridge RX clock.
+ Valid values are between 0 to 7, that maps to
+ 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
+ Default value is 2, which corresponds to 899 ps
Example:
menetclk: menetclk {
@@ -72,5 +80,7 @@ Example:
/* Board-specific peripheral configurations */
&menet {
+ tx-delay = <4>;
+ rx-delay = <2>;
status = "ok";
};
diff --git a/dts/Bindings/net/brcm,iproc-mdio.txt b/dts/Bindings/net/brcm,iproc-mdio.txt
new file mode 100644
index 0000000..8ba9ed1
--- /dev/null
+++ b/dts/Bindings/net/brcm,iproc-mdio.txt
@@ -0,0 +1,23 @@
+* Broadcom iProc MDIO bus controller
+
+Required properties:
+- compatible: should be "brcm,iproc-mdio"
+- reg: address and length of the register set for the MDIO interface
+- #size-cells: must be 1
+- #address-cells: must be 0
+
+Child nodes of this MDIO bus controller node are standard Ethernet PHY device
+nodes as described in Documentation/devicetree/bindings/net/phy.txt
+
+Example:
+
+mdio@18002000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x18002000 0x8>;
+ #size-cells = <1>;
+ #address-cells = <0>;
+
+ enet-gphy@0 {
+ reg = <0>;
+ };
+};
diff --git a/dts/Bindings/net/can/sun4i_can.txt b/dts/Bindings/net/can/sun4i_can.txt
new file mode 100644
index 0000000..84ed190
--- /dev/null
+++ b/dts/Bindings/net/can/sun4i_can.txt
@@ -0,0 +1,36 @@
+Allwinner A10/A20 CAN controller Device Tree Bindings
+-----------------------------------------------------
+
+Required properties:
+- compatible: "allwinner,sun4i-a10-can"
+- reg: physical base address and size of the Allwinner A10/A20 CAN register map.
+- interrupts: interrupt specifier for the sole interrupt.
+- clock: phandle and clock specifier.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+ can0_pins_a: can0@0 {
+ allwinner,pins = "PH20","PH21";
+ allwinner,function = "can";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+...
+ can0: can@01c2bc00 {
+ compatible = "allwinner,sun4i-a10-can";
+ reg = <0x01c2bc00 0x400>;
+ interrupts = <0 26 4>;
+ clocks = <&apb1_gates 4>;
+ status = "disabled";
+ };
+
+Board specific .dts file:
+
+ can0: can@01c2bc00 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins_a>;
+ status = "okay";
+ };
diff --git a/dts/Bindings/net/cpsw.txt b/dts/Bindings/net/cpsw.txt
index a2cae4e..9853f8e 100644
--- a/dts/Bindings/net/cpsw.txt
+++ b/dts/Bindings/net/cpsw.txt
@@ -30,6 +30,13 @@ Optional properties:
- dual_emac : Specifies Switch to act as Dual EMAC
- syscon : Phandle to the system control device node, which is
the control module device of the am33x
+- mode-gpios : Should be added if one/multiple gpio lines are
+ required to be driven so that cpsw data lines
+ can be connected to the phy via selective mux.
+ For example in dra72x-evm, pcf gpio has to be
+ driven low so that cpsw slave 0 and phy data
+ lines are connected via mux.
+
Slave Properties:
Required properties:
@@ -41,6 +48,11 @@ Optional properties:
- mac-address : See ethernet.txt file in the same directory
- phy-handle : See ethernet.txt file in the same directory
+Slave sub-nodes:
+- fixed-link : See fixed-link.txt file in the same directory
+ Either the properties phy_id and phy-mode,
+ or the sub-node fixed-link can be specified
+
Note: "ti,hwmods" field is used to fetch the base address and irq
resources from TI, omap hwmod data base during device registration.
Future plan is to migrate hwmod data base contents into device tree
diff --git a/dts/Bindings/net/fsl-tsec-phy.txt b/dts/Bindings/net/fsl-tsec-phy.txt
index 1e97532..db74f0d 100644
--- a/dts/Bindings/net/fsl-tsec-phy.txt
+++ b/dts/Bindings/net/fsl-tsec-phy.txt
@@ -57,6 +57,10 @@ Properties:
"rgmii-id", as all other connection types are detected by hardware.
- fsl,magic-packet : If present, indicates that the hardware supports
waking up via magic packet.
+ - fsl,wake-on-filer : If present, indicates that the hardware supports
+ waking up by Filer General Purpose Interrupt (FGPI) asserted on the
+ Rx int line. This is an advanced power management capability allowing
+ certain packet types (user) defined by filer rules to wake up the system.
- bd-stash : If present, indicates that the hardware supports stashing
buffer descriptors in the L2.
- rx-stash-len : Denotes the number of bytes of a received buffer to stash
diff --git a/dts/Bindings/net/hisilicon-hip04-net.txt b/dts/Bindings/net/hisilicon-hip04-net.txt
index 988fc69..d1df8a0 100644
--- a/dts/Bindings/net/hisilicon-hip04-net.txt
+++ b/dts/Bindings/net/hisilicon-hip04-net.txt
@@ -32,13 +32,13 @@ Required properties:
Required properties:
-- compatible: should be "hisilicon,hip04-mdio".
+- compatible: should be "hisilicon,mdio".
- Inherits from MDIO bus node binding [2]
[2] Documentation/devicetree/bindings/net/phy.txt
Example:
mdio {
- compatible = "hisilicon,hip04-mdio";
+ compatible = "hisilicon,mdio";
reg = <0x28f1000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/Bindings/net/hisilicon-hns-dsaf.txt b/dts/Bindings/net/hisilicon-hns-dsaf.txt
new file mode 100644
index 0000000..80411b2
--- /dev/null
+++ b/dts/Bindings/net/hisilicon-hns-dsaf.txt
@@ -0,0 +1,49 @@
+Hisilicon DSA Fabric device controller
+
+Required properties:
+- compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
+ "hisilicon,hns-dsaf-v1" is for hip05.
+ "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
+- dsa-name: dsa fabric name who provide this interface.
+ should be "dsafX", X is the dsaf id.
+- mode: dsa fabric mode string. only support one of dsaf modes like these:
+ "2port-64vf",
+ "6port-16rss",
+ "6port-16vf".
+- interrupt-parent: the interrupt parent of this device.
+- interrupts: should contain the DSA Fabric and rcb interrupt.
+- reg: specifies base physical address(es) and size of the device registers.
+ The first region is external interface control register base and size.
+ The second region is SerDes base register and size.
+ The third region is the PPE register base and size.
+ The fourth region is dsa fabric base register and size.
+ The fifth region is cpld base register and size, it is not required if do not use cpld.
+- phy-handle: phy handle of physicl port, 0 if not any phy device. see ethernet.txt [1].
+- buf-size: rx buffer size, should be 16-1024.
+- desc-num: number of description in TX and RX queue, should be 512, 1024, 2048 or 4096.
+
+[1] Documentation/devicetree/bindings/net/phy.txt
+
+Example:
+
+dsa: dsa@c7000000 {
+ compatible = "hisilicon,hns-dsaf-v1";
+ dsa_name = "dsaf0";
+ mode = "6port-16rss";
+ interrupt-parent = <&mbigen_dsa>;
+ reg = <0x0 0xC0000000 0x0 0x420000
+ 0x0 0xC2000000 0x0 0x300000
+ 0x0 0xc5000000 0x0 0x890000
+ 0x0 0xc7000000 0x0 0x60000>;
+ phy-handle = <0 0 0 0 &soc0_phy4 &soc0_phy5 0 0>;
+ interrupts = <131 4>,<132 4>, <133 4>,<134 4>,
+ <135 4>,<136 4>, <137 4>,<138 4>,
+ <139 4>,<140 4>, <141 4>,<142 4>,
+ <143 4>,<144 4>, <145 4>,<146 4>,
+ <147 4>,<148 4>, <384 1>,<385 1>,
+ <386 1>,<387 1>, <388 1>,<389 1>,
+ <390 1>,<391 1>,
+ buf-size = <4096>;
+ desc-num = <1024>;
+ dma-coherent;
+};
diff --git a/dts/Bindings/net/hisilicon-hns-mdio.txt b/dts/Bindings/net/hisilicon-hns-mdio.txt
new file mode 100644
index 0000000..9c23fdf
--- /dev/null
+++ b/dts/Bindings/net/hisilicon-hns-mdio.txt
@@ -0,0 +1,22 @@
+Hisilicon MDIO bus controller
+
+Properties:
+- compatible: "hisilicon,mdio","hisilicon,hns-mdio".
+- reg: The base address of the MDIO bus controller register bank.
+- #address-cells: Must be <1>.
+- #size-cells: Must be <0>. MDIO addresses have no size component.
+
+Typically an MDIO bus might have several children.
+
+Example:
+ mdio@803c0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "hisilicon,hns-mdio","hisilicon,mdio";
+ reg = <0x0 0x803c0000 0x0 0x10000>;
+
+ ethernet-phy@0 {
+ ...
+ reg = <0>;
+ };
+ };
diff --git a/dts/Bindings/net/hisilicon-hns-nic.txt b/dts/Bindings/net/hisilicon-hns-nic.txt
new file mode 100644
index 0000000..41d19be
--- /dev/null
+++ b/dts/Bindings/net/hisilicon-hns-nic.txt
@@ -0,0 +1,47 @@
+Hisilicon Network Subsystem NIC controller
+
+Required properties:
+- compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
+ "hisilicon,hns-nic-v1" is for hip05.
+ "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
+- ae-name: accelerator name who provides this interface,
+ is simply a name referring to the name of name in the accelerator node.
+- port-id: is the index of port provided by DSAF (the accelerator). DSAF can
+ connect to 8 PHYs. Port 0 to 1 are both used for adminstration purpose. They
+ are called debug ports.
+
+ The remaining 6 PHYs are taken according to the mode of DSAF.
+
+ In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
+ port-id can be 2 to 7. Here is the diagram:
+ +-----+---------------+
+ | CPU |
+ +-+-+-+---+-+-+-+-+-+-+
+ | | | | | | | |
+ debug service
+ port port
+ (0,1) (2-7)
+
+ In Switch mode of DSAF, all 6 PHYs are taken as physical ports connect to a
+ LAN Switch while the CPU side assume itself have one single NIC connect to
+ this switch. In this case, the port-id will be 2 only.
+ +-----+---------------+
+ | CPU |
+ +-+-+-+---+-+-+-+-+-+-+
+ | | service| port(2)
+ debug +------------+
+ port | switch |
+ (0,1) +-+-+-+-+-+-++
+ | | | | | |
+ external port
+
+- local-mac-address: mac addr of the ethernet interface
+
+Example:
+
+ ethernet@0{
+ compatible = "hisilicon,hns-nic-v1";
+ ae-name = "dsaf0";
+ port-id = <0>;
+ local-mac-address = [a2 14 e4 4b 56 76];
+ };
diff --git a/dts/Bindings/net/ieee802154/mrf24j40.txt b/dts/Bindings/net/ieee802154/mrf24j40.txt
new file mode 100644
index 0000000..a4ed2ef
--- /dev/null
+++ b/dts/Bindings/net/ieee802154/mrf24j40.txt
@@ -0,0 +1,20 @@
+* MRF24J40 IEEE 802.15.4 *
+
+Required properties:
+ - compatible: should be "microchip,mrf24j40", "microchip,mrf24j40ma",
+ or "microchip,mrf24j40mc" depends on your transceiver
+ board
+ - spi-max-frequency: maximal bus speed, should be set something under or equal
+ 10000000
+ - reg: the chipselect index
+ - interrupts: the interrupt generated by the device.
+
+Example:
+
+ mrf24j40ma@0 {
+ compatible = "microchip,mrf24j40ma";
+ spi-max-frequency = <8500000>;
+ reg = <0>;
+ interrupts = <19 8>;
+ interrupt-parent = <&gpio3>;
+ };
diff --git a/dts/Bindings/net/maxim,ds26522.txt b/dts/Bindings/net/maxim,ds26522.txt
new file mode 100644
index 0000000..ee8bb72
--- /dev/null
+++ b/dts/Bindings/net/maxim,ds26522.txt
@@ -0,0 +1,13 @@
+* Maxim (Dallas) DS26522 Dual T1/E1/J1 Transceiver
+
+Required properties:
+- compatible: Should contain "maxim,ds26522".
+- reg: SPI CS.
+- spi-max-frequency: SPI clock.
+
+Example:
+ slic@1 {
+ compatible = "maxim,ds26522";
+ reg = <1>;
+ spi-max-frequency = <2000000>; /* input clock */
+ };
diff --git a/dts/Bindings/net/nfc/nfcmrvl.txt b/dts/Bindings/net/nfc/nfcmrvl.txt
index 7c4a0cc..76df917 100644
--- a/dts/Bindings/net/nfc/nfcmrvl.txt
+++ b/dts/Bindings/net/nfc/nfcmrvl.txt
@@ -1,7 +1,10 @@
* Marvell International Ltd. NCI NFC Controller
Required properties:
-- compatible: Should be "mrvl,nfc-uart".
+- compatible: Should be:
+ - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices
+ - "marvell,nfc-i2c" for I2C devices
+ - "marvell,nfc-spi" for SPI devices
Optional SoC specific properties:
- pinctrl-names: Contains only one value - "default".
@@ -13,13 +16,19 @@ Optional UART-based chip specific properties:
- flow-control: Specifies that the chip is using RTS/CTS.
- break-control: Specifies that the chip needs specific break management.
+Optional I2C-based chip specific properties:
+- i2c-int-falling: Specifies that the chip read event shall be trigged on
+ falling edge.
+- i2c-int-rising: Specifies that the chip read event shall be trigged on
+ rising edge.
+
Example (for ARM-based BeagleBoard Black with 88W8887 on UART5):
&uart5 {
status = "okay";
nfcmrvluart: nfcmrvluart@5 {
- compatible = "mrvl,nfc-uart";
+ compatible = "marvell,nfc-uart";
reset-n-io = <&gpio3 16 0>;
@@ -27,3 +36,51 @@ Example (for ARM-based BeagleBoard Black with 88W8887 on UART5):
flow-control;
}
};
+
+
+Example (for ARM-based BeagleBoard Black with 88W8887 on I2C1):
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ nfcmrvli2c0: i2c@1 {
+ compatible = "marvell,nfc-i2c";
+
+ reg = <0x8>;
+
+ /* I2C INT configuration */
+ interrupt-parent = <&gpio3>;
+ interrupts = <21 0>;
+
+ /* I2C INT trigger configuration */
+ i2c-int-rising;
+
+ /* Reset IO */
+ reset-n-io = <&gpio3 19 0>;
+ };
+};
+
+
+Example (for ARM-based BeagleBoard Black on SPI0):
+
+&spi0 {
+
+ mrvlnfcspi0: spi@0 {
+ compatible = "marvell,nfc-spi";
+
+ reg = <0>;
+
+ /* SPI Bus configuration */
+ spi-max-frequency = <3000000>;
+ spi-cpha;
+ spi-cpol;
+
+ /* SPI INT configuration */
+ interrupt-parent = <&gpio1>;
+ interrupts = <17 0>;
+
+ /* Reset IO */
+ reset-n-io = <&gpio3 19 0>;
+ };
+};
diff --git a/dts/Bindings/net/nfc/st-nci-i2c.txt b/dts/Bindings/net/nfc/st-nci-i2c.txt
index d707588..263732e 100644
--- a/dts/Bindings/net/nfc/st-nci-i2c.txt
+++ b/dts/Bindings/net/nfc/st-nci-i2c.txt
@@ -11,6 +11,10 @@ Required properties:
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
+- ese-present: Specifies that an ese is physically connected to the nfc
+controller.
+- uicc-present: Specifies that the uicc swp signal can be physically
+connected to the nfc controller.
Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2):
@@ -29,5 +33,8 @@ Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2):
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+
+ ese-present;
+ uicc-present;
};
};
diff --git a/dts/Bindings/net/nfc/st-nci-spi.txt b/dts/Bindings/net/nfc/st-nci-spi.txt
index 525681b..711ca85 100644
--- a/dts/Bindings/net/nfc/st-nci-spi.txt
+++ b/dts/Bindings/net/nfc/st-nci-spi.txt
@@ -2,7 +2,7 @@
Required properties:
- compatible: Should be "st,st21nfcb-spi"
-- spi-max-frequency: Maximum SPI frequency (<= 10000000).
+- spi-max-frequency: Maximum SPI frequency (<= 4000000).
- interrupt-parent: phandle for the interrupt gpio controller
- interrupts: GPIO interrupt to which the chip is connected
- reset-gpios: Output GPIO pin used to reset the ST21NFCB
@@ -10,6 +10,10 @@ Required properties:
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
+- ese-present: Specifies that an ese is physically connected to the nfc
+controller.
+- uicc-present: Specifies that the uicc swp signal can be physically
+connected to the nfc controller.
Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4):
@@ -27,5 +31,8 @@ Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4):
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+
+ ese-present;
+ uicc-present;
};
};
diff --git a/dts/Bindings/net/renesas,ravb.txt b/dts/Bindings/net/renesas,ravb.txt
index 1fd8831..b486f3f 100644
--- a/dts/Bindings/net/renesas,ravb.txt
+++ b/dts/Bindings/net/renesas,ravb.txt
@@ -6,8 +6,12 @@ interface contains.
Required properties:
- compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC.
"renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC.
+ "renesas,etheravb-r8a7795" if the device is a part of R8A7795 SoC.
- reg: offset and length of (1) the register block and (2) the stream buffer.
-- interrupts: interrupt specifier for the sole interrupt.
+- interrupts: A list of interrupt-specifiers, one for each entry in
+ interrupt-names.
+ If interrupt-names is not present, an interrupt specifier
+ for a single muxed interrupt.
- phy-mode: see ethernet.txt file in the same directory.
- phy-handle: see ethernet.txt file in the same directory.
- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
@@ -18,6 +22,12 @@ Required properties:
Optional properties:
- interrupt-parent: the phandle for the interrupt controller that services
interrupts for this device.
+- interrupt-names: A list of interrupt names.
+ For the R8A7795 SoC this property is mandatory;
+ it should include one entry per channel, named "ch%u",
+ where %u is the channel number ranging from 0 to 24.
+ For other SoCs this property is optional; if present
+ it should contain "mux" for a single muxed interrupt.
- pinctrl-names: pin configuration state name ("default").
- renesas,no-ether-link: boolean, specify when a board does not provide a proper
AVB_LINK signal.
@@ -27,13 +37,46 @@ Optional properties:
Example:
ethernet@e6800000 {
- compatible = "renesas,etheravb-r8a7790";
- reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ compatible = "renesas,etheravb-r8a7795";
+ reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
interrupt-parent = <&gic>;
- interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
- phy-mode = "rmii";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&mstp8_clks R8A7795_CLK_ETHERAVB>;
+ power-domains = <&cpg_clocks>;
+ phy-mode = "rgmii-id";
phy-handle = <&phy0>;
+
pinctrl-0 = <&ether_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
@@ -41,8 +84,20 @@ Example:
#size-cells = <0>;
phy0: ethernet-phy@0 {
+ rxc-skew-ps = <900>;
+ rxdv-skew-ps = <0>;
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txc-skew-ps = <900>;
+ txen-skew-ps = <0>;
+ txd0-skew-ps = <0>;
+ txd1-skew-ps = <0>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <0>;
reg = <0>;
interrupt-parent = <&gpio2>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/dts/Bindings/nvmem/imx-ocotp.txt b/dts/Bindings/nvmem/imx-ocotp.txt
new file mode 100644
index 0000000..383d588
--- /dev/null
+++ b/dts/Bindings/nvmem/imx-ocotp.txt
@@ -0,0 +1,20 @@
+Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
+
+This binding represents the on-chip eFuse OTP controller found on
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+
+Required properties:
+- compatible: should be one of
+ "fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
+ "fsl,imx6sl-ocotp" (i.MX6SL), or
+ "fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
+- reg: Should contain the register base and length.
+- clocks: Should contain a phandle pointing to the gated peripheral clock.
+
+Example:
+
+ ocotp: ocotp@021bc000 {
+ compatible = "fsl,imx6q-ocotp", "syscon";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6QDL_CLK_IIM>;
+ };
diff --git a/dts/Bindings/nvmem/mxs-ocotp.txt b/dts/Bindings/nvmem/mxs-ocotp.txt
new file mode 100644
index 0000000..daebce9
--- /dev/null
+++ b/dts/Bindings/nvmem/mxs-ocotp.txt
@@ -0,0 +1,25 @@
+On-Chip OTP Memory for Freescale i.MX23/i.MX28
+
+Required properties :
+- compatible :
+ - "fsl,imx23-ocotp" for i.MX23
+ - "fsl,imx28-ocotp" for i.MX28
+- #address-cells : Should be 1
+- #size-cells : Should be 1
+- reg : Address and length of OTP controller registers
+- clocks : Should contain a reference to the hbus clock
+
+= Data cells =
+Are child nodes of mxs-ocotp, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+Example for i.MX28:
+
+ ocotp: ocotp@8002c000 {
+ compatible = "fsl,imx28-ocotp", "fsl,ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x8002c000 0x2000>;
+ clocks = <&clks 25>;
+ status = "okay";
+ };
diff --git a/dts/Bindings/nvmem/rockchip-efuse.txt b/dts/Bindings/nvmem/rockchip-efuse.txt
new file mode 100644
index 0000000..8f86ab3
--- /dev/null
+++ b/dts/Bindings/nvmem/rockchip-efuse.txt
@@ -0,0 +1,38 @@
+= Rockchip eFuse device tree bindings =
+
+Required properties:
+- compatible: Should be "rockchip,rockchip-efuse"
+- reg: Should contain the registers location and exact eFuse size
+- clocks: Should be the clock id of eFuse
+- clock-names: Should be "pclk_efuse"
+
+= Data cells =
+Are child nodes of eFuse, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+Example:
+
+ efuse: efuse@ffb40000 {
+ compatible = "rockchip,rockchip-efuse";
+ reg = <0xffb40000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE256>;
+ clock-names = "pclk_efuse";
+
+ /* Data cells */
+ cpu_leakage: cpu_leakage {
+ reg = <0x17 0x1>;
+ };
+ };
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+Example:
+
+ cpu_leakage {
+ ...
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+ };
diff --git a/dts/Bindings/nvmem/vf610-ocotp.txt b/dts/Bindings/nvmem/vf610-ocotp.txt
new file mode 100644
index 0000000..56ed481
--- /dev/null
+++ b/dts/Bindings/nvmem/vf610-ocotp.txt
@@ -0,0 +1,19 @@
+On-Chip OTP Memory for Freescale Vybrid
+
+Required Properties:
+ compatible:
+ - "fsl,vf610-ocotp" for VF5xx/VF6xx
+ #address-cells : Should be 1
+ #size-cells : Should be 1
+ reg : Address and length of OTP controller and fuse map registers
+ clocks : ipg clock we associate with the OCOTP peripheral
+
+Example for Vybrid VF5xx/VF6xx:
+
+ ocotp: ocotp@400a5000 {
+ compatible = "fsl,vf610-ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x400a5000 0xCF0>;
+ clocks = <&clks VF610_CLK_OCOTP>;
+ };
diff --git a/dts/Bindings/pci/altera-pcie-msi.txt b/dts/Bindings/pci/altera-pcie-msi.txt
new file mode 100644
index 0000000..09cd3bc
--- /dev/null
+++ b/dts/Bindings/pci/altera-pcie-msi.txt
@@ -0,0 +1,28 @@
+* Altera PCIe MSI controller
+
+Required properties:
+- compatible: should contain "altr,msi-1.0"
+- reg: specifies the physical base address of the controller and
+ the length of the memory mapped region.
+- reg-names: must include the following entries:
+ "csr": CSR registers
+ "vector_slave": vectors slave port region
+- interrupt-parent: interrupt source phandle.
+- interrupts: specifies the interrupt source of the parent interrupt
+ controller. The format of the interrupt specifier depends on the
+ parent interrupt controller.
+- num-vectors: number of vectors, range 1 to 32.
+- msi-controller: indicates that this is MSI controller node
+
+
+Example
+msi0: msi@0xFF200000 {
+ compatible = "altr,msi-1.0";
+ reg = <0xFF200000 0x00000010
+ 0xFF200010 0x00000080>;
+ reg-names = "csr", "vector_slave";
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 42 4>;
+ msi-controller;
+ num-vectors = <32>;
+};
diff --git a/dts/Bindings/pci/altera-pcie.txt b/dts/Bindings/pci/altera-pcie.txt
new file mode 100644
index 0000000..2951a6a
--- /dev/null
+++ b/dts/Bindings/pci/altera-pcie.txt
@@ -0,0 +1,49 @@
+* Altera PCIe controller
+
+Required properties:
+- compatible : should contain "altr,pcie-root-port-1.0"
+- reg: a list of physical base address and length for TXS and CRA.
+- reg-names: must include the following entries:
+ "Txs": TX slave port region
+ "Cra": Control register access region
+- interrupt-parent: interrupt source phandle.
+- interrupts: specifies the interrupt source of the parent interrupt controller.
+ The format of the interrupt specifier depends on the parent interrupt
+ controller.
+- device_type: must be "pci"
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- #interrupt-cells: set to <1>
+- ranges: describes the translation of addresses for root ports and standard
+ PCI regions.
+- interrupt-map-mask and interrupt-map: standard PCI properties to define the
+ mapping of the PCIe interface to interrupt numbers.
+
+Optional properties:
+- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe
+ controller.
+- bus-range: PCI bus numbers covered
+
+Example
+ pcie_0: pcie@0xc00000000 {
+ compatible = "altr,pcie-root-port-1.0";
+ reg = <0xc0000000 0x20000000>,
+ <0xff220000 0x00004000>;
+ reg-names = "Txs", "Cra";
+ interrupt-parent = <&hps_0_arm_gic_0>;
+ interrupts = <0 40 4>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ bus-range = <0x0 0xFF>;
+ device_type = "pci";
+ msi-parent = <&msi_to_gic_gen_0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_0 1>,
+ <0 0 0 2 &pcie_0 2>,
+ <0 0 0 3 &pcie_0 3>,
+ <0 0 0 4 &pcie_0 4>;
+ ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
+ 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
+ };
diff --git a/dts/Bindings/pci/arm,juno-r1-pcie.txt b/dts/Bindings/pci/arm,juno-r1-pcie.txt
new file mode 100644
index 0000000..f7514c1
--- /dev/null
+++ b/dts/Bindings/pci/arm,juno-r1-pcie.txt
@@ -0,0 +1,10 @@
+* ARM Juno R1 PCIe interface
+
+This PCIe host controller is based on PLDA XpressRICH3-AXI IP
+and thus inherits all the common properties defined in plda,xpressrich3-axi.txt
+as well as the base properties defined in host-generic-pci.txt.
+
+Required properties:
+ - compatible: "arm,juno-r1-pcie"
+ - dma-coherent: The host controller bridges the AXI transactions into PCIe bus
+ in a manner that makes the DMA operations to appear coherent to the CPUs.
diff --git a/dts/Bindings/pci/brcm,iproc-pcie.txt b/dts/Bindings/pci/brcm,iproc-pcie.txt
index f7ce50e..45c2a80 100644
--- a/dts/Bindings/pci/brcm,iproc-pcie.txt
+++ b/dts/Bindings/pci/brcm,iproc-pcie.txt
@@ -17,6 +17,21 @@ Optional properties:
- phys: phandle of the PCIe PHY device
- phy-names: must be "pcie-phy"
+- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
+by the ASIC after power on reset. In this case, SW needs to configure it
+
+If the brcm,pcie-ob property is present, the following properties become
+effective:
+
+Required:
+- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal
+address used by the iProc PCIe core (not the PCIe address)
+- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB)
+
+Optional:
+- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
+increase the outbound window size
+
Example:
pcie0: pcie@18012000 {
compatible = "brcm,iproc-pcie";
@@ -38,6 +53,11 @@ Example:
phys = <&phy 0 5>;
phy-names = "pcie-phy";
+
+ brcm,pcie-ob;
+ brcm,pcie-ob-oarr-size;
+ brcm,pcie-ob-axi-offset = <0x00000000>;
+ brcm,pcie-ob-window-size = <256>;
};
pcie1: pcie@18013000 {
diff --git a/dts/Bindings/pci/designware-pcie.txt b/dts/Bindings/pci/designware-pcie.txt
index 9f4faa8..5b0853d 100644
--- a/dts/Bindings/pci/designware-pcie.txt
+++ b/dts/Bindings/pci/designware-pcie.txt
@@ -15,14 +15,16 @@ Required properties:
to define the mapping of the PCIe interface to interrupt
numbers.
- num-lanes: number of lanes to use
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - "pcie"
- - "pcie_bus"
Optional properties:
+- num-lanes: number of lanes to use (this property should be specified unless
+ the link is brought already up in BIOS)
- reset-gpio: gpio pin number of power good signal
- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
specify this property, to keep backwards compatibility a range of 0x00-0xff
is assumed if not present)
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - "pcie"
+ - "pcie_bus"
diff --git a/dts/Bindings/pci/hisilicon-pcie.txt b/dts/Bindings/pci/hisilicon-pcie.txt
new file mode 100644
index 0000000..17c6ed9
--- /dev/null
+++ b/dts/Bindings/pci/hisilicon-pcie.txt
@@ -0,0 +1,44 @@
+HiSilicon PCIe host bridge DT description
+
+HiSilicon PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver and inherits
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible: Should contain "hisilicon,hip05-pcie".
+- reg: Should contain rc_dbi, config registers location and length.
+- reg-names: Must include the following entries:
+ "rc_dbi": controller configuration registers;
+ "config": PCIe configuration space registers.
+- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
+- port-id: Should be 0, 1, 2 or 3.
+
+Optional properties:
+- status: Either "ok" or "disabled".
+- dma-coherent: Present if DMA operations are coherent.
+
+Example:
+ pcie@0xb0080000 {
+ compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
+ reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
+ reg-names = "rc_dbi", "config";
+ bus-range = <0 15>;
+ msi-parent = <&its_pcie>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
+ num-lanes = <8>;
+ port-id = <1>;
+ #interrupts-cells = <1>;
+ interrupts-map-mask = <0xf800 0 0 7>;
+ interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10
+ 0x0 0 0 2 &mbigen_pcie 2 11
+ 0x0 0 0 3 &mbigen_pcie 3 12
+ 0x0 0 0 4 &mbigen_pcie 4 13>;
+ status = "ok";
+ };
diff --git a/dts/Bindings/pci/host-generic-pci.txt b/dts/Bindings/pci/host-generic-pci.txt
index cf3e205..3f1d3fc 100644
--- a/dts/Bindings/pci/host-generic-pci.txt
+++ b/dts/Bindings/pci/host-generic-pci.txt
@@ -34,8 +34,9 @@ Properties of the host controller node:
- #size-cells : Must be 2.
- reg : The Configuration Space base address and size, as accessed
- from the parent bus.
-
+ from the parent bus. The base address corresponds to
+ the first bus in the "bus-range" property. If no
+ "bus-range" is specified, this will be bus 0 (the default).
Properties of the /chosen node:
diff --git a/dts/Bindings/pci/layerscape-pci.txt b/dts/Bindings/pci/layerscape-pci.txt
index 6286f04..e376785 100644
--- a/dts/Bindings/pci/layerscape-pci.txt
+++ b/dts/Bindings/pci/layerscape-pci.txt
@@ -1,10 +1,20 @@
Freescale Layerscape PCIe controller
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
+This controller derives its clocks from the Reset Configuration Word (RCW)
+which is used to describe the PLL settings at the time of chip-reset.
+
+Also as per the available Reference Manuals, there is no specific 'version'
+register available in the Freescale PCIe controller register set,
+which can allow determining the underlying DesignWare PCIe controller version
+information.
+
Required properties:
-- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
+- compatible: should contain the platform identifier such as:
+ "fsl,ls1021a-pcie", "snps,dw-pcie"
+ "fsl,ls2080a-pcie", "snps,dw-pcie"
- reg: base addresses and lengths of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
diff --git a/dts/Bindings/pci/pci-msi.txt b/dts/Bindings/pci/pci-msi.txt
new file mode 100644
index 0000000..9b3cc81
--- /dev/null
+++ b/dts/Bindings/pci/pci-msi.txt
@@ -0,0 +1,220 @@
+This document describes the generic device tree binding for describing the
+relationship between PCI devices and MSI controllers.
+
+Each PCI device under a root complex is uniquely identified by its Requester ID
+(AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
+Function number.
+
+For the purpose of this document, when treated as a numeric value, a RID is
+formatted such that:
+
+* Bits [15:8] are the Bus number.
+* Bits [7:3] are the Device number.
+* Bits [2:0] are the Function number.
+* Any other bits required for padding must be zero.
+
+MSIs may be distinguished in part through the use of sideband data accompanying
+writes. In the case of PCI devices, this sideband data may be derived from the
+Requester ID. A mechanism is required to associate a device with both the MSI
+controllers it can address, and the sideband data that will be associated with
+its writes to those controllers.
+
+For generic MSI bindings, see
+Documentation/devicetree/bindings/interrupt-controller/msi.txt.
+
+
+PCI root complex
+================
+
+Optional properties
+-------------------
+
+- msi-map: Maps a Requester ID to an MSI controller and associated
+ msi-specifier data. The property is an arbitrary number of tuples of
+ (rid-base,msi-controller,msi-base,length), where:
+
+ * rid-base is a single cell describing the first RID matched by the entry.
+
+ * msi-controller is a single phandle to an MSI controller
+
+ * msi-base is an msi-specifier describing the msi-specifier produced for the
+ first RID matched by the entry.
+
+ * length is a single cell describing how many consecutive RIDs are matched
+ following the rid-base.
+
+ Any RID r in the interval [rid-base, rid-base + length) is associated with
+ the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
+
+- msi-map-mask: A mask to be applied to each Requester ID prior to being mapped
+ to an msi-specifier per the msi-map property.
+
+- msi-parent: Describes the MSI parent of the root complex itself. Where
+ the root complex and MSI controller do not pass sideband data with MSI
+ writes, this property may be used to describe the MSI controller(s)
+ used by PCI devices under the root complex, if defined as such in the
+ binding for the root complex.
+
+
+Example (1)
+===========
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ msi: msi-controller@a {
+ reg = <0xa 0x1>;
+ compatible = "vendor,some-controller";
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ pci: pci@f {
+ reg = <0xf 0x1>;
+ compatible = "vendor,pcie-root-complex";
+ device_type = "pci";
+
+ /*
+ * The sideband data provided to the MSI controller is
+ * the RID, identity-mapped.
+ */
+ msi-map = <0x0 &msi_a 0x0 0x10000>,
+ };
+};
+
+
+Example (2)
+===========
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ msi: msi-controller@a {
+ reg = <0xa 0x1>;
+ compatible = "vendor,some-controller";
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ pci: pci@f {
+ reg = <0xf 0x1>;
+ compatible = "vendor,pcie-root-complex";
+ device_type = "pci";
+
+ /*
+ * The sideband data provided to the MSI controller is
+ * the RID, masked to only the device and function bits.
+ */
+ msi-map = <0x0 &msi_a 0x0 0x100>,
+ msi-map-mask = <0xff>
+ };
+};
+
+
+Example (3)
+===========
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ msi: msi-controller@a {
+ reg = <0xa 0x1>;
+ compatible = "vendor,some-controller";
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ pci: pci@f {
+ reg = <0xf 0x1>;
+ compatible = "vendor,pcie-root-complex";
+ device_type = "pci";
+
+ /*
+ * The sideband data provided to the MSI controller is
+ * the RID, but the high bit of the bus number is
+ * ignored.
+ */
+ msi-map = <0x0000 &msi 0x0000 0x8000>,
+ <0x8000 &msi 0x0000 0x8000>;
+ };
+};
+
+
+Example (4)
+===========
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ msi: msi-controller@a {
+ reg = <0xa 0x1>;
+ compatible = "vendor,some-controller";
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ pci: pci@f {
+ reg = <0xf 0x1>;
+ compatible = "vendor,pcie-root-complex";
+ device_type = "pci";
+
+ /*
+ * The sideband data provided to the MSI controller is
+ * the RID, but the high bit of the bus number is
+ * negated.
+ */
+ msi-map = <0x0000 &msi 0x8000 0x8000>,
+ <0x8000 &msi 0x0000 0x8000>;
+ };
+};
+
+
+Example (5)
+===========
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ msi_a: msi-controller@a {
+ reg = <0xa 0x1>;
+ compatible = "vendor,some-controller";
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ msi_b: msi-controller@b {
+ reg = <0xb 0x1>;
+ compatible = "vendor,some-controller";
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ msi_c: msi-controller@c {
+ reg = <0xc 0x1>;
+ compatible = "vendor,some-controller";
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ pci: pci@c {
+ reg = <0xf 0x1>;
+ compatible = "vendor,pcie-root-complex";
+ device_type = "pci";
+
+ /*
+ * The sideband data provided to MSI controller a is the
+ * RID, but the high bit of the bus number is negated.
+ * The sideband data provided to MSI controller b is the
+ * RID, identity-mapped.
+ * MSI controller c is not addressable.
+ */
+ msi-map = <0x0000 &msi_a 0x8000 0x08000>,
+ <0x8000 &msi_a 0x0000 0x08000>,
+ <0x0000 &msi_b 0x0000 0x10000>;
+ };
+};
diff --git a/dts/Bindings/pci/pci.txt b/dts/Bindings/pci/pci.txt
index f8fbe9a..08dcfad 100644
--- a/dts/Bindings/pci/pci.txt
+++ b/dts/Bindings/pci/pci.txt
@@ -1,12 +1,12 @@
PCI bus bridges have standardized Device Tree bindings:
PCI Bus Binding to: IEEE Std 1275-1994
-http://www.openfirmware.org/ofwg/bindings/pci/pci2_1.pdf
+http://www.firmware.org/1275/bindings/pci/pci2_1.pdf
And for the interrupt mapping part:
Open Firmware Recommended Practice: Interrupt Mapping
-http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf
+http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
Additionally to the properties specified in the above standards a host bridge
driver implementation may support the following properties:
diff --git a/dts/Bindings/pci/plda,xpressrich3-axi.txt b/dts/Bindings/pci/plda,xpressrich3-axi.txt
new file mode 100644
index 0000000..f3f75bf
--- /dev/null
+++ b/dts/Bindings/pci/plda,xpressrich3-axi.txt
@@ -0,0 +1,12 @@
+* PLDA XpressRICH3-AXI host controller
+
+The PLDA XpressRICH3-AXI host controller can be configured in a manner that
+makes it compliant with the SBSA[1] standard published by ARM Ltd. For those
+scenarios, the host-generic-pci.txt bindings apply with the following additions
+to the compatible property:
+
+Required properties:
+ - compatible: should contain "plda,xpressrich3-axi" to identify the IP used.
+
+
+[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/
diff --git a/dts/Bindings/phy/brcm,cygnus-pcie-phy.txt b/dts/Bindings/phy/brcm,cygnus-pcie-phy.txt
new file mode 100644
index 0000000..761c4bc
--- /dev/null
+++ b/dts/Bindings/phy/brcm,cygnus-pcie-phy.txt
@@ -0,0 +1,47 @@
+Broadcom Cygnus PCIe PHY
+
+Required properties:
+- compatible: must be "brcm,cygnus-pcie-phy"
+- reg: base address and length of the PCIe PHY block
+- #address-cells: must be 1
+- #size-cells: must be 0
+
+Each PCIe PHY should be represented by a child node
+
+Required properties For the child node:
+- reg: the PHY ID
+0 - PCIe RC 0
+1 - PCIe RC 1
+- #phy-cells: must be 0
+
+Example:
+ pcie_phy: phy@0301d0a0 {
+ compatible = "brcm,cygnus-pcie-phy";
+ reg = <0x0301d0a0 0x14>;
+
+ pcie0_phy: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ pcie1_phy: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
+ /* users of the PCIe phy */
+
+ pcie0: pcie@18012000 {
+ ...
+ ...
+ phys = <&pcie0_phy>;
+ phy-names = "pcie-phy";
+ };
+
+ pcie1: pcie@18013000 {
+ ...
+ ...
+ phys = <pcie1_phy>;
+ phy-names = "pcie-phy";
+ };
diff --git a/dts/Bindings/arm/calxeda/combophy.txt b/dts/Bindings/phy/calxeda-combophy.txt
index 6622bdb..6622bdb 100644
--- a/dts/Bindings/arm/calxeda/combophy.txt
+++ b/dts/Bindings/phy/calxeda-combophy.txt
diff --git a/dts/Bindings/usb/keystone-phy.txt b/dts/Bindings/phy/keystone-usb-phy.txt
index f37b3a8..f37b3a8 100644
--- a/dts/Bindings/usb/keystone-phy.txt
+++ b/dts/Bindings/phy/keystone-usb-phy.txt
diff --git a/dts/Bindings/usb/mxs-phy.txt b/dts/Bindings/phy/mxs-usb-phy.txt
index 379b84a..379b84a 100644
--- a/dts/Bindings/usb/mxs-phy.txt
+++ b/dts/Bindings/phy/mxs-usb-phy.txt
diff --git a/dts/Bindings/usb/nvidia,tegra20-usb-phy.txt b/dts/Bindings/phy/nvidia,tegra20-usb-phy.txt
index a9aa79f..a9aa79f 100644
--- a/dts/Bindings/usb/nvidia,tegra20-usb-phy.txt
+++ b/dts/Bindings/phy/nvidia,tegra20-usb-phy.txt
diff --git a/dts/Bindings/phy/phy-mt65xx-usb.txt b/dts/Bindings/phy/phy-mt65xx-usb.txt
new file mode 100644
index 0000000..00100cf
--- /dev/null
+++ b/dts/Bindings/phy/phy-mt65xx-usb.txt
@@ -0,0 +1,68 @@
+mt65xx USB3.0 PHY binding
+--------------------------
+
+This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
+
+Required properties (controller (parent) node):
+ - compatible : should be "mediatek,mt8173-u3phy"
+ - reg : offset and length of register for phy, exclude port's
+ register.
+ - clocks : a list of phandle + clock-specifier pairs, one for each
+ entry in clock-names
+ - clock-names : must contain
+ "u3phya_ref": for reference clock of usb3.0 analog phy.
+
+Required nodes : a sub-node is required for each port the controller
+ provides. Address range information including the usual
+ 'reg' property is used inside these nodes to describe
+ the controller's topology.
+
+Required properties (port (child) node):
+- reg : address and length of the register set for the port.
+- #phy-cells : should be 1 (See second example)
+ cell after port phandle is phy type from:
+ - PHY_TYPE_USB2
+ - PHY_TYPE_USB3
+
+Example:
+
+u3phy: usb-phy@11290000 {
+ compatible = "mediatek,mt8173-u3phy";
+ reg = <0 0x11290000 0 0x800>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "u3phya_ref";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ phy_port0: port@11290800 {
+ reg = <0 0x11290800 0 0x800>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ phy_port1: port@11291000 {
+ reg = <0 0x11291000 0 0x800>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+};
+
+Specifying phy control of devices
+---------------------------------
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy port node and a device type;
+phy-names for each port are optional.
+
+Example:
+
+#include <dt-bindings/phy/phy.h>
+
+usb30: usb@11270000 {
+ ...
+ phys = <&phy_port0 PHY_TYPE_USB3>;
+ phy-names = "usb3-0";
+ ...
+};
diff --git a/dts/Bindings/usb/qcom,usb-8x16-phy.txt b/dts/Bindings/phy/qcom,usb-8x16-phy.txt
index 2cb2168..2cb2168 100644
--- a/dts/Bindings/usb/qcom,usb-8x16-phy.txt
+++ b/dts/Bindings/phy/qcom,usb-8x16-phy.txt
diff --git a/dts/Bindings/phy/samsung-phy.txt b/dts/Bindings/phy/samsung-phy.txt
index 60c6f2a..0289d3b 100644
--- a/dts/Bindings/phy/samsung-phy.txt
+++ b/dts/Bindings/phy/samsung-phy.txt
@@ -44,6 +44,9 @@ Required properties:
- the "ref" clock is used to get the rate of the clock provided to the
PHY module
+Optional properties:
+- vbus-supply: power-supply phandle for vbus power source
+
The first phandle argument in the PHY specifier identifies the PHY, its
meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
and Exynos 4212) it is as follows:
diff --git a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 3c821cd..b321b26 100644
--- a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -17,6 +17,7 @@ Required properties:
"allwinner,sun8i-a23-pinctrl"
"allwinner,sun8i-a23-r-pinctrl"
"allwinner,sun8i-a33-pinctrl"
+ "allwinner,sun8i-a83t-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/dts/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/dts/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
new file mode 100644
index 0000000..61ac757
--- /dev/null
+++ b/dts/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
@@ -0,0 +1,90 @@
+* Atmel PIO4 Controller
+
+The Atmel PIO4 controller is used to select the function of a pin and to
+configure it.
+
+Required properties:
+- compatible: "atmel,sama5d2-pinctrl".
+- reg: base address and length of the PIO controller.
+- interrupts: interrupt outputs from the controller, one for each bank.
+- interrupt-controller: mark the device node as an interrupt controller.
+- #interrupt-cells: should be two.
+- gpio-controller: mark the device node as a gpio controller.
+- #gpio-cells: should be two.
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+Subnode format
+Each node (or subnode) will list the pins it needs and how to configured these
+pins.
+
+ node {
+ pinmux = <PIN_NUMBER_PINMUX>;
+ GENERIC_PINCONFIG;
+ };
+
+Required properties:
+- pinmux: integer array. Each integer represents a pin number plus mux and
+ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the
+right representation of the pin.
+
+Optional properties:
+- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
+bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
+input-debounce, output-low, output-high.
+
+Example:
+
+#include <sama5d2-pinfunc.h>
+
+...
+{
+ pioA: pinctrl@fc038000 {
+ compatible = "atmel,sama5d2-pinctrl";
+ reg = <0xfc038000 0x600>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
+ <68 IRQ_TYPE_LEVEL_HIGH 7>,
+ <69 IRQ_TYPE_LEVEL_HIGH 7>,
+ <70 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&pioA_clk>;
+
+ pinctrl_i2c0_default: i2c0_default {
+ pinmux = <PIN_PD21__TWD0>,
+ <PIN_PD22__TWCK0>;
+ bias-disable;
+ };
+
+ pinctrl_led_gpio_default: led_gpio_default {
+ pinmux = <PIN_PB0>,
+ <PIN_PB5>;
+ bias-pull-up;
+ };
+
+ pinctrl_sdmmc1_default: sdmmc1_default {
+ cmd_data {
+ pinmux = <PIN_PA28__SDMMC1_CMD>,
+ <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>;
+ bias-pull-up;
+ };
+
+ ck_cd {
+ pinmux = <PIN_PA22__SDMMC1_CK>,
+ <PIN_PA30__SDMMC1_CD>;
+ bias-disable;
+ };
+ };
+ ...
+ };
+};
+...
diff --git a/dts/Bindings/pinctrl/berlin,pinctrl.txt b/dts/Bindings/pinctrl/berlin,pinctrl.txt
index a8bb5e2..f8fa28c 100644
--- a/dts/Bindings/pinctrl/berlin,pinctrl.txt
+++ b/dts/Bindings/pinctrl/berlin,pinctrl.txt
@@ -20,7 +20,10 @@ Required properties:
"marvell,berlin2cd-soc-pinctrl",
"marvell,berlin2cd-system-pinctrl",
"marvell,berlin2q-soc-pinctrl",
- "marvell,berlin2q-system-pinctrl"
+ "marvell,berlin2q-system-pinctrl",
+ "marvell,berlin4ct-avio-pinctrl",
+ "marvell,berlin4ct-soc-pinctrl",
+ "marvell,berlin4ct-system-pinctrl"
Required subnode-properties:
- groups: a list of strings describing the group names.
diff --git a/dts/Bindings/pinctrl/brcm,cygnus-gpio.txt b/dts/Bindings/pinctrl/brcm,cygnus-gpio.txt
index 6540ca5..16589fb 100644
--- a/dts/Bindings/pinctrl/brcm,cygnus-gpio.txt
+++ b/dts/Bindings/pinctrl/brcm,cygnus-gpio.txt
@@ -3,8 +3,8 @@ Broadcom Cygnus GPIO/PINCONF Controller
Required properties:
- compatible:
- Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
- "brcm,cygnus-crmu-gpio"
+ Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio",
+ "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio"
- reg:
Define the base and range of the I/O address space that contains the Cygnus
@@ -26,9 +26,13 @@ Optional properties:
- interrupt-controller:
Specifies that the node is an interrupt controller
-- pinmux:
- Specifies the phandle to the IOMUX device, where pins can be individually
-muxed to GPIO
+- gpio-ranges:
+ Specifies the mapping between gpio controller and pin-controllers pins.
+ This requires 4 fields in cells defined as -
+ 1. Phandle of pin-controller.
+ 2. GPIO base pin offset.
+ 3 Pin-control base pin offset.
+ 4. number of gpio pins which are linearly mapped from pin base.
Supported generic PINCONF properties in child nodes:
@@ -78,6 +82,8 @@ Example:
gpio-controller;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
+ gpio-ranges = <&pinctrl 0 42 1>,
+ <&pinctrl 1 44 3>;
};
/*
diff --git a/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d..457b2c6 100644
--- a/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/dts/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -1,16 +1,42 @@
* Freescale i.MX7 Dual IOMUX Controller
+iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
+as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
+power state retention capabilities on gpios that are part of iomuxc-lpsr
+(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
+mux and pad control settings, it shares the input select register from main
+iomuxc controller for daisy chain settings, the fsl,input-sel property extends
+fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
+
+iomuxc_lpsr: iomuxc-lpsr@302c0000 {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c0000 0x10000>;
+ fsl,input-sel = <&iomuxc>;
+};
+
+iomuxc: iomuxc@30330000 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x30330000 0x10000>;
+};
+
+Pheriparials using pads from iomuxc-lpsr support low state retention power
+state, under LPSR mode GPIO's state of pads are retain.
+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
-- compatible: "fsl,imx7d-iomuxc"
+- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
+ "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
Reference Manual for detailed CONFIG settings.
+- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
+ a phandle for main iomuxc controller which shares the input select register for
+ daisy chain settings.
CONFIG bits definition:
PAD_CTL_PUS_100K_DOWN (0 << 5)
@@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
+
+Examples:
+While iomuxc-lpsr is intended to be used by dedicated peripherals to take
+advantages of LPSR power mode, is also possible that an IP to use pads from
+any of the iomux controllers. For example the I2C1 IP can use SCL pad from
+iomuxc-lpsr controller and SDA pad from iomuxc controller as:
+
+i2c1: i2c@30a20000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
+ status = "okay";
+};
+
+iomuxc-lpsr@302c0000 {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c0000 0x10000>;
+ fsl,input-sel = <&iomuxc>;
+
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
+ >;
+ };
+};
+
+iomuxc@30330000 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x30330000 0x10000>;
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
+ >;
+ };
+};
diff --git a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
index 9496934..ffadb7a 100644
--- a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -19,6 +19,7 @@ Required Properties:
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
+ - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
diff --git a/dts/Bindings/power/bq24257.txt b/dts/Bindings/power/bq24257.txt
index 5c9d394..d693702 100644
--- a/dts/Bindings/power/bq24257.txt
+++ b/dts/Bindings/power/bq24257.txt
@@ -1,21 +1,64 @@
-Binding for TI bq24257 Li-Ion Charger
+Binding for TI bq24250/bq24251/bq24257 Li-Ion Charger
Required properties:
- compatible: Should contain one of the following:
+ * "ti,bq24250"
+ * "ti,bq24251"
* "ti,bq24257"
-- reg: integer, i2c address of the device.
+- reg: integer, i2c address of the device.
+- interrupt-parent: Should be the phandle for the interrupt controller. Use in
+ conjunction with "interrupts".
+- interrupts: Interrupt mapping for GPIO IRQ (configure for both edges). Use in
+ conjunction with "interrupt-parent".
- ti,battery-regulation-voltage: integer, maximum charging voltage in uV.
-- ti,charge-current: integer, maximum charging current in uA.
-- ti,termination-current: integer, charge will be terminated when current in
- constant-voltage phase drops below this value (in uA).
+- ti,charge-current: integer, maximum charging current in uA.
+- ti,termination-current: integer, charge will be terminated when current in
+ constant-voltage phase drops below this value (in uA).
+
+Optional properties:
+- pg-gpios: GPIO used for connecting the bq2425x device PG (Power Good) pin.
+ This pin is not available on all devices however it should be used if
+ possible as this is the recommended way to obtain the charger's input PG
+ state. If this pin is not specified a software-based approach for PG
+ detection is used.
+- ti,current-limit: The maximum current to be drawn from the charger's input
+ (in uA). If this property is not specified, the input limit current is
+ set automatically using USB D+/D- signal based charger type detection.
+ If the hardware does not support the D+/D- based detection, a default
+ of 500,000 is used (=500mA) instead.
+- ti,ovp-voltage: Configures the over voltage protection voltage (in uV). If
+ not specified a default of 6,5000,000 (=6.5V) is used.
+- ti,in-dpm-voltage: Configures the threshold input voltage for the dynamic
+ power path management (in uV). If not specified a default of 4,360,000
+ (=4.36V) is used.
Example:
bq24257 {
compatible = "ti,bq24257";
reg = <0x6a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 IRQ_TYPE_EDGE_BOTH>;
+
+ pg-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
ti,battery-regulation-voltage = <4200000>;
ti,charge-current = <1000000>;
ti,termination-current = <50000>;
};
+
+Example:
+
+bq24250 {
+ compatible = "ti,bq24250";
+ reg = <0x6a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 IRQ_TYPE_EDGE_BOTH>;
+
+ ti,battery-regulation-voltage = <4200000>;
+ ti,charge-current = <500000>;
+ ti,termination-current = <50000>;
+ ti,current-limit = <900000>;
+ ti,ovp-voltage = <9500000>;
+ ti,in-dpm-voltage = <4440000>;
+};
diff --git a/dts/Bindings/power/da9150-fg.txt b/dts/Bindings/power/da9150-fg.txt
new file mode 100644
index 0000000..00236fe
--- /dev/null
+++ b/dts/Bindings/power/da9150-fg.txt
@@ -0,0 +1,23 @@
+Dialog Semiconductor DA9150 Fuel-Gauge Power Supply bindings
+
+Required properties:
+- compatible: "dlg,da9150-fuel-gauge" for DA9150 Fuel-Gauge Power Supply
+
+Optional properties:
+- dlg,update-interval: Interval time (milliseconds) between battery level checks.
+- dlg,warn-soc-level: Battery discharge level (%) where warning event raised.
+ [1 - 100]
+- dlg,crit-soc-level: Battery discharge level (%) where critical event raised.
+ This value should be lower than the warning level.
+ [1 - 100]
+
+
+Example:
+
+ fuel-gauge {
+ compatible = "dlg,da9150-fuel-gauge";
+
+ dlg,update-interval = <10000>;
+ dlg,warn-soc-level = /bits/ 8 <15>;
+ dlg,crit-soc-level = /bits/ 8 <5>;
+ };
diff --git a/dts/Bindings/arm/exynos/power_domain.txt b/dts/Bindings/power/pd-samsung.txt
index e151057..4e94737 100644
--- a/dts/Bindings/arm/exynos/power_domain.txt
+++ b/dts/Bindings/power/pd-samsung.txt
@@ -43,9 +43,8 @@ Example:
mfc_pd: power-domain@10044060 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044060 0x20>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
- <&clock CLK_MOUT_USER_ACLK333>;
- clock-names = "oscclk", "pclk0", "clk0";
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
+ clock-names = "oscclk", "clk0";
#power-domain-cells = <0>;
};
diff --git a/dts/Bindings/power/wakeup-source.txt b/dts/Bindings/power/wakeup-source.txt
new file mode 100644
index 0000000..963c6df
--- /dev/null
+++ b/dts/Bindings/power/wakeup-source.txt
@@ -0,0 +1,71 @@
+Specifying wakeup capability for devices
+============================================
+
+Any device nodes
+----------------
+Nodes that describe devices which has wakeup capability must contain an
+"wakeup-source" boolean property.
+
+Also, if device is marked as a wakeup source, then all the primary
+interrupt(s) can be used as wakeup interrupt(s).
+
+However if the devices have dedicated interrupt as the wakeup source
+then they need to specify/identify the same using device specific
+interrupt name. In such cases only that interrupt can be used as wakeup
+interrupt.
+
+List of legacy properties and respective binding document
+---------------------------------------------------------
+
+1. "enable-sdio-wakeup" Documentation/devicetree/bindings/mmc/mmc.txt
+2. "gpio-key,wakeup" Documentation/devicetree/bindings/input/gpio-keys{,-polled}.txt
+3. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt
+4. "isil,irq2-can-wakeup-machine" Documentation/devicetree/bindings/rtc/isil,isl12057.txt
+5. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
+ Documentation/devicetree/bindings/mfd/tc3589x.txt
+ Documentation/devicetree/bindings/input/ads7846.txt
+6. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
+7. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt
+8. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+
+Examples
+--------
+
+1. With "wakeup" interrupt name
+
+ device@10000 {
+ compatible = "vendor,device-id";
+ reg = <0x10000 0x1000>;
+ interrupts = <0 19 4>, <0 21 4>, <0 22 4>;
+ interrupt-names = "ack", "err", "wakeup";
+ wakeup-source;
+ };
+
+2. Without "wakeup" interrupt name
+
+ embedded-controller {
+ compatible = "google,cros-ec-i2c";
+ reg = <0x1e>;
+ interrupts = <6 0>;
+ interrupt-parent = <&gpx1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ec_irq>;
+ wakeup-source;
+ };
+
+3. Without interrupts
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@1 {
+ debounce_interval = <50>;
+ wakeup-source;
+ linux,code = <116>;
+ label = "POWER";
+ gpios = <&iofpga_gpio0 0 0x4>;
+ };
+ [....]
+ };
diff --git a/dts/Bindings/power_supply/axp20x_usb_power.txt b/dts/Bindings/power_supply/axp20x_usb_power.txt
new file mode 100644
index 0000000..862f4a4
--- /dev/null
+++ b/dts/Bindings/power_supply/axp20x_usb_power.txt
@@ -0,0 +1,34 @@
+AXP20x USB power supply
+
+Required Properties:
+-compatible: "x-powers,axp202-usb-power-supply"
+
+This node is a subnode of the axp20x PMIC.
+
+Example:
+
+axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ regulators {
+ x-powers,dcdc-freq = <1500>;
+
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ ...
+ };
+
+ usb-power-supply: usb-power-supply {
+ compatible = "x-powers,axp202-usb-power-supply";
+ };
+};
diff --git a/dts/Bindings/power_supply/qcom_smbb.txt b/dts/Bindings/power_supply/qcom_smbb.txt
new file mode 100644
index 0000000..65b88fa
--- /dev/null
+++ b/dts/Bindings/power_supply/qcom_smbb.txt
@@ -0,0 +1,131 @@
+Qualcomm Switch-Mode Battery Charger and Boost
+
+PROPERTIES
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Description: Must be one of:
+ - "qcom,pm8941-charger"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Description: Base address of registers for SMBB block
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Description: The format of the specifier is defined by the binding document
+ describing the node's interrupt parent. Must contain one
+ specifier for each of the following interrupts, in order:
+ - charge done
+ - charge fast mode
+ - charge trickle mode
+ - battery temperature ok
+ - battery present
+ - charger disconnected
+ - USB-in valid
+ - DC-in valid
+
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Description: Must contain the following list, strictly ordered:
+ "chg-done",
+ "chg-fast",
+ "chg-trkl",
+ "bat-temp-ok",
+ "bat-present",
+ "chg-gone",
+ "usb-valid",
+ "dc-valid"
+
+- qcom,fast-charge-current-limit:
+ Usage: optional (default: 1A, or pre-configured value)
+ Value type: <u32>; uA; range [100mA : 3A]
+ Description: Maximum charge current; May be clamped to safety limits.
+
+- qcom,fast-charge-low-threshold-voltage:
+ Usage: optional (default: 3.2V, or pre-configured value)
+ Value type: <u32>; uV; range [2.1V : 3.6V]
+ Description: Battery voltage limit above which fast charging may operate;
+ Below this value linear or switch-mode auto-trickle-charging
+ will operate.
+
+- qcom,fast-charge-high-threshold-voltage:
+ Usage: optional (default: 4.2V, or pre-configured value)
+ Value type: <u32>; uV; range [3.24V : 5V]
+ Description: Battery voltage limit below which fast charging may operate;
+ The fast charger will attempt to charge the battery to this
+ voltage. May be clamped to safety limits.
+
+- qcom,fast-charge-safe-voltage:
+ Usage: optional (default: 4.2V, or pre-configured value)
+ Value type: <u32>; uV; range [3.24V : 5V]
+ Description: Maximum safe battery voltage; May be pre-set by bootloader, in
+ which case, setting this will harmlessly fail. The property
+ 'fast-charge-high-watermark' will be clamped by this value.
+
+- qcom,fast-charge-safe-current:
+ Usage: optional (default: 1A, or pre-configured value)
+ Value type: <u32>; uA; range [100mA : 3A]
+ Description: Maximum safe battery charge current; May pre-set by bootloader,
+ in which case, setting this will harmlessly fail. The property
+ 'qcom,fast-charge-current-limit' will be clamped by this value.
+
+- qcom,auto-recharge-threshold-voltage:
+ Usage: optional (default: 4.1V, or pre-configured value)
+ Value type: <u32>; uV; range [3.24V : 5V]
+ Description: Battery voltage limit below which auto-recharge functionality
+ will restart charging after end-of-charge; The high cutoff
+ limit for auto-recharge is 5% above this value.
+
+- qcom,minimum-input-voltage:
+ Usage: optional (default: 4.3V, or pre-configured value)
+ Value type: <u32>; uV; range [4.2V : 9.6V]
+ Description: Input voltage level above which charging may operate
+
+- qcom,dc-current-limit:
+ Usage: optional (default: 100mA, or pre-configured value)
+ Value type: <u32>; uA; range [100mA : 2.5A]
+ Description: Default DC charge current limit
+
+- qcom,disable-dc:
+ Usage: optional (default: false)
+ Value type: boolean: <u32> or <empty>
+ Description: Disable DC charger
+
+- qcom,jeita-extended-temp-range:
+ Usage: optional (default: false)
+ Value type: boolean: <u32> or <empty>
+ Description: Enable JEITA extended temperature range; This does *not*
+ adjust the maximum charge voltage or current in the extended
+ temperature range. It only allows charging when the battery
+ is in the extended temperature range. Voltage/current
+ regulation must be done externally to fully comply with
+ the JEITA safety guidelines if this flag is set.
+
+EXAMPLE
+charger@1000 {
+ compatible = "qcom,pm8941-charger";
+ reg = <0x1000 0x700>;
+ interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "chg-done",
+ "chg-fast",
+ "chg-trkl",
+ "bat-temp-ok",
+ "bat-present",
+ "chg-gone",
+ "usb-valid",
+ "dc-valid";
+
+ qcom,fast-charge-current-limit = <1000000>;
+ qcom,dc-charge-current-limit = <1000000>;
+};
diff --git a/dts/Bindings/power_supply/tps65217_charger.txt b/dts/Bindings/power_supply/tps65217_charger.txt
new file mode 100644
index 0000000..98d131a
--- /dev/null
+++ b/dts/Bindings/power_supply/tps65217_charger.txt
@@ -0,0 +1,12 @@
+TPS65217 Charger
+
+Required Properties:
+-compatible: "ti,tps65217-charger"
+
+This node is a subnode of the tps65217 PMIC.
+
+Example:
+
+ tps65217-charger {
+ compatible = "ti,tps65090-charger";
+ };
diff --git a/dts/Bindings/powerpc/fsl/mpc512x_lpbfifo.txt b/dts/Bindings/powerpc/fsl/mpc512x_lpbfifo.txt
new file mode 100644
index 0000000..b3b392f
--- /dev/null
+++ b/dts/Bindings/powerpc/fsl/mpc512x_lpbfifo.txt
@@ -0,0 +1,21 @@
+Freescale MPC512x LocalPlus Bus FIFO (called SCLPC in the Reference Manual)
+
+Required properties:
+- compatible: should be "fsl,mpc512x-lpbfifo";
+- reg: should contain the offset and length of SCLPC register set;
+- interrupts: should contain the interrupt specifier for SCLPC; syntax of an
+ interrupt client node is described in interrupt-controller/interrupts.txt;
+- dmas: should contain the DMA specifier for SCLPC as described at
+ dma/dma.txt and dma/mpc512x-dma.txt;
+- dma-names: should be "rx-tx";
+
+Example:
+
+ sclpc@10100 {
+ compatible = "fsl,mpc512x-lpbfifo";
+ reg = <0x10100 0x50>;
+ interrupts = <7 0x8>;
+ dmas = <&dma0 26>;
+ dma-names = "rx-tx";
+ };
+
diff --git a/dts/Bindings/pwm/brcm,bcm7038-pwm.txt b/dts/Bindings/pwm/brcm,bcm7038-pwm.txt
new file mode 100644
index 0000000..d9254a6
--- /dev/null
+++ b/dts/Bindings/pwm/brcm,bcm7038-pwm.txt
@@ -0,0 +1,20 @@
+Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller)
+
+Required properties:
+
+- compatible: must be "brcm,bcm7038-pwm"
+- reg: physical base address and length for this controller
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description
+ of the cells format
+- clocks: a phandle to the reference clock for this block which is fed through
+ its internal variable clock frequency generator
+
+
+Example:
+
+ pwm: pwm@f0408000 {
+ compatible = "brcm,bcm7038-pwm";
+ reg = <0xf0408000 0x28>;
+ #pwm-cells = <2>;
+ clocks = <&upg_fixed>;
+ };
diff --git a/dts/Bindings/pwm/pwm-berlin.txt b/dts/Bindings/pwm/pwm-berlin.txt
new file mode 100644
index 0000000..82cbe16
--- /dev/null
+++ b/dts/Bindings/pwm/pwm-berlin.txt
@@ -0,0 +1,17 @@
+Berlin PWM controller
+
+Required properties:
+- compatible: should be "marvell,berlin-pwm"
+- reg: physical base address and length of the controller's registers
+- clocks: phandle to the input clock
+- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
+ the cells format.
+
+Example:
+
+pwm: pwm@f7f20000 {
+ compatible = "marvell,berlin-pwm";
+ reg = <0xf7f20000 0x40>;
+ clocks = <&chip_clk CLKID_CFG>;
+ #pwm-cells = <3>;
+}
diff --git a/dts/Bindings/pwm/pwm-mtk-disp.txt b/dts/Bindings/pwm/pwm-mtk-disp.txt
new file mode 100644
index 0000000..f8f59ba
--- /dev/null
+++ b/dts/Bindings/pwm/pwm-mtk-disp.txt
@@ -0,0 +1,42 @@
+MediaTek display PWM controller
+
+Required properties:
+ - compatible: should be "mediatek,<name>-disp-pwm":
+ - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
+ - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
+ - reg: physical base address and length of the controller's registers.
+ - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
+ the cell format.
+ - clocks: phandle and clock specifier of the PWM reference clock.
+ - clock-names: must contain the following:
+ - "main": clock used to generate PWM signals.
+ - "mm": sync signals from the modules of mmsys.
+ - pinctrl-names: Must contain a "default" entry.
+ - pinctrl-0: One property must exist for each entry in pinctrl-names.
+ See pinctrl/pinctrl-bindings.txt for details of the property values.
+
+Example:
+ pwm0: pwm@1401e000 {
+ compatible = "mediatek,mt8173-disp-pwm",
+ "mediatek,mt6595-disp-pwm";
+ reg = <0 0x1401e000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&mmsys CLK_MM_DISP_PWM026M>,
+ <&mmsys CLK_MM_DISP_PWM0MM>;
+ clock-names = "main", "mm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&disp_pwm0_pins>;
+ };
+
+ backlight_lcd: backlight_lcd {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 1000000>;
+ brightness-levels = <
+ 0 16 32 48 64 80 96 112
+ 128 144 160 176 192 208 224 240
+ 255
+ >;
+ default-brightness-level = <9>;
+ power-supply = <&mt6397_vio18_reg>;
+ enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/Bindings/pwm/pwm-sun4i.txt b/dts/Bindings/pwm/pwm-sun4i.txt
index ae0273e..cf6068b 100644
--- a/dts/Bindings/pwm/pwm-sun4i.txt
+++ b/dts/Bindings/pwm/pwm-sun4i.txt
@@ -3,6 +3,8 @@ Allwinner sun4i and sun7i SoC PWM controller
Required properties:
- compatible: should be one of:
- "allwinner,sun4i-a10-pwm"
+ - "allwinner,sun5i-a10s-pwm"
+ - "allwinner,sun5i-a13-pwm"
- "allwinner,sun7i-a20-pwm"
- reg: physical base address and length of the controller's registers
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
diff --git a/dts/Bindings/pwm/renesas,pwm-rcar.txt b/dts/Bindings/pwm/renesas,pwm-rcar.txt
new file mode 100644
index 0000000..0822a08
--- /dev/null
+++ b/dts/Bindings/pwm/renesas,pwm-rcar.txt
@@ -0,0 +1,26 @@
+* Renesas R-Car PWM Timer Controller
+
+Required Properties:
+- compatible: should be "renesas,pwm-rcar" and one of the following.
+ - "renesas,pwm-r8a7778": for R-Car M1A
+ - "renesas,pwm-r8a7779": for R-Car H1
+ - "renesas,pwm-r8a7790": for R-Car H2
+ - "renesas,pwm-r8a7791": for R-Car M2-W
+ - "renesas,pwm-r8a7794": for R-Car E2
+- reg: base address and length of the registers block for the PWM.
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+ the cells format.
+- clocks: clock phandle and specifier pair.
+- pinctrl-0: phandle, referring to a default pin configuration node.
+- pinctrl-names: Set to "default".
+
+Example: R8A7790 (R-Car H2) PWM Timer node
+
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x8>;
+ #pwm-cells = <2>;
+ clocks = <&mstp5_clks R8A7790_CLK_PWM>;
+ pinctrl-0 = <&pwm0_pins>;
+ pinctrl-names = "default";
+ };
diff --git a/dts/Bindings/regulator/act8865-regulator.txt b/dts/Bindings/regulator/act8865-regulator.txt
index e91485d..6067d98 100644
--- a/dts/Bindings/regulator/act8865-regulator.txt
+++ b/dts/Bindings/regulator/act8865-regulator.txt
@@ -8,6 +8,8 @@ Required properties:
Optional properties:
- system-power-controller: Telling whether or not this pmic is controlling
the system power. See Documentation/devicetree/bindings/power/power-controller.txt .
+- active-semi,vsel-high: Indicates the VSEL pin is high.
+ If this property is missing, assume the VSEL pin is low(0).
Optional input supply properties:
- for act8600:
@@ -49,6 +51,7 @@ Example:
pmic: act8865@5b {
compatible = "active-semi,act8865";
reg = <0x5b>;
+ active-semi,vsel-high;
status = "disabled";
regulators {
diff --git a/dts/Bindings/regulator/anatop-regulator.txt b/dts/Bindings/regulator/anatop-regulator.txt
index 758eae2..37c4ea0 100644
--- a/dts/Bindings/regulator/anatop-regulator.txt
+++ b/dts/Bindings/regulator/anatop-regulator.txt
@@ -13,6 +13,7 @@ Optional properties:
- anatop-delay-reg-offset: Anatop MFD step time register offset
- anatop-delay-bit-shift: Bit shift for the step time register
- anatop-delay-bit-width: Number of bits used in the step time register
+- vin-supply: The supply for this regulator
Any property defined as part of the core regulator
binding, defined in regulator.txt, can also be used.
diff --git a/dts/Bindings/regulator/arizona-regulator.txt b/dts/Bindings/regulator/arizona-regulator.txt
new file mode 100644
index 0000000..443564d
--- /dev/null
+++ b/dts/Bindings/regulator/arizona-regulator.txt
@@ -0,0 +1,17 @@
+Cirrus Logic Arizona class audio SoCs
+
+These devices are audio SoCs with extensive digital capabilities and a range
+of analogue I/O.
+
+This document lists regulator specific bindings, see the primary binding
+document:
+ ../mfd/arizona.txt
+
+Optional properties:
+ - wlf,ldoena : GPIO specifier for the GPIO controlling LDOENA
+
+Optional subnodes:
+ - ldo1 : Initial data for the LDO1 regulator, as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt
+ - micvdd : Initial data for the MICVDD regulator, as covered in
+ Documentation/devicetree/bindings/regulator/regulator.txt
diff --git a/dts/Bindings/regulator/max77802.txt b/dts/Bindings/regulator/max77802.txt
index 79e5476..09d796e 100644
--- a/dts/Bindings/regulator/max77802.txt
+++ b/dts/Bindings/regulator/max77802.txt
@@ -8,7 +8,28 @@ regulators that can be controlled over I2C.
Following properties should be present in main device node of the MFD chip.
-Optional node:
+Optional properties:
+- inb1-supply: The input supply for BUCK1
+- inb2-supply: The input supply for BUCK2
+- inb3-supply: The input supply for BUCK3
+- inb4-supply: The input supply for BUCK4
+- inb5-supply: The input supply for BUCK5
+- inb6-supply: The input supply for BUCK6
+- inb7-supply: The input supply for BUCK7
+- inb8-supply: The input supply for BUCK8
+- inb9-supply: The input supply for BUCK9
+- inb10-supply: The input supply for BUCK10
+- inl1-supply: The input supply for LDO8 and LDO15
+- inl2-supply: The input supply for LDO17, LDO27, LDO30 and LDO35
+- inl3-supply: The input supply for LDO3, LDO5, LDO6 and LDO7
+- inl4-supply: The input supply for LDO10, LDO11, LDO13 and LDO14
+- inl5-supply: The input supply for LDO9 and LDO19
+- inl6-supply: The input supply for LDO4, LDO21, LDO24 and LDO33
+- inl7-supply: The input supply for LDO18, LDO20, LDO28 and LDO29
+- inl9-supply: The input supply for LDO12, LDO23, LDO25, LDO26, LDO32 and LDO34
+- inl10-supply: The input supply for LDO1 and LDO2
+
+Optional nodes:
- regulators : The regulators of max77802 have to be instantiated
under subnode named "regulators" using the following format.
@@ -58,6 +79,8 @@ Example:
#address-cells = <1>;
#size-cells = <0>;
+ inb1-supply = <&parent_reg>;
+
regulators {
ldo1_reg: LDO1 {
regulator-name = "vdd_1v0";
diff --git a/dts/Bindings/regulator/regulator.txt b/dts/Bindings/regulator/regulator.txt
index 24bd422..1d112fc 100644
--- a/dts/Bindings/regulator/regulator.txt
+++ b/dts/Bindings/regulator/regulator.txt
@@ -11,6 +11,7 @@ Optional properties:
- regulator-always-on: boolean, regulator should never be disabled
- regulator-boot-on: bootloader/firmware enabled regulator
- regulator-allow-bypass: allow the regulator to go into bypass mode
+- regulator-allow-set-load: allow the regulator performance level to be configured
- <name>-supply: phandle to the parent supply/regulator node
- regulator-ramp-delay: ramp delay for regulator(in uV/uS)
For hardware which supports disabling ramp rate, it should be explicitly
diff --git a/dts/Bindings/regulator/tps65023.txt b/dts/Bindings/regulator/tps65023.txt
new file mode 100644
index 0000000..a4714e4
--- /dev/null
+++ b/dts/Bindings/regulator/tps65023.txt
@@ -0,0 +1,60 @@
+TPS65023 family of regulators
+
+Required properties:
+- compatible: Must be one of the following.
+ "ti,tps65020",
+ "ti,tps65021",
+ "ti,tps65023",
+- reg: I2C slave address
+- regulators: list of regulators provided by this controller, must be named
+ after their hardware counterparts: VDCDC[1-3] and LDO[1-2]
+- regulators: This is the list of child nodes that specify the regulator
+ initialization data for defined regulators. The definition for each of
+ these nodes is defined using the standard binding for regulators found at
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+
+Each regulator is defined using the standard binding for regulators.
+
+Example:
+
+ tps65023@48 {
+ compatible = "ti,tps65023";
+ reg = <0x48>;
+
+ regulators {
+ VDCDC1 {
+ regulator-name = "vdd_mpu";
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ VDCDC2 {
+ regulator-name = "vdd_core";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ VDCDC3 {
+ regulator-name = "vdd_io";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ LDO1 {
+ regulator-name = "vdd_usb18";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ LDO2 {
+ regulator-name = "vdd_usb33";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
diff --git a/dts/Bindings/hwrng/atmel-trng.txt b/dts/Bindings/rng/atmel-trng.txt
index 4ac5aaa..4ac5aaa 100644
--- a/dts/Bindings/hwrng/atmel-trng.txt
+++ b/dts/Bindings/rng/atmel-trng.txt
diff --git a/dts/Bindings/hwrng/brcm,iproc-rng200.txt b/dts/Bindings/rng/brcm,iproc-rng200.txt
index e25a456..e25a456 100644
--- a/dts/Bindings/hwrng/brcm,iproc-rng200.txt
+++ b/dts/Bindings/rng/brcm,iproc-rng200.txt
diff --git a/dts/Bindings/hwrng/omap_rng.txt b/dts/Bindings/rng/omap_rng.txt
index 6a62acd..6a62acd 100644
--- a/dts/Bindings/hwrng/omap_rng.txt
+++ b/dts/Bindings/rng/omap_rng.txt
diff --git a/dts/Bindings/rng/samsung,exynos-rng4.txt b/dts/Bindings/rng/samsung,exynos-rng4.txt
new file mode 100644
index 0000000..4ca8dd4
--- /dev/null
+++ b/dts/Bindings/rng/samsung,exynos-rng4.txt
@@ -0,0 +1,17 @@
+Exynos Pseudo Random Number Generator
+
+Required properties:
+
+- compatible : Should be "samsung,exynos4-rng".
+- reg : Specifies base physical address and size of the registers map.
+- clocks : Phandle to clock-controller plus clock-specifier pair.
+- clock-names : "secss" as a clock name.
+
+Example:
+
+ rng@10830400 {
+ compatible = "samsung,exynos4-rng";
+ reg = <0x10830400 0x200>;
+ clocks = <&clock CLK_SSS>;
+ clock-names = "secss";
+ };
diff --git a/dts/Bindings/rng/st,rng.txt b/dts/Bindings/rng/st,rng.txt
new file mode 100644
index 0000000..35734bc
--- /dev/null
+++ b/dts/Bindings/rng/st,rng.txt
@@ -0,0 +1,15 @@
+STMicroelectronics HW Random Number Generator
+----------------------------------------------
+
+Required parameters:
+compatible : Should be "st,rng"
+reg : Base address and size of IP's register map.
+clocks : Phandle to device's clock (See: ../clocks/clock-bindings.txt)
+
+Example:
+
+rng@fee80000 {
+ compatible = "st,rng";
+ reg = <0xfee80000 0x1000>;
+ clocks = <&clk_sysin>;
+}
diff --git a/dts/Bindings/rng/st,stm32-rng.txt b/dts/Bindings/rng/st,stm32-rng.txt
new file mode 100644
index 0000000..47f0417
--- /dev/null
+++ b/dts/Bindings/rng/st,stm32-rng.txt
@@ -0,0 +1,21 @@
+STMicroelectronics STM32 HW RNG
+===============================
+
+The STM32 hardware random number generator is a simple fixed purpose IP and
+is fully separated from other crypto functions.
+
+Required properties:
+
+- compatible : Should be "st,stm32-rng"
+- reg : Should be register base and length as documented in the datasheet
+- interrupts : The designated IRQ line for the RNG
+- clocks : The clock needed to enable the RNG
+
+Example:
+
+ rng: rng@50060800 {
+ compatible = "st,stm32-rng";
+ reg = <0x50060800 0x400>;
+ interrupts = <80>;
+ clocks = <&rcc 0 38>;
+ };
diff --git a/dts/Bindings/hwrng/timeriomem_rng.txt b/dts/Bindings/rng/timeriomem_rng.txt
index 6616d15..6616d15 100644
--- a/dts/Bindings/hwrng/timeriomem_rng.txt
+++ b/dts/Bindings/rng/timeriomem_rng.txt
diff --git a/dts/Bindings/rtc/dallas,ds1390.txt b/dts/Bindings/rtc/dallas,ds1390.txt
new file mode 100644
index 0000000..8e76f26
--- /dev/null
+++ b/dts/Bindings/rtc/dallas,ds1390.txt
@@ -0,0 +1,18 @@
+* Dallas DS1390 SPI Serial Real-Time Clock
+
+Required properties:
+- compatible: Should contain "dallas,ds1390".
+- reg: SPI address for chip
+
+Optional properties:
+- trickle-resistor-ohms : Selected resistor for trickle charger
+ Values usable for ds1390 are 250, 2000, 4000
+ Should be given if trickle charger should be enabled
+- trickle-diode-disable : Do not use internal trickle charger diode
+ Should be given if internal trickle charger diode should be disabled
+Example:
+ ds1390: rtc@68 {
+ compatible = "dallas,ds1390";
+ trickle-resistor-ohms = <250>;
+ reg = <0>;
+ };
diff --git a/dts/Bindings/rtc/isil,isl12057.txt b/dts/Bindings/rtc/isil,isl12057.txt
index 501c39c..cf83e09 100644
--- a/dts/Bindings/rtc/isil,isl12057.txt
+++ b/dts/Bindings/rtc/isil,isl12057.txt
@@ -5,7 +5,7 @@ consisting of a compatible field, an address and possibly an interrupt
line).
Nonetheless, it also supports an option boolean property
-("isil,irq2-can-wakeup-machine") to handle the specific use-case found
+("wakeup-source") to handle the specific use-case found
on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
(associated with the alarm supported by the driver) is not connected
@@ -22,9 +22,9 @@ Required properties supported by the device:
Optional properties:
- - "isil,irq2-can-wakeup-machine": mark the chip as a wakeup source,
- independently of the availability of an IRQ line connected to the
- SoC.
+ - "wakeup-source": mark the chip as a wakeup source, independently of
+ the availability of an IRQ line connected to the SoC.
+ (Legacy property supported: "isil,irq2-can-wakeup-machine")
- "interrupt-parent", "interrupts": for passing the interrupt line
of the SoC connected to IRQ#2 of the RTC chip.
@@ -74,5 +74,5 @@ PMIC, allowing the device to be started based on configured alarm:
isl12057: isl12057@68 {
compatible = "isil,isl12057";
reg = <0x68>;
- isil,irq2-can-wakeup-machine;
+ wakeup-source;
};
diff --git a/dts/Bindings/rtc/pcf8563.txt b/dts/Bindings/rtc/pcf8563.txt
new file mode 100644
index 0000000..72f6d2c
--- /dev/null
+++ b/dts/Bindings/rtc/pcf8563.txt
@@ -0,0 +1,25 @@
+* Philips PCF8563/Epson RTC8564 Real Time Clock
+
+Philips PCF8563/Epson RTC8564 Real Time Clock
+
+Required properties:
+see: Documentation/devicetree/bindings/i2c/trivial-devices.txt
+
+Optional property:
+- #clock-cells: Should be 0.
+- clock-output-names:
+ overwrite the default clock name "pcf8563-clkout"
+
+Example:
+
+pcf8563: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+};
+
+device {
+...
+ clocks = <&pcf8563>;
+...
+};
diff --git a/dts/Bindings/rtc/rtc-opal.txt b/dts/Bindings/rtc/rtc-opal.txt
index af87e5e..a1734e5 100644
--- a/dts/Bindings/rtc/rtc-opal.txt
+++ b/dts/Bindings/rtc/rtc-opal.txt
@@ -5,12 +5,13 @@ Required properties:
- comapatible: Should be "ibm,opal-rtc"
Optional properties:
-- has-tpo: Decides if the wakeup is supported or not.
+- wakeup-source: Decides if the wakeup is supported or not
+ (Legacy property supported: "has-tpo")
Example:
rtc {
compatible = "ibm,opal-rtc";
- has-tpo;
+ wakeup-source;
phandle = <0x10000029>;
linux,phandle = <0x10000029>;
};
diff --git a/dts/Bindings/serial/ingenic,uart.txt b/dts/Bindings/serial/ingenic,uart.txt
index c2d3b3a..02cb7fe 100644
--- a/dts/Bindings/serial/ingenic,uart.txt
+++ b/dts/Bindings/serial/ingenic,uart.txt
@@ -1,7 +1,8 @@
* Ingenic SoC UART
Required properties:
-- compatible : "ingenic,jz4740-uart" or "ingenic,jz4780-uart"
+- compatible : "ingenic,jz4740-uart", "ingenic,jz4760-uart",
+ "ingenic,jz4775-uart" or "ingenic,jz4780-uart"
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
- clocks : phandles to the module & baud clocks.
diff --git a/dts/Bindings/serial/mrvl,pxa-ssp.txt b/dts/Bindings/serial/mrvl,pxa-ssp.txt
index 669b814..d10cc06 100644
--- a/dts/Bindings/serial/mrvl,pxa-ssp.txt
+++ b/dts/Bindings/serial/mrvl,pxa-ssp.txt
@@ -10,7 +10,6 @@ Required properties:
mvrl,pxa168-ssp
mrvl,pxa910-ssp
mrvl,ce4100-ssp
- mrvl,lpss-ssp
- reg: The memory base
- dmas: Two dma phandles, one for rx, one for tx
diff --git a/dts/Bindings/serial/pl011.txt b/dts/Bindings/serial/pl011.txt
index cbae3d9..77863ae 100644
--- a/dts/Bindings/serial/pl011.txt
+++ b/dts/Bindings/serial/pl011.txt
@@ -19,7 +19,7 @@ Optional properties:
must correspond to the PCLK clocking the internal logic
of the block. Just listing one clock (the first one) is
deprecated.
-- clocks-names:
+- clock-names:
When present, the first clock listed must be named
"uartclk" and the second clock listed must be named
"apb_pclk"
diff --git a/dts/Bindings/serial/qcom,msm-uartdm.txt b/dts/Bindings/serial/qcom,msm-uartdm.txt
index a2114c2..182777f 100644
--- a/dts/Bindings/serial/qcom,msm-uartdm.txt
+++ b/dts/Bindings/serial/qcom,msm-uartdm.txt
@@ -26,6 +26,12 @@ Required properties:
Optional properties:
- dmas: Should contain dma specifiers for transmit and receive channels
- dma-names: Should contain "tx" for transmit and "rx" for receive channels
+- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be
+ used with TX DMA channel. Required when using DMA for transmission
+ with UARTDM v1.3 and bellow.
+- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be
+ used with RX DMA channel. Required when using DMA for reception
+ with UARTDM v1.3 and bellow.
Note: Aliases may be defined to ensure the correct ordering of the UARTs.
The alias serialN will result in the UART being assigned port N. If any
diff --git a/dts/Bindings/serial/renesas,sci-serial.txt b/dts/Bindings/serial/renesas,sci-serial.txt
index e84b13a..73f825e 100644
--- a/dts/Bindings/serial/renesas,sci-serial.txt
+++ b/dts/Bindings/serial/renesas,sci-serial.txt
@@ -23,6 +23,8 @@ Required properties:
- "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
- "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
- "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART.
+ - "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART.
+ - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
- "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
- "renesas,scif" for generic SCIF compatible UART.
diff --git a/dts/Bindings/serial/snps-dw-apb-uart.txt b/dts/Bindings/serial/snps-dw-apb-uart.txt
index 289c40e..12bbe9f 100644
--- a/dts/Bindings/serial/snps-dw-apb-uart.txt
+++ b/dts/Bindings/serial/snps-dw-apb-uart.txt
@@ -15,6 +15,9 @@ The supplying peripheral clock can also be handled, needing a second property
Required elements: "baudclk", "apb_pclk"
Optional properties:
+- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE
+ configuration parameter. Define this if your UART does not implement the busy
+ functionality.
- resets : phandle to the parent reset controller.
- reg-shift : quantity to shift the register offsets by. If this property is
not present then the register offsets are not shifted.
diff --git a/dts/Bindings/soc/mediatek/scpsys.txt b/dts/Bindings/soc/mediatek/scpsys.txt
index c051114..a6c8afc 100644
--- a/dts/Bindings/soc/mediatek/scpsys.txt
+++ b/dts/Bindings/soc/mediatek/scpsys.txt
@@ -17,9 +17,9 @@ Required properties:
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
- clock, clock-names: clocks according to the common clock binding.
- The clocks needed "mm" and "mfg". These are the
- clocks which hardware needs to be enabled before
- enabling certain power domains.
+ The clocks needed "mm", "mfg", "venc" and "venc_lt".
+ These are the clocks which hardware needs to be enabled
+ before enabling certain power domains.
Example:
@@ -30,7 +30,9 @@ Example:
infracfg = <&infracfg>;
clocks = <&clk26m>,
<&topckgen CLK_TOP_MM_SEL>;
- clock-names = "mfg", "mm";
+ <&topckgen CLK_TOP_VENC_SEL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "mfg", "mm", "venc", "venc_lt";
};
Example consumer:
diff --git a/dts/Bindings/soc/qcom/qcom,smem.txt b/dts/Bindings/soc/qcom/qcom,smem.txt
new file mode 100644
index 0000000..9326cdf
--- /dev/null
+++ b/dts/Bindings/soc/qcom/qcom,smem.txt
@@ -0,0 +1,57 @@
+Qualcomm Shared Memory Manager binding
+
+This binding describes the Qualcomm Shared Memory Manager, used to share data
+between various subsystems and OSes in Qualcomm platforms.
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be:
+ "qcom,smem"
+
+- memory-region:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: handle to memory reservation for main SMEM memory region.
+
+- qcom,rpm-msg-ram:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: handle to RPM message memory resource
+
+- hwlocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to a hwspinlock used to protect allocations from
+ the shared memory
+
+= EXAMPLE
+The following example shows the SMEM setup for MSM8974, with a main SMEM region
+at 0xfa00000 and the RPM message ram at 0xfc428000:
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ smem_region: smem@fa00000 {
+ reg = <0xfa00000 0x200000>;
+ no-map;
+ };
+ };
+
+ smem@fa00000 {
+ compatible = "qcom,smem";
+
+ memory-region = <&smem_region>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ soc {
+ rpm_msg_ram: memory@fc428000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0xfc428000 0x4000>;
+ };
+ };
diff --git a/dts/Bindings/soc/rockchip/power_domain.txt b/dts/Bindings/soc/rockchip/power_domain.txt
new file mode 100644
index 0000000..112756e
--- /dev/null
+++ b/dts/Bindings/soc/rockchip/power_domain.txt
@@ -0,0 +1,46 @@
+* Rockchip Power Domains
+
+Rockchip processors include support for multiple power domains which can be
+powered up/down by software based on different application scenes to save power.
+
+Required properties for power domain controller:
+- compatible: Should be one of the following.
+ "rockchip,rk3288-power-controller" - for RK3288 SoCs.
+- #power-domain-cells: Number of cells in a power-domain specifier.
+ Should be 1 for multiple PM domains.
+- #address-cells: Should be 1.
+- #size-cells: Should be 0.
+
+Required properties for power domain sub nodes:
+- reg: index of the power domain, should use macros in:
+ "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
+- clocks (optional): phandles to clocks which need to be enabled while power domain
+ switches state.
+
+Example:
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu {
+ reg = <RK3288_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ };
+ };
+
+Node of a device using power domains must have a power-domains property,
+containing a phandle to the power device node and an index specifying which
+power domain to use.
+The index should use macros in:
+ "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
+
+Example of the node using power domain:
+
+ node {
+ /* ... */
+ power-domains = <&power RK3288_PD_GPU>;
+ /* ... */
+ };
diff --git a/dts/Bindings/soc/ti/keystone-navigator-qmss.txt b/dts/Bindings/soc/ti/keystone-navigator-qmss.txt
index d8e8cdb..d1ce21a 100644
--- a/dts/Bindings/soc/ti/keystone-navigator-qmss.txt
+++ b/dts/Bindings/soc/ti/keystone-navigator-qmss.txt
@@ -221,7 +221,6 @@ qmss: qmss@2a40000 {
#size-cells = <1>;
ranges;
pdsp0@0x2a10000 {
- firmware = "keystone/qmss_pdsp_acc48_k2_le_1_0_0_8.fw";
reg = <0x2a10000 0x1000>,
<0x2a0f000 0x100>,
<0x2a0c000 0x3c8>,
diff --git a/dts/Bindings/sound/ak4554.c b/dts/Bindings/sound/ak4554.txt
index 934fa02..934fa02 100644
--- a/dts/Bindings/sound/ak4554.c
+++ b/dts/Bindings/sound/ak4554.txt
diff --git a/dts/Bindings/sound/ak4613.txt b/dts/Bindings/sound/ak4613.txt
new file mode 100644
index 0000000..15a9195
--- /dev/null
+++ b/dts/Bindings/sound/ak4613.txt
@@ -0,0 +1,17 @@
+AK4613 I2C transmitter
+
+This device supports I2C mode only.
+
+Required properties:
+
+- compatible : "asahi-kasei,ak4613"
+- reg : The chip select number on the I2C bus
+
+Example:
+
+&i2c {
+ ak4613: ak4613@0x10 {
+ compatible = "asahi-kasei,ak4613";
+ reg = <0x10>;
+ };
+};
diff --git a/dts/Bindings/sound/ak4642.txt b/dts/Bindings/sound/ak4642.txt
index 623d4e7..340784d 100644
--- a/dts/Bindings/sound/ak4642.txt
+++ b/dts/Bindings/sound/ak4642.txt
@@ -7,7 +7,14 @@ Required properties:
- compatible : "asahi-kasei,ak4642" or "asahi-kasei,ak4643" or "asahi-kasei,ak4648"
- reg : The chip select number on the I2C bus
-Example:
+Optional properties:
+
+ - #clock-cells : common clock binding; shall be set to 0
+ - clocks : common clock binding; MCKI clock
+ - clock-frequency : common clock binding; frequency of MCKO
+ - clock-output-names : common clock binding; MCKO clock name
+
+Example 1:
&i2c {
ak4648: ak4648@0x12 {
@@ -15,3 +22,16 @@ Example:
reg = <0x12>;
};
};
+
+Example 2:
+
+&i2c {
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ reg = <0x12>;
+ #clock-cells = <0>;
+ clocks = <&audio_clock>;
+ clock-frequency = <12288000>;
+ clock-output-names = "ak4643_mcko";
+ };
+};
diff --git a/dts/Bindings/sound/atmel-classd.txt b/dts/Bindings/sound/atmel-classd.txt
new file mode 100644
index 0000000..0018451
--- /dev/null
+++ b/dts/Bindings/sound/atmel-classd.txt
@@ -0,0 +1,52 @@
+* Atmel ClassD driver under ALSA SoC architecture
+
+Required properties:
+- compatible
+ Should be "atmel,sama5d2-classd".
+- reg
+ Should contain ClassD registers location and length.
+- interrupts
+ Should contain the IRQ line for the ClassD.
+- dmas
+ One DMA specifiers as described in atmel-dma.txt and dma.txt files.
+- dma-names
+ Must be "tx".
+- clock-names
+ Tuple listing input clock names.
+ Required elements: "pclk", "gclk" and "aclk".
+- clocks
+ Please refer to clock-bindings.txt.
+
+Optional properties:
+- pinctrl-names, pinctrl-0
+ Please refer to pinctrl-bindings.txt.
+- atmel,model
+ The user-visible name of this sound complex.
+ The default value is "CLASSD".
+- atmel,pwm-type
+ PWM modulation type, "single" or "diff".
+ The default value is "single".
+- atmel,non-overlap-time
+ Set non-overlapping time, the unit is nanosecond(ns).
+ There are four values,
+ <5>, <10>, <15>, <20>, the default value is <10>.
+ Non-overlapping will be disabled if not specified.
+
+Example:
+classd: classd@fc048000 {
+ compatible = "atmel,sama5d2-classd";
+ reg = <0xfc048000 0x100>;
+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
+ | AT91_XDMAC_DT_PERID(47))>;
+ dma-names = "tx";
+ clocks = <&classd_clk>, <&classd_gclk>, <&audio_pll_pmc>;
+ clock-names = "pclk", "gclk", "aclk";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_classd_default>;
+ atmel,model = "classd @ SAMA5D2-Xplained";
+ atmel,pwm-type = "diff";
+ atmel,non-overlap-time = <10>;
+};
diff --git a/dts/Bindings/sound/da7213.txt b/dts/Bindings/sound/da7213.txt
new file mode 100644
index 0000000..5890280
--- /dev/null
+++ b/dts/Bindings/sound/da7213.txt
@@ -0,0 +1,41 @@
+Dialog Semiconductor DA7213 Audio Codec bindings
+
+======
+
+Required properties:
+- compatible : Should be "dlg,da7213"
+- reg: Specifies the I2C slave address
+
+Optional properties:
+- clocks : phandle and clock specifier for codec MCLK.
+- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
+
+- dlg,micbias1-lvl : Voltage (mV) for Mic Bias 1
+ [<1600>, <2200>, <2500>, <3000>]
+- dlg,micbias2-lvl : Voltage (mV) for Mic Bias 2
+ [<1600>, <2200>, <2500>, <3000>]
+- dlg,dmic-data-sel : DMIC channel select based on clock edge.
+ ["lrise_rfall", "lfall_rrise"]
+- dlg,dmic-samplephase : When to sample audio from DMIC.
+ ["on_clkedge", "between_clkedge"]
+- dlg,dmic-clkrate : DMIC clock frequency (Hz).
+ [<1500000>, <3000000>]
+
+======
+
+Example:
+
+ codec_i2c: da7213@1a {
+ compatible = "dlg,da7213";
+ reg = <0x1a>;
+
+ clocks = <&clks 201>;
+ clock-names = "mclk";
+
+ dlg,micbias1-lvl = <2500>;
+ dlg,micbias2-lvl = <2500>;
+
+ dlg,dmic-data-sel = "lrise_rfall";
+ dlg,dmic-samplephase = "between_clkedge";
+ dlg,dmic-clkrate = <3000000>;
+ };
diff --git a/dts/Bindings/sound/da7219.txt b/dts/Bindings/sound/da7219.txt
new file mode 100644
index 0000000..1b70309
--- /dev/null
+++ b/dts/Bindings/sound/da7219.txt
@@ -0,0 +1,106 @@
+Dialog Semiconductor DA7219 Audio Codec bindings
+
+DA7219 is an audio codec with advanced accessory detect features.
+
+======
+
+Required properties:
+- compatible : Should be "dlg,da7219"
+- reg: Specifies the I2C slave address
+
+- interrupt-parent : Specifies the phandle of the interrupt controller to which
+ the IRQs from DA7219 are delivered to.
+- interrupts : IRQ line info for DA7219.
+ (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+ further information relating to interrupt properties)
+
+- VDD-supply: VDD power supply for the device
+- VDDMIC-supply: VDDMIC power supply for the device
+- VDDIO-supply: VDDIO power supply for the device
+ (See Documentation/devicetree/bindings/regulator/regulator.txt for further
+ information relating to regulators)
+
+Optional properties:
+- interrupt-names : Name associated with interrupt line. Should be "wakeup" if
+ interrupt is to be used to wake system, otherwise "irq" should be used.
+- wakeup-source: Flag to indicate this device can wake system (suspend/resume).
+
+- clocks : phandle and clock specifier for codec MCLK.
+- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
+
+- dlg,ldo-lvl : Required internal LDO voltage (mV) level for digital engine
+ [<1050>, <1100>, <1200>, <1400>]
+- dlg,micbias-lvl : Voltage (mV) for Mic Bias
+ [<1800>, <2000>, <2200>, <2400>, <2600>]
+- dlg,mic-amp-in-sel : Mic input source type
+ ["diff", "se_p", "se_n"]
+
+======
+
+Child node - 'da7219_aad':
+
+Optional properties:
+- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
+ [<2800>, <2900>]
+- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
+- dlg,btn-cfg : Periodic button press measurements for 4-pole jack (ms)
+ [<2>, <5>, <10>, <50>, <100>, <200>, <500>]
+- dlg,mic-det-thr : Impedance threshold for mic detection measurement (Ohms)
+ [<200>, <500>, <750>, <1000>]
+- dlg,jack-ins-deb : Debounce time for jack insertion (ms)
+ [<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>]
+- dlg,jack-det-rate: Jack type detection latency (3/4 pole)
+ ["32ms_64ms", "64ms_128ms", "128ms_256ms", "256ms_512ms"]
+- dlg,jack-rem-deb : Debounce time for jack removal (ms)
+ [<1>, <5>, <10>, <20>]
+- dlg,a-d-btn-thr : Impedance threshold between buttons A and D
+ [0x0 - 0xFF]
+- dlg,d-b-btn-thr : Impedance threshold between buttons D and B
+ [0x0 - 0xFF]
+- dlg,b-c-btn-thr : Impedance threshold between buttons B and C
+ [0x0 - 0xFF]
+- dlg,c-mic-btn-thr : Impedance threshold between button C and Mic
+ [0x0 - 0xFF]
+- dlg,btn-avg : Number of 8-bit readings for averaged button measurement
+ [<1>, <2>, <4>, <8>]
+- dlg,adc-1bit-rpt : Repeat count for 1-bit button measurement
+ [<1>, <2>, <4>, <8>]
+
+======
+
+Example:
+
+ codec: da7219@1a {
+ compatible = "dlg,da7219";
+ reg = <0x1a>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+
+ VDD-supply = <&reg_audio>;
+ VDDMIC-supply = <&reg_audio>;
+ VDDIO-supply = <&reg_audio>;
+
+ clocks = <&clks 201>;
+ clock-names = "mclk";
+
+ dlg,ldo-lvl = <1200>;
+ dlg,micbias-lvl = <2600>;
+ dlg,mic-amp-in-sel = "diff";
+
+ da7219_aad {
+ dlg,btn-cfg = <50>;
+ dlg,mic-det-thr = <500>;
+ dlg,jack-ins-deb = <20>;
+ dlg,jack-det-rate = "32ms_64ms";
+ dlg,jack-rem-deb = <1>;
+
+ dlg,a-d-btn-thr = <0xa>;
+ dlg,d-b-btn-thr = <0x16>;
+ dlg,b-c-btn-thr = <0x21>;
+ dlg,c-mic-btn-thr = <0x3E>;
+
+ dlg,btn-avg = <4>;
+ dlg,adc-1bit-rpt = <1>;
+ };
+ };
diff --git a/dts/Bindings/sound/fsl-asoc-card.txt b/dts/Bindings/sound/fsl-asoc-card.txt
index a96774c..ce55c0a 100644
--- a/dts/Bindings/sound/fsl-asoc-card.txt
+++ b/dts/Bindings/sound/fsl-asoc-card.txt
@@ -13,13 +13,15 @@ So having this generic sound card allows all Freescale SoC users to benefit
from the simplification of a new card support and the capability of the wide
sample rates support through ASRC.
-Note: The card is initially designed for those sound cards who use I2S and
- PCM DAI formats. However, it'll be also possible to support those non
- I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as long
- as the driver has been properly upgraded.
+Note: The card is initially designed for those sound cards who use AC'97, I2S
+ and PCM DAI formats. However, it'll be also possible to support those non
+ AC'97/I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as
+ long as the driver has been properly upgraded.
The compatible list for this generic sound card currently:
+ "fsl,imx-audio-ac97"
+
"fsl,imx-audio-cs42888"
"fsl,imx-audio-wm8962"
diff --git a/dts/Bindings/sound/nau8825.txt b/dts/Bindings/sound/nau8825.txt
new file mode 100644
index 0000000..d337423
--- /dev/null
+++ b/dts/Bindings/sound/nau8825.txt
@@ -0,0 +1,102 @@
+Nuvoton NAU8825 audio codec
+
+This device supports I2C only.
+
+Required properties:
+ - compatible : Must be "nuvoton,nau8825"
+
+ - reg : the I2C address of the device. This is either 0x1a (CSB=0) or 0x1b (CSB=1).
+
+Optional properties:
+ - nuvoton,jkdet-enable: Enable jack detection via JKDET pin.
+ - nuvoton,jkdet-pull-enable: Enable JKDET pin pull. If set - pin pull enabled,
+ otherwise pin in high impedance state.
+ - nuvoton,jkdet-pull-up: Pull-up JKDET pin. If set then JKDET pin is pull up, otherwise pull down.
+ - nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low.
+
+ - nuvoton,vref-impedance: VREF Impedance selection
+ 0 - Open
+ 1 - 25 kOhm
+ 2 - 125 kOhm
+ 3 - 2.5 kOhm
+
+ - nuvoton,micbias-voltage: Micbias voltage level.
+ 0 - VDDA
+ 1 - VDDA
+ 2 - VDDA * 1.1
+ 3 - VDDA * 1.2
+ 4 - VDDA * 1.3
+ 5 - VDDA * 1.4
+ 6 - VDDA * 1.53
+ 7 - VDDA * 1.53
+
+ - nuvoton,sar-threshold-num: Number of buttons supported
+ - nuvoton,sar-threshold: Impedance threshold for each button. Array that contains up to 8 buttons configuration. SAR value is calculated as
+ SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R)
+ where MICBIAS is configured by 'nuvoton,micbias-voltage', SAR_VOLTAGE is configured by 'nuvoton,sar-voltage', R - button impedance.
+ Refer datasheet section 10.2 for more information about threshold calculation.
+
+ - nuvoton,sar-hysteresis: Button impedance measurement hysteresis.
+
+ - nuvoton,sar-voltage: Reference voltage for button impedance measurement.
+ 0 - VDDA
+ 1 - VDDA
+ 2 - VDDA * 1.1
+ 3 - VDDA * 1.2
+ 4 - VDDA * 1.3
+ 5 - VDDA * 1.4
+ 6 - VDDA * 1.53
+ 7 - VDDA * 1.53
+
+ - nuvoton,sar-compare-time: SAR compare time
+ 0 - 500 ns
+ 1 - 1 us
+ 2 - 2 us
+ 3 - 4 us
+
+ - nuvoton,sar-sampling-time: SAR sampling time
+ 0 - 2 us
+ 1 - 4 us
+ 2 - 8 us
+ 3 - 16 us
+
+ - nuvoton,short-key-debounce: Button short key press debounce time.
+ 0 - 30 ms
+ 1 - 50 ms
+ 2 - 100 ms
+ 3 - 30 ms
+
+ - nuvoton,jack-insert-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
+ - nuvoton,jack-eject-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
+
+ - clocks: list of phandle and clock specifier pairs according to common clock bindings for the
+ clocks described in clock-names
+ - clock-names: should include "mclk" for the MCLK master clock
+
+Example:
+
+ headset: nau8825@1a {
+ compatible = "nuvoton,nau8825";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
+ nuvoton,jkdet-enable;
+ nuvoton,jkdet-pull-enable;
+ nuvoton,jkdet-pull-up;
+ nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>;
+ nuvoton,vref-impedance = <2>;
+ nuvoton,micbias-voltage = <6>;
+ // Setup 4 buttons impedance according to Android specification
+ nuvoton,sar-threshold-num = <4>;
+ nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
+ nuvoton,sar-hysteresis = <1>;
+ nuvoton,sar-voltage = <0>;
+ nuvoton,sar-compare-time = <0>;
+ nuvoton,sar-sampling-time = <0>;
+ nuvoton,short-key-debounce = <2>;
+ nuvoton,jack-insert-debounce = <7>;
+ nuvoton,jack-eject-debounce = <7>;
+
+ clock-names = "mclk";
+ clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
+ };
diff --git a/dts/Bindings/sound/renesas,rsnd.txt b/dts/Bindings/sound/renesas,rsnd.txt
index 1173395..c57cbd6 100644
--- a/dts/Bindings/sound/renesas,rsnd.txt
+++ b/dts/Bindings/sound/renesas,rsnd.txt
@@ -4,10 +4,12 @@ Required properties:
- compatible : "renesas,rcar_sound-<soctype>", fallbacks
"renesas,rcar_sound-gen1" if generation1, and
"renesas,rcar_sound-gen2" if generation2
+ "renesas,rcar_sound-gen3" if generation3
Examples with soctypes are:
- "renesas,rcar_sound-r8a7778" (R-Car M1A)
- "renesas,rcar_sound-r8a7790" (R-Car H2)
- "renesas,rcar_sound-r8a7791" (R-Car M2-W)
+ - "renesas,rcar_sound-r8a7795" (R-Car H3)
- reg : Should contain the register physical address.
required register is
SRU/ADG/SSI if generation1
@@ -30,6 +32,11 @@ Required properties:
- rcar_sound,dai : DAI contents.
The number of DAI subnode should be same as HW.
see below for detail.
+- #sound-dai-cells : it must be 0 if your system is using single DAI
+ it must be 1 if your system is using multi DAI
+- #clock-cells : it must be 0 if your system has audio_clkout
+ it must be 1 if your system has audio_clkout0/1/2/3
+- clock-frequency : for all audio_clkout0/1/2/3
SSI subnode properties:
- interrupts : Should contain SSI interrupt for PIO transfer
diff --git a/dts/Bindings/sound/rockchip-i2s.txt b/dts/Bindings/sound/rockchip-i2s.txt
index 9b82c20..2267d24 100644
--- a/dts/Bindings/sound/rockchip-i2s.txt
+++ b/dts/Bindings/sound/rockchip-i2s.txt
@@ -12,8 +12,6 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: should contain the I2S interrupt.
-- #address-cells: should be 1.
-- #size-cells: should be 0.
- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
Documentation/devicetree/bindings/dma/dma.txt
- dma-names: should include "tx" and "rx".
@@ -21,6 +19,7 @@ Required properties:
- clock-names: should contain followings:
- "i2s_hclk": clock for I2S BUS
- "i2s_clk" : clock for I2S controller
+- rockchip,capture-channels: max capture channels, if not set, 2 channels default.
Example for rk3288 I2S controller:
@@ -28,10 +27,9 @@ i2s@ff890000 {
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
reg = <0xff890000 0x10000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
dmas = <&pdma1 0>, <&pdma1 1>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+ rockchip,capture-channels = <2>;
};
diff --git a/dts/Bindings/sound/rockchip-spdif.txt b/dts/Bindings/sound/rockchip-spdif.txt
new file mode 100644
index 0000000..e64dbde
--- /dev/null
+++ b/dts/Bindings/sound/rockchip-spdif.txt
@@ -0,0 +1,40 @@
+* Rockchip SPDIF transceiver
+
+The S/PDIF audio block is a stereo transceiver that allows the
+processor to receive and transmit digital audio via an coaxial cable or
+a fibre cable.
+
+Required properties:
+
+- compatible: should be one of the following:
+ - "rockchip,rk3288-spdif", "rockchip,rk3188-spdif" or
+ "rockchip,rk3066-spdif"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: should contain the SPDIF interrupt.
+- dmas: DMA specifiers for tx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: should be "tx"
+- clocks: a list of phandle + clock-specifier pairs, one for each entry
+ in clock-names.
+- clock-names: should contain following:
+ - "hclk": clock for SPDIF controller
+ - "mclk" : clock for SPDIF bus
+
+Required properties on RK3288:
+ - rockchip,grf: the phandle of the syscon node for the general register
+ file (GRF)
+
+Example for the rk3188 SPDIF controller:
+
+spdif: spdif@0x1011e000 {
+ compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
+ reg = <0x1011e000 0x2000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac1_s 8>;
+ dma-names = "tx";
+ clock-names = "hclk", "mclk";
+ clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
+ status = "disabled";
+ #sound-dai-cells = <0>;
+};
diff --git a/dts/Bindings/sound/rt5640.txt b/dts/Bindings/sound/rt5640.txt
index bac4d9a..9e62f6e 100644
--- a/dts/Bindings/sound/rt5640.txt
+++ b/dts/Bindings/sound/rt5640.txt
@@ -14,7 +14,8 @@ Optional properties:
- realtek,in1-differential
- realtek,in2-differential
- Boolean. Indicate MIC1/2 input are differential, rather than single-ended.
+- realtek,in3-differential
+ Boolean. Indicate MIC1/2/3 input are differential, rather than single-ended.
- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
@@ -24,9 +25,11 @@ Pins on the device (for linking into audio routes) for RT5639/RT5640:
* DMIC2
* MICBIAS1
* IN1P
- * IN1R
+ * IN1N
* IN2P
- * IN2R
+ * IN2N
+ * IN3P
+ * IN3N
* HPOL
* HPOR
* LOUTL
diff --git a/dts/Bindings/sound/sun4i-codec.txt b/dts/Bindings/sound/sun4i-codec.txt
new file mode 100644
index 0000000..c92966b
--- /dev/null
+++ b/dts/Bindings/sound/sun4i-codec.txt
@@ -0,0 +1,27 @@
+* Allwinner A10 Codec
+
+Required properties:
+- compatible: must be either "allwinner,sun4i-a10-codec" or
+ "allwinner,sun7i-a20-codec"
+- reg: must contain the registers location and length
+- interrupts: must contain the codec interrupt
+- dmas: DMA channels for tx and rx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: should include "tx" and "rx".
+- clocks: a list of phandle + clock-specifer pairs, one for each entry
+ in clock-names.
+- clock-names: should contain followings:
+ - "apb": the parent APB clock for this controller
+ - "codec": the parent module clock
+
+Example:
+codec: codec@01c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun7i-a20-codec";
+ reg = <0x01c22c00 0x40>;
+ interrupts = <0 30 4>;
+ clocks = <&apb0_gates 0>, <&codec_clk>;
+ clock-names = "apb", "codec";
+ dmas = <&dma 0 19>, <&dma 0 19>;
+ dma-names = "rx", "tx";
+};
diff --git a/dts/Bindings/sound/tdm-slot.txt b/dts/Bindings/sound/tdm-slot.txt
index 6a2c842..34cf70e 100644
--- a/dts/Bindings/sound/tdm-slot.txt
+++ b/dts/Bindings/sound/tdm-slot.txt
@@ -4,11 +4,15 @@ This specifies audio DAI's TDM slot.
TDM slot properties:
dai-tdm-slot-num : Number of slots in use.
-dai-tdm-slot-width : Width in bits for each slot.
+dai-tdm-slot-width : Width in bits for each slot.
+dai-tdm-slot-tx-mask : Transmit direction slot mask, optional
+dai-tdm-slot-rx-mask : Receive direction slot mask, optional
For instance:
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <8>;
+ dai-tdm-slot-tx-mask = <0 1>;
+ dai-tdm-slot-rx-mask = <1 0>;
And for each spcified driver, there could be one .of_xlate_tdm_slot_mask()
to specify a explicit mapping of the channels and the slots. If it's absent
@@ -18,3 +22,8 @@ tx and rx masks.
For snd_soc_of_xlate_tdm_slot_mask(), the tx and rx masks will use a 1 bit
for an active slot as default, and the default active bits are at the LSB of
the masks.
+
+The explicit masks are given as array of integers, where the first
+number presents bit-0 (LSB), second presents bit-1, etc. Any non zero
+number is considered 1 and 0 is 0. snd_soc_of_xlate_tdm_slot_mask()
+does not do anything, if either mask is set non zero value.
diff --git a/dts/Bindings/spi/brcm,bcm2835-aux-spi.txt b/dts/Bindings/spi/brcm,bcm2835-aux-spi.txt
new file mode 100644
index 0000000..9887b07
--- /dev/null
+++ b/dts/Bindings/spi/brcm,bcm2835-aux-spi.txt
@@ -0,0 +1,38 @@
+Broadcom BCM2835 auxiliar SPI1/2 controller
+
+The BCM2835 contains two forms of SPI master controller, one known simply as
+SPI0, and the other known as the "Universal SPI Master"; part of the
+auxiliary block. This binding applies to the SPI1/2 controller.
+
+Required properties:
+- compatible: Should be "brcm,bcm2835-aux-spi".
+- reg: Should contain register location and length for the spi block
+- interrupts: Should contain shared interrupt of the aux block
+- clocks: The clock feeding the SPI controller - needs to
+ point to the auxiliar clock driver of the bcm2835,
+ as this clock will enable the output gate for the specific
+ clock.
+- cs-gpios: the cs-gpios (native cs is NOT supported)
+ see also spi-bus.txt
+
+Example:
+
+spi1@7e215080 {
+ compatible = "brcm,bcm2835-aux-spi";
+ reg = <0x7e215080 0x40>;
+ interrupts = <1 29>;
+ clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>;
+};
+
+spi2@7e2150c0 {
+ compatible = "brcm,bcm2835-aux-spi";
+ reg = <0x7e2150c0 0x40>;
+ interrupts = <1 29>;
+ clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>;
+};
diff --git a/dts/Bindings/spi/spi-mt65xx.txt b/dts/Bindings/spi/spi-mt65xx.txt
index 6160ffb..ce363c9 100644
--- a/dts/Bindings/spi/spi-mt65xx.txt
+++ b/dts/Bindings/spi/spi-mt65xx.txt
@@ -29,8 +29,11 @@ Required properties:
muxes clock, and "spi-clk" for the clock gate.
Optional properties:
+-cs-gpios: see spi-bus.txt, only required for MT8173.
+
- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
- controller used, this value should be 0~3, only required for MT8173.
+ controller used. This is a array, the element value should be 0~3,
+ only required for MT8173.
0: specify GPIO69,70,71,72 for spi pins.
1: specify GPIO102,103,104,105 for spi pins.
2: specify GPIO128,129,130,131 for spi pins.
@@ -49,7 +52,7 @@ spi: spi@1100a000 {
<&topckgen CLK_TOP_SPI_SEL>,
<&pericfg CLK_PERI_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
-
- mediatek,pad-select = <0>;
+ cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
+ mediatek,pad-select = <1>, <0>;
status = "disabled";
};
diff --git a/dts/Bindings/thermal/rockchip-thermal.txt b/dts/Bindings/thermal/rockchip-thermal.txt
index ef802de..b38200d 100644
--- a/dts/Bindings/thermal/rockchip-thermal.txt
+++ b/dts/Bindings/thermal/rockchip-thermal.txt
@@ -12,6 +12,11 @@ Required properties:
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the name "tsadc-apb".
+- pinctrl-names : The pin control state names;
+- pinctrl-0 : The "init" pinctrl state, it will be set before device probe.
+- pinctrl-1 : The "default" pinctrl state, it will be set after reset the
+ TSADC controller.
+- pinctrl-2 : The "sleep" pinctrl state, it will be in for suspend.
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
@@ -27,8 +32,10 @@ tsadc: tsadc@ff280000 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
diff --git a/dts/Bindings/thermal/ti_soc_thermal.txt b/dts/Bindings/thermal/ti_soc_thermal.txt
index 0c9222d..6299dd8 100644
--- a/dts/Bindings/thermal/ti_soc_thermal.txt
+++ b/dts/Bindings/thermal/ti_soc_thermal.txt
@@ -10,6 +10,8 @@ to the silicon temperature.
Required properties:
- compatible : Should be:
+ - "ti,omap34xx-bandgap" : for OMAP34xx bandgap
+ - "ti,omap36xx-bandgap" : for OMAP36xx bandgap
- "ti,omap4430-bandgap" : for OMAP4430 bandgap
- "ti,omap4460-bandgap" : for OMAP4460 bandgap
- "ti,omap4470-bandgap" : for OMAP4470 bandgap
@@ -25,6 +27,18 @@ to each bandgap version, because the mapping may change from
soc to soc, apart of depending on available features.
Example:
+OMAP34xx:
+bandgap {
+ reg = <0x48002524 0x4>;
+ compatible = "ti,omap34xx-bandgap";
+};
+
+OMAP36xx:
+bandgap {
+ reg = <0x48002524 0x4>;
+ compatible = "ti,omap36xx-bandgap";
+};
+
OMAP4430:
bandgap {
reg = <0x4a002260 0x4 0x4a00232C 0x4>;
diff --git a/dts/Bindings/timer/mediatek,mtk-timer.txt b/dts/Bindings/timer/mediatek,mtk-timer.txt
index 53a3029..64083bc 100644
--- a/dts/Bindings/timer/mediatek,mtk-timer.txt
+++ b/dts/Bindings/timer/mediatek,mtk-timer.txt
@@ -3,10 +3,12 @@ Mediatek MT6577, MT6572 and MT6589 Timers
Required properties:
- compatible should contain:
- * "mediatek,mt6589-timer" for MT6589 compatible timers
* "mediatek,mt6580-timer" for MT6580 compatible timers
- * "mediatek,mt6577-timer" for all compatible timers (MT6589, MT6580,
- MT6577)
+ * "mediatek,mt6589-timer" for MT6589 compatible timers
+ * "mediatek,mt8127-timer" for MT8127 compatible timers
+ * "mediatek,mt8135-timer" for MT8135 compatible timers
+ * "mediatek,mt8173-timer" for MT8173 compatible timers
+ * "mediatek,mt6577-timer" for MT6577 and all above compatible timers
- reg: Should contain location and length for timers register.
- clocks: Clocks driving the timer hardware. This list should include two
clocks. The order is system clock and as second clock the RTC clock.
diff --git a/dts/Bindings/ufs/ufs-qcom.txt b/dts/Bindings/ufs/ufs-qcom.txt
new file mode 100644
index 0000000..070baf4
--- /dev/null
+++ b/dts/Bindings/ufs/ufs-qcom.txt
@@ -0,0 +1,58 @@
+* Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
+
+UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
+Each UFS PHY node should have its own node.
+
+To bind UFS PHY with UFS host controller, the controller node should
+contain a phandle reference to UFS PHY node.
+
+Required properties:
+- compatible : compatible list, contains "qcom,ufs-phy-qmp-20nm"
+ or "qcom,ufs-phy-qmp-14nm" according to the relevant phy in use.
+- reg : should contain PHY register address space (mandatory),
+- reg-names : indicates various resources passed to driver (via reg proptery) by name.
+ Required "reg-names" is "phy_mem".
+- #phy-cells : This property shall be set to 0
+- vdda-phy-supply : phandle to main PHY supply for analog domain
+- vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
+- clocks : List of phandle and clock specifier pairs
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property. "ref_clk_src", "ref_clk",
+ "tx_iface_clk" & "rx_iface_clk" are mandatory but
+ "ref_clk_parent" is optional
+
+Optional properties:
+- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply
+- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
+- vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply
+- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
+- vddp-ref-clk-always-on : specifies if this supply needs to be kept always on
+
+Example:
+
+ ufsphy1: ufsphy@0xfc597000 {
+ compatible = "qcom,ufs-phy-qmp-20nm";
+ reg = <0xfc597000 0x800>;
+ reg-names = "phy_mem";
+ #phy-cells = <0>;
+ vdda-phy-supply = <&pma8084_l4>;
+ vdda-pll-supply = <&pma8084_l12>;
+ vdda-phy-max-microamp = <50000>;
+ vdda-pll-max-microamp = <1000>;
+ clock-names = "ref_clk_src",
+ "ref_clk_parent",
+ "ref_clk",
+ "tx_iface_clk",
+ "rx_iface_clk";
+ clocks = <&clock_rpm clk_ln_bb_clk>,
+ <&clock_gcc clk_pcie_1_phy_ldo >,
+ <&clock_gcc clk_ufs_phy_ldo>,
+ <&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
+ <&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
+ };
+
+ ufshc@0xfc598000 {
+ ...
+ phys = <&ufsphy1>;
+ phy-names = "ufsphy";
+ };
diff --git a/dts/Bindings/ufs/ufshcd-pltfrm.txt b/dts/Bindings/ufs/ufshcd-pltfrm.txt
index 5357919..03c0e98 100644
--- a/dts/Bindings/ufs/ufshcd-pltfrm.txt
+++ b/dts/Bindings/ufs/ufshcd-pltfrm.txt
@@ -4,11 +4,18 @@ UFSHC nodes are defined to describe on-chip UFS host controllers.
Each UFS controller instance should have its own node.
Required properties:
-- compatible : compatible list, contains "jedec,ufs-1.1"
+- compatible : must contain "jedec,ufs-1.1", may also list one or more
+ of the following:
+ "qcom,msm8994-ufshc"
+ "qcom,msm8996-ufshc"
+ "qcom,ufshc"
- interrupts : <interrupt mapping for UFS host controller IRQ>
- reg : <registers mapping>
Optional properties:
+- phys : phandle to UFS PHY node
+- phy-names : the string "ufsphy" when is found in a node, along
+ with "phys" attribute, provides phandle to UFS PHY node
- vdd-hba-supply : phandle to UFS host controller supply regulator node
- vcc-supply : phandle to VCC supply regulator node
- vccq-supply : phandle to VCCQ supply regulator node
@@ -54,4 +61,6 @@ Example:
clocks = <&core 0>, <&ref 0>, <&iface 0>;
clock-names = "core_clk", "ref_clk", "iface_clk";
freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;
+ phys = <&ufsphy1>;
+ phy-names = "ufsphy";
};
diff --git a/dts/Bindings/usb/ci-hdrc-usb2.txt b/dts/Bindings/usb/ci-hdrc-usb2.txt
index a057b75..781296b 100644
--- a/dts/Bindings/usb/ci-hdrc-usb2.txt
+++ b/dts/Bindings/usb/ci-hdrc-usb2.txt
@@ -27,10 +27,6 @@ Optional properties:
- vbus-supply: reference to the VBUS regulator
- maximum-speed: limit the maximum connection speed to "full-speed".
- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
-- fsl,usbmisc: (FSL only) phandler of non-core register device, with one
- argument that indicate usb controller index
-- disable-over-current: (FSL only) disable over current detect
-- external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus
- itc-setting: interrupt threshold control register control, the setting
should be aligned with ITC bits at register USBCMD.
- ahb-burst-config: it is vendor dependent, the required value should be
@@ -41,11 +37,28 @@ Optional properties:
- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
(4 bytes), This register represents the maximum length of a the burst
in 32-bit words while moving data from system memory to the USB
- bus, changing this value takes effect only the SBUSCFG.AHBBRST is 0.
+ bus, the value of this property will only take effect if property
+ "ahb-burst-config" is set to 0, if this property is missing the reset
+ default of the hardware implementation will be used.
- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
(4 bytes), This register represents the maximum length of a the burst
in 32-bit words while moving data from the USB bus to system memory,
- changing this value takes effect only the SBUSCFG.AHBBRST is 0.
+ the value of this property will only take effect if property
+ "ahb-burst-config" is set to 0, if this property is missing the reset
+ default of the hardware implementation will be used.
+- extcon: phandles to external connector devices. First phandle should point to
+ external connector, which provide "USB" cable events, the second should point
+ to external connector device, which provide "USB-HOST" cable events. If one
+ of the external connector devices is not required, empty <0> phandle should
+ be specified.
+- phy-clkgate-delay-us: the delay time (us) between putting the PHY into
+ low power mode and gating the PHY clock.
+
+i.mx specific properties
+- fsl,usbmisc: phandler of non-core register device, with one
+ argument that indicate usb controller index
+- disable-over-current: disable over current detect
+- external-vbus-divider: enables off-chip resistor divider for Vbus
Example:
@@ -62,4 +75,6 @@ Example:
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>; /* 64 bytes */
rx-burst-size-dword = <0x10>;
+ extcon = <0>, <&usb_id>;
+ phy-clkgate-delay-us = <400>;
};
diff --git a/dts/Bindings/usb/dwc3.txt b/dts/Bindings/usb/dwc3.txt
index 0815eac..fb2ad0a 100644
--- a/dts/Bindings/usb/dwc3.txt
+++ b/dts/Bindings/usb/dwc3.txt
@@ -1,6 +1,7 @@
synopsys DWC3 CORE
-DWC3- USB3 CONTROLLER
+DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
+ as described in 'usb/generic.txt'
Required properties:
- compatible: must be "snps,dwc3"
@@ -35,11 +36,16 @@ Optional properties:
LTSSM during USB3 Compliance mode.
- snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
- snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
+ - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG,
+ disabling the suspend signal to the PHY.
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
utmi_l1_suspend_n, false when asserts utmi_sleep_n
- snps,hird-threshold: HIRD threshold
- snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
+ - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
+ register for post-silicon frame length adjustment when the
+ fladj_30mhz_sdbnd signal is invalid or incorrect.
This is usually a subnode to DWC3 glue to which it is connected.
diff --git a/dts/Bindings/usb/samsung-usbphy.txt b/dts/Bindings/usb/samsung-usbphy.txt
deleted file mode 100644
index 33fd354..0000000
--- a/dts/Bindings/usb/samsung-usbphy.txt
+++ /dev/null
@@ -1,117 +0,0 @@
-SAMSUNG USB-PHY controllers
-
-** Samsung's usb 2.0 phy transceiver
-
-The Samsung's usb 2.0 phy transceiver is used for controlling
-usb 2.0 phy for s3c-hsotg as well as ehci-s5p and ohci-exynos
-usb controllers across Samsung SOCs.
-TODO: Adding the PHY binding with controller(s) according to the under
-development generic PHY driver.
-
-Required properties:
-
-Exynos4210:
-- compatible : should be "samsung,exynos4210-usb2phy"
-- reg : base physical address of the phy registers and length of memory mapped
- region.
-- clocks: Clock IDs array as required by the controller.
-- clock-names: names of clock correseponding IDs clock property as requested
- by the controller driver.
-
-Exynos5250:
-- compatible : should be "samsung,exynos5250-usb2phy"
-- reg : base physical address of the phy registers and length of memory mapped
- region.
-
-Optional properties:
-- #address-cells: should be '1' when usbphy node has a child node with 'reg'
- property.
-- #size-cells: should be '1' when usbphy node has a child node with 'reg'
- property.
-- ranges: allows valid translation between child's address space and parent's
- address space.
-
-- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
- interface for usb-phy. It should provide the following information required by
- usb-phy controller to control phy.
- - reg : base physical address of PHY_CONTROL registers.
- The size of this register is the total sum of size of all PHY_CONTROL
- registers that the SoC has. For example, the size will be
- '0x4' in case we have only one PHY_CONTROL register (e.g.
- OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
- and, '0x8' in case we have two PHY_CONTROL registers (e.g.
- USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
- and so on.
-
-Example:
- - Exynos4210
-
- usbphy@125B0000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "samsung,exynos4210-usb2phy";
- reg = <0x125B0000 0x100>;
- ranges;
-
- clocks = <&clock 2>, <&clock 305>;
- clock-names = "xusbxti", "otg";
-
- usbphy-sys {
- /* USB device and host PHY_CONTROL registers */
- reg = <0x10020704 0x8>;
- };
- };
-
-
-** Samsung's usb 3.0 phy transceiver
-
-Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver
-which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0
-controllers across Samsung SOCs.
-
-Required properties:
-
-Exynos5250:
-- compatible : should be "samsung,exynos5250-usb3phy"
-- reg : base physical address of the phy registers and length of memory mapped
- region.
-- clocks: Clock IDs array as required by the controller.
-- clock-names: names of clocks correseponding to IDs in the clock property
- as requested by the controller driver.
-
-Optional properties:
-- #address-cells: should be '1' when usbphy node has a child node with 'reg'
- property.
-- #size-cells: should be '1' when usbphy node has a child node with 'reg'
- property.
-- ranges: allows valid translation between child's address space and parent's
- address space.
-
-- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
- interface for usb-phy. It should provide the following information required by
- usb-phy controller to control phy.
- - reg : base physical address of PHY_CONTROL registers.
- The size of this register is the total sum of size of all PHY_CONTROL
- registers that the SoC has. For example, the size will be
- '0x4' in case we have only one PHY_CONTROL register (e.g.
- OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
- and, '0x8' in case we have two PHY_CONTROL registers (e.g.
- USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
- and so on.
-
-Example:
- usbphy@12100000 {
- compatible = "samsung,exynos5250-usb3phy";
- reg = <0x12100000 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- clocks = <&clock 1>, <&clock 286>;
- clock-names = "ext_xtal", "usbdrd30";
-
- usbphy-sys {
- /* USB device and host PHY_CONTROL registers */
- reg = <0x10040704 0x8>;
- };
- };
diff --git a/dts/Bindings/vendor-prefixes.txt b/dts/Bindings/vendor-prefixes.txt
index 82d2ac9..55df1d4 100644
--- a/dts/Bindings/vendor-prefixes.txt
+++ b/dts/Bindings/vendor-prefixes.txt
@@ -34,6 +34,7 @@ avago Avago Technologies
avic Shanghai AVIC Optoelectronics Co., Ltd.
axis Axis Communications AB
bosch Bosch Sensortec GmbH
+boundary Boundary Devices Inc.
brcm Broadcom Corporation
buffalo Buffalo, Inc.
calxeda Calxeda
@@ -51,6 +52,7 @@ cirrus Cirrus Logic, Inc.
cloudengines Cloud Engines, Inc.
cnm Chips&Media, Inc.
cnxt Conexant Systems, Inc.
+compulab CompuLab Ltd.
cortina Cortina Systems, Inc.
cosmic Cosmic Circuits
crystalfontz Crystalfontz America, Inc.
@@ -82,6 +84,7 @@ everspin Everspin Technologies, Inc.
excito Excito
fcs Fairchild Semiconductor
firefly Firefly
+focaltech FocalTech Systems Co.,Ltd
fsl Freescale Semiconductor
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
@@ -101,6 +104,7 @@ himax Himax Technologies, Inc.
hisilicon Hisilicon Limited.
hit Hitachi Ltd.
hitex Hitex Development Tools
+holt Holt Integrated Circuits, Inc.
honeywell Honeywell
hp Hewlett Packard
i2se I2SE GmbH
@@ -168,7 +172,9 @@ pericom Pericom Technology Inc.
phytec PHYTEC Messtechnik GmbH
picochip Picochip Ltd
plathome Plat'Home Co., Ltd.
+plda PLDA
pixcir PIXCIR MICROELECTRONICS Co., Ltd
+pulsedlight PulsedLight, Inc
powervr PowerVR (deprecated, use img)
qca Qualcomm Atheros, Inc.
qcom Qualcomm Technologies, Inc
@@ -191,7 +197,9 @@ sbs Smart Battery System
schindler Schindler
seagate Seagate Technology PLC
semtech Semtech Corporation
+sgx SGX Sensortech
sharp Sharp Corporation
+sigma Sigma Designs, Inc.
sil Silicon Image
silabs Silicon Laboratories
siliconmitus Silicon Mitus, Inc.
@@ -222,7 +230,9 @@ toradex Toradex AG
toshiba Toshiba Corporation
toumaz Toumaz
tplink TP-LINK Technologies Co., Ltd.
+tronfy Tronfy
truly Truly Semiconductors Limited
+upisemi uPI Semiconductor Corp.
usi Universal Scientific Industrial Co., Ltd.
v3 V3 Semiconductor
variscite Variscite Ltd.
diff --git a/dts/Bindings/w1/omap-hdq.txt b/dts/Bindings/w1/omap-hdq.txt
index fef7947..913c5f9 100644
--- a/dts/Bindings/w1/omap-hdq.txt
+++ b/dts/Bindings/w1/omap-hdq.txt
@@ -1,11 +1,15 @@
* OMAP HDQ One wire bus master controller
Required properties:
-- compatible : should be "ti,omap3-1w"
+- compatible : should be "ti,omap3-1w" or "ti,am4372-hdq"
- reg : Address and length of the register set for the device
- interrupts : interrupt line.
- ti,hwmods : "hdq1w"
+Optional properties:
+- ti,mode: should be "hdq": HDQ mode "1w": one-wire mode.
+ If not specified HDQ mode is implied.
+
Example:
- From omap3.dtsi
@@ -14,4 +18,5 @@ Example:
reg = <0x480b2000 0x1000>;
interrupts = <58>;
ti,hwmods = "hdq1w";
+ ti,mode = "hdq";
};
diff --git a/dts/Bindings/watchdog/brcm,bcm7038-wdt.txt b/dts/Bindings/watchdog/brcm,bcm7038-wdt.txt
new file mode 100644
index 0000000..8412227
--- /dev/null
+++ b/dts/Bindings/watchdog/brcm,bcm7038-wdt.txt
@@ -0,0 +1,19 @@
+BCM7038 Watchdog timer
+
+Required properties:
+
+- compatible : should be "brcm,bcm7038-wdt"
+- reg : Specifies base physical address and size of the registers.
+
+Optional properties:
+
+- clocks: The clock running the watchdog. If no clock is found the
+ driver will default to 27000000 Hz.
+
+Example:
+
+watchdog@f040a7e8 {
+ compatible = "brcm,bcm7038-wdt";
+ clocks = <&upg_fixed>;
+ reg = <0xf040a7e8 0x16>;
+};
diff --git a/dts/include/dt-bindings/clock/at91.h b/dts/include/dt-bindings/clock/at91.h
index 0b4cb99..ab3ee24 100644
--- a/dts/include/dt-bindings/clock/at91.h
+++ b/dts/include/dt-bindings/clock/at91.h
@@ -18,5 +18,6 @@
#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
+#define AT91_PMC_GCKRDY 24 /* Gene