diff options
Diffstat (limited to 'include/asm-arm/arch-imx/imx35-regs.h')
| -rw-r--r-- | include/asm-arm/arch-imx/imx35-regs.h | 139 |
1 files changed, 0 insertions, 139 deletions
diff --git a/include/asm-arm/arch-imx/imx35-regs.h b/include/asm-arm/arch-imx/imx35-regs.h index b8620a8d94..db1eeba70d 100644 --- a/include/asm-arm/arch-imx/imx35-regs.h +++ b/include/asm-arm/arch-imx/imx35-regs.h @@ -132,144 +132,5 @@ /* important definition of some bits of WCR */ #define WCR_WDE 0x04 -/* bits in the SW_MUX_CTL registers */ -#define MUX_CTL_ALT0 (0 << 0) -#define MUX_CTL_ALT1 (1 << 0) -#define MUX_CTL_ALT2 (2 << 0) -#define MUX_CTL_ALT3 (3 << 0) -#define MUX_CTL_ALT4 (4 << 0) -#define MUX_CTL_ALT5 (5 << 0) -#define MUX_CTL_ALT6 (6 << 0) -#define MUX_CTL_ALT7 (7 << 0) - -#define MUX_CTL_PAD_SION (1 << 4) - -/* Register offsets based on IOMUXC_BASE */ -#define MUX_CTL_COMPARE 0x8 -#define MUX_CTL_WDOG_RST 0xc - -#define MUX_CTL_I2C1_CLK 0x110 -#define MUX_CTL_I2C1_DAT 0x114 -#define MUX_CTL_I2C2_CLK 0x118 - -#define MUX_CTL_STXD5 0x130 -#define MUX_CTL_SRXD5 0x134 -#define MUX_CTL_SCK5 0x138 -#define MUX_CTL_STXFS5 0x13c - -#define MUX_CTL_TX5_RX0 0x158 -#define MUX_CTL_TX4_RX1 0x15c - -#define MUX_CTL_CSPI1_MOSI 0x170 -#define MUX_CTL_CSPI1_MISO 0x174 -#define MUX_CTL_CSPI1_SS0 0x178 -#define MUX_CTL_CSPI1_SS1 0x17c -#define MUX_CTL_CSPI1_SCLK 0x180 -#define MUX_CTL_CSPI1_SPI_RDY 0x184 -#define MUX_CTL_RXD1 0x188 -#define MUX_CTL_TXD1 0x18c -#define MUX_CTL_RTS1 0x190 -#define MUX_CTL_CTS1 0x194 - -#define MUX_CTL_ATA_RESET_B 0x274 - -#define MUX_CTL_FEC_TX_CLK 0x2e0 -#define MUX_CTL_FEC_RX_CLK 0x2e4 -#define MUX_CTL_FEC_RX_DV 0x2e8 -#define MUX_CTL_FEC_COL 0x2ec -#define MUX_CTL_FEC_RDATA0 0x2f0 -#define MUX_CTL_FEC_TDATA0 0x2f4 -#define MUX_CTL_FEC_TX_EN 0x2f8 -#define MUX_CTL_FEC_MDC 0x2fc -#define MUX_CTL_FEC_MDIO 0x300 -#define MUX_CTL_FEC_TX_ERR 0x304 -#define MUX_CTL_FEC_RX_ERR 0x308 -#define MUX_CTL_FEC_CRS 0x30c -#define MUX_CTL_FEC_RDATA1 0x310 -#define MUX_CTL_FEC_TDATA1 0x314 -#define MUX_CTL_FEC_RDATA2 0x318 -#define MUX_CTL_FEC_TDATA2 0x31c -#define MUX_CTL_FEC_RDATA3 0x320 -#define MUX_CTL_FEC_TDATA3 0x324 - -#define PAD_CTL_COMPARE 0x32c -#define PAD_CTL_WDOG_RST 0x330 - -#define PAD_CTL_I2C1_CLK 0x554 -#define PAD_CTL_I2C1_DAT 0x558 -#define PAD_CTL_I2C2_CLK 0x55c - -#define PAD_CTL_STXD5 0x574 -#define PAD_CTL_SRXD5 0x578 -#define PAD_CTL_SCK5 0x57c -#define PAD_CTL_STXFS5 0x580 - -#define PAD_CTL_TX5_RX0 0x59c -#define PAD_CTL_TX4_RX1 0x5a0 - -#define PAD_CTL_CSPI1_MOSI 0x5b4 -#define PAD_CTL_CSPI1_MISO 0x5b8 -#define PAD_CTL_CSPI1_SS0 0x5bc -#define PAD_CTL_CSPI1_SS1 0x5c0 -#define PAD_CTL_CSPI1_SCLK 0x5c4 -#define PAD_CTL_CSPI1_SPI_RDY 0x5c8 -#define PAD_CTL_RXD1 0x5cc -#define PAD_CTL_TXD1 0x5d0 -#define PAD_CTL_RTS1 0x5d4 -#define PAD_CTL_CTS1 0x5d8 - -#define PAD_CTL_ATA_RESET_B 0x6d8 - -#define PAD_CTL_FEC_TX_CLK 0x744 -#define PAD_CTL_FEC_RX_CLK 0x748 -#define PAD_CTL_FEC_RX_DV 0x74c -#define PAD_CTL_FEC_COL 0x750 -#define PAD_CTL_FEC_RDATA0 0x754 -#define PAD_CTL_FEC_TDATA0 0x758 -#define PAD_CTL_FEC_TX_EN 0x75c -#define PAD_CTL_FEC_MDC 0x760 -#define PAD_CTL_FEC_MDIO 0x764 -#define PAD_CTL_FEC_TX_ERR 0x768 -#define PAD_CTL_FEC_RX_ERR 0x76c -#define PAD_CTL_FEC_CRS 0x770 -#define PAD_CTL_FEC_RDATA1 0x774 -#define PAD_CTL_FEC_TDATA1 0x778 -#define PAD_CTL_FEC_RDATA2 0x77c -#define PAD_CTL_FEC_TDATA2 0x780 -#define PAD_CTL_FEC_RDATA3 0x784 -#define PAD_CTL_FEC_TDATA3 0x788 - -/* The modes a specific pin can be in - * these macros can be used in mx31_gpio_mux() and have the form - * MUX_[contact name]__[pin function] - */ - -#define MUX_RXD1_UART1_RXD_MUX ((MUX_CTL_ALT0 << 16) | MUX_CTL_RXD1) -#define MUX_TXD1_UART1_TXD_MUX ((MUX_CTL_ALT0 << 16) | MUX_CTL_TXD1) -#define MUX_RTS1_UART1_RTS_B ((MUX_CTL_ALT0 << 16) | MUX_CTL_RTS1) -#define MUX_RTS1_UART1_CTS_B ((MUX_CTL_ALT0 << 16) | MUX_CTL_CTS1) - -#define MUX_I2C1_CLK_I2C1_SLC ((MUX_CTL_ALT0 << 16) | MUX_CTL_I2C1_CLK) -#define MUX_I2C1_DAT_I2C1_SDA ((MUX_CTL_ALT0 << 16) | MUX_CTL_I2C1_DAT) - -#define MUX_FEC_TX_CLK_FEC_TX_CLK ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TX_CLK) -#define MUX_FEC_RX_CLK_FEC_RX_CLK ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RX_CLK) -#define MUX_FEC_RX_DV_FEC_RX_DV ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RX_DV) -#define MUX_FEC_COL_FEC_COL ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_COL) -#define MUX_FEC_TX_EN_FEC_TX_EN ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TX_EN) -#define MUX_FEC_MDC_FEC_MDC ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_MDC) -#define MUX_FEC_MDIO_FEC_MDIO ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_MDIO) -#define MUX_FEC_TX_ERR_FEC_TX_ERR ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TX_ERR) -#define MUX_FEC_RX_ERR_FEC_RX_ERR ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RX_ERR) -#define MUX_FEC_CRS_FEC_CRS ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_CRS) -#define MUX_FEC_RDATA0_FEC_RDATA0 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RDATA0) -#define MUX_FEC_TDATA0_FEC_TDATA0 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TDATA0) -#define MUX_FEC_RDATA1_FEC_RDATA1 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RDATA1) -#define MUX_FEC_TDATA1_FEC_TDATA1 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TDATA1) -#define MUX_FEC_RDATA2_FEC_RDATA2 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RDATA2) -#define MUX_FEC_TDATA2_FEC_TDATA2 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TDATA2) -#define MUX_FEC_RDATA3_FEC_RDATA3 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_RDATA3) -#define MUX_FEC_TDATA3_FEC_TDATA3 ((MUX_CTL_ALT0 << 16) | PAD_CTL_FEC_TDATA3) - #endif /* __ASM_ARCH_MX35_REGS_H */ |